Terminal structure of semiconductor power device and manufacturing method thereof

Abstract

The invention discloses a semiconductor power device, which comprises a terminal region, and the terminal region comprises a terminal groove located in a device terminal region; a first terminal electrode in the terminal trench, electrically connected to a source potential of the semiconductor power device; a second terminal electrode in the terminal trench, electrically connected to a drain potential of the semiconductor power device; and the terminal dielectric layer is filled in the terminal groove to isolate the first terminal electrode and the second terminal electrode from the terminal groove. According to the terminal structure of the semiconductor power device provided by the invention, the electrodes respectively connected to the source and drain potential are arranged in the terminal groove, and the device is changed from the epitaxial layer withstand voltage to the dielectric layer withstand voltage in the terminal groove, so that the withstand voltage is ensured, the area of the terminal is reduced, and the withstand voltage stability of the terminal structure is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a terminal structure and a manufacturing method of a semiconductor power device. Background Art

[0002] Semiconductor power devices, also known as power electronic devices, refer to electronic devices that can be directly used in the main circuit for processing electric energy and realizing electric energy conversion or control. They can be applied to various fields such as industry, automobiles, rail traction, and household appliances. For example, insulated gate bipolar transistors (IGBT) are widely used in inverters, frequency converters, switching power supplies, lighting circuits, traction drives, and other occasions due to their excellent performance, while semiconductor power devices made of wide bandgap materials such as SiC and GaN have shown great application potential in emerging fields such as new energy vehicles and smart grids due to their higher efficiency and stability. Semiconductor power devices can be classified according to different classification standards, mainly including the following: Common devices include bipolar junction transistors (BJT, Bipolar Junction Transistor), gate turn-off thyristors (GTO, Gate Turn Off thyristor), metal oxide semiconductor field effect transistors (MOSFET, MetalOxide Semiconductor Field Effect Transistor), insulated gate bipolar transistors, etc.

[0003] Breakdown voltage is an important electrical parameter of power devices. It determines the maximum voltage that the device can withstand under normal working conditions, and further determines the maximum output power of the device. The level of breakdown voltage is directly related to the stability and reliability of power devices in complex working environments. Devices with high breakdown voltage can better resist voltage fluctuations and overvoltage shocks, and extend their service life.

[0004] Semiconductor power devices generally include an active region and a terminal region. The active region is located in the center of the device and is used to enable the flow of current between the source and drain under the control of the bias voltage. The terminal region surrounds the active region and is the transition area between the active region and the external environment, which is used to improve the voltage resistance and reliability of the device. Summary of the invention

[0005] The present application provides a terminal structure of a semiconductor power device. By arranging electrodes respectively connected to source and drain potentials in terminal grooves, the device is transformed from an epitaxial layer voltage-resistant device to a dielectric layer voltage-resistant device in the terminal grooves. While ensuring the voltage-resistant device, the terminal area is reduced and the voltage-resistant stability of the terminal structure is improved.

[0006] According to an embodiment of the present invention, a semiconductor power device is provided, comprising a terminal region. The terminal region comprises: a terminal trench located in the device terminal region; a first terminal electrode located in the terminal trench and electrically connected to a source potential of the semiconductor power device; a second terminal electrode located in the terminal trench and electrically connected to a drain potential of the semiconductor power device; and a terminal dielectric layer filled in the terminal trench to isolate the first terminal electrode and the second terminal electrode from the terminal trench.

[0007] According to one embodiment of the present invention, a method for manufacturing a semiconductor power device is also provided, comprising: forming a plurality of grooves in an epitaxial layer, including a gate groove, a terminal groove and a guard ring groove; forming a dielectric layer at the bottom and sidewall of each groove; filling electrode material in each groove after the dielectric layer is formed; etching the electrode material in the terminal groove, retaining part of the electrode material to form a first terminal electrode and a second terminal electrode, and forming a groove between the first terminal electrode and the second terminal electrode; filling dielectric material in the terminal groove after the first terminal electrode and the second terminal electrode are formed; etching away the upper half of the electrode material in the gate groove, retaining the lower half, to form a gate electrode; filling dielectric material in the gate groove for forming the gate electrode, and etching the filled dielectric material, retaining a dielectric material having a certain thickness on the trench sidewalls and the top of the gate electrode, to form a groove for accommodating the gate electrode; filling electrode material in the groove in the upper half of the gate groove to form a gate electrode; and forming a well region, a source region and a doping layer at corresponding positions of the epitaxial layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings:

[0009] Figure 1 It is a schematic diagram of a partial cross-sectional structure of an existing semiconductor power device 100 perpendicular to the device surface;

[0010] Figure 2 A partial cross-sectional view of a semiconductor power device 200 according to an embodiment of the present invention is shown;

[0011] Figure 3 A partial cross-sectional view of a semiconductor power device 300 according to an embodiment of the present invention is shown;

[0012] Figure 4 A partial cross-sectional view of a semiconductor power device 400 according to an embodiment of the present invention is shown;

[0013] Figure 5 A partial cross-sectional view of a semiconductor power device 500 according to an embodiment of the present invention is shown;

[0014] Fig. 6A A plan view of an epitaxial layer upper surface ES1 of a semiconductor power device 500 according to an embodiment of the present invention is shown;

[0015] Figure 6B A plan view of an epitaxial layer upper surface ES1 of a semiconductor power device 500 according to another embodiment of the present invention is shown;

[0016] Figure 7 A method 700 for manufacturing a semiconductor power device according to an embodiment of the present invention is shown;

[0017] Figure 8A-8I 1 and 2 show a cross-sectional view of a device during the implementation of each step of a manufacturing method 700 according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The specific embodiments of the present invention will be described in detail below. It should be noted that the embodiments described herein are only for illustration and are not intended to limit the present invention. In the following description, a large number of specific details are set forth in order to provide a thorough understanding of the present invention. However, it is obvious to those of ordinary skill in the art that these specific details do not have to be used to implement the present invention. In other examples, in order to avoid confusing the present invention, known circuits, materials or methods are not specifically described.

[0019] Throughout the specification, references to "one embodiment", "an embodiment", "an example" or "an example" mean that a particular feature, structure or characteristic described in conjunction with the embodiment or example is included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment", "in an embodiment", "an example" or "an example" appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. In addition, particular features, structures or characteristics may be combined in one or more embodiments or examples in any appropriate combination and / or sub-combination. In addition, it should be understood by those of ordinary skill in the art that the drawings provided herein are for illustrative purposes and that the drawings are not necessarily drawn to scale. The same reference numerals indicate the same elements. The term "and / or" used herein includes any and all combinations of one or more related listed items. The drawings are not drawn to scale and are for illustrative purposes only. For clarity, unless otherwise specified, the same elements have been designated by corresponding reference numerals in different drawings.

[0020] The terms “having,” “comprising,” “including,” “including,” and the like are open ended, and these terms indicate the presence of stated structures, elements, or features, but do not exclude additional elements or features.

[0021] When describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly on the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the device is turned over, the layer or region will be "below" or "beneath" another layer or region.

[0022] If it is intended to describe a situation where it is directly on another layer or another area, this article will use the expression “directly on…” or “on… and adjacent to…”.

[0023] In some of the figures, the relative doping concentration is illustrated by indicating "-" or "+" next to the doping type "n" or "p". For example, "n-" means that the doping concentration is lower than the doping concentration of the "n"-doping region, while the "n"-doping region has a higher doping concentration than the "n-"-doping region. Doping regions with the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n"-doping regions may have the same or different absolute doping concentrations.

[0024] In an embodiment of the present invention, each semiconductor layer or region has a first conductivity type or a second conductivity type. The first conductivity type refers to one of n-type or p-type, and the second conductivity type is the other one. That is to say, the semiconductor layer with the first conductivity type can be an n-type semiconductor layer or a p-type semiconductor layer. When the semiconductor layer with the first conductivity type is an n-type semiconductor layer, the semiconductor layer with the second conductivity type is a p-type semiconductor layer. The n-type semiconductor layer is formed by doping n-type impurities in the semiconductor layer. The n-type impurities can be pentavalent elements such as phosphorus and arsenic. The p-type semiconductor layer is formed by doping p-type impurities in the semiconductor layer. The p-type impurities can be trivalent elements such as boron, indium, and gallium.

[0025] Figure 1 FIG. 1 is a schematic diagram of a partial cross-sectional structure of an existing semiconductor power device 100 perpendicular to the device surface. Figure 1 As shown, the semiconductor power device 100 includes a substrate layer 101 , an epitaxial layer 102 , an active region A1 and a terminal region A2 located in the epitaxial layer 102 , a source metal layer 110 and a drain metal layer 130 .

[0026] exist Figure 1In the embodiment, the active area A1 includes a gate trench 103. The gate trench 103 is located in the epitaxial layer 102 and extends from the upper surface of the epitaxial layer 102 to the inside of the epitaxial layer 102. The field plate electrode 104 is located in the lower half of the gate trench 103, and the gate electrode 106 is located in the upper half of the gate trench 103. The gate trench 103 is filled with a gate dielectric layer 105, which isolates the gate electrode 106 and the field plate electrode 104 from the gate trench 103, and at the same time, isolates the gate electrode 106 from the field plate electrode 104 thereunder.

[0027] like Figure 1 As shown, a well region 107 is provided in the epitaxial layer between the gate trenches 103, extending from the upper surface of the epitaxial layer 102 to the inside of the epitaxial layer 102 and exposed to the upper surface of the epitaxial layer 102. A source region 109 is provided in the well region 107, extending from the upper surface of the epitaxial layer 102, that is, the surface of the well region 107, to the inside of the well region 107. The source metal layer 110 is connected to the source region 109 through a connection structure (contact plug or through hole), so as to connect the potential of the source region 109 to the source potential S of the semiconductor power device 100.

[0028] Figure 1 In the embodiment, the terminal region A2 includes a terminal trench 113. The terminal trench 113 is located in the epitaxial layer 102 and extends from the upper surface of the epitaxial layer 102 to the inside of the epitaxial layer 102. The terminal electrode 114 is located in the terminal trench 113 and is isolated from the terminal trench 113 by a terminal dielectric layer 115.

[0029] In the semiconductor power device 100, the terminal electrode 114 is connected to the source metal layer 110 through a connection structure. The terminal groove 113 forms a protection around the active area A1. When the device is reverse biased, it bears a large part of the reverse bias voltage, which determines the voltage resistance of the device. The number of terminal grooves 113 increases with the increase of the voltage resistance requirements of the device. However, the increase in the number of terminal grooves 113 will cause the increase of the terminal area, occupy a larger chip area, and increase the cost of the device.

[0030] Figure 2 FIG. 2 shows a partial cross-sectional view of a semiconductor power device 200 according to an embodiment of the present invention. The cross section is perpendicular to the surface of the device and also perpendicular to the length direction of each groove of the device. Figure 2 As shown, the semiconductor power device 200 includes a substrate layer 201, an epitaxial layer 202, a source metal layer 210, a drain metal layer 230 and a guard ring metal layer 220. The epitaxial layer 202 is located on the substrate layer 201, and has an epitaxial layer upper surface ES1 and an epitaxial layer lower surface ES2. The epitaxial layer upper surface ES1 and the epitaxial layer lower surface ES2 are parallel and opposite to each other, and the epitaxial layer lower surface ES2 is in contact with the substrate layer 201. Figure 2In the embodiment, the epitaxial layer upper surface ES1 is also the semiconductor layer upper surface of the semiconductor power device 200. The source metal layer 210 and the guard ring metal layer 220 are located on one side of the epitaxial layer upper surface ES1, that is, on the front side of the device 200. The drain metal layer 230 is located on one side of the substrate layer 201 and is connected to the substrate layer 201, that is, on the reverse side of the device.

[0031] exist Figure 2 In the figure, the semiconductor power device 200 can be divided into an active area A1, a terminal area A2 and a guard ring area A3 according to the different functions of each part, and the three are distributed in the epitaxial layer 202 and share the epitaxial layer 202. The active area A1 is located in the central area of ​​the semiconductor power device 200, the terminal area A2 is distributed in a ring around the active area A1, and the guard ring area A3 is distributed in a ring around the terminal area A2.

[0032] The active area A1 is provided with gate trenches 203 and well regions 207 between the gate trenches 203. The gate trenches 203 are located in the epitaxial layer 202 and extend from the upper surface ES1 of the epitaxial layer 202 to the inside of the epitaxial layer 202. The gate trenches 203 are provided with field plate electrodes 204 and gate electrodes 206. The field plate electrode 204 is located in the lower half of the gate trenches 203, and the gate electrode 206 is located in the upper half of the gate trenches 203. The gate trenches 203 are filled with a gate dielectric layer 205, which isolates the gate electrode 206 and the field plate electrode 204 from the gate trenches 203, and at the same time, isolates the gate electrode 206 from the field plate electrode 204 thereunder. The well region 207 is distributed in the epitaxial layer region between adjacent gate trenches 203 and extends from the upper surface ES1 of the epitaxial layer 202 to the inside of the epitaxial layer 202. An active region 209 is distributed in the well region 207. The source region 209 extends from the surface of the well region 207, that is, the upper surface ES1 of the epitaxial layer, to the inside of the well region 207. Figure 2 In the embodiment, the depth of the source region 209 is less than the depth of the well region 207. In some embodiments, a well contact region is also embedded in the source region 209, and the well contact region connects the well region 207 to the source metal layer 210. The source region 209 and the source metal layer 210 are electrically connected through a connection structure CT, and are commonly connected to the source potential S of the semiconductor power device 200. The connection structure CT includes any suitable structure capable of realizing an electrical connection function, such as a contact plug and a through hole.

[0033] The substrate layer 201, the epitaxial layer 202 and the source region 208 have a first doping type, and the well region 207 has a second doping type. In some embodiments, the first doping type is n-type doping, and the second doping type is p-type doping. In other embodiments, the first doping type is p-type doping, and the second doping type is n-type doping.

[0034] A terminal groove 213 is distributed in the terminal area A2. The terminal groove 213 is located in the epitaxial layer 202. A first terminal electrode 214 and a second terminal electrode 234 are distributed in the terminal groove 213. The first terminal electrode 214 and the second terminal electrode 234 are respectively located on both sides of the terminal groove 213. The terminal groove 213 is filled with a terminal dielectric layer 215 to isolate the first terminal electrode 214 and the second terminal electrode 234 from the terminal groove 213. The first terminal electrode 214 is connected to the source metal layer 210 through the connection structure CT, that is, the first terminal electrode 214 is connected to the source potential S of the device. The second terminal electrode 234 is connected to the guard ring metal layer 220 through the connection structure CT, and finally connected to the drain potential D of the semiconductor power device 200. In one embodiment, the spacing between the first terminal electrode 214 and the second terminal electrode 234 ranges from 0.1μm to 5μm.

[0035] A guard ring trench 223 and a doped layer 229 are distributed in the guard ring area A3. The guard ring trench 223 is located in the epitaxial layer 202. A guard ring electrode 224 and a guard ring dielectric layer 225 are distributed in the guard ring trench 223. The guard ring electrode 224 is isolated from the guard ring trench 223 by the guard ring dielectric layer 225. The doped layer 229 is located in the epitaxial layer 202, extending from the epitaxial layer upper surface ES1 to the inside of the epitaxial layer 202. In one embodiment, the doped layer 229 has the same doping type as the epitaxial layer 202. In one embodiment, the doped layer 229, the epitaxial layer 202 and the substrate layer 201 are all n-type doped. Figure 2 In an embodiment, the guard ring electrode 224 and the doping layer 229 are each connected to the guard ring metal layer 220 via a connection structure CT.

[0036] In the embodiment of the present invention, the source metal layer 210 is connected to the source potential S of the device, and the potential of the guard ring metal layer 220 is the same as the drain potential D. Figure 2 In the illustrated embodiment, the guard ring metal layer 220 is located on the front side of the device and is located on the upper surface ES1 of the epitaxial layer like the source metal layer 210. The guard ring metal layer 220 and the source metal layer 210 are separated from the upper surface ES1 of the epitaxial layer by an insulating layer such as an interlayer dielectric layer (for the sake of clarity of the illustration, Figure 2 The guard ring metal layer 220 is electrically connected to the epitaxial layer 202, the substrate layer 201, and the drain metal layer 230 through the doping layer 229, that is, they are all connected to the drain potential D. Figure 2In the embodiment, after the guard ring metal layer 220 is connected to the second terminal electrode 234, the guard ring electrode 224 and the doping layer 229 through the connection structure CT, it does not need to be connected to other regions or metal layers. Through the doping layer 229, the potential is the same as that of the epitaxial layer 202, and thus its potential is equal to the drain potential D. In some embodiments, in order to further stabilize the potential of the second terminal electrode 234, the guard ring metal layer 220 can also be connected to the drain potential D through the metal layer.

[0037] exist Figure 2 In the embodiment, the first terminal electrode 214 and the second terminal electrode 234 in the terminal groove 213 are respectively connected to different source potentials S and drain potentials D, which form a potential difference. When the semiconductor power device 200 is reverse biased, the maximum electric field of the device is located in the terminal dielectric layer 215 between the first terminal electrode 214 and the second terminal electrode 234, rather than in the epitaxial layer near the terminal groove. In other words, the semiconductor power device 200 of the embodiment of the present invention transforms the withstand voltage of the traditional epitaxial layer in the terminal region into the withstand voltage of the dielectric layer, thereby improving the withstand voltage capability and withstand voltage stability of the device. And, as Figure 2 As shown, the semiconductor power device 200 uses two terminal electrodes connected to different potentials to achieve the voltage resistance of the terminal area. Even if the voltage resistance requirement is increased, it is only necessary to increase the dielectric thickness between the two terminal electrodes, that is, the distance between the two terminal electrodes. There is no need to increase the number of terminal grooves, so that the area of ​​the terminal can be greatly reduced, which is beneficial to reducing the size of the device.

[0038] Figure 3 FIG. 3 shows a partial cross-sectional view of a semiconductor power device 300 according to an embodiment of the present invention. The cross section is perpendicular to the surface of the device and perpendicular to the length direction of each groove of the device. Figure 2 In contrast, the guard ring metal layer 220 is connected to the second terminal electrode 234 and the guard ring electrode 224, the epitaxial layer does not include the doping layer 229, and the guard ring metal layer 220 is connected to the drain potential D through the upper metal or other means (for example, the device external connection structure electrically connects the guard ring metal layer 220 and the drain metal layer 230). In some embodiments, the guard ring metal layer 220 can also be connected to other potentials different from the source potential S. The working principle of the semiconductor power device 300 is similar to that of the semiconductor power device 200, and will not be repeated here.

[0039] Figure 4 FIG. 4 shows a partial cross-sectional view of a semiconductor power device 400 according to an embodiment of the present invention. The cross section is perpendicular to the surface of the device and also perpendicular to the length direction of each trench of the device. Figure 2 In contrast, there is no guard ring trench in the guard ring area A3 of the semiconductor power device 400. Figure 4In the embodiment, the guard ring area A3 includes a doped layer 229, and the guard ring metal layer 220 is electrically connected to the doped layer 229 through the connection structure CT. The guard ring metal layer 220 connects the potential of the second terminal electrode 234 to the drain potential D through the doped layer 229, the epitaxial layer 202, and the substrate layer 201. The working principle of the semiconductor power device 300 is similar to that of the semiconductor power device 200, which will not be repeated here.

[0040] Figure 5 FIG. 5 shows a partial cross-sectional view of a semiconductor power device 500 according to an embodiment of the present invention. The cross section is perpendicular to the surface of the device and perpendicular to the length direction of each groove of the device. Figure 2 In contrast, the guard ring groove 223 in the guard ring area A3 of the semiconductor power device 500 is connected to the terminal groove 213 through the bridge structure 501. The bridge structure 501 includes a bridge groove 523, a bridge electrode 524 and a bridge dielectric layer 525. Specifically, the bridge groove 523 extends downward from the upper surface ES1 of the epitaxial layer, and its depth is shallower than the depth of the terminal groove 213 and the guard ring groove 223. The bridge groove 523 is located between the guard ring groove 223 and the terminal groove 213, connecting the guard ring groove 223 and the terminal groove 213. The bridge dielectric layer 525 is located on the inner wall of the bridge groove 523, connecting the terminal dielectric layer 215 and the guard ring dielectric layer 225, and connecting the terminal dielectric layer 215 and the guard ring dielectric layer 225 into a whole. The bridge electrode 524 is located in the bridge trench 523 and is isolated from the bridge trench 523 by the bridge dielectric layer 525. The bridge electrode 524 connects the second terminal electrode 234 and the guard ring electrode 224. Figure 5 In the embodiment, the bridge structure 501 connects the potential of the second terminal electrode 234 to the potential of the guard ring electrode 224. The guard ring metal layer 220 connects the potential of the guard ring electrode 224 to the drain potential D through the doped layer 229, the epitaxial layer 202, and the substrate layer 201. The working principle of the semiconductor power device 500 is similar to that of the semiconductor power device 200, which will not be repeated here.

[0041] In some embodiments, based on the semiconductor power device 500, the doping layer 229 can be omitted, and the guard ring metal layer 220 is connected to the drain potential D through the upper metal or other methods (for example, the device external connection structure electrically connects the guard ring metal layer 220 and the drain metal layer 230).

[0042] Fig. 6A FIG. 5 shows a plan view of an epitaxial layer upper surface ES1 of a semiconductor power device 500 according to an embodiment of the present invention. It should be understood that Fig. 6A Only a part of the epitaxial layer upper surface ES1 is shown, not the whole area. Fig. 6AAs shown, the gate electrode 206, the source region 209 exposed on both sides of the gate trench to the upper surface ES1 of the epitaxial layer, etc. are distributed in strips, and the strip structure can be a partial structure of one straight side of the device structure with a quadrilateral ring structure, or a partial structure of an arc side of the device structure with a circular ring structure. Fig. 6A As shown, the bridge structure 501 connects the second terminal electrode 234 and the guard ring electrode 224, thereby connecting the potentials of the second terminal electrode 234 and the guard ring electrode 224. Fig. 6A The AA' line shown is perpendicular to the epitaxial layer upper surface ES1 and downward to obtain the following Figure 5 Cross section shown.

[0043] Figure 6B FIG. 5 shows a plan view of an epitaxial layer upper surface ES1 of a semiconductor power device 500 according to another embodiment of the present invention. It should be understood that Figure 6B Only a part of the epitaxial layer upper surface ES1 is shown, not the whole area. Figure 6B As shown, the gate electrode 206, the source region 208 exposed on both sides of the gate trench to the upper surface ES1 of the epitaxial layer, etc. are distributed in strips, and the strip structure can be a partial structure of one straight side of the device structure with a quadrilateral ring structure, or a partial structure of an arc side of the device structure with a circular ring structure. Figure 6B As shown, the bridge structure 501 connects the second terminal electrode 234 and the guard ring electrode 224, thereby connecting the potentials of the second terminal electrode 234 and the guard ring electrode 224. Fig. 6A The difference is that in Figure 6B In the embodiment, in the terminal trench, in a partial region, the first terminal electrode 214 is buried in the lower half of the trench like the field plate electrode 204, and a gate electrode 206 is distributed above the first terminal electrode 214. In a partial region, the first terminal electrode 214 is exposed upward to the upper surface ES1 of the epitaxial layer, and the portion of the first terminal electrode 214 exposed to the upper surface ES1 of the epitaxial layer is connected to the source metal layer 210 through the connection structure CT, thereby connecting the potential of the first terminal electrode 214 to the source potential S. Figure 6B The BB' line shown is perpendicular to the epitaxial layer upper surface ES1 and downward to obtain the following Figure 5 Cross section shown.

[0044] Figure 7 A method 700 for manufacturing a semiconductor power device according to an embodiment of the present invention is shown. Figure 8A-8I 1 and 2 show a cross-sectional view of a device during the implementation of each step of a manufacturing method 700 according to an embodiment of the present invention.

[0045] like Figure 7 As shown, the manufacturing method 700 includes steps 701 to 709. Figure 8A-8I Each step of the manufacturing method 700 is described in detail.

[0046] Step 701, forming a plurality of trenches in the epitaxial layer, including a gate trench 203, a terminal trench 213 and a guard ring trench 223. The device cross section after the trenches are formed is as follows: Fig. 8A The method of forming the groove may include photolithography, multi-layer epitaxy, etc.

[0047] Step 702, forming a dielectric layer at the bottom and sidewalls of each trench. The cross section of the device after the dielectric layer is formed is as follows: Figure 8B As shown. The dielectric layer may include an insulating material, such as an oxide or a nitride. The dielectric layer in the gate trench 203 forms a gate dielectric layer 205. The dielectric layer in the terminal trench 213 forms a dielectric layer 245. The dielectric layer in the guard ring trench 223 forms a guard ring dielectric layer 225. In one embodiment, the method of forming the dielectric layer includes filling the trench with a dielectric material, and then removing the excess dielectric material in the trench by a photolithography process to leave the dielectric layer.

[0048] Step 703, filling the trenches with electrode materials after the dielectric layer is formed. The cross section of the device after the electrode materials are filled is as follows: Figure 8C As shown. The electrode material may include a suitable conductive material, such as metal or polysilicon. The electrode material 254 in the gate trench 203 is used to form the field plate electrode 204 in a subsequent step. The electrode material 264 in the terminal trench 213 is used to form the terminal electrodes 214 and 234 in a subsequent step. The electrode material in the guard ring trench 223 forms the guard ring electrode 224.

[0049] Step 704, etching the electrode material 264 in the terminal groove 213, retaining a portion of the electrode material 264 to form the first terminal electrode 214 and the second terminal electrode 234, and forming a groove between the first terminal electrode 214 and the second terminal electrode 234. The device cross section after etching the electrode material 264 is as follows: Fig.8D The etching method may include a photolithography process and the like.

[0050] Step 705, filling the terminal trench 213 with dielectric material after forming the first terminal electrode 214 and the second terminal electrode 234. The cross section of the device after filling with dielectric material is as follows: Fig. 8E The dielectric material includes an insulating material. The dielectric material may be consistent with or different from the material used to form the dielectric layer in step 702. The filled dielectric material and the dielectric layer 245 in the original trench together form the dielectric layer 215 in the terminal trench 213.

[0051] Step 706, etching the electrode material 254 in the gate trench 203, removing the upper half of the electrode material 254 in the gate trench 203, and retaining the lower half to form the gate electrode 204. The device cross section after etching the electrode material 254 is as follows: Fig.8F The etching method may include photolithography, dry etching, wet etching, etc.

[0052] Step 707, fill the gate trench 203 where the gate electrode 204 is formed with a dielectric material, and etch the filled dielectric material, leaving a dielectric layer with a certain thickness on the trench sidewall and a dielectric layer with a certain thickness on the top of the gate electrode 204, to form a trench for accommodating the gate electrode 206. The dielectric material filled this time includes an insulating material. The dielectric material can be the same as the material of the dielectric layer formed in step 702, or it can be different, and finally a dielectric layer 205 is formed in the gate trench 203. The cross section of the device after filling and etching the dielectric material is as follows: Figure 8G shown.

[0053] Step 708, fill the upper half of the gate trench 203 with electrode material to form a gate electrode 206. The cross section of the device after the gate electrode 206 is formed is as follows: Figure 8H The electrode material may include a suitable conductive material, such as metal or polysilicon.

[0054] Step 709, forming a well region 207, a source region 209 and a doping layer 229 at corresponding positions of the epitaxial layer 202. Specifically, the well region 207 is distributed in the epitaxial layer region between adjacent gate trenches, extending from the upper surface of the epitaxial layer 202 to the inside of the epitaxial layer. The source region 209 is distributed in the well region 207, extending from the surface of the well region 207 to the inside of the well region 207. The method of forming the well region 207, the source region 209 and the doping layer 229 includes any existing technical means such as photolithography, ion implantation, etc. The device cross section after forming the well region 207, the source region 209 and the doping layer 229 is as follows: Figure 8I shown.

[0055] It should be understood that the above steps do not have to be implemented in order. For example, steps 704 and 705 and steps 706, 707, and 708 can be implemented in a reversed order, and step 709 can also be implemented before step 702. Figure 4 The embodiments only show some process steps in the device manufacturing process, not all of them. After understanding the essence of the present invention, those skilled in the art can add or reduce process steps according to the guidance of the embodiments of the present application and according to the application requirements.

[0056] It should be understood that the embodiments of the present application only illustrate device structures related to the technical solutions of the present application. At the same time, the structures in the embodiments of the present application are only schematic diagrams of partial structures of semiconductor power devices. In order to more clearly and concisely illustrate the technical solutions of the present invention, some areas of the device are not shown in the figures. For example, in order to prevent short circuits between the source metal layer, the guard ring metal layer and partial areas of the upper surface of the epitaxial layer, the interlayer dielectric layer between the upper surface of the epitaxial layer and the metal layer is not shown in the figures. For another example, the well contact area is not shown in the figures.

[0057] After the process steps of the semiconductor layer are completed, a source metal layer 210, a guard ring metal layer 220 and a drain metal layer 230 are also made on the front and back sides of the device, as well as other back-end processes of the device. The source metal layer 210 and the guard ring metal layer 220 are located on the front side of the device, above the epitaxial layer 202. The source metal layer 210 is electrically connected to the source region 209 and the first terminal electrode 214. The guard ring metal layer 220 is electrically connected to the second terminal electrode 234, the guard ring electrode 224 and the doping layer 229. The drain metal layer 230 covers the back side of the device, that is, it is located on the substrate layer 201 where the epitaxial layer 202 is located, and is located on two opposite surfaces of the substrate layer 201 with the epitaxial layer 202. The drain metal layer 230 is electrically connected to the substrate layer 201. The manufacturing process of the metal layer and other back-end processes are commonly used technical means in the field and will not be repeated here.

[0058] The embodiment of the present invention takes a shielded gate power device as an example to illustrate the working principle of the technical solution of the present invention. It should be understood that the present invention can also be applied to other power devices, such as power devices with gate electrodes and field plate electrodes located in different grooves, planar gate devices, super junction devices, IGBT devices, etc.

[0059] The embodiments of the present application are described above, and these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A semiconductor power device, comprising a terminal region, wherein the terminal region comprises: terminal groove; A first terminal electrode, located in the terminal trench and electrically connected to a source potential of the semiconductor power device; A second terminal electrode, located in the terminal trench and electrically connected to a drain potential of the semiconductor power device; as well as The terminal dielectric layer is filled in the terminal trench to isolate the first terminal electrode and the second terminal electrode from the terminal trench. 2 . The semiconductor power device according to claim 1 , wherein a distance between the first terminal electrode and the second terminal electrode is in a range of 0.1 μm to 5 μm.

3. The semiconductor power device according to claim 1, further comprising an active region, wherein the active region comprises: Gate trench; A field plate electrode, located in the lower half of the gate trench; A gate electrode, located in the upper part of the gate trench; as well as The gate dielectric layer is filled in the gate trench and isolates the field plate electrode, the gate electrode and the gate trench respectively.

4. The semiconductor power device according to claim 1, further comprising a guard ring region, wherein the guard ring region comprises: Guard ring groove; A guard ring electrode, located in the guard ring groove; as well as A guard ring dielectric layer is located in the guard ring trench and isolates the guard ring electrode from the guard ring trench; The guard ring electrode is electrically connected to the second terminal electrode through a guard ring metal layer, and the guard ring metal layer is connected to the drain potential of the semiconductor power device.

5. The semiconductor power device according to claim 1, further comprising a guard ring region, wherein the guard ring region comprises: Guard ring groove; A guard ring electrode, located in the guard ring groove; A guard ring dielectric layer is located in the guard ring trench and isolates the guard ring electrode from the guard ring trench; as well as A doping layer extending from the upper surface of the epitaxial layer to the inside of the epitaxial layer, wherein the doping type of the doping layer is the same as that of the epitaxial layer, and the doping concentration of the doping layer is greater than the doping concentration of the epitaxial layer; Wherein, the guard ring electrode, the doping layer and the second terminal electrode are electrically connected together through a guard ring metal layer.

6. The semiconductor power device according to claim 1, further comprising a guard ring region, wherein the guard ring region comprises: The doped layer extends from the upper surface of the epitaxial layer to the inside of the epitaxial layer, wherein the doped layer has the same doping type as the epitaxial layer, the doping concentration of the doped layer is greater than the doping concentration of the epitaxial layer, and the doped layer is electrically connected to the second terminal electrode through the guard ring metal layer.

7. The semiconductor power device according to claim 1, further comprising: Protection ring area, including: Guard ring groove; A guard ring electrode, located in the guard ring groove; a guard ring dielectric layer, located in the guard ring trench, isolating the guard ring electrode from the guard ring trench; and A doping layer extending from the upper surface of the epitaxial layer to the inside of the epitaxial layer, wherein the doping type of the doping layer is the same as that of the epitaxial layer, and the doping concentration of the doping layer is greater than the doping concentration of the epitaxial layer; Bridge structure, including: A bridge groove, located between the guard ring groove and the terminal groove, connecting the guard ring groove and the terminal groove; a bridge electrode, located in the bridge groove, connecting the second terminal electrode and the guard ring electrode; and The bridge dielectric layer is located in the bridge trench, isolates the bridge electrode from the bridge trench, and connects the guard ring dielectric layer and the terminal dielectric layer; wherein the guard ring electrode and the doping layer are electrically connected together through the guard ring metal layer.

8. The semiconductor power device according to claim 1, further comprising: Protection ring area, including: Guard ring groove; a guard ring electrode disposed in the guard ring trench; and A guard ring dielectric layer is located in the guard ring trench and isolates the guard ring electrode from the guard ring trench; Bridge structure, including: A bridge groove, located between the guard ring groove and the terminal groove, connecting the guard ring groove and the terminal groove; a bridge electrode, located in the bridge groove, connecting the second terminal electrode and the guard ring electrode; and A bridge dielectric layer is located in the bridge trench, isolating the bridge electrode from the bridge trench and connecting the guard ring dielectric layer and the terminal dielectric layer; wherein the second terminal electrode and the guard ring electrode are electrically connected to the drain potential of the semiconductor power device through the guard ring metal layer.

9. The semiconductor power device according to any one of claims 4 to 8, further comprising: a source metal layer, located on the upper surface of the epitaxial layer; A guard ring metal layer, located on the upper surface of the epitaxial layer and isolated from the source metal layer; as well as An active region, including a well region and a source region, extending from the upper surface of the epitaxial layer to the inside of the epitaxial layer, wherein the source region is located in the well region, and the depth of the source region is less than the depth of the well region; The source metal layer is electrically connected to the source region and the first terminal electrode.

10. The semiconductor power device of claim 1, wherein the termination dielectric layer comprises oxide or nitride.

11. A method for manufacturing a semiconductor power device, comprising: forming a plurality of trenches in the epitaxial layer, including a gate trench, a terminal trench, and a guard ring trench; forming a dielectric layer on the bottom and sidewalls of each trench; filling the trenches with electrode materials after forming the dielectric layer; Etching the electrode material in the terminal groove, retaining part of the electrode material to form a first terminal electrode and a second terminal electrode, and forming a groove between the first terminal electrode and the second terminal electrode; filling a dielectric material in the terminal groove after forming the first terminal electrode and the second terminal electrode; Carving away the upper half of the electrode material in the gate trench and retaining the lower half to form a gate electrode; Filling a dielectric material in a gate trench for forming a gate electrode, and etching the filled dielectric material to retain a dielectric material having a certain thickness on the trench sidewall and the top of the gate electrode, thereby forming a trench for accommodating the gate electrode; Filling an electrode material in the upper half of the gate trench to form a gate electrode; as well as A well region, a source region and a doping layer are formed at corresponding positions of the epitaxial layer. 12 . The method for manufacturing a semiconductor power device according to claim 11 , wherein a distance between the first terminal electrode and the second terminal electrode is in a range of 0.1 μm to 5 μm.

13. The method for manufacturing a semiconductor power device according to claim 11, further comprising: forming a source metal layer and a guard ring metal layer on the upper surface of the epitaxial layer, wherein the source metal layer is electrically connected to the source region and the first terminal electrode, and the guard ring metal layer is electrically connected to the second terminal electrode, the guard ring electrode and the doping layer; as well as A drain metal layer is covered on the substrate layer where the epitaxial layer is located, and the drain metal layer and the epitaxial layer are respectively on two opposite surfaces of the substrate layer.

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