Glass-based three-dimensional interconnection structure and packaging framework based on same

Abstract

The invention relates to the technical field of semiconductors, and discloses a glass-based three-dimensional interconnection structure and a packaging framework based on the glass-based three-dimensional interconnection structure, the glass-based three-dimensional interconnection structure comprises a glass plate core, two opposite sides of the glass plate core are respectively a first surface and a second surface; the front rewiring layer is arranged on the first surface; the back rewiring layer is arranged on the second surface; the glass through hole penetrates through the glass plate core, and a base metal interconnection layer is filled in the glass through hole; the base metal interconnection layer extends to the first surface and is electrically connected with the front rewiring layer; and the base metal interconnection layer extends to the second surface and is electrically connected with the back rewiring layer. According to the technical scheme provided by the invention, the technical effects of vertical integration capability, thermal management efficiency, electromagnetic performance and the like can be remarkably improved in a high-frequency and high-integration scene.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a glass-based three-dimensional interconnection structure and a packaging architecture based on the same. Background Art

[0002] The current resin substrate technology faces core problems such as insufficient vertical integration ability, inefficient thermal management, and limited electromagnetic performance in high-frequency and high-integration scenarios, and it is difficult to meet the requirements of 5G radio frequency front-end modules for three-dimensional heterogeneous integration, high-density interconnection, and high reliability.

[0003] Therefore, there is an urgent need to solve the above technical problems through innovative structures. Summary of the Invention

[0004] This application provides a glass-based three-dimensional interconnection structure and a packaging architecture based on the same. By providing an innovative structural design, technical effects such as significantly improving the vertical integration ability, thermal management efficiency, and electromagnetic performance are achieved in high-frequency and high-integration scenarios.

[0005] To achieve the above objectives, the main technical solutions adopted in this application include: In a first aspect, an embodiment of this application provides a glass-based three-dimensional interconnection structure, including: A glass plate core, with a first surface and a second surface on opposite sides of the glass plate core; A front-side redistribution layer disposed on the first surface and a back-side redistribution layer disposed on the second surface; Glass vias penetrating through the glass plate core, with a base metal interconnection layer filled in the glass vias; the base metal interconnection layer extends to the first surface and is electrically connected to the front-side redistribution layer; the base metal interconnection layer extends to the second surface and is electrically connected to the back-side redistribution layer.

[0006] The glass-based three-dimensional interconnection structure provided in this embodiment can effectively improve the integration degree of the circuit and achieve higher-density wiring in a limited space by respectively arranging redistribution layers on the front and back sides of the glass plate core and realizing electrical interconnection through glass vias. This double-sided wiring structure not only enhances the signal processing ability of the package but also improves the thermal management efficiency, reduces the impact of thermal stress on the device, and ensures a stable working environment. In addition, the multi-layer design of the back-side redistribution layer improves the electrical interconnection performance, reduces losses and interference in signal transmission, and is particularly suitable for high-frequency and high-power application requirements. At the same time, this design improves the reliability and scalability of the package, enabling it to provide excellent electrical performance, thermal stability, and flexibility in different application scenarios.

[0007] In one embodiment, the upper surface of the first surface and the lower surface of the second surface include an intermediate pattern medium of a wiring pattern, and the intermediate pattern medium is filled with intermediate metal wirings to form an intermediate metal wiring layer, and the intermediate metal wiring layer is connected to the base metal interconnect layer.

[0008] In this embodiment, by adopting the design of the intermediate metal wiring layer, the electrical interconnect performance and signal transmission efficiency can be significantly improved. This wiring layer is connected to the base metal interconnect layer, effectively realizing the electrical connection between different layers, optimizing signal conduction, reducing losses, and reducing interference. At the same time, this design rationally utilizes the multi-layer structure, improves the wiring density and space utilization, and meets the requirements of miniaturized packaging. In addition, the excellent electrical conductivity and thermal conductivity of the metal wiring not only improve the electrical performance, but also enhance the thermal management ability of the system, avoid damage to the device caused by overheating, and enhance the overall stability and reliability. Through this flexible layout, the intermediate metal wiring layer also provides good scalability for the package, meeting the requirements of different application scenarios.

[0009] In one embodiment, the front-side redistribution layer includes at least one front-side intermediate layer and a front-side solder mask layer stacked, and the front-side intermediate layer is closer to the first surface of the glass substrate core than the front-side solder mask layer; The back-side redistribution layer includes at least one back-side intermediate layer and a back-side solder mask layer stacked, and the back-side intermediate layer is closer to the second surface of the glass substrate core than the back-side solder mask layer.

[0010] In this embodiment, the hierarchical design of the front-side and back-side redistribution layers effectively improves the wiring density and space utilization, while reducing signal interference and optimizing the signal transmission performance. By dividing the front-side redistribution layer into a front-side intermediate layer and a front-side solder mask layer, and the back-side redistribution layer into a back-side intermediate layer and a back-side solder mask layer, each layer works independently, avoiding mutual interference, thereby improving the integration degree of the wiring. The hierarchical structure can not only reduce signal crosstalk and losses, but also optimize the signal transmission quality and improve the electrical performance. In addition, this design helps to improve the heat dissipation performance. Multiple wiring layers provide more paths for heat conduction, enhance the thermal management ability, and avoid overheating problems. Finally, the hierarchical structure also enhances the flexibility and scalability of the design, meets the changes in high integration and complex electrical requirements, and provides higher reliability and performance.

[0011] In one embodiment, each front-side intermediate layer is embedded with a corresponding front-side metal interconnect structure; The upper surface of each front-side intermediate layer includes a front-side pattern medium of a wiring pattern, and the front-side pattern medium is filled with front-side metal wirings to form a front-side metal wiring layer, and the front-side metal wiring layer is electrically connected to the front-side metal interconnect structure.

[0012] In this embodiment, by embedding a front metal interconnect structure in the middle layer of each front layer and electrically connecting it to the front metal wiring layer, the wiring density and integration degree are significantly improved. Through this optimization, the signal transmission path of the circuit is reasonably planned, reducing signal delay, crosstalk and attenuation, thereby enhancing the electrical performance. The use of the front metal interconnect structure realizes a three-dimensional interconnect architecture, makes full use of the space, enhances the efficiency of vertical and horizontal interconnections, and meets the requirements of high-integration circuits. In addition, this design improves the flexibility of the manufacturing process, provides more space for wiring pattern optimization, thereby achieving higher wiring accuracy and flexibility. At the same time, signal interference is effectively reduced, and the signal transmission quality is improved, ensuring efficient circuit performance.

[0013] In one embodiment, a plurality of top vias are provided on the front solder mask layer, and the top vias are connected to the front metal wiring layer; A chip flip-chip bonding area is formed on the upper surface of the front metal wiring layer and corresponding to the top vias; a top metal surface treatment layer is provided in the chip flip-chip bonding area, and the top metal surface treatment layer covers the opening area of the front solder mask layer.

[0014] In this embodiment, through reasonable wiring layer setting, flip-chip bonding technology and solder mask layer protection, the signal transmission path is optimized, the integration degree is improved, and the electrical performance is enhanced. The setting of the top vias enables signals to be directly transmitted from the top layer to the metal wiring layer, reducing the traditional vertical transmission path, thereby reducing signal delay and loss. At the same time, the metal surface treatment layer on the upper surface of the front metal wiring layer effectively prevents the influence of the external environment, enhancing the stability and long-term reliability of the package. Through these designs, not only the performance and reliability of the package are improved, but also the process is simplified, the manufacturing cost is reduced, and the requirements of high-performance and high-reliability packaging are met.

[0015] In one embodiment, a corresponding back metal interconnect structure is embedded in the middle layer of each back layer; A back graphic medium of the wiring pattern is included between the back middle layer and the back solder mask layer, and the back graphic medium is filled with back metal wiring to form a back metal wiring layer, and the back metal wiring layer is electrically connected to the back metal interconnect structure; Wherein, the distance between the lower surface of the middle metal wiring layer on the second surface and the upper surface of the back metal wiring is greater than or equal to 20 μm.

[0016] In this embodiment, by embedding a backside metal interconnect structure in the middle layer of the backside and filling a backside metal wiring layer in the backside graphic medium, the electrical connection and signal transmission are optimized, ensuring that the electrical connection between layers is more stable and reliable. The backside graphic medium provides an effective electrical isolation function, preventing signal interference and enhancing the anti-interference ability of the overall circuit. The electrical connection between the backside metal wiring layer and the backside metal interconnect structure improves the signal transmission efficiency, reduces signal loss and delay, thereby enhancing the signal quality. This design also improves the circuit integration density through a compact wiring structure, enhances the stability and reliability of the package, and meets the packaging requirements of high performance and high reliability.

[0017] In one embodiment, a plurality of bottom vias are provided on the backside solder mask layer, and the bottom vias are connected to the backside metal wiring layer; A bottom pad area is formed on the lower surface of the backside metal wiring layer and corresponding to the bottom vias; A bottom metal surface treatment layer is provided in the bottom pad area, and the bottom metal surface treatment layer covers the opening area of the backside solder mask layer.

[0018] In this embodiment, by reasonably setting the bottom vias, the bottom pad area and the bottom metal surface treatment layer, the performance and reliability of the circuit are significantly optimized. The bottom vias are connected to the backside metal wiring layer, ensuring the stable transmission of electrical signals and avoiding signal interference or failure. The bottom pad area provides a reliable soldering surface, ensuring the firmness of the soldering connection and reducing the risk of poor soldering. At the same time, the bottom metal surface treatment layer effectively prevents short circuits and corrosion problems during the soldering process and plays a role in shielding external electromagnetic interference, enhancing the anti-interference ability of the circuit.

[0019] In one embodiment, on the first surface of the glass substrate core, a ring-shaped glass bonding area is formed near the periphery of the front-side redistribution layer, and the front-side redistribution layer is not provided in the ring-shaped glass bonding area.

[0020] In this embodiment, the ring-shaped glass bonding area formed on the first surface of the glass substrate core is located near the periphery of the front-side redistribution layer and does not cover this layer. This design significantly enhances the mechanical stability of the package structure. By dispersing the externally applied stress and thermal stress, the risk of cracking or deformation is reduced. The ring-shaped glass bonding area effectively protects the front-side redistribution layer, preventing external substances such as moisture, oxygen, and contaminants from entering, and ensuring the long-term stability of the electronic components. In addition, due to the good electrical insulation performance of the glass material, electrical interference is avoided and the stability of the circuit is maintained.

[0021] In one embodiment, when a capacitor structure is configured in the front-side redistribution layer, the lower electrode plate of the capacitor structure reuses the intermediate metal wiring layer.

[0022] In this embodiment, by reusing the intermediate metal wiring layer as the lower electrode plate of the capacitor structure, not only is space effectively saved and the integration degree improved, but also the electrical performance of the capacitor is optimized. It can directly connect the capacitor to the metal wiring in the circuit, improving the response speed and processing efficiency of the capacitor, especially in high-frequency applications. In addition, the manufacturing process is simplified, the cost is reduced, the number of wiring layers is reduced, and the production efficiency is improved. The reuse design also enhances the reliability and stability of the capacitor structure, reduces the risks brought by the physical number of layers, and improves the stability of the electrical performance.

[0023] In a second aspect, an embodiment of the present application provides a packaging architecture, which includes: The glass-based three-dimensional interconnection structure as described above; A printed circuit board, which is electrically connected to the glass-based three-dimensional interconnection structure through the bottom pad area of the glass-based three-dimensional interconnection structure; A semiconductor die, which is electrically connected to the glass-based three-dimensional interconnection structure through the chip flip-chip bonding area of the glass-based three-dimensional interconnection structure; A glass shielding cover, the bottom end of which is connected to the annular glass bonding area of the glass-based three-dimensional interconnection structure to form a sealed microcavity; wherein, a composite shielding layer is also deposited on the inner wall of the glass shielding cover.

[0024] In this embodiment, with the glass-based three-dimensional interconnection structure as the core component, it provides high-density electrical interconnection and passive device integration capabilities, significantly improving signal integrity and system integration. The printed circuit board is electrically connected to the glass-based three-dimensional interconnection structure through the bottom pad area, realizing efficient connection with the external circuit and reducing the assembly complexity at the same time. The semiconductor die is electrically connected to the glass-based three-dimensional interconnection structure through the chip flip-chip bonding area, achieving high-density integration, shortening the interconnection path, and optimizing the thermal management performance. The glass shielding cover is connected to the annular glass bonding area to form a sealed microcavity, providing excellent airtightness and electromagnetic shielding performance. The composite shielding layer deposited on its inner wall further suppresses electromagnetic interference and internal crosstalk. Overall, through the synergistic effect of high-density interconnection, airtight packaging, and electromagnetic shielding technologies, this design realizes system-level high integration, high-performance signal transmission, and high reliability, while reducing material costs and manufacturing costs, providing strong technical support for high-frequency applications such as communication. Description of the Drawings

[0025] To more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0026] Figure 1 Schematic diagram of a glass-based three-dimensional interconnection structure provided by an embodiment of the present application; Figure 2 Schematic diagram of a packaging architecture provided by an embodiment of the present application.

[0027] Description of reference numerals 1 - Glass plate core, 11 - Glass through-hole, 2 - Front-side redistribution layer, 21 - Front-side intermediate layer, 211 - Front-side metal interconnection structure, 212 - Front-side metal wiring layer, 22 - Front-side solder mask layer, 3 - Back-side redistribution layer, 31 - Back-side intermediate layer, 311 - Back-side metal interconnection structure, 312 - Back-side metal wiring layer, 32 - Back-side solder mask layer, 4 - Base metal interconnection layer, 5 - Intermediate metal wiring layer, 6 - Chip flip-chip bonding area, 7 - Top metal surface treatment layer, 8 - Bottom pad area, 9 - Bottom metal surface treatment layer, 10 - Ring-shaped glass bonding area, 20 - Capacitor structure. Specific embodiments

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present application.

[0029] Driven by the requirements of 5G millimeter-wave communication and sub-6GHz multi-band, the radio frequency front-end module needs to meet strict requirements such as high frequency, high integration, miniaturization, and low power consumption. The current mainstream system-in-package (SiP) solution uses a resin-based coreless laminate substrate and realizes module design through two-dimensional planar integration: passive components such as resistors, capacitors, and inductors, surface acoustic wave / bulk acoustic wave filters (SAW / BAW), and multi-mode semiconductor chiplets are arranged on the substrate surface through surface mount technology (SMT), and then the encapsulation is completed through plastic encapsulation. However, this traditional solution has the following systematic defects: 1. Insufficient vertical integration density: Limited by two-dimensional layout, it is difficult to break through the bottleneck of the module thickness of 0.7 mm, unable to meet the requirements of mobile terminals for ultra-thinness and miniaturization. At the same time, the insufficient multi-layer stacking ability leads to limited function expansion and it is difficult to achieve three-dimensional heterogeneous integration.

[0030] 2. Low integration efficiency of acoustic filters: SAW / BAW filters need to be pre-packaged in a cavity-type chip-scale package (CSP) and then integrated into the module through secondary assembly. This process increases the overall height of the module by 15%-20%, and the physical distance between the transmit (TX) and receive (RX) channels is insufficient, which is prone to intermodulation distortion (IMD), seriously affecting the signal quality.

[0031] 3. Weak thermal management ability: The resin substrate has a low thermal conductivity (usually <0.3 W / m·K), making it difficult to effectively conduct the heat generated by power devices (such as PAs), resulting in local heat accumulation effect and reducing the system reliability.

[0032] In addition, the currently widely used coreless multi-layer laminated substrate is composed of a prepreg insulating layer, a copper interconnect layer, and a solder mask green oil. Its core material, prepreg, is a composite of semi-solid resin and glass fiber reinforced material. However, due to material characteristics and process limitations, the following key problems exist in this substrate: 1. Poor mechanical stability: The lack of a rigid support layer makes the substrate prone to warping, affecting the packaging yield and long-term reliability.

[0033] 2. Limited interconnect accuracy and integration ability: The minimum line width / line pitch only reaches 25 / 25 μm, making it difficult to support the fine wiring required for high-frequency signal transmission; the dielectric constant of the dielectric material fluctuates greatly (Dk ± 5%), and there is a lack of thin film deposition process, unable to integrate embedded capacitors (MIM) or thin film resistors (TFR), resulting in passive devices relying on external SMT components, occupying additional area.

[0034] 3. Thermal stress and electrical performance bottlenecks: The significant difference in the coefficient of thermal expansion (CTE) between the resin substrate and the semiconductor chip is prone to the risk of interface delamination; the two-dimensional layout limits the quality factor (Q value) of passive devices such as inductors, resulting in increased matching loss and deteriorated high-frequency performance.

[0035] To solve the above technical problems, a glass-based three-dimensional interconnect structure is provided in this embodiment. Figure 1 As shown in the schematic diagram of a glass-based three-dimensional interconnect structure provided by an embodiment of the present application, Figure 1 as shown, this structure includes: A glass plate core 1, with a first surface and a second surface on opposite sides of the glass plate core 1; A front-side redistribution layer 2 provided on the first surface and a back-side redistribution layer 3 provided on the second surface; A glass through-hole 11 runs through the glass plate core 1, and a base metal interconnection layer 4 is filled in the glass through-hole. The base metal interconnection layer 4 extends to the first surface and is electrically connected to the front-side redistribution layer 2; the base metal interconnection layer 4 extends to the second surface and is electrically connected to the back-side redistribution layer 3.

[0036] Specifically, compared with a resin substrate, the glass plate core 1 has higher thermal conductivity and better thermal stability. This means that using the glass plate core 1 as the core carrier helps to effectively dissipate heat, avoid local heat accumulation, and can better match the thermal expansion characteristics of semiconductor chips, reduce the interface delamination problem caused by thermal stress, and improve thermal management performance and reliability. Preferably, the glass plate core 1 can adopt 200-μm-thick borosilicate glass.

[0037] A glass through-hole 11 with a tapered structure having a diameter of 55 μm is formed on the glass plate core 1 through the TGV technology (through-glass via technology) to achieve vertical interconnection. Here, the diameter refers to the diameter at the maximum position of the tapered structure. First, the glass plate core 1 is modified by laser-induced etching, and then a titanium / copper thin film is deposited by magnetron sputtering technology. The titanium layer enhances adhesion, and the copper layer serves as a conductive layer. Then, copper pillars (void ratio < 2%) are electrochemically deposited to complete the construction of the base metal interconnection layer 4. In addition, the tapered glass through-hole 11 helps to achieve better coverage of the sputtering seed layer during the magnetron sputtering process. The vertical interconnection structure enables the glass plate core 1 to arrange redistribution layers on both the front and back sides, meeting the requirements of miniaturization and ultra-thinness.

[0038] The glass plate core 1 realizes vertical interconnection through the TGV technology, and can directly integrate an acoustic filter (such as a SAW / BAW device) inside the glass plate core 1 without using a cavity-type CSP package, thereby reducing the module height, optimizing the device layout, reducing intermodulation distortion, improving the module performance, and solving the bottleneck problem in the integration of acoustic filters.

[0039] The glass plate core 1 also has high rigidity, which can effectively avoid the warping problem caused by the lack of a rigid support layer. Its low dielectric constant fluctuation (Dk ± 5%) helps to improve the integration ability, support the construction of embedded capacitors (MIM) and resistors (TFR), and achieve inductors with higher Q values through optimized wiring design, reduce the matching loss, and improve the overall electrical performance.

[0040] A glass-based three-dimensional interconnection structure provided by this embodiment can effectively improve the circuit integration by respectively arranging redistribution layers on the front and back surfaces of a glass plate core and realizing electrical interconnection through glass vias, and achieve higher-density wiring within a limited space. This double-sided wiring structure not only enhances the signal processing ability of the package but also improves the thermal management efficiency, reduces the influence of thermal stress on devices, and ensures a stable working environment. In addition, the multi-layer design of the back redistribution layer improves the electrical interconnection performance, reduces losses and interference in signal transmission, and is particularly suitable for high-frequency and high-power application requirements. At the same time, this design improves the reliability and scalability of the package, enabling it to provide excellent electrical performance, thermal stability, and flexibility in different application scenarios.

[0041] In one embodiment, the upper surface of the first surface and the lower surface of the second surface include an intermediate pattern medium of a wiring pattern, and an intermediate metal wiring is filled in the intermediate pattern medium to form an intermediate metal wiring layer 5, and the intermediate metal wiring layer 5 is connected to the base metal interconnection layer 4.

[0042] Specifically, the intermediate pattern medium is located on the upper and lower surfaces of the first and second surfaces of the glass plate core 1. These dielectric layers are used to define the wiring pattern and provide support and insulation for the metal wiring. The intermediate metal wiring layer 5 is the metal wiring filled in the intermediate pattern medium and is used to achieve electrical interconnection. These intermediate metal wiring layers 5 are connected to the base metal interconnection layer 4, providing a shorter signal transmission path, reducing signal transmission loss and delay. At the same time, the multi-layer wiring structure can better isolate different signal paths, reduce crosstalk, and ensure the effective transmission of signals and power. In this embodiment, the improved semi-additive process (mSAP) is used to realize fine copper lines with a line width / spacing of 5 / 5 μm on the glass plate core 1, that is, to form the intermediate metal wiring layer 5, which can significantly improve the interconnection accuracy and meet the requirements of high-density wiring.

[0043] In addition, the intermediate metal wiring layer 5 can be used to integrate passive components (such as capacitors, inductors, resistors, etc.). These passive components can be directly embedded in the intermediate metal wiring layer 5, reducing the need for additional space.

[0044] In this embodiment, by adopting the design of the intermediate metal wiring layer, the electrical interconnection performance and signal transmission efficiency can be significantly improved. This wiring layer connects the base metal interconnection layer, effectively realizes the electrical connection between different layers, optimizes signal conduction, reduces losses, and decreases interference. At the same time, this design rationally utilizes the multi-layer structure, improves the wiring density and space utilization, and meets the requirements of miniaturized packaging. In addition, the excellent electrical conductivity and thermal conductivity of the metal wiring not only improve the electrical performance but also enhance the thermal management ability of the system, avoid damage to the device caused by overheating, and enhance the overall stability and reliability. Through this flexible layout, the intermediate metal wiring layer also provides good scalability for the packaging, meeting the requirements of different application scenarios.

[0045] In one embodiment, the front-side redistribution layer 2 includes at least one front-side intermediate layer 21 and a front-side solder mask layer 22 which are stacked, and the front-side intermediate layer 21 is closer to the first surface of the glass substrate core 1 than the front-side solder mask layer 22; the back-side redistribution layer 3 includes at least one back-side intermediate layer 31 and a back-side solder mask layer 32 which are stacked, and the back-side intermediate layer 31 is closer to the second surface of the glass substrate core 1 than the back-side solder mask layer 32.

[0046] Specifically, by designing the front-side redistribution layer 2 and the back-side redistribution layer 3 as a hierarchical structure, more wiring paths can be realized within a limited space. This design allows for the implementation of complex wiring networks on the front side and the back side respectively, thus significantly increasing the wiring density. Secondly, the hierarchical design can better isolate different signal paths and reduce interference between signals. At the same time, by optimizing the wiring paths, signal transmission losses and delays can be reduced. The multi-layer wiring structure provides more heat dissipation paths, which helps to improve the heat dissipation performance of the packaging.

[0047] It should be noted here that the different colors in the front-side intermediate layer 21, the front-side solder mask layer 22, the back-side intermediate layer 31, and the back-side solder mask layer 32 only represent different layers. Taking the Figure 1 structure as an example, the front-side intermediate layer 21 has two layers, the front-side solder mask layer 22 has one layer, the back-side intermediate layer 31 has three layers, the back-side solder mask layer 32 has one layer, and the materials of the front-side intermediate layer 21 and the back-side intermediate layer 31 are preferably polyimide (PI), the material of the front-side solder mask layer 22 is preferably polyimide (PI) or green oil, with a thickness of 5 μm; the material of the back-side solder mask layer 32 is preferably green oil, with a thickness of 15 μm.

[0048] In this embodiment, the hierarchical design of the front and back redistribution layers effectively improves the wiring density and space utilization, reduces signal interference, and optimizes signal transmission performance. By dividing the front redistribution layer into a front intermediate layer and a front solder mask layer, and the back redistribution layer into a back intermediate layer and a back solder mask layer, each layer works independently, avoiding mutual interference, thus improving the integration of wiring. The hierarchical structure can not only reduce signal crosstalk and loss, but also optimize signal transmission quality and enhance electrical performance. In addition, this design helps to improve the heat dissipation performance. Multiple wiring layers provide more paths for heat conduction, enhancing the thermal management ability and avoiding overheating problems. Finally, the hierarchical structure also enhances the flexibility and scalability of the design, meets the changes in high integration and complex electrical requirements, and provides higher reliability and performance.

[0049] In one embodiment, a corresponding front metal interconnect structure 211 is embedded in each layer of the front intermediate layer 21; the upper surface of each layer of the front intermediate layer 21 includes a front pattern medium of a wiring pattern, and the front pattern medium is filled with front metal wiring to form a front metal wiring layer 212, and the front metal wiring layer 212 is electrically connected to the front metal interconnect structure 211.

[0050] Specifically, the front metal interconnect structure 211 is embedded in the front intermediate layer 21 and is used to achieve vertical interconnection between different layers. Vertical interconnection is an essential part of three-dimensional circuit design. It can effectively connect different layers in a multi-layer circuit structure to form a continuous current path. In this design, the front metal interconnect structure 211 plays the role of electrical connection across multiple wiring layers and is one of the core components for achieving high-density wiring. The upper surface of each layer of the front intermediate layer 21 forms a front pattern medium, and the front pattern medium is filled with front metal wiring to form a front metal wiring layer 212. This front metal wiring layer 212 forms a wiring pattern within the same layer to achieve horizontal interconnection. The front metal wiring layer 212 can ensure the horizontal transmission of signals on the circuit board and provides extremely fine lines (such as a line width and pitch of 5 / 5μm), which is crucial for achieving high-density wiring. The smaller line width and pitch enable the wiring to adapt to more compact design requirements, especially in high-frequency and high-speed circuits, where fine wiring can reduce signal attenuation and improve signal transmission speed.

[0051] That is to say, the combination of the front metal interconnect structure 211 and the front metal wiring layer 212 realizes three-dimensional interconnection, which means that signals can not only be transmitted horizontally within the same layer, but also cross different layers through vertical interconnection. The advantage of three-dimensional interconnection is that it can significantly improve the density and flexibility of circuit design. By expanding the wiring from two dimensions to three dimensions, the number of wiring paths per unit area can be significantly increased, thus meeting the requirements of modern electronic devices for higher integration.

[0052] In this embodiment, by embedding a front metal interconnection structure in the middle layer of each front layer and electrically connecting it to the front metal wiring layer, the wiring density and integration degree are significantly improved. Through this optimization, the signal transmission path of the circuit is reasonably planned, reducing signal delay, crosstalk and attenuation, thereby improving the electrical performance. The use of the front metal interconnection structure realizes a three-dimensional interconnection architecture, makes full use of space, enhances the efficiency of vertical and horizontal interconnections, and meets the requirements of high-integration circuits. In addition, this design improves the flexibility of the manufacturing process, provides more space for wiring pattern optimization, thereby achieving higher wiring accuracy and flexibility. At the same time, signal interference is effectively reduced, and the signal transmission quality is improved, ensuring efficient circuit performance.

[0053] In one embodiment, a plurality of top vias are provided on the front solder mask layer 22, and the top vias are connected to the front metal wiring layer 212; a chip flip-chip bonding region 6 is formed on the upper surface of the front metal wiring layer 212 and corresponding to the top vias; a top metal surface treatment layer 7 is provided in the chip flip-chip bonding region 6, and the top metal surface treatment layer 7 covers the opening region of the front solder mask layer 22.

[0054] Specifically, the front solder mask layer 22 covers the surface of the copper circuit, forming a protective film to prevent the copper circuit from oxidizing due to exposure to air, and at the same time can resist the erosion of moisture, dust and chemical substances. The opening region of the front solder mask layer 22 can define the welding region, ensuring that the solder only flows to the predetermined welding points, which can improve the accuracy and quality of welding. Through these vias, current can be directly transmitted from the top layer to the wiring layer, so that the electrical connection between the die and the wiring layer can be realized, and a stable electrical path is formed. This structure also helps to reduce the impedance of signal transmission and improve the electrical performance. The chip flip-chip bonding region 6 is located on the upper surface of the front metal wiring layer 212 and corresponds to the top vias. The purpose is to implement the flip-chip technology, that is, by inverting the semiconductor die and directly bonding it to the front metal wiring layer 212, the integration degree is further improved, and the signal transmission path length is reduced. This structure can significantly reduce signal delay, reduce signal loss, and improve the overall performance.

[0055] The top metal surface treatment layer 7 covers the opening area of the positive solder mask layer 22 and mainly plays a protective role. Its function is to prevent damage to the positive metal wiring layer 212 from the external environment (such as moisture, chemical substances, etc.). Preferably, the top metal surface treatment layer 7 is nickel-palladium-gold. Among them, the nickel layer in the nickel-palladium-gold serves as the bottom layer, mainly playing a role in blocking the diffusion of copper and enhancing the adhesion of the plating layer. The diffusion of copper may lead to a decrease in welding performance and reliability problems, and the nickel layer can effectively prevent this phenomenon. The palladium layer has high hardness and good chemical stability, which can significantly improve the surface wear resistance and corrosion resistance. In addition, the palladium layer can prevent the "black nickel" phenomenon (i.e., the nickel layer is corroded during the welding process). The gold layer has excellent electrical conductivity and oxidation resistance and is an ideal material for welding. The gold layer can also prevent the oxidation of copper and nickel, ensuring the reliability of the welding point.

[0056] In this embodiment, through the reasonable setting of the wiring layer, flip-chip bonding technology, and solder mask layer protection, the signal transmission path is optimized, the integration degree is improved, and the electrical performance is enhanced. The setting of the top vias enables the signal to be directly transmitted from the top layer to the metal wiring layer, reducing the traditional vertical transmission path, thereby reducing signal delay and loss. At the same time, the metal surface treatment layer on the upper surface of the positive metal wiring layer effectively prevents the influence of the external environment, enhancing the stability and long-term reliability of the package. Through these designs, not only the performance and reliability of the package are improved, but also the process is simplified, the manufacturing cost is reduced, and the requirements for high-performance and high-reliability packaging are met.

[0057] In one embodiment, each of the back intermediate layers 31 is embedded with a corresponding back metal interconnect structure 311; a back pattern medium including a wiring pattern is provided between the back intermediate layer 31 and the back solder mask layer 32, and back metal wiring is filled in the back pattern medium to form a back metal wiring layer 312, and the back metal wiring layer 312 is electrically connected to the back metal interconnect structure 311; Wherein, the distance between the lower surface of the intermediate metal wiring layer located on the second surface and the upper surface of the back metal wiring is greater than or equal to 20 μm.

[0058] Specifically, the backside metal interconnect structure 311 is embedded in the backside intermediate layer 31 for realizing vertical interconnection between different layers. Vertical interconnection is an indispensable part of three-dimensional circuit design, which can effectively connect different layers in a multi-layer circuit structure to form a continuous current path. In this design, the backside metal interconnect structure 311 plays the role of electrical connection across multiple wiring layers and is one of the core components for realizing high-density wiring. A backside pattern dielectric is formed between the backside intermediate layer 31 and the backside solder mask layer 32, and the backside metal wiring is filled inside the backside pattern dielectric to form the backside metal wiring layer 312. This backside metal wiring layer 312 forms a wiring pattern within the same layer to realize horizontal interconnection. The backside metal wiring layer 312 can ensure the horizontal transmission of signals on the circuit board and provides extremely fine lines (such as a line width and pitch of 5 / 5μm), which is crucial for realizing high-density wiring. The smaller line width and pitch enable the wiring to adapt to more compact design requirements. Especially in high-frequency and high-speed circuits, fine wiring can reduce signal attenuation and improve signal transmission speed.

[0059] That is to say, the combination of the backside metal interconnect structure 311 and the backside metal wiring layer 312 realizes three-dimensional interconnection, which means that signals can not only be transmitted horizontally within the same layer but also cross different layers through vertical interconnection. The advantage of three-dimensional interconnection is that it can greatly improve the density and flexibility of circuit design. By expanding the wiring from two dimensions to three dimensions, the number of wiring paths per unit area can be significantly increased, thus meeting the requirements for higher integration of modern electronic devices. In addition, the shapes of the backside metal interconnect structure 311 and the frontside metal interconnect structure 211 are also conical structures, and the method adopted is to form a conical structure with a diameter of not less than 20μm by using the technology of lithography / electroplating / etching to realize vertical interconnection.

[0060] In this embodiment, by embedding the backside metal interconnect structure in the backside intermediate layer and filling the backside metal wiring layer in the backside pattern dielectric, the electrical connection and signal transmission are optimized to ensure that the electrical connection between layers is more stable and reliable. The backside pattern dielectric provides an effective electrical isolation function, preventing signal interference and enhancing the anti-interference ability of the overall circuit. The electrical connection between the backside metal wiring layer and the backside metal interconnect structure improves the signal transmission efficiency, reduces signal loss and delay, thereby improving the signal quality. This design also improves the circuit integration through a compact wiring structure, enhances the stability and reliability of the package, and meets the packaging requirements of high performance and high reliability.

[0061] In one embodiment, a plurality of bottom vias are provided on the back solder mask layer 32, and the bottom vias are connected to the back metal wiring layer 312; a bottom pad area 8 is formed on the lower surface of the back metal wiring layer 312 and corresponding to the bottom vias; a bottom metal surface treatment layer 9 is provided in the bottom pad area 8, and the bottom metal surface treatment layer 9 covers the opening area of the back solder mask layer 32.

[0062] Specifically, a plurality of bottom vias are provided on the back solder mask layer 32, and these vias are connected to the back metal wiring layer 312 to form a channel for electrical connection. Specifically, the bottom vias enable signals to be transmitted from the back solder mask layer 32 to the back metal wiring layer 312, thereby achieving electrical connection between layers. This design makes the signal transmission between the bottom layer and the upper layer more direct and stable. On the lower surface of the back metal wiring layer 312, a bottom pad area 8 is formed corresponding to the bottom vias. The bottom pad area 8 is a key area for electrical connection, which provides an interface for the package structure to connect to an external circuit (such as a PCB). Through the bottom pad area 8, the package structure can be electrically connected to the external circuit by means of soldering, etc., which is very important for high-density integrated circuit packaging and ensures stable communication between the external circuit and the internal circuit of the package.

[0063] In addition, a bottom metal surface treatment layer 9 is provided in the bottom pad area 8, and the bottom metal surface treatment layer 9 covers the opening area of the back solder mask layer 32. The purpose of this design is to protect the back metal wiring layer 312 from the influence of the external environment, such as moisture, oxidation, chemical corrosion, etc., and at the same time prevent unnecessary short circuits or soldering errors. The metal surface treatment layer isolates part of the metal wiring layer, ensuring that only the bottom pad area 8 can be soldered during the soldering process, thereby improving the accuracy and reliability of soldering. Preferably, the bottom metal surface treatment layer 9 is nickel-palladium-gold.

[0064] It should be noted here that both the top metal surface treatment layer 7 and the bottom metal surface treatment layer 9 use electroless nickel-palladium-gold (ENEPIG) surface treatment, with a minimum pad size of 60 μm and a minimum pad pitch of 150 μm.

[0065] In this embodiment, by reasonably setting the bottom vias, the bottom pad area, and the bottom metal surface treatment layer, the performance and reliability of the circuit are significantly optimized. The bottom vias are connected to the back metal wiring layer, ensuring stable transmission of electrical signals and avoiding signal interference or failure. The bottom pad area provides a reliable soldering surface, ensuring the firmness of the soldering connection and reducing the risk of poor soldering. At the same time, the bottom metal surface treatment layer effectively prevents short circuits and corrosion problems during the soldering process and plays a role in shielding external electromagnetic interference, improving the anti-interference ability of the circuit.

[0066] In one embodiment, on the first surface of the glass plate core 1, an annular glass bonding region 10 is formed near the periphery of the front-side rewiring layer 2, and the front-side rewiring layer 2 is not provided in the annular glass bonding region 10.

[0067] Specifically, one of the main functions of the annular glass bonding region 10 is to isolate the influence of the external environment on the internal circuit. The ring width is 160 μm, and the surface roughness of the annular glass bonding region 10 is less than 5 nm. Since circuit packaging usually involves tiny integrated circuits and high-density wiring, these components are very sensitive to environmental factors (such as humidity, oxygen, chemicals, etc.). The glass plate core 1, as the substrate of the package, usually can play a certain protective role, while the design of the annular glass bonding region 10 ensures the sealing of the package structure by strengthening the tight connection between the glass plate core 1 and other components (such as a glass shield), forming a sealed microcavity. This sealed microcavity can effectively block water vapor, oxygen, and external pollutants in the air, preventing them from corroding or aging the internal circuit. In particular, moisture and oxygen have a great impact on electronic components, which can cause oxidation of the circuit, resulting in a decline or failure of the circuit performance. The annular glass bonding region 10 ensures the long-term stable operation of the internal circuit of the package by effectively isolating these external factors.

[0068] The annular glass bonding region 10 is located at the periphery of the glass plate core 1, providing additional mechanical support and enhancing the stability of the entire package structure. Especially in the packaging of high-density integrated circuits, the tiny size and complex layout of the components will lead to the fragility of the overall package structure. The setting of the annular glass bonding region 10 can effectively disperse external mechanical stress, avoiding excessive pressure or impact on local areas, thereby reducing the risk of cracking or delamination of the glass plate core 1.

[0069] For example, during the packaging process, temperature fluctuations or mechanical shocks may occur, resulting in local thermal stress or physical stress on the glass plate core 1. The presence of the annular glass bonding region 10 can play a buffering role when these stresses occur, dispersing and homogenizing the stresses, thereby reducing the possibility of cracking, delamination, or permanent deformation of the glass plate core 1 due to stress concentration.

[0070] Temperature fluctuations are a common phenomenon during the packaging process. Especially in high-power electronic components, temperature changes may cause the expansion and contraction of the packaging materials. The annular glass bonding region 10 plays a role in dispersing thermal stress in the design. When the temperature inside or outside the package changes, the expansion or contraction of the glass plate core 1 may affect the entire package structure. The presence of the annular glass bonding region 10 can disperse thermal stress through bonding with the glass plate core 1, thereby reducing the damaging effect of local thermal stress on the glass plate core 1. It effectively reduces the structural damage caused by uneven thermal expansion through tight connection with other packaging components.

[0071] In this embodiment, an annular glass bonding region formed on the first surface of the glass substrate core is located near the periphery of the front-side redistribution layer and does not cover this layer. This design significantly enhances the mechanical stability of the packaging structure. By dispersing externally applied stress and thermal stress, the risk of cracking or deformation is reduced. The annular glass bonding region effectively protects the front-side redistribution layer, preventing external substances such as moisture, oxygen, and contaminants from entering, ensuring the long-term stability of the electronic components. In addition, due to the good electrical insulation performance of the glass material, electrical interference is avoided, maintaining the stability of the circuit.

[0072] In one embodiment, when a capacitor structure 20 is configured in the front-side redistribution layer 2, the lower electrode plate of the capacitor structure 20 reuses the intermediate metal wiring layer 5.

[0073] Specifically, the capacitor structure 20 consists of three layers, namely a lower electrode plate (M1), an isolation layer (SN), and an upper electrode plate (MC). Among them, the lower electrode plate (M1) reuses the intermediate metal wiring layer 5, that is, the existing redistribution layer is used as the lower electrode plate of the capacitor. The isolation layer (SN) is a 150-nm-thick SiNx (silicon nitride) dielectric film deposited by the PE-CVD (plasma-enhanced chemical vapor deposition) process. The upper electrode plate (MC) is a 0.2-μm-thick copper-gold film sputtered by the PVD (physical vapor deposition) process. By reusing the intermediate metal wiring layer 5 as the lower electrode plate of the capacitor structure 20, the need for additional wiring is reduced, saving space.

[0074] In this embodiment, by reusing the intermediate metal wiring layer as the lower electrode plate of the capacitor structure, not only is space effectively saved and the integration density improved, but also the electrical performance of the capacitor is optimized. It can directly connect the capacitor to the metal wiring in the circuit, improving the response speed and processing efficiency of the capacitor, especially in high-frequency applications. In addition, the manufacturing process is simplified, the cost is reduced, the number of wiring layers is reduced, and the production efficiency is improved. The reuse design also enhances the reliability and stability of the capacitor structure, reduces the risk brought by the physical number of layers, and improves the stability of the electrical performance.

[0075] Figure 2 The figure is a schematic diagram of a packaging architecture provided by an embodiment of the present application, as Figure 2 shown, this packaging architecture includes: the glass-based three-dimensional interconnection structure described above; A printed circuit board, which is electrically connected to the glass-based three-dimensional interconnection structure through the bottom pad region of the glass-based three-dimensional interconnection structure; A semiconductor die, which is electrically connected to the glass-based three-dimensional interconnection structure through the chip flip-chip bonding region of the glass-based three-dimensional interconnection structure; A glass shielding cover, the bottom end of the glass shielding cover is connected to the annular glass bonding area of the glass-based three-dimensional interconnection structure to form a sealed microcavity; wherein, a composite shielding layer is also deposited on the inner wall of the glass shielding cover.

[0076] Specifically, the glass-based three-dimensional interconnection structure, as the core component, provides high-density electrical interconnection and passive device integration capabilities. The printed circuit board (PCB) is electrically connected to the glass-based three-dimensional interconnection structure through the bottom pad area to achieve connection with the external circuit. The semiconductor die is electrically connected to the glass-based three-dimensional interconnection structure through the chip flip-chip bonding area to achieve high-density integration. The glass shielding cover is connected to the annular glass bonding area to form a sealed microcavity, providing airtightness and electromagnetic shielding.

[0077] In this embodiment, the glass-based three-dimensional interconnection structure is used as the core component, providing high-density electrical interconnection and passive device integration capabilities, significantly improving signal integrity and system integration. The printed circuit board is electrically connected to the glass-based three-dimensional interconnection structure through the bottom pad area, achieving efficient connection with the external circuit and reducing assembly complexity at the same time. The semiconductor die is electrically connected to the glass-based three-dimensional interconnection structure through the chip flip-chip bonding area, achieving high-density integration, shortening the interconnection path, and optimizing the thermal management performance. The glass shielding cover is connected to the annular glass bonding area to form a sealed microcavity, providing excellent airtightness and electromagnetic shielding performance. The composite shielding layer deposited on its inner wall further suppresses electromagnetic interference and internal crosstalk. Overall, this design realizes high system-level integration, high-performance signal transmission, and high reliability through the synergistic effect of high-density interconnection, airtight packaging, and electromagnetic shielding technologies, while reducing material costs and manufacturing costs, providing strong technical support for high-frequency applications such as communication.

[0078] The specific implementation of the present invention will be described below in conjunction with a specific application. Using a 200-μm-thick borosilicate glass as the substrate, a hierarchical functional integration design is adopted. Through laser-induced etching (LIDE), conical vias with a diameter of 55 μm are formed, and a dense copper pillar (void ratio < 2%) is filled by combining magnetron sputtering of titanium / copper seed layers and electrochemical deposition (ECD) process to form a base metal interconnection layer. Using the improved semi-additive process (mSAP), copper lines with a line width / spacing of 5 / 5 μm are formed on the polyimide (PI) dielectric layers on both sides of the glass plate core. The MIM capacitor integration consists of an M1-SN-MC sandwich structure: the lower electrode plate (M1) reuses the intermediate metal wiring layer; the isolation layer (SN) prepares a 150-nm-thick SiNx dielectric thin film by plasma-enhanced chemical vapor deposition (PE-CVD); the upper electrode plate (MC) sputters a 0.2-μm-thick copper-gold composite thin film by physical vapor deposition (PVD). The chip flip-chip bonding area and the bottom pad area both adopt the electroless nickel-palladium-gold (ENEPIG) surface treatment process, with a minimum pad size of 60 μm and a minimum pad pitch of 150 μm. The annular area (ring width 160 μm) on the front side of the glass plate core is bonded to the substrate by exposing the glass surface (roughness < 5 nm) to form a sealed structure. There is no polyimide (PI) dielectric and circuit in this area to ensure electromagnetic shielding and airtightness. The material is polyimide (PI) with a thickness of 5 μm, covering the front metal wiring layer; the material is solder mask with a thickness of 15 μm, covering the back metal wiring layer.

[0079] The above embodiments can achieve: System-level integration optimization: Eliminate the need for traditional SMT soldering processes; reduce the bill of materials (BOM) cost by 22% - 35%; reduce the complexity of the supply chain hierarchy.

[0080] Enhanced electromagnetic compatibility: Based on the high dielectric constant stability (Dk = 5.2 ± 0.1 @ 10 GHz) and ultra-fine line width / line pitch capability (5 / 5 μm) of the glass plate core. Adopt a multi-physical domain isolation layout strategy, and extend the spatial distance between the LNA receiving chain and the PA transmitting chain to more than 800 μm through a three-dimensional shielding wall structure (Shielding Wall). The measured crosstalk suppression is improved by > 15 dB (from -32 dB of the traditional solution to -47 dB @ 3.5 GHz).

[0081] Breakthrough in energy efficiency performance: Adopt the collaborative design of vertical spiral inductors (VLSI) and differential baluns (Balun); achieve an insertion loss ≤ 0.25 dB in the full frequency band of 2.5 - 5 GHz (the traditional solution ≥ 0.45 dB). The power added efficiency (PAE) is relatively increased by 8.5%; the maximum linear output power (Pout) reaches 34 dBm @ ACLR - 36 dBc.

[0082] High-reliability packaging architecture: A hermetic microcavity is formed by using the wafer-level glass-to-glass direct bonding process. The airtightness meets the MIL-STD-883K standard (helium leak rate < 1×10 -8 atm·cc / s). Combining the built-in sub-cavity shielding technology in the glass shield, a continuous composite shielding layer (including but not limited to Cu / Ni / Au composite structure, stainless steel / Cu / stainless steel, nano silver, with a thickness of 3-5μm) is constructed on the inner surface of the glass shield by using the physical vapor deposition (PVD) process. The electromagnetic shielding effectiveness (SE) across the cavity is achieved to be > 60 dB@6 GHz.

[0083] It should also be noted that the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or elements inherent to such process, method, commodity or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, commodity or device including the said element.

[0084] The above are only the embodiments of the present application and are not used to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.

[0085] Although the embodiments of the present application are described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A glass-based three-dimensional interconnected structure, characterized in that: include: A glass plate core, wherein two opposite sides of the glass plate core are respectively a first surface and a second surface; A front redistribution layer disposed on the first surface and a back redistribution layer disposed on the second surface; A through-glass hole runs through the glass core, wherein the through-glass hole is filled with a base metal interconnection layer; the base metal interconnection layer extends to the first surface and is electrically connected to the front redistribution layer; the base metal interconnection layer extends to the second surface and is electrically connected to the back redistribution layer.

2. The glass-based three-dimensional interconnected structure according to claim 1, characterized in that: The upper surface of the first surface and the lower surface of the second surface include an intermediate pattern medium of a wiring pattern, wherein the intermediate pattern medium is filled with intermediate metal wiring to form an intermediate metal wiring layer, and the intermediate metal wiring layer is connected to the base metal interconnection layer.

3. The glass-based three-dimensional interconnected structure according to claim 1, characterized in that: The front redistribution layer comprises at least one front intermediate layer and a front solder resist layer which are stacked, and the front intermediate layer is closer to the first surface of the glass plate core than the front solder resist layer; The back side redistribution layer includes at least one back side intermediate layer and a back side solder resist layer which are stacked. The back side intermediate layer is closer to the second surface of the glass core than the back side solder resist layer.

4. The glass-based three-dimensional interconnected structure according to claim 3, characterized in that: Each of the front intermediate layers is embedded with a corresponding front metal interconnection structure; The upper surface of each front intermediate layer includes a front pattern medium of a wiring pattern, and the front pattern medium is filled with front metal wiring to form a front metal wiring layer, and the front metal wiring layer is electrically connected to the front metal interconnection structure.

5. The glass-based three-dimensional interconnected structure according to claim 4, characterized in that: The front solder resist layer is provided with a plurality of top-layer through holes, and the top-layer through holes are connected to the front metal wiring layer; A chip flip-chip bonding area is formed on the upper surface of the front metal wiring layer and in an area corresponding to the top through hole; a top metal surface treatment layer is arranged in the chip flip-chip bonding area, and the top metal surface treatment layer covers the opening area of ​​the front solder resist layer.

6. The glass-based three-dimensional interconnected structure according to claim 3, characterized in that: Each back intermediate layer is embedded with a corresponding back metal interconnection structure; A back pattern medium including a wiring pattern is included between the back intermediate layer and the back solder resist layer, the back pattern medium is filled with back metal wiring to form a back metal wiring layer, and the back metal wiring layer is electrically connected to the back metal interconnect structure; Wherein, a distance between a lower surface of the intermediate metal wiring layer located on the second surface and an upper surface of the back metal wiring is greater than or equal to 20 μm.

7. The glass-based three-dimensional interconnected structure according to claim 6, characterized in that: The back solder resist layer is provided with a plurality of bottom through holes, and the bottom through holes are connected to the back metal wiring layer; A bottom pad area is formed on the lower surface of the back metal wiring layer and in an area corresponding to the bottom through hole; A bottom metal surface treatment layer is arranged in the bottom pad area, and the bottom metal surface treatment layer covers the opening area of ​​the back solder resist layer.

8. The glass-based three-dimensional interconnected structure according to claim 1, characterized in that: An annular glass bonding area is formed on the first surface of the glass core near the periphery of the front redistribution layer, and the front redistribution layer is not provided in the annular glass bonding area.

9. The glass-based three-dimensional interconnected structure according to claim 2, characterized in that: When a capacitor structure is configured in the front redistribution layer, the lower electrode plate of the capacitor structure reuses the intermediate metal wiring layer.

10. A packaging architecture, characterized in that: The packaging architecture includes: The glass-based three-dimensional interconnected structure according to any one of claims 1 to 9; a printed circuit board, the printed circuit board being electrically connected to the glass-based three-dimensional interconnect structure through a bottom pad area of ​​the glass-based three-dimensional interconnect structure; Semiconductor crystal grains, wherein the semiconductor crystal grains are electrically connected to the glass-based three-dimensional interconnect structure through a chip flip-chip bonding region of the glass-based three-dimensional interconnect structure; A glass shielding cover, the bottom end of which is connected to the annular glass bonding area of ​​the glass-based three-dimensional interconnected structure to form a closed microcavity; wherein a composite shielding layer is also deposited on the inner wall of the glass shielding cover.

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