Thin film transistor and preparation method thereof, display panel and display device

Abstract

The invention discloses a thin film transistor and a preparation method thereof, a display panel and a display device. The thin film transistor comprises a substrate; the active layer is located on one side of the substrate and comprises a channel region, a source electrode contact region and a drain electrode contact region in the direction parallel to the substrate, and the source electrode contact region and the drain electrode contact region are located on the two sides of the channel region; the source electrode at least comprises a first source electrode branch part, and Schottky contact is formed between a part of the first source electrode branch part and the source electrode contact region; the drain electrode is in contact with the drain electrode contact region; and the grid electrode is located on one side of the substrate, part of the first source electrode branch exists in the direction perpendicular to the substrate, and part of the source electrode contact area is overlapped with the grid electrode. Part of the first source subsection and the active layer form Schottky contact, free flow of carriers is inhibited, the current stability of the thin film transistor in a saturation region is improved, and the power consumption of the thin film transistor is reduced.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a thin film transistor and a manufacturing method thereof, a display panel and a display device. Background Art

[0002] Display panels generally use thin film transistors made of amorphous silicon. With the development of display panel technology, higher and higher requirements are placed on the performance of thin film transistors. How to improve the stability of thin film transistors has become an important factor affecting the performance of display panels. Summary of the invention

[0003] The present invention provides a thin film transistor and a method for manufacturing the same, a display panel and a display device, so as to improve the current stability in a saturation region and reduce the power consumption of the thin film transistor.

[0004] In a first aspect, the present invention provides a thin film transistor, comprising:

[0005] substrate;

[0006] An active layer, located on one side of the substrate, along a direction parallel to the substrate, the active layer comprising a channel region and a source contact region and a drain contact region located on both sides of the channel region;

[0007] A source electrode, the source electrode at least comprising a first source electrode portion, a portion of the first source electrode portion forming a Schottky contact with the source contact region;

[0008] a drain electrode, the drain electrode being in contact with the drain contact region;

[0009] The gate is located at one side of the substrate, and along a direction perpendicular to the substrate, part of the first source portion and part of the source contact region overlap with the gate.

[0010] In a second aspect, the present invention provides a method for preparing a thin film transistor, which is used to prepare the thin film transistor described in any one of the first aspects; the source electrode comprises a first source electrode portion and a second source electrode portion; the passivation layer comprises at least a first passivation layer and a second passivation layer;

[0011] providing a substrate;

[0012] forming the first source portion on one side of the substrate;

[0013] An active layer is formed on the side of the first source portion away from the substrate, and along a direction parallel to the substrate, the active layer includes a channel region and a source contact region and a drain contact region located on both sides of the channel region; a Schottky contact is formed between a portion of the first source portion and the source contact region;

[0014] forming a first passivation layer on a side of the active layer away from the substrate;

[0015] A gate is formed on the side of the first passivation layer away from the substrate; along a direction perpendicular to the substrate, part of the first source portion and part of the source contact region overlap with the gate;

[0016] forming a second passivation layer on a side of the gate away from the substrate;

[0017] A first through hole exposing the first source portion and a second through hole exposing the drain contact region are formed in the first passivation layer and the second passivation layer;

[0018] The second source portion is formed in the first through hole and connected to the first source portion, and a drain is formed in the second through hole and connected to the drain contact region.

[0019] In a third aspect, the present invention provides a display panel comprising the thin film transistor described in any one of the first aspects.

[0020] In a fourth aspect, the present invention provides a display device, comprising the display panel described in any one of the third aspects.

[0021] The technical solution of the embodiment of the present invention provides a thin film transistor, which includes: a substrate; an active layer, located on one side of the substrate, along a direction parallel to the substrate, the active layer includes a channel region and a source contact region and a drain contact region located on both sides of the channel region; a source, the source includes at least a first source portion, and a Schottky contact is formed between a portion of the first source portion and the source contact region; a drain, the drain contacts the drain contact region; a gate, located on one side of the substrate, along a direction perpendicular to the substrate, a portion of the first source portion, a portion of the source contact region overlaps with the gate. By using a portion of the first source portion to form a Schottky contact with the active layer, the free flow of carriers is suppressed, so that the driving thin film transistor has a lower saturation voltage, the current stability of the thin film transistor in the saturation region is improved, and the power consumption of the thin film transistor is reduced.

[0022] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 A schematic diagram of the structure of a thin film transistor provided by an embodiment of the present invention;

[0025] Figure 2 A schematic diagram of the structure of another thin film transistor provided by an embodiment of the present invention;

[0026] Figure 3 A schematic diagram of the structure of another thin film transistor provided by an embodiment of the present invention;

[0027] Figure 4 A flow chart of a method for preparing a thin film transistor provided by an embodiment of the present invention;

[0028] Figure 5 A flow chart of another method for preparing a thin film transistor provided by an embodiment of the present invention;

[0029] Figure 6 A flow chart of another method for preparing a thin film transistor provided by an embodiment of the present invention;

[0030] Figure 7 A flow chart of another method for preparing a thin film transistor provided by an embodiment of the present invention;

[0031] Figure 8 A flow chart of another method for preparing a thin film transistor provided by an embodiment of the present invention;

[0032] Fig. 9 A flow chart of another method for preparing a thin film transistor provided by an embodiment of the present invention;

[0033] Fig.10 A schematic diagram of the structure of a display panel is provided for an embodiment of the present invention;

[0034] Fig.11 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0036] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0037] Figure 1 A schematic diagram of the structure of a thin film transistor provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, the thin film transistor includes: a substrate 101, an active layer 102, a source 103, a drain 104 and a gate 105; the active layer 102 is located at one side of the substrate 101, and along a direction X parallel to the substrate 101, the active layer 102 includes a channel region 1021 and a source contact region 1022 and a drain contact region 1023 located on both sides of the channel region 1021; the source 103 at least includes a first source portion 1031, and a Schottky contact is formed between a portion of the first source portion 1031 and the source contact region 1022; the drain 104 is in contact with the drain contact region 1023; the gate 105 is located at one side of the substrate 101, and along a direction Y perpendicular to the substrate 101, a portion of the first source portion 1031 and a portion of the source contact region 1022 overlap with the gate 105.

[0038] Among them, the substrate 101 substrate can be a rigid substrate 101 substrate or a flexible substrate 101 substrate, and the material of the substrate 101 substrate can be selected according to actual design requirements, and the embodiment of the present invention does not limit this. An active layer 102 is arranged on one side of the substrate 101, and the active layer 102 includes a conductive area and a non-conductive area. The channel area 1021 is a conductive area, and the source contact area 1022 and the drain contact area 1023 are non-conductive areas. The active area may include silicon. The material and thickness of the active layer 102 can be selected according to actual design requirements, and the embodiment of the present invention does not specifically limit this. The thin film transistor includes a source 103 and a drain 104, and the source 103 and the drain 104 may include a single layer or multiple layers of metal. The drain 104 contacts the drain contact region 1023, and the source 103 includes a first source portion 1031. The first source portion 1031 contacts and overlaps the active layer 102 to form a Schottky contact. The Schottky contact has extremely high reverse impedance, inhibits the free flow of carriers, has rectification characteristics, improves the electrical stability of the thin film transistor, and reduces the power consumption of the thin film transistor. The thin film transistor also includes a gate 105, which is located on one side of the substrate 101. The gate 105 is made of a conductive material, such as a metal or alloy material such as aluminum, gold, copper, chromium, titanium, platinum, etc. The gate 105 is insulated from the active layer 102, the source 103 and the drain 104. Along a direction Y perpendicular to the substrate 101, the gate 105 overlaps with the channel region 1021. By applying a voltage between the gate 105 and the channel, the channel region 1021 in the active layer 102 is controlled to accumulate carriers. When the carriers accumulate to a certain extent, the source 103 and the drain 104 will be turned on, so that current flows from the source 103 through the active layer 102 to the drain 104. Specifically, when the source 103 is connected to a low voltage, the drain 104 is connected to a high voltage, and the gate 105 applies a positive voltage to control the channel formation, hole injection, and the thin film transistor is turned on. At this time, the source 103 flows to the drain 104 through the active layer 102, forming a continuous current to ensure the conduction effect of the thin film transistor. Along the direction Y perpendicular to the substrate 101, part of the first source portion 1031 and part of the source contact area 1022 overlap with the gate 105. The overlapping area is reasonably set to ensure the Schottky contact characteristics, inhibit the free flow of carriers, and improve the current stability of the thin film transistor in the saturation region.

[0039] In the embodiment of the present invention, a Schottky contact is formed between a part of the first source portion and the source contact region in the thin film transistor; and a part of the first source portion and a part of the source contact region overlap with the gate. The Schottky contact is formed by a part of the first source portion and the active layer to suppress the free flow of carriers, so that the driving thin film transistor has a lower saturation voltage, improves the current stability in the saturation region, and reduces the power consumption of the thin film transistor.

[0040] Optional, continue to refer to Figure 1, the gate 105 is located on the side of the active layer 102 away from the substrate 101 ; there is a partial source contact region 1022 located between the gate 105 and the first source portion 1031 .

[0041] Among them, the gate 105 is arranged on the side of the active layer 102 away from the substrate 101 to form a top-gate thin film transistor, the source contact area 1022 covers at least part of the first source division 1031, the source contact area 1022 is located between the gate 105 and the first source division 1031, the side of the source contact area 1022 close to the first source division 1031 contacts the side of the first source division 1031 close to the source contact area 1022 to form a Schottky contact, thereby suppressing the free flow of carriers, applying a reasonable gate voltage at the gate 105, generating an electric field between the gate 105 and the channel region 1021, and controlling the conduction or cutoff of the thin film transistor.

[0042] Optional, continue to refer to Figure 1 The active layer 102 includes a first active sub-portion 11 and a second active sub-portion 12 connected to each other. The first active sub-portion 11 is located between the second active sub-portion 12 and the substrate 101 ; the first active sub-portion 11 is in contact with the first source sub-portion 1031 .

[0043] The active layer 102 has a certain thickness, and the active layer 102 is arranged into a first active subdivision 11 close to the substrate 101 side and a second active subdivision 12 away from the substrate 101 side. The first active subdivision 11 contacts the first source subdivision 1031. There is a certain work function difference between the materials of the first active subdivision 11 and the first source subdivision 1031, forming a Schottky contact, inhibiting the free movement of carriers, inhibiting leakage current, improving the current stability of the thin film transistor in the saturation region, and reducing the power consumption of the thin film transistor. During the preparation of the active layer 102, the first active subdivision 11 and the second active subdivision 12 can be prepared in sequence, or a semiconductor layer with a certain thickness, such as amorphous silicon (a-Si), can be deposited as a whole layer, and the side of the semiconductor layer away from the substrate 101 is treated by an ELA (excimer laser annealing) process to convert the amorphous silicon into polycrystalline silicon, so that part of the semiconductor layer forms the second active subdivision 12, increasing the carrier mobility, and thus achieving the structural stability and performance of the thin film transistor.

[0044] Optional, continue to refer to Figure 1 The first source portion 1031 includes a first surface 13 away from the substrate 101 and a first side surface 14 connected to the first surface 13 and close to the first active portion 11 ; the first active portion 11 at least covers the first side surface 14 and a portion of the first surface 13 .

[0045] Among them, in order to ensure that the first source division 1031 forms a stable Schottky contact with the source contact area 1022, the first semiconductor layer division covers the first side surface 14 of the first source division 1031 close to the first active division 11 and the first surface 13 of the first source division 1031 away from the substrate 101, ensuring that the first active division 11 in the active layer 102 can have a sufficient contact area with the first source division 1031, ensuring the performance of forming a Schottky contact, effectively suppressing the free flow of carriers, so that the driving thin film transistor has a lower saturation voltage, improving the current stability in the saturation region, and reducing the power consumption of the thin film transistor.

[0046] Optional, Figure 2 A schematic diagram of the structure of another thin film transistor provided by an embodiment of the present invention is shown in FIG. Figure 2 As shown, the gate 105 is located on the side of the active layer 102 close to the substrate 101 ; there is a partial source contact region 1022 located in the first source portion 1031 between the gate 105 and the substrate 101 .

[0047] Among them, the gate 105 can also be arranged on the side of the active layer 102 close to the substrate 101 to form a bottom-gate thin film transistor. The first source division 1031 covers at least part of the source contact area 1022, and the covered area at least includes the side of the source contact area 1022 close to the first source division 1031 and the surface of the source contact area away from the substrate and connected to the side. The source contact area 1022 is located between the gate 105 and the first source division 1031. The side of the source contact area 1022 close to the first source division 1031 contacts the side of the first source division 1031 close to the source contact area 1022 to form a Schottky contact, so as to suppress the free flow of carriers. A reasonable gate voltage is applied at the gate 105, and an electric field is generated between the gate 105 and the channel region 1021 to control the conduction or cutoff of the thin film transistor.

[0048] Optional, continue to refer to the reference Figure 1 and Figure 2 , the work function of the material of the source electrode 103 is smaller than the work function of the material of the active layer 102. When the first source portion 1031 in the source electrode 103 contacts the active layer 102, the work function of the material of the source electrode 103 is smaller than the work function of the active layer 102, and it is easier to form a Schottky contact between the metal and the semiconductor, hindering the free flow of carriers, improving the electrical stability of the thin film transistor, and reducing the power consumption of the thin film transistor. By reasonably selecting the material of the source electrode 103 and the material of the active layer 102, the work function difference between the work function of the material of the source electrode 103 and the work function of the material of the active layer 102 is adjusted, so that a good Schottky contact is formed between the source electrode 103 and the active layer 102, and the working performance of the thin film transistor is guaranteed.

[0049] Optional, continue to refer to Figure 1 , the thickness of the active layer 102 is H, where H≥45nm. When the thin film transistor is a top-gate transistor, the thickness of the active layer 102 is reasonably set so that the side of the active layer 102 close to the substrate 101 is amorphous silicon, which is convenient for contacting with the first source portion 1031 to form a Schottky contact, and the side of the active layer 102 far from the substrate 101 is converted into polycrystalline silicon by ELA (excimer laser annealing) process, so as to increase the carrier mobility and ensure the working ability of the thin film transistor.

[0050] Optional, Figure 3 A schematic diagram of the structure of another thin film transistor provided by an embodiment of the present invention is shown in FIG. Figure 3 As shown, the thin film transistor further includes a light shielding layer 106, and the light shielding layer 106 is located between the substrate 101 and the active layer 102. When the thin film transistor is a top-gate thin film transistor, the light shielding layer 106 is arranged between the substrate 101 and the active layer 102. By setting the light shielding layer 106, the influence of the light taken from the direction of the substrate 101 on the active layer 102 can be resisted, and the active layer 102 is prevented from receiving the irradiation of the light and causing the threshold voltage of the thin film transistor to drift, thereby improving the stability of the thin film transistor. The light shielding layer 106 can be at least one of a metal such as aluminum, titanium, copper, molybdenum or tantalum, a non-metal such as a-Si, and an organic material. The material and thickness of the light shielding layer 106 can be selected according to actual design requirements, and the embodiment of the present invention does not make specific limitations.

[0051] Optional, continue to refer to Figure 1 and Figure 2 The thin film transistor also includes a passivation layer 107, which covers the active layer 102; the source electrode 103 also includes a second source electrode portion 1032; the passivation layer 107 is provided with a first through hole exposing the first source electrode portion 1031 and a second through hole exposing the drain contact area 1023; the second source electrode portion 1032 is connected to the first source electrode portion 1031 through the first through hole; the drain electrode 104 is connected to the drain contact area 1023 through the second through hole.

[0052] Among them, Figure 1As shown, when the thin film transistor is a top-gate thin film transistor, the passivation layer 107 includes a first passivation layer 1071 and a second passivation layer 1072, the first passivation layer 1071 covers the active layer 102 and the first source portion 1031, the second passivation layer 1072 is located on the side of the first passivation layer 1071 away from the substrate 101, the second passivation layer 1072 covers the gate 105, a first through hole is set on the first passivation layer 1071 and the second passivation layer 1072 to expose the first source portion 1031, and a second through hole is set to expose the drain contact area 1023, the second source portion 1032 is prepared by means of the first through hole, so that the second source portion 1032 is electrically connected to the first source portion 1031, and the drain 104 is prepared by means of the second through hole, and signals are transmitted by means of the second source portion 1032 and the drain 104 to ensure the normal use of the thin film transistor.

[0053] like Figure 2 As shown, when the thin film transistor is a bottom-gate thin film transistor, the passivation layer 107 covers the active layer 102, and plays a certain protective role on the active layer 102. Then, a first through hole is set on the passivation layer 107 to expose the first source portion 1031, and a second through hole is set to expose the drain contact area 1023. The second source portion 1032 is prepared with the help of the first through hole, so that the second source portion 1032 is electrically connected to the first source portion 1031, and the drain 104 is prepared with the help of the second through hole, and signals are transmitted with the help of the second source portion 1032 and the drain 104 to ensure the normal use of the thin film transistor.

[0054] Optional, continue to refer to Figure 1 The first source portion 1031 includes a first source sub-portion 15, and a Schottky contact is formed between the first source sub-portion 15 and the source contact region 1022; the width of the first source sub-portion 15 is W1, and the width of the gate 105 is W2; wherein W1≥1μm, W1≥2μm.

[0055] Among them, there is a part of the first source subdivision 1031 that contacts with the source contact area 1022 to form a Schottky contact. This part of the first source subdivision 1031 is the first source subdivision 15. Along the direction parallel to the substrate 101, the width of the gate 105 is usually greater than or equal to 2μm. The width of the gate 105 is reasonably set to ensure the control effect of the gate 105 on the flow of carriers and adjust the loss of the thin film transistor. In combination with the width W2 of the gate 105, the width W1 of the first source subdivision 15 is adjusted accordingly to ensure the overlapping area of ​​the gate 105 and the first source subdivision 1031, so that the width W1 of the first source subdivision 15 is greater than or equal to 1μm, so that the area of ​​the Schottky contact formed by the first source subdivision 1031 and the active layer 102 is increased, thereby ensuring the stability of the saturation region current of the thin film transistor. For example, when the width W2 of the gate 105 is 2 μm, the width W1 of the first source sub-division 15 may be 1 μm; when the width W2 of the gate 105 is 5 μm, the width W1 of the first source sub-division 15 may be 2 μm; the width of the first source sub-division 15 may be selected according to the width of the gate 105 and actual design requirements, and is not specifically limited in the embodiment of the present invention.

[0056] Figure 4 A flowchart of a method for preparing a thin film transistor provided by an embodiment of the present invention, Figure 5 A flow chart of another method for preparing a thin film transistor provided by an embodiment of the present invention, such as Figure 1 , 4 and Figure 5 As shown, the preparation method is used to prepare the thin film transistor described in any one of the above embodiments; the source electrode 103 includes a first source electrode portion 1031 and a second source electrode portion 1032; the passivation layer 107 includes at least a first passivation layer 1071 and a second passivation layer 1072. The preparation method of the thin film transistor includes:

[0057] S101, providing a substrate.

[0058] S102, forming a first source portion on one side of the substrate.

[0059] A buffer layer is prepared on one side of the substrate 101, and the material of the buffer layer may include any one or any two or more of silicon oxide, silicon nitride and silicon oxynitride, and then a first source portion 1031 is prepared on the side of the buffer layer away from the substrate 101, and the first source portion 1031 is composed of a metal material.

[0060] S103, forming an active layer on the side of the first source portion away from the substrate, along a direction parallel to the substrate, the active layer includes a channel region and a source contact region and a drain contact region located on both sides of the channel region; a Schottky contact is formed between part of the first source portion and the source contact region.

[0061] An active layer 102 is prepared on the side of the first source portion 1031 away from the substrate 101, and the work function of the first source portion 1031 is adjusted to be smaller than the work function of the active layer 102, so that the non-conductive source contact area 1022 in the active layer 102 is in contact with the first source portion 1031 to form a Schottky contact, which hinders the free flow of carriers, thereby improving the electrical stability of the thin film transistor formed subsequently and reducing the power consumption of the thin film transistor.

[0062] S104, forming a first passivation layer on a side of the active layer away from the substrate.

[0063] Wherein, a first passivation layer 1071 is prepared on the side of the active layer 102 away from the substrate 101, and the first passivation layer 1071 may include any one or any two or more of silicon oxide, silicon nitride and silicon oxynitride, and the first passivation layer 1071 is used to cover and protect the first source portion 1031 and the first source portion 1031 to ensure the stability of the formed thin film transistor. The first passivation layer 1071 can be prepared by plasma enhanced chemical vapor deposition, atomic layer deposition, magnetron sputtering, reactive sputtering or spin coating.

[0064] S105, forming a gate on the side of the first passivation layer away from the substrate; along the direction perpendicular to the substrate, part of the first source portion and part of the source contact region overlap with the gate.

[0065] Among them, a conductive layer, such as metal molybdenum, is prepared on the side of the first passivation layer 1071 away from the substrate 101. The conductive layer is usually photolithographically formed into a gate 105 so that along a direction Y perpendicular to the substrate 101, the gate 105 overlaps with part of the first source portion 1031 and part of the source contact area 1022, thereby ensuring the performance of the thin film transistor.

[0066] S106, forming a second passivation layer on a side of the gate away from the substrate.

[0067] Among them, a second passivation layer 1072 is prepared on the side of the gate 105 away from the substrate 101, and the second passivation layer 1072 may include any one or any two or more of silicon oxide, silicon nitride and silicon oxynitride, and the second passivation layer 1072 protects the gate 105. The second passivation layer 1072 can be prepared by plasma enhanced chemical vapor deposition, atomic layer deposition, magnetron sputtering, reactive sputtering or spin coating.

[0068] S107, opening a first through hole exposing the first source portion and a second through hole exposing the drain contact region in the first passivation layer and the second passivation layer.

[0069] The first through hole 21 and the second through hole 22 can be formed in the same photolithography process, thereby reducing the complexity of the manufacturing process.

[0070] S108, forming a second source portion in the first through hole and connected to the first source portion, forming a drain in the second through hole and connected to the drain contact area.

[0071] A second source portion 1032 is formed in the first through hole 21, and the second source portion 1032 is electrically connected to the first source portion 1031. The second source portion 1032 and the first source portion 1031 may be made of the same material to form the source 103. A drain 104 is formed in the second through hole 22 and electrically connected to the drain contact region 1023 to ensure the structural stability and working stability of the thin film transistor.

[0072] The embodiment of the present invention forms a top-gate thin film transistor by preparing a first source portion and an active layer in a thin film transistor, forming a gate on the side of the active layer away from the substrate, and forming a Schottky contact between the first source portion and the source contact area in the active layer. The Schottky contact is used to suppress the free flow of carriers, so that the driving thin film transistor has a lower saturation voltage, improves the current stability in the saturation region, and reduces the power consumption of the thin film transistor.

[0073] Figure 6 A flowchart of another method for preparing a thin film transistor provided by an embodiment of the present invention, Figure 7 A flow chart of another method for preparing a thin film transistor provided by an embodiment of the present invention, such as Figure 6 and Figure 7 As shown, along a direction Y perpendicular to the substrate 101, the active layer 102 includes a first active sub-portion 11 and a second active sub-portion 12. The method for preparing a thin film transistor includes:

[0074] S201, providing a substrate.

[0075] S202, forming a first source portion on one side of the substrate.

[0076] S203, forming a semiconductor layer on a side of the first source portion away from the substrate.

[0077] S204, performing conductor processing on the side of the semiconductor layer away from the substrate to form a second active portion and forming a first active portion on the side of the semiconductor layer close to the substrate, wherein the first active portion is in contact with the first source portion.

[0078] Among them, a semiconductor layer 30 with a certain thickness, such as an amorphous silicon layer, is prepared on the side of the first source portion 1031 away from the substrate 101, and a conductor treatment is performed on the side of the semiconductor layer 30 away from the substrate 101, such as using an ELA process to convert amorphous silicon into polycrystalline silicon to form the second active portion 12, thereby increasing the carrier mobility. Since the semiconductor layer 30 has a certain thickness, only the semiconductor layer 30 on the side away from the substrate 101 can be made to be conductive and converted to form the second active portion 12, while the semiconductor layer on the side close to the substrate 101 still maintains a semiconductor state to form the first active portion 11, and then the first active portion 11 contacts the first source portion 1031 to form a Schottky contact, so as to achieve the current stability of the prepared thin film transistor in the saturation region and reduce the power consumption of the thin film transistor.

[0079] S205, along a direction parallel to the substrate, the first active section and the second active section include a channel region and a source contact region and a drain contact region located on both sides of the channel region; a Schottky contact is formed between a portion of the first source section and the first active section.

[0080] S206, forming a first passivation layer on a side of the second active portion away from the substrate.

[0081] S207, forming a gate on the side of the first passivation layer away from the substrate; along the direction perpendicular to the substrate, part of the first source portion and part of the source contact region overlap with the gate.

[0082] S208, forming a second passivation layer on a side of the gate away from the substrate.

[0083] S209, opening a first through hole exposing the first source portion and a second through hole exposing the drain contact region in the first passivation layer and the second passivation layer.

[0084] S210, forming a second source portion in the first through hole and connected to the first source portion, forming a drain in the second through hole and connected to the drain contact region.

[0085] The embodiment of the present invention prepares a first source portion in a thin film transistor, forms a semiconductor layer on the side of the first source portion away from the substrate, performs conductor processing on the side of the semiconductor layer away from the substrate to form a second active portion, and forms a first active portion on the side of the semiconductor layer close to the substrate. The first active portion contacts the first source portion to form a Schottky contact to suppress the free flow of carriers, so that the driving thin film transistor has a lower saturation voltage, improves the current stability in the saturation region, and reduces the power consumption of the thin film transistor.

[0086] Figure 8 A flowchart of another method for preparing a thin film transistor provided by an embodiment of the present invention, Fig. 9A flow chart of another method for preparing a thin film transistor provided by an embodiment of the present invention, such as Figure 8 and Fig. 9 As shown, the method for preparing the thin film transistor is used to prepare the thin film transistor described in any one of the above embodiments;

[0087] S301, providing a substrate.

[0088] S302, forming a gate on one side of the substrate.

[0089] A buffer layer is prepared on one side of the substrate 101, and the material of the buffer layer may include any one or any two or more of silicon oxide, silicon nitride and silicon oxynitride, and then a gate 105 metal layer is prepared on the side of the buffer layer away from the substrate 101, and the gate 105 metal layer is patterned to form the gate 105.

[0090] S303, forming an active layer on a side of the gate away from the substrate, wherein the active layer includes a channel region and a source contact region and a drain contact region located on both sides of the channel region in a direction parallel to the substrate.

[0091] Among them, a gate insulating layer 50 is prepared on a layer away from the substrate 101 of the gate 105, and the gate insulating layer 50 protects the gate 105. The material of the gate insulating layer 50 may include any one or any two or more of silicon oxide, silicon nitride and silicon oxynitride. The gate insulating layer 50 can be prepared by plasma enhanced chemical vapor deposition, atomic layer deposition, magnetron sputtering, reactive sputtering or spin coating. According to the position of the gate 105, the active layer 102 is prepared on the side of the gate insulating layer 50 away from the substrate 101, and the active layer 102 is divided into a channel region 1021, and a source contact region 1022 and a drain contact region 1023 located on both sides of the channel region 1021. The channel region 1021 is a conductive region, and the source contact region 1022 and the drain contact region 1023 are non-conductive regions.

[0092] S304, forming a first source portion on a side of the active layer away from the substrate; forming a Schottky contact between a portion of the first source portion and the source contact region; and overlapping a portion of the first source portion and a portion of the source contact region with the gate in a direction perpendicular to the substrate.

[0093] Among them, the material of the first source portion 1031 is selected according to the work function of the material of the active layer 102, and the first source portion 1031 is prepared on the side of the active layer 102 away from the substrate 101, so that the first source portion 1031 contacts the source contact area 1022 in the active layer 102 to form a Schottky contact, and the gate 105 overlaps with part of the first source portion 1031 and part of the source contact area 1022 to ensure the performance of the Schottky contact. The Schottky contact has extremely high reverse impedance, which inhibits the free flow of carriers, improves the electrical stability of the thin film transistor, and reduces the power consumption of the thin film transistor.

[0094] S305, forming a passivation layer on a side of the first source portion away from the substrate.

[0095] A passivation layer 107 is prepared on the side of the first source portion 1031 away from the substrate 101, and the passivation layer 107 covers the first source portion 1031 and the active layer 102 to achieve protection. The materials of the passivation layer 107 and the gate insulating layer 50 may be the same or different, and the material of the passivation layer 107 may include any one or any two or more of silicon oxide, silicon nitride and silicon oxynitride. The passivation layer 107 may be prepared by plasma enhanced chemical vapor deposition, atomic layer deposition, magnetron sputtering, reactive sputtering or spin coating.

[0096] S306, opening a first through hole exposing the first source portion and a second through hole exposing the drain contact region in the passivation layer.

[0097] The first through hole 21 and the second through hole 22 are respectively formed on the passivation layer 107 by adopting the same process.

[0098] S307, forming a second source portion in the first through hole and connected to the first source portion, forming a drain in the second through hole and connected to the drain contact area.

[0099] The first through hole 21 includes a first source portion 1031, and then a second source portion 1032 is formed in the through hole, so that the first source portion 1031 and the second source portion 1032 are electrically connected to form the source 103 of the thin film transistor. The second through hole 22 exposes the source contact area 1022, and a drain 104 is formed in the through hole, so that the drain 104 is electrically connected to the drain contact area 1023, thereby ensuring the structural stability and working stability of the thin film transistor.

[0100] The embodiment of the present invention forms a bottom-gate thin film transistor by preparing a first source portion and an active layer in a thin film transistor, forming a gate between the active layer and the substrate, and forming a Schottky contact between the first source portion and the source contact area in the active layer. The Schottky contact is used to suppress the free flow of carriers, so that the driving thin film transistor has a lower saturation voltage, improves the current stability in the saturation region, and reduces the power consumption of the thin film transistor.

[0101] Fig.10 A schematic diagram of the structure of a display panel is provided in an embodiment of the present invention. Fig.10 As shown, the display panel 100 includes a plurality of pixel units 200, each pixel unit 200 includes the thin film transistor 201 described in the above embodiment, and has the same or corresponding beneficial effects of the thin film transistor 201 in the above embodiment, which will not be described in detail here. The display panel can be a liquid crystal display panel, an organic light emitting display panel or a micro light emitting diode display panel, which is not particularly limited in the embodiment of the present invention.

[0102] Fig.11 A schematic diagram of a display device according to an embodiment of the present invention is shown in FIG. Fig.11 As shown, the display device 300 includes the display panel 100 described in the above embodiment.

[0103] It should be noted that since the display device provided in this embodiment has the same or corresponding beneficial effects as the display panel in the above embodiment, no further description is given here. The display device 300 provided in the embodiment of the present invention can be Fig.11 The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc. The embodiments of the present invention do not specifically limit this.

[0104] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A thin film transistor, characterized in that: include: substrate; An active layer, located on one side of the substrate, along a direction parallel to the substrate, the active layer comprising a channel region and a source contact region and a drain contact region located on both sides of the channel region; A source electrode, the source electrode at least comprising a first source electrode portion, a portion of the first source electrode portion forming a Schottky contact with the source contact region; a drain electrode, the drain electrode being in contact with the drain contact region; The gate is located at one side of the substrate, and along a direction perpendicular to the substrate, part of the first source portion and part of the source contact region overlap with the gate.

2. The thin film transistor according to claim 1, characterized in that: The gate is located on a side of the active layer away from the substrate; A portion of the source contact region is located between the gate and the first source portion.

3. The thin film transistor according to claim 2, characterized in that: The active layer includes a first active subsection and a second active subsection connected to each other, wherein the first active subsection is located between the second active subsection and the substrate; The first active subdivision is in contact with the first source subdivision.

4. The thin film transistor according to claim 3, characterized in that: The first source portion includes a first surface away from the substrate and a first side surface connected to the first surface and close to the first active portion; The first active section at least covers the first side surface and a portion of the first surface.

5. The thin film transistor according to claim 1, characterized in that: The gate is located on a side of the active layer close to the substrate; A portion of the source contact region is located between the first source portion and the substrate.

6. The thin film transistor according to claim 1, characterized in that: A work function of a material of the source electrode is smaller than a work function of a material of the active layer.

7. The thin film transistor according to claim 1, characterized in that: The thickness of the active layer is H, where H≥45nm.

8. The thin film transistor according to claim 1, characterized in that: The thin film transistor further includes a light shielding layer, and the light shielding layer is located between the substrate and the active layer.

9. The thin film transistor according to claim 1, characterized in that: The thin film transistor further comprises a passivation layer, wherein the passivation layer covers the active layer; The source also includes a second source subdivision; The passivation layer is provided with a first through hole exposing the first source portion and a second through hole exposing the drain contact region; The second source portion is connected to the first source portion through the first through hole; the drain is connected to the drain contact area through the second through hole.

10. The thin film transistor according to claim 1, characterized in that: The first source subdivision includes a first source subdivision, and a Schottky contact is formed between the first source subdivision and the source contact region; the width of the first source subdivision is W1, and the width of the gate is W2; Among them, W1≥1μm, W1≥2μm.

11. A method for preparing a thin film transistor, characterized in that: Used to prepare the thin film transistor according to any one of claims 1 to 10; the source electrode comprises a first source electrode portion and a second source electrode portion; the passivation layer comprises at least a first passivation layer and a second passivation layer; providing a substrate; forming the first source portion on one side of the substrate; An active layer is formed on the side of the first source portion away from the substrate, and along a direction parallel to the substrate, the active layer includes a channel region and a source contact region and a drain contact region located on both sides of the channel region; a Schottky contact is formed between a portion of the first source portion and the source contact region; forming a first passivation layer on a side of the active layer away from the substrate; forming a gate on a side of the first passivation layer away from the substrate; Along the direction perpendicular to the substrate, part of the first source portion, part of the source contact region and the gate overlap; forming a second passivation layer on a side of the gate away from the substrate; A first through hole exposing the first source portion and a second through hole exposing the drain contact region are formed in the first passivation layer and the second passivation layer; The second source portion is formed in the first through hole and connected to the first source portion, and a drain is formed in the second through hole and connected to the drain contact region.

12. The method for preparing a thin film transistor according to claim 11, characterized in that: Along the direction perpendicular to the substrate, the active layer includes a first active sub-section and a second active sub-section; An active layer is formed on a side of the first source portion away from the substrate, comprising: forming a semiconductor layer on a side of the first source portion away from the substrate; Conductive processing is performed on the side of the semiconductor layer away from the substrate to form a second active portion, and a first active portion is formed on the side of the semiconductor layer close to the substrate, wherein the first active portion is in contact with the first source portion.

13. A method for preparing a thin film transistor, characterized in that: Used to prepare a thin film transistor according to any one of claims 1 to 10; providing a substrate; forming a gate on one side of the substrate; An active layer is formed on a side of the gate away from the substrate, wherein the active layer includes a channel region and a source contact region and a drain contact region located on both sides of the channel region in a direction parallel to the substrate; forming a first source portion on a side of the active layer away from the substrate; A Schottky contact is formed between a portion of the first source portion and the source contact region; Along the direction perpendicular to the substrate, part of the first source portion, part of the source contact region and the gate overlap; forming a passivation layer on a side of the first source portion away from the substrate; Opening a first through hole exposing the first source portion and a second through hole exposing the drain contact region in the passivation layer; A second source portion is formed in the first through hole and connected to the first source portion, and a drain is formed in the second through hole and connected to the drain contact region.

14. A display panel, characterized in that: A thin film transistor comprising the thin film transistor described in any one of claims 1 to 10.

15. A display device, characterized in that: A display panel comprising the display panel described in any one of claims 14.

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