Display device and method of manufacturing same

Abstract

The invention relates to a display device and a method of manufacturing the same. The display device includes a pixel and a driver electrically connected to the pixel. The driver may include a first oxide semiconductor layer including a first source region, a first drain region, and a first channel region disposed between the first source region and the first drain region. The driver may include a first gate electrode disposed on the first oxide semiconductor layer and overlapping a first channel region of the first oxide semiconductor layer in a plan view. The driver may include a first charge layer disposed between the first gate electrode and the first oxide semiconductor layer and overlapping at least a portion of the first channel region in plan view.

Description

Technical Field

[0001] Embodiments relate to a display device and a method of manufacturing the same, and more particularly, to a display device including an oxide semiconductor and a method of manufacturing the same. Background Art

[0002] The display device may include pixels and a driver. The driver may generate a drive signal and provide the drive signal to the pixel. The driver may include a transistor for generating the drive signal. A silicon semiconductor (amorphous silicon or polycrystalline silicon, etc.) or an oxide semiconductor may be used as a semiconductor layer of the transistor.

[0003] Recently, in order to simplify the circuit structure of a driver and reduce power consumption, a driver having a complementary metal oxide semiconductor (CMOS) structure including a transistor including a silicon semiconductor and a transistor including an oxide semiconductor has been developed. Summary of the invention

[0004] The embodiment provides a display device including a transistor having improved reliability.

[0005] The embodiment provides a method of manufacturing a display device.

[0006] A display device according to an embodiment includes pixels and a driver electrically connected to the pixels.

[0007] In an embodiment, the driver may include: a first oxide semiconductor layer, including a first source region, a first drain region, and a first channel region disposed between the first source region and the first drain region; a first gate electrode disposed on the first oxide semiconductor layer and overlapping with the first channel region of the first oxide semiconductor layer in a plan view; and a first charge layer disposed between the first gate electrode and the first oxide semiconductor layer and overlapping with at least a portion of the first channel region in a plan view.

[0008] In an embodiment, the first charge layer may be disposed adjacent to the first source region of the first oxide semiconductor layer.

[0009] In an embodiment, the display device may further include a first insulating layer covering the first oxide semiconductor layer.

[0010] In an embodiment, the first charge layer may be disposed in the first insulating layer.

[0011] In an embodiment, the first charge layer may be disposed such that the first charge layer is spaced apart from the first oxide semiconductor layer and a portion of the first insulating layer is interposed between the first charge layer and the first oxide semiconductor layer.

[0012] In an embodiment, the first source region of the first oxide semiconductor layer and the first drain region of the first oxide semiconductor layer may be spaced apart from each other in the first direction with the first channel region of the first oxide semiconductor layer interposed between the first source region and the first drain region.

[0013] In an embodiment, a width of the first charge layer in the first direction may be less than or equal to half a width of the first channel region of the first oxide semiconductor layer in the first direction.

[0014] In an embodiment, a width of the first charge layer in the first direction may be greater than a width of the first channel region of the first oxide semiconductor layer in the first direction.

[0015] In an embodiment, the first oxide semiconductor layer may include an N-type semiconductor.

[0016] In an embodiment, the first charge layer may include negatively charged particles.

[0017] In an embodiment, the display device may further include: a first source electrode, which is disposed on the first gate electrode, connected to the first source region of the first oxide semiconductor layer and input with a signal; and a first drain electrode, which is disposed on the first gate electrode, connected to the first drain region of the first oxide semiconductor layer and separated from the first source electrode.

[0018] In an embodiment, the signal may be output to the first drain electrode.

[0019] In an embodiment, a pixel may include pixel circuitry.

[0020] In an embodiment, the pixel circuit may include: a second oxide semiconductor layer, including a second source region, a second drain region, and a second channel region disposed between the second source region and the second drain region; a second gate electrode disposed on the second oxide semiconductor layer and overlapping with the second channel region of the second oxide semiconductor layer in a plan view; and a second charge layer disposed between the second gate electrode and the second oxide semiconductor layer and overlapping with at least a portion of the second channel region of the second oxide semiconductor layer in a plan view.

[0021] In an embodiment, the second charge layer may be disposed adjacent to the second source region of the second oxide semiconductor layer.

[0022] In an embodiment, the display device may further include a second insulating layer covering the second oxide semiconductor layer.

[0023] In an embodiment, the second charge layer may be disposed in the second insulating layer.

[0024] In an embodiment, the second source region of the second oxide semiconductor layer and the second drain region of the second oxide semiconductor layer may be spaced apart from each other in the first direction with the second channel region of the second oxide semiconductor layer interposed between the second source region and the second drain region.

[0025] In an embodiment, a width of the second charge layer in the first direction may be less than or equal to half a width of the second channel region of the second oxide semiconductor layer in the first direction.

[0026] In an embodiment, the driver may be a gate driver coupled to the pixel and configured to provide a gate signal to the pixel.

[0027] In an embodiment, the driver may be an emission driver coupled to the pixel and configured to provide an emission signal to the pixel.

[0028] A method of manufacturing a display device according to an embodiment includes forming a driver electrically connected to a pixel.

[0029] In an embodiment, forming a driver may include: forming an oxide semiconductor layer including a source region, a drain region, and a channel region disposed between the source region and the drain region on a substrate; forming an insulating layer covering the oxide semiconductor layer; forming a charge layer in the insulating layer that overlaps with at least a portion of the channel region of the oxide semiconductor layer in a plan view; and forming a gate electrode that is disposed on the insulating layer and overlaps with the channel region of the oxide semiconductor layer in a plan view.

[0030] In an embodiment, forming the charge layer may include implanting ions into the insulating layer using a mask.

[0031] In an embodiment, implanting the ions may include selectively implanting the ions into a portion of the insulating layer overlapping the channel region of the oxide semiconductor layer and adjacent to the source region of the oxide semiconductor layer in plan view using a mask.

[0032] In an embodiment, the energy of the ions implanted into the insulating layer may range from 5 kV to 10 kV, and the implantation amount of the ions implanted into the insulating layer may range from 3e11 ions / cm 2 Up to 3e12 ions / cm 2 .

[0033] In an embodiment, the charge layer may be formed such that the charge layer is spaced apart from the oxide semiconductor layer with a portion of the insulating layer interposed between the charge layer and the oxide semiconductor layer.

[0034] According to an embodiment, a display device includes a pixel and a driver electrically connected to the pixel, and the driver may include: a first oxide semiconductor layer, including a first source region, a first drain region, and a first channel region arranged between the first source region and the first drain region; a first gate electrode, arranged on the first oxide semiconductor layer and overlapping with the first channel region of the first oxide semiconductor layer in a plan view; and a first charge layer, arranged between the first gate electrode and the first oxide semiconductor layer, and overlapping with at least a portion of the first channel region in a plan view.

[0035] That is, the first charge layer can be disposed between the first oxide semiconductor layer and the first gate electrode. Therefore, the threshold voltage of the transistor included in the driver can be shifted in the positive direction. Therefore, the embodiment of the present disclosure supports preventing the phenomenon that the transistor is turned on when a signal value lower than a specific signal value is provided to the first gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0037] Figure 1 is a plan view illustrating a display device according to one or more embodiments of the present disclosure.

[0038] Figure 2 is a diagram illustrating one or more embodiments of the present disclosure Figure 1 A block diagram of a display device.

[0039] Figure 3 It is used to describe one or more embodiments of the present disclosure. Figure 1 A circuit diagram of a pixel included in a display device.

[0040] Figure 4 It is used to describe one or more embodiments of the present disclosure. Figure 2 A circuit diagram of a gate driver included in a display device.

[0041] Figure 5 It is used to describe one or more embodiments of the present disclosure. Figure 2 A circuit diagram of an emission driver included in a display device.

[0042] Figure 6 It is used to describe one or more embodiments of the present disclosure. Figure 2 A cross-sectional view of a gate driver and / or an emission driver included in a display device.

[0043] Figure 7 is a diagram illustrating a method of performing a Figure 1 A cross-sectional view of a pixel included in a display device.

[0044] Figure 8 is a diagram illustrating one or more embodiments of the present disclosure Figure 6 An enlarged cross-sectional view of an example of region A.

[0045] Fig. 9 is a diagram illustrating one or more embodiments of the present disclosure Figure 6 An enlarged cross-sectional view of another example of region A.

[0046] Fig.10 is a diagram illustrating one or more embodiments of the present disclosure Figure 7 An enlarged cross-sectional view of an example of region B.

[0047] Fig.11 is a diagram illustrating one or more embodiments of the present disclosure Figure 7 An enlarged cross-sectional view of another example of region B.

[0048] Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16 is a diagram illustrating a method of manufacturing a Figure 2 A cross-sectional view of a method of including a gate driver and / or an emission driver in a display device. DETAILED DESCRIPTION

[0049] Hereinafter, a display device according to an embodiment will be described in more detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same components, and redundant descriptions of the same components will be omitted.

[0050] Embodiments supported by the present disclosure will now be more fully described below with reference to the accompanying drawings in which one or more example embodiments are illustrated. However, aspects supported by the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these example embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the example aspects of the present invention to those skilled in the art.

[0051] Figure 1 is a plan view illustrating a display device according to one or more embodiments of the present disclosure. Figure 2 is a diagram illustrating one or more embodiments of the present disclosure Figure 1 A block diagram of a display device.

[0052] refer to Figure 1, the display device DD according to the embodiment may include a display area DA and a non-display area NDA. The display area DA may be defined as an area capable of displaying an image by generating light or adjusting the transmittance of light provided from an external light source. The non-display area NDA may be an area where an image is not displayed. In some aspects, the non-display area NDA may surround at least a portion of the display area DA.

[0053] A plurality of pixels may be disposed in the display area DA. For example, a pixel PX may be disposed in the display area DA. A plurality of pixels may be repeatedly arranged in a first direction DR1 and a second direction DR2 crossing the first direction DR1.

[0054] In an embodiment, a first direction DR1 and a second direction DR2 intersecting the first direction DR1 may be defined. For example, the second direction DR2 may be perpendicular to the first direction DR1. However, the present disclosure is not limited thereto, and the second direction DR2 may form an acute angle or an obtuse angle with the first direction DR1. In addition, a third direction DR3 intersecting a plane formed by the first direction DR1 and the second direction DR2 may be defined. For example, the third direction DR3 may be perpendicular to the plane formed by the first direction DR1 and the second direction DR2. However, the present disclosure is not limited thereto, and the third direction DR3 may form an acute angle or an obtuse angle with the plane formed by the first direction DR1 and the second direction DR2.

[0055] Further references Figure 2 , the driver may be disposed in the non-display area NDA. The driver may include a driving controller 100, a gate driver 200, a gamma reference voltage generator 300, a data driver 400, and an emission driver 500. The pixel PX may be electrically connected to the gate driver 200, the data driver 400, and the emission driver 500.

[0056] The driving controller 100 may receive input image data IMG and an input control signal CONT from an external device. In an embodiment, the input image data IMG may include red image data, green image data, and blue image data. In another embodiment, the input image data IMG may further include white image data. In another embodiment, the input image data IMG may include magenta image data, yellow image data, and cyan image data.

[0057] The input control signal CONT may include a main clock signal and a data enable signal, etc. The input control signal CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

[0058] The driving controller 100 may generate a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , a fourth control signal CONT4 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0059] The driving controller 100 may generate a first control signal CONT1 based on the input control signal CONT. The driving controller 100 may output the first control signal CONT1 to the gate driver 200. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0060] The driving controller 100 may generate a second control signal CONT2 based on the input control signal CONT. The driving controller 100 may output the second control signal CONT2 to the data driver 400. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0061] The driving controller 100 may generate a third control signal CONT3 based on the input control signal CONT. The driving controller 100 may output the third control signal CONT3 to the gamma reference voltage generator 300.

[0062] The driving controller 100 may generate a fourth control signal CONT4 based on the input control signal CONT. The driving controller 100 may output the fourth control signal CONT4 to the emission driver 500.

[0063] The driving controller 100 may generate a data signal DATA based on the input image data IMG. The driving controller 100 may output the data signal DATA to the data driver 400.

[0064] The gate driver 200 may generate a gate signal G in response to the first control signal CONT1 received from the driving controller 100. The gate driver 200 may transmit the gate signal G to a plurality of pixels. For example, the gate driver 200 may transmit the gate signal G to the pixel PX.

[0065] In an example, the gate signal G may include a gate compensation signal (eg, Figure 3 The gate compensation signal GC in the gate bias signal (for example, Figure 3 The gate bias signal GB in the gate initialization signal (for example, Figure 3 The gate initialization signal GI in the gate write signal (for example, Figure 3 The gate write signal GW in .

[0066] In an example, the gate driver 200 may include a first stage STG1. The first stage STG1 may sequentially output a gate signal G. In an embodiment, each of the first stages STG1 may output a gate signal G to a plurality of pixels. For example, each of the first stages STG1 may output a gate signal G to a pixel PX.

[0067] Figure 2 The illustrated display device DD includes an example of a gate driver 200. However, the embodiments of the present disclosure are not limited thereto. For example, the display device DD may include a plurality of gate drivers. In the example, the display device DD may include a first gate driver and a second gate driver. The first gate driver may transmit a gate compensation signal to the pixel PX. In some aspects, the second gate driver may provide a gate bias signal to the pixel PX.

[0068] The gamma reference voltage generator 300 may generate a gamma reference voltage VGREF in response to a third control signal CONT3 received from the driving controller 100. The gamma reference voltage generator 300 may provide the gamma reference voltage VGREF to the data driver 400. The gamma reference voltage VGREF may have a value corresponding to the data signal DATA. In some examples, the driving controller 100 may generate a plurality of data signals DATA, and the gamma reference voltage VGREF may have a value corresponding to each of the data signals DATA.

[0069] In an embodiment, the gamma reference voltage generator 300 may be spaced apart or separated from the data driver 400. In another embodiment, the gamma reference voltage generator 300 may be integrated with the driving controller 100. For example, the gamma reference voltage generator 300 may be provided in the driving controller 100. In another embodiment, the gamma reference voltage generator 300 may be integrated with the data driver 400. For example, the gamma reference voltage generator 300 may be provided in the data driver 400.

[0070] The data driver 400 may receive the second control signal CONT2 and the data signal DATA from the driving controller 100. In some aspects, the data driver 400 may receive the gamma reference voltage VGREF from the gamma reference voltage generator 300. The data driver 400 may convert the data signal DATA into an analog data voltage DT using the gamma reference voltage VGREF. The data driver 400 may transmit the data voltage DT to a plurality of pixels. For example, the data driver 400 may transmit the data voltage DT to the pixel PX.

[0071] The emission driver 500 may generate an emission control signal EM in response to the fourth control signal CONT4 received from the driving controller 100. The emission driver 500 may transmit the emission control signal EM to a plurality of pixels. For example, the emission driver 500 may transmit the emission control signal EM to the pixel PX.

[0072] In an example, the emission driver 500 may include a second stage STG2. The second stage STG2 may sequentially output an emission control signal EM. In an embodiment, each of the second stages STG2 may output an emission control signal EM to a plurality of pixels. For example, each of the second stages STG2 may output an emission control signal EM to a pixel PX.

[0073] For convenience, Figure 2 An example is illustrated in which the gate driver 200 is disposed in the non-display area NDA adjacent to the first side of the display area DA and the emission driver 500 is disposed in the non-display area NDA adjacent to the second side of the display area DA. However, the embodiments of the present disclosure are not limited thereto. For example, both the gate driver 200 and the emission driver 500 may be disposed in the non-display area NDA adjacent to the first side of the display area DA. For example, the gate driver 200 and the emission driver 500 may be integrally formed.

[0074] Figure 3 It is used to describe one or more embodiments of the present disclosure. Figure 1 A circuit diagram of a pixel included in a display device. Figure 4 It is used to describe one or more embodiments of the present disclosure. Figure 2 A circuit diagram of a gate driver included in a display device. Figure 5 It is used to describe one or more embodiments of the present disclosure. Figure 2 A circuit diagram of an emission driver included in a display device.

[0075] refer to Figure 3 The pixel PX may include a pixel circuit PXC and a light emitting element EE. The pixel circuit PXC may generate a driving current corresponding to the data voltage DT. The light emitting element EE may emit light corresponding to the driving current.

[0076] The pixel circuit PXC may include a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , a seventh transistor T7 , an eighth transistor T8 , and a storage capacitor CST.

[0077] The storage capacitor CST may include a first electrode and a second electrode. The first electrode of the storage capacitor CST may receive a first power supply voltage ELVDD. In some aspects, the second electrode of the storage capacitor CST may be connected to the first transistor T1. The storage capacitor CST may maintain the voltage level of the gate electrode of the first transistor T1 during a deactivation period of the gate write signal GW (e.g., a period in which the gate write signal GW is a negative voltage level or a voltage level associated with a low logic level, etc.). The term "connection" may refer to electrical coupling or electrical connection. The term "connection" may refer to a physical connection that supports electrical coupling or electrical connection.

[0078] The first transistor T1 may include a first electrode, a second electrode, and a gate electrode. The gate electrode of the first transistor T1 may be connected to the second electrode of the storage capacitor CST. The first electrode of the first transistor T1 may be connected to the second transistor T2 and may be provided with a data voltage DT. The second electrode of the first transistor T1 may be connected to the sixth transistor T6. The first transistor T1 may generate a driving current based on a voltage difference between the gate electrode and the first electrode. For example, the first transistor T1 may be referred to as a driving transistor.

[0079] The second transistor T2 may include a first electrode, a second electrode, and a gate electrode. The gate electrode of the second transistor T2 may receive a gate write signal GW.

[0080] The second transistor T2 may be turned on or off in response to the gate write signal GW. In an example where the second transistor T2 is a PMOS transistor, the second transistor T2 may be turned off when the gate write signal GW has a positive voltage level, and may be turned on when the gate write signal GW has a negative voltage level.

[0081] The first electrode of the second transistor T2 may be provided with the data voltage DT. The second electrode of the second transistor T2 may provide the data voltage DT to the first electrode of the first transistor T1 during a period in which the second transistor T2 is turned on. For example, the second transistor T2 may be referred to as a switching transistor.

[0082] The third transistor T3 may include a first electrode, a second electrode and a gate electrode. The gate electrode of the third transistor T3 may receive a gate compensation signal GC. The first electrode of the third transistor T3 may be connected to the gate electrode of the first transistor T1. The second electrode of the third transistor T3 may be connected to the second electrode of the first transistor T1.

[0083] The third transistor T3 may be turned on or off in response to the gate compensation signal GC. In an example where the third transistor T3 is an NMOS transistor, the third transistor T3 may be turned on when the gate compensation signal GC has a positive voltage level, and may be turned off when the gate compensation signal GC has a negative voltage level.

[0084] During the period when the third transistor T3 is turned on in response to the gate compensation signal GC, the third transistor T3 can diode-couple the first transistor T1. Therefore, the third transistor T3 can compensate for the threshold voltage of the first transistor T1. For example, the third transistor T3 can be referred to as a compensation transistor.

[0085] The fourth transistor T4 may include a first electrode, a second electrode and a gate electrode. The gate electrode of the fourth transistor T4 may receive a gate initialization signal GI. The first electrode of the fourth transistor T4 may be connected to the gate electrode of the first transistor T1. The second electrode of the fourth transistor T4 may receive a gate initialization voltage VINT.

[0086] The fourth transistor T4 may be turned on or off in response to the gate initialization signal GI. In an example where the fourth transistor T4 is an NMOS transistor, the fourth transistor T4 may be turned on when the gate initialization signal GI has a positive voltage level, and may be turned off when the gate initialization signal GI has a negative voltage level.

[0087] During the period in which the fourth transistor T4 is turned on in response to the gate initialization signal GI, the fourth transistor T4 can provide the gate initialization voltage VINT to the gate electrode of the first transistor T1. Therefore, the fourth transistor T4 can initialize the voltage of the gate electrode of the first transistor T1 to the gate initialization voltage VINT. For example, the fourth transistor T4 can be referred to as a gate initialization transistor.

[0088] The fifth transistor T5 may include a first electrode, a second electrode, and a gate electrode. The gate electrode of the fifth transistor T5 may receive an emission control signal EM. The first electrode of the fifth transistor T5 may receive a first power supply voltage ELVDD. The second electrode of the fifth transistor T5 may be connected to the first electrode of the first transistor T1. In an example in which the fifth transistor T5 is turned on in response to the emission control signal EM, the fifth transistor T5 may provide the first power supply voltage ELVDD to the first transistor T1.

[0089] The sixth transistor T6 may include a first electrode, a second electrode, and a gate electrode. The gate electrode of the sixth transistor T6 may receive an emission control signal EM. The first electrode of the sixth transistor T6 may be connected to the second electrode of the first transistor T1. The second electrode of the sixth transistor T6 may be connected to the light emitting element EE. In an example in which the sixth transistor T6 is turned on in response to the emission control signal EM, the sixth transistor T6 may provide a driving current to the light emitting element EE.

[0090] The seventh transistor T7 may include a first electrode, a second electrode and a gate electrode. The gate electrode of the seventh transistor T7 may receive a gate bias signal GB. The first electrode of the seventh transistor T7 may receive an anode initialization voltage AINT. The second electrode of the seventh transistor T7 may be connected to the light emitting element EE.

[0091] When the seventh transistor T7 is turned on in response to the gate bias signal GB, the seventh transistor T7 can provide the anode initialization voltage AINT to the light emitting element EE. Therefore, the seventh transistor T7 can initialize the voltage of the first electrode of the light emitting element EE to the anode initialization voltage AINT. For example, the seventh transistor T7 can be called an anode initialization transistor.

[0092] The eighth transistor T8 may include a first electrode, a second electrode and a gate electrode. The gate electrode of the eighth transistor T8 may receive a gate bias signal GB. The first electrode of the eighth transistor T8 may receive a bias voltage VBIAS. The second electrode of the eighth transistor T8 may be connected to the first electrode of the first transistor T1.

[0093] When the eighth transistor T8 is turned on in response to the gate bias signal GB, the eighth transistor T8 can transmit the bias voltage VBIAS to the first transistor T1. The bias voltage VBIAS can be 5V to 6V similar to the data voltage of the black gray level. Therefore, the embodiment of the present disclosure supports preventing the degradation of the first transistor T1 in low-frequency driving.

[0094] The light emitting element EE may include a first electrode and a second electrode. The first electrode of the light emitting element EE may be connected to the second electrode of the sixth transistor T6. The second electrode of the light emitting element EE may receive the second power supply voltage ELVSS. The light emitting element EE may emit light corresponding to the driving current.

[0095] In an embodiment, each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 may be a PMOS transistor. In some aspects, each of the third transistor T3 and the fourth transistor T4 may be an NMOS transistor.

[0096] However, the embodiments of the present disclosure are not limited thereto, and in another embodiment, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 may be an NMOS transistor.

[0097] refer to Figure 2 and Figure 4, the gate driver 200 may include a first stage STG1. Each of the first stages STG1 may include a first gate transistor GT1, a second gate transistor GT2, a third gate transistor GT3, a fourth gate transistor GT4, a fifth gate transistor GT5, a sixth gate transistor GT6, a seventh gate transistor GT7, and a gate capacitor GC1.

[0098] Each of the first stages STG1 may receive a start signal FLM, a first clock signal CLK, a second clock signal CLKB, a high voltage VGH, a low voltage VGL, and a reset signal ESR. In some aspects, each of the first stages STG1 may output a gate signal G.

[0099] In an embodiment, each of the first gate transistor GT1, the second gate transistor GT2, the third gate transistor GT3 and the fourth gate transistor GT4 may be a PMOS transistor. In some aspects, each of the fifth gate transistor GT5, the sixth gate transistor GT6 and the seventh gate transistor GT7 may be an NMOS transistor.

[0100] However, the embodiments of the present disclosure are not limited thereto, and in another embodiment, each of the first gate transistor GT1, the second gate transistor GT2, the third gate transistor GT3, the fourth gate transistor GT4, the fifth gate transistor GT5, the sixth gate transistor GT6 and the seventh gate transistor GT7 may be an NMOS transistor.

[0101] refer to Figure 2 and Figure 5 , the emission driver 500 may include second stages STG2. Each of the second stages STG2 may include first, second, third, fourth, fifth, sixth, and seventh emission transistors ET1, ET2, ET3, ET4, ET5, ET6, and ET7, and an emission capacitor EC1.

[0102] Each of the second stages STG2 may receive a start signal FLM, a first clock signal CLK, a second clock signal CLKB, a high voltage VGH, a low voltage VGL, and a reset signal ESR. In some aspects, each of the second stages STG2 may output an emission control signal EM.

[0103] In an embodiment, each of the first emission transistor ET1, the second emission transistor ET2, the third emission transistor ET3 and the fourth emission transistor ET4 may be a PMOS transistor. In some aspects, each of the fifth emission transistor ET5, the sixth emission transistor ET6 and the seventh emission transistor ET7 may be an NMOS transistor.

[0104] However, the embodiments of the present disclosure are not limited thereto, and in another embodiment, each of the first emission transistor ET1, the second emission transistor ET2, the third emission transistor ET3, the fourth emission transistor ET4, the fifth emission transistor ET5, the sixth emission transistor ET6 and the seventh emission transistor ET7 may be an NMOS transistor.

[0105] In an embodiment, the first stage STG1 and the second stage STG2 may have substantially the same circuit structure. In another embodiment, the first stage STG1 and the second stage STG2 may have different circuit structures.

[0106] Figure 6 It is used to describe one or more embodiments of the present disclosure. Figure 2 A cross-sectional view of a gate driver and / or an emission driver included in a display device. Figure 7 is a diagram illustrating a method of performing a Figure 1 A cross-sectional view of a pixel included in a display device.

[0107] Specifically, Figure 6 It is a graphic Figure 4 The second gate transistor GT2 (or Figure 5 The second emission transistor ET2) and Figure 4 The fifth gate transistor GT5 (or Figure 5 In some aspects, Figure 7 It is a graphic Figure 3 sectional view of the third transistor T3 and the fifth transistor T5.

[0108] refer to Figure 4 , Figure 5 and Figure 6 , display device (e.g., Figure 2 The display device DD) may include a substrate SUB, a blocking layer BAR, a buffer layer BUF, a first gate insulating layer GI1, a second gate insulating layer GI2, a first interlayer insulating layer ILD1, a third gate insulating layer GI3, a second interlayer insulating layer ILD2, a first silicon semiconductor layer PACT1, a first lower gate electrode GE1A, a 1-1 source electrode PSE1, a 1-1 drain electrode PDE1, a first lower metal layer BML1, a first oxide semiconductor layer ACT1, a first upper gate electrode GE3A, a 1-2 source electrode SE1, a 1-2 drain electrode DE1 and a first charge layer CL1.

[0109] The substrate SUB may include a transparent material or an opaque material. The substrate SUB may be formed of a transparent resin substrate. Examples of the transparent resin substrate may include a polyimide substrate. In the example of the polyimide substrate, the polyimide substrate may include a first organic layer, a first barrier layer, a second organic layer, and the like.

[0110] Alternatively or additionally, the substrate SUB may include a quartz substrate (eg, a synthetic quartz substrate, a fluorine-doped quartz substrate), a calcium fluoride substrate, a soda aluminum substrate, or a non-alkali glass substrate, etc. The example materials may be used alone or in combination with each other.

[0111] The barrier layer BAR may be disposed on the substrate SUB. The barrier layer BAR may prevent impurities from penetrating into the upper portion of the substrate SUB from the outside. For example, the barrier layer BAR may include an inorganic material such as, for example, silicon oxide, silicon nitride, or silicon oxynitride. The example materials may be used alone or in combination with each other. In some aspects, the barrier layer BAR may be formed in a single-layer structure or a multi-layer structure.

[0112] The buffer layer BUF may be disposed on the barrier layer BAR. The buffer layer BUF may prevent metal atoms or impurities from diffusing from the substrate SUB into the first silicon semiconductor layer PACT1.

[0113] For example, the buffer layer BUF may include an inorganic material such as, for example, silicon oxide, silicon nitride, or silicon oxynitride, etc. The example materials may be used alone or in combination with each other.

[0114] The first silicon semiconductor layer PACT1 may be disposed on the buffer layer BUF. In an embodiment, the first silicon semiconductor layer PACT1 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon and polycrystalline silicon, etc. For example, the first silicon semiconductor layer PACT1 may include polycrystalline silicon formed by crystallizing amorphous silicon.

[0115] The first silicon semiconductor layer PACT1 may include a first source region PSA1, a first drain region PDA1, and a first channel region PCH1. The first channel region PCH1 may be disposed between the first source region PSA1 and the first drain region PDA1. That is, the first drain region PDA1 may be spaced apart from the first source region PSA1 in the first direction DR1, and the first channel region PCH1 is interposed between the first drain region PDA1 and the first source region PSA1.

[0116] The first gate insulating layer GI1 may be disposed on the buffer layer BUF. The first gate insulating layer GI1 may cover the first silicon semiconductor layer PACT1.

[0117] For example, the first gate insulating layer GI1 may include an inorganic material such as, for example, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxycarbide, etc. The example materials may be used alone or in combination with each other.

[0118] The first lower gate electrode GE1A may be disposed on the first gate insulating layer GI1. In a plan view, the first lower gate electrode GE1A may overlap the first channel region PCH1 of the first silicon semiconductor layer PACT1.

[0119] For example, the first lower gate electrode GE1A may include a metal, an alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material, etc. The example materials may be used alone or in combination with each other.

[0120] Examples of the metal may include silver ("Ag"), molybdenum ("Mo"), aluminum ("Al"), tungsten ("W"), copper ("Cu"), nickel ("Ni"), chromium ("Cr"), titanium ("Ti"), tantalum ("Ta"), platinum ("Pt"), or scandium ("Sc"), etc. The example materials may be used alone or in combination with each other.

[0121] Examples of the conductive metal oxide may include indium tin oxide or indium zinc oxide, etc. The example materials may be used alone or in combination with each other.

[0122] In some aspects, examples of metal nitrides may include aluminum nitride (“AlN x ”), tungsten nitride (“WN x ”) or chromium nitride (“CrN x ”) etc. The exemplary materials may be used alone or in combination with each other.

[0123] The second gate insulating layer GI2 may be disposed on the first gate insulating layer GI1. The second gate insulating layer GI2 may cover the first lower gate electrode GE1A. The second gate insulating layer GI2 may include substantially the same material as the first gate insulating layer GI1.

[0124] The first lower metal layer BML1 may be disposed on the second gate insulating layer GI2. The first lower metal layer BML1 may include substantially the same material as the first lower gate electrode GE1A.

[0125] The first interlayer insulating layer ILD1 may be disposed on the second gate insulating layer GI2. The first interlayer insulating layer ILD1 may cover the first lower metal layer BML1.

[0126] For example, the first interlayer insulating layer ILD1 may include an inorganic material such as, for example, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxycarbide, etc. The example materials may be used alone or in combination with each other.

[0127] The first oxide semiconductor layer ACT1 may be disposed on the first interlayer insulating layer ILD1. In a plan view, the first oxide semiconductor layer ACT1 may overlap the first lower metal layer BML1. The first oxide semiconductor layer ACT1 may include a first source region SA1, a first drain region DA1, and a first channel region CH1. The first channel region CH1 may be disposed between the first source region SA1 and the first drain region DA1. That is, the first drain region DA1 may be spaced apart from the first source region SA1 in the first direction DR1, and the first channel region CH1 is between the first drain region DA1 and the first source region SA1. The first oxide semiconductor layer ACT1 may include an oxide semiconductor.

[0128] In an embodiment, the oxide semiconductor may include an N-type semiconductor. For example, the oxide semiconductor may include zinc oxide ("ZnO"), indium oxide ("In 2 O 3 ”), indium zinc oxide (“IZO”), zinc tin oxide (“ZTO”), indium gallium zinc oxide (“IGZO”), indium tin zinc oxide (“ITZO”), gallium zinc oxide (“GZO”), indium tin oxide (“ITO”), hafnium indium zinc oxide (“HIZO”), or tin oxide (“SnO 2 ”) etc. The exemplary materials may be used alone or in combination with each other.

[0129] In another embodiment, the oxide semiconductor may include a P-type semiconductor. For example, the oxide semiconductor may include tin oxide ("SnO") or copper oxide ("Cu 2 O”), etc. The exemplary materials may be used alone or in combination with each other.

[0130] In an embodiment, the oxide semiconductor may further include indium ("In"), gallium ("Ga"), tin ("Sn"), zirconium ("Zr"), vanadium ("V"), hafnium ("Hf"), cadmium ("Cd"), germanium ("Ge"), chromium ("Cr"), titanium ("Ti"), and zinc ("Zn"). The example materials may be used alone or in combination.

[0131] The third gate insulating layer GI3 may be disposed on the first interlayer insulating layer ILD1. The third gate insulating layer GI3 may cover the first oxide semiconductor layer ACT1. The third gate insulating layer GI3 may include substantially the same material as the first gate insulating layer GI1. For example, a portion of the third gate insulating layer GI3 covering the first oxide semiconductor layer ACT1 may be referred to as a first insulating layer.

[0132] The first upper gate electrode GE3A may be disposed on the third gate insulating layer GI3. In a plan view, the first upper gate electrode GE3A may overlap with the first channel region CH1 of the first oxide semiconductor layer ACT1. The first upper gate electrode GE3A may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material, etc. The example materials may be used alone or in combination with each other. For example, the first upper gate electrode GE3A may be referred to as a first gate electrode.

[0133] The first charge layer CL1 may be disposed between the first upper gate electrode GE3A and the first oxide semiconductor layer ACT1. That is, the first charge layer CL1 may be disposed in the third gate insulating layer GI3. In a plan view, the first charge layer CL1 may overlap at least a portion of the first channel region CH1 of the first oxide semiconductor layer ACT1.

[0134] The second interlayer insulating layer ILD2 may be disposed on the third gate insulating layer GI3. The second interlayer insulating layer ILD2 may cover the first upper gate electrode GE3A. The second interlayer insulating layer ILD2 may include substantially the same material as the first interlayer insulating layer ILD1.

[0135] The 1-1 source electrode PSE1 , the 1-1 drain electrode PDE1 , the 1-2 source electrode SE1 , and the 1-2 drain electrode DE1 may be disposed on the second interlayer insulating layer ILD2 .

[0136] The 1-2 source electrode SE1 may be connected to the first source region SA1 of the first oxide semiconductor layer ACT1. In some aspects, a signal may be input to the 1-2 source electrode SE1. For example, a start signal FLM may be input to the 1-2 source electrode SE1.

[0137] The 1-2 drain electrode DE1 may be connected to the first drain region DA1 of the first oxide semiconductor layer ACT1. In some aspects, a signal may be output to the 1-2 drain electrode DE1. For example, the start signal FLM may be output to the 1-2 drain electrode DE1. Thus, for example, the fifth gate transistor GT5 (and similarly, the fifth emission transistor ET5) may receive a signal (e.g., the start signal FLM) at the 1-2 source electrode SE1 and output the signal via the 1-2 drain electrode DE1.

[0138] The 1-1 drain electrode PDE1 may be connected to the first drain region PDA1 of the first silicon semiconductor layer PACT1. In some aspects, the 1-1 source electrode PSE1 may be connected to the first source region PSA1 of the first silicon semiconductor layer PACT1.

[0139] The 1-1 source electrode PSE1, the 1-1 drain electrode PDE1, the 1-2 source electrode SE1, and the 1-2 drain electrode DE1 may be disposed at the same layer and may include the same material. For example, the 1-1 source electrode PSE1, the 1-1 drain electrode PDE1, the 1-2 source electrode SE1, and the 1-2 drain electrode DE1 may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material, etc. The example materials may be used alone or in combination with each other.

[0140] In an embodiment, the second gate transistor GT2 may include a first silicon semiconductor layer PACT1, a first lower gate electrode GE1A, a 1-1 source electrode PSE1, and a 1-1 drain electrode PDE1. That is, the second gate transistor GT2 may be a PMOS transistor including a silicon semiconductor layer. In some aspects, each of the first gate transistor GT1, the third gate transistor GT3, and the fourth gate transistor GT4 may have substantially the same structure as the second gate transistor GT2. That is, each of the first gate transistor GT1, the third gate transistor GT3, and the fourth gate transistor GT4 may be a PMOS transistor.

[0141] However, the embodiments of the present disclosure are not limited thereto, and in another embodiment, each of the first gate transistor GT1 , the second gate transistor GT2 , the third gate transistor GT3 , and the fourth gate transistor GT4 may be an NMOS transistor.

[0142] In another embodiment, some of the first gate transistor GT1 , the second gate transistor GT2 , the third gate transistor GT3 , and the fourth gate transistor GT4 may be PMOS transistors, and the others may be NMOS transistors.

[0143] The second emission transistor ET2 may have substantially the same structure as the second gate transistor GT2. That is, the second emission transistor ET2 may be a PMOS transistor. In some aspects, each of the first emission transistor ET1, the third emission transistor ET3, and the fourth emission transistor ET4 may have substantially the same structure as the second emission transistor ET2. That is, each of the first emission transistor ET1, the third emission transistor ET3, and the fourth emission transistor ET4 may be a PMOS transistor.

[0144] However, the embodiments of the present disclosure are not limited thereto, and in another embodiment, each of the first emission transistor ET1 , the second emission transistor ET2 , the third emission transistor ET3 , and the fourth emission transistor ET4 may be an NMOS transistor.

[0145] In another embodiment, some of the first emission transistor ET1 , the second emission transistor ET2 , the third emission transistor ET3 , and the fourth emission transistor ET4 may be PMOS transistors, and the others may be NMOS transistors.

[0146] In an embodiment, the fifth gate transistor GT5 may include a first oxide semiconductor layer ACT1, a first upper gate electrode GE3A, a 1-2 source electrode SE1, and a 1-2 drain electrode DE1. That is, the fifth gate transistor GT5 may be an NMOS transistor including an oxide semiconductor layer. In some aspects, each of the sixth gate transistor GT6 and the seventh gate transistor GT7 may have substantially the same structure as the fifth gate transistor GT5. That is, each of the sixth gate transistor GT6 and the seventh gate transistor GT7 may be an NMOS transistor.

[0147] The fifth emission transistor ET5 may have substantially the same structure as the fifth gate transistor GT5. That is, the fifth emission transistor ET5 may be an NMOS transistor. In some aspects, each of the sixth emission transistor ET6 and the seventh emission transistor ET7 may have substantially the same structure as the fifth emission transistor ET5. That is, each of the sixth emission transistor ET6 and the seventh emission transistor ET7 may be an NMOS transistor.

[0148] refer to Figure 3 and Figure 7 The pixel PX may include a substrate SUB, a blocking layer BAR, a buffer layer BUF, a first gate insulating layer GI1, a second gate insulating layer GI2, a first interlayer insulating layer ILD1, a third gate insulating layer GI3, a second interlayer insulating layer ILD2, a second silicon semiconductor layer PACT2, a second lower gate electrode GE1B, a 2-1 source electrode PSE2, a 2-1 drain electrode PDE2, a second lower metal layer BML2, a second oxide semiconductor layer ACT2, a second upper gate electrode GE3B, a 2-2 source electrode SE2, a 2-2 drain electrode DE2 and a second charge layer CL2.

[0149] Figure 3 and Figure 7 The pixel PX includes the Figure 6 In the description of the gate driver and / or emission driver, repeated descriptions of similar elements are omitted for brevity. Figure 3 and Figure 7 When illustrating the cross-sectional structure of the pixel PX, the same reference numerals are given as in Figure 6 The gate driver and / or the emission driver include substantially the same configuration, and a repeated detailed description thereof may be omitted.

[0150] The second silicon semiconductor layer PACT2 may be disposed on the buffer layer BUF. Figure 6 The first silicon semiconductor layer PACT1 includes substantially the same material.

[0151] The second silicon semiconductor layer PACT2 may include a second source region PSA2, a second drain region PDA2, and a second channel region PCH2. The second channel region PCH2 may be disposed between the second source region PSA2 and the second drain region PDA2. That is, the second drain region PDA2 may be spaced apart from the second source region PSA2 in the first direction DR1, and the second channel region PCH2 is interposed between the second drain region PDA2 and the second source region PSA2.

[0152] The second lower gate electrode GE1B may be disposed on the first gate insulating layer GI1. In a plan view, the second lower gate electrode GE1B may overlap with the second channel region PCH2 of the second silicon semiconductor layer PACT2. For example, the second lower gate electrode GE1B may overlap with the second channel region PCH2 of the second silicon semiconductor layer PACT2. Figure 6 The first lower gate electrode GE1A includes substantially the same material.

[0153] The second lower metal layer BML2 may be disposed on the second gate insulating layer GI2. Figure 6 The first lower metal layer BML1 includes substantially the same material.

[0154] The second oxide semiconductor layer ACT2 may be disposed on the first interlayer insulating layer ILD1. In a plan view, the second oxide semiconductor layer ACT2 may overlap the second lower metal layer BML2. The second oxide semiconductor layer ACT2 may include a second source region SA2, a second drain region DA2, and a second channel region CH2. The second channel region CH2 may be disposed between the second source region SA2 and the second drain region DA2. That is, the second drain region DA2 may be spaced apart from the second source region SA2 in the first direction DR1, and the second channel region CH2 is between the second drain region DA2 and the second source region SA2. The second oxide semiconductor layer ACT2 may overlap the second lower metal layer BML2 in a plan view. Figure 6 The first oxide semiconductor layer ACT1 includes substantially the same material.

[0155] The second upper gate electrode GE3B may be disposed on the third gate insulating layer GI3. In a plan view, the second upper gate electrode GE3B may overlap with the second channel region CH2 of the second oxide semiconductor layer ACT2. Figure 6 The first upper gate electrode GE3A includes substantially the same material. For example, the second upper gate electrode GE3B may be referred to as a second gate electrode. In some aspects, a portion of the third gate insulating layer GI3 covering the second oxide semiconductor layer ACT2 may be referred to as a second insulating layer.

[0156] The second charge layer CL2 may be disposed between the second upper gate electrode GE3B and the second oxide semiconductor layer ACT2. That is, the second charge layer CL2 may be disposed in the third gate insulating layer GI3. In a plan view, the second charge layer CL2 may overlap at least a portion of the second channel region CH2 of the second oxide semiconductor layer ACT2.

[0157] The 2-1 source electrode PSE2 , the 2-1 drain electrode PDE2 , the 2-2 source electrode SE2 , and the 2-2 drain electrode DE2 may be disposed on the second interlayer insulating layer ILD2 .

[0158] The 2-2 source electrode SE2 may be connected to the second source region SA2 of the second oxide semiconductor layer ACT2. In some aspects, a signal or voltage may be input to the 2-2 source electrode SE2. For example, the first power supply voltage EVLDD may be input to the 2-2 source electrode SE2.

[0159] The 2-2 drain electrode DE2 may be connected to the second drain region DA2 of the second oxide semiconductor layer ACT2. In some aspects, a signal or voltage may be output to the 2-2 drain electrode DE2. For example, the first power supply voltage ELVDD may be output to the 2-2 drain electrode DE2.

[0160] The 2-1 drain electrode PDE2 may be connected to the second drain area PDA2 of the second silicon semiconductor layer PACT2. In some aspects, the 2-1 source electrode PSE2 may be connected to the second source area PSA2 of the second silicon semiconductor layer PACT2.

[0161] The 2-1 source electrode PSE2, the 2-1 drain electrode PDE2, the 2-2 source electrode SE2, and the 2-2 drain electrode DE2 may be disposed in the same layer and may include the same material. For example, the 2-1 source electrode PSE2, the 2-1 drain electrode PDE2, the 2-2 source electrode SE2, and the 2-2 drain electrode DE2 may include a metal, an alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material, etc. The example materials may be used alone or in combination with each other.

[0162] In an embodiment, the fifth transistor T5 may include a second silicon semiconductor layer PACT2, a second lower gate electrode GE1B, a 2-1 source electrode PSE2, and a 2-1 drain electrode PDE2. That is, the fifth transistor T5 may be a PMOS transistor including a silicon semiconductor layer. In some aspects, each of the first transistor T1, the second transistor T2, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may have substantially the same structure as the fifth transistor T5. That is, each of the first transistor T1, the second transistor T2, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be a PMOS transistor.

[0163] However, the embodiments of the present disclosure are not limited thereto, and in another embodiment, each of the first transistor T1 , the second transistor T2 , the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 , and the eighth transistor T8 may be an NMOS transistor.

[0164] In another embodiment, some of the first transistor T1 , the second transistor T2 , the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 , and the eighth transistor T8 may be PMOS transistors, and the others may be NMOS transistors.

[0165] In an embodiment, the third transistor T3 may include a second oxide semiconductor layer ACT2, a second upper gate electrode GE3B, a 2-2 source electrode SE2, and a 2-2 drain electrode DE2. That is, the third transistor T3 may be an NMOS transistor including an oxide semiconductor layer. In some aspects, the fourth transistor T4 may have substantially the same structure as the third transistor T3. That is, the fourth transistor T4 may be an NMOS transistor.

[0166] Figure 8 is a diagram illustrating one or more embodiments of the present disclosure Figure 6 An enlarged cross-sectional view of an example of region A. Fig. 9 is a diagram illustrating one or more embodiments of the present disclosure Figure 6 An enlarged cross-sectional view of another example of region A.

[0167] refer to Figure 6 and Figure 8 , the first charge layer CL1 may overlap at least a portion of the first channel region CH1 of the first oxide semiconductor layer ACT1. In an embodiment, the first charge layer CL1 may be disposed adjacent to the first source region SA1. In some aspects, the first charge layer CL1 may be disposed such that the first charge layer CL1 is spaced apart from the first drain region DA1.

[0168] In an embodiment, the first charge layer CL1 may be disposed such that the first charge layer CL1 is spaced apart from the first oxide semiconductor layer ACT1. For example, the first charge layer CL1 may be disposed such that the first charge layer CL1 is spaced apart from the first oxide semiconductor layer ACT1 and a portion of the third gate insulating layer GI3 is interposed between the first charge layer CL1 and the first oxide semiconductor layer ACT1. That is, the first charge layer CL1 may not be in contact with the first oxide semiconductor layer ACT1.

[0169] In an embodiment, a width L2 of the first charge layer CL1 in the first direction DR1 may be less than half of a width L1 of the first channel region CH1 of the first oxide semiconductor layer ACT1 in the first direction DR1. In another embodiment (not shown), a width L2 of the first charge layer CL1 in the first direction DR1 may be substantially the same as half of a width L1 of the first channel region CH1 of the first oxide semiconductor layer ACT1 in the first direction DR1.

[0170] refer to Fig. 9 In another embodiment, the width L2 ′ of the first charge layer CL1 ′ may be greater than half the width L1 of the first channel region CH1 of the first oxide semiconductor layer ACT1 .

[0171] Return to reference Figure 6 and Figure 8 , the first charge layer CL1 may include particles PC1. As mentioned herein, in an embodiment, the first oxide semiconductor layer ACT1 may be an N-type semiconductor. In this case, each of the first source region SA1 and the first drain region DA1 may be doped with N-type impurity ions.

[0172] In this case, the particle PC1 may include a negatively charged particle. For example, the particle PC1 may include an electron. However, the embodiment of the present disclosure is not limited thereto, and the particle PC1 may include a particle other than an electron.

[0173] Since the first charge layer CL1 is disposed between the first oxide semiconductor layer ACT1 and the first upper gate electrode GE3A, the threshold voltage of the fifth gate transistor GT5 and / or the fifth emission transistor ET5 can be shifted in the positive direction. Therefore, the embodiment of the present disclosure supports preventing a phenomenon in which the fifth gate transistor GT5 and / or the fifth emission transistor ET5 is turned on when a signal value lower than a specific value is provided to the first upper gate electrode GE3A of the fifth gate transistor GT5 and / or the fifth emission transistor ET5. Therefore, the gate driver (for example, Figure 2 200) and an emission driver (eg, Figure 2 The reliability of the transmit driver 500).

[0174] As mentioned herein, in another embodiment, the first oxide semiconductor layer ACT1 may be a P-type semiconductor. In this case, each of the first source area SA1 and the first drain area DA1 may be doped with P-type impurity ions. In this case, the particles PC1 may include positively charged particles.

[0175] In this case, since the first charge layer CL1 is disposed between the first oxide semiconductor layer ACT1 and the first upper gate electrode GE3A, the threshold voltage of the fifth gate transistor GT5 and / or the fifth emission transistor ET5 may be shifted in a negative direction.

[0176] Fig.10 is a diagram illustrating one or more embodiments of the present disclosure Figure 7 An enlarged cross-sectional view of an example of region B. Fig.11 is a diagram illustrating one or more embodiments of the present disclosure Figure 7 An enlarged cross-sectional view of another example of region B.

[0177] refer to Figure 7 and Fig.10 , the second charge layer CL2 may overlap at least a portion of the second channel region CH2 of the second oxide semiconductor layer ACT2. In an embodiment, the second charge layer CL2 may be disposed adjacent to the second source region SA2. In some aspects, the second charge layer CL2 may be disposed such that the second charge layer CL2 is spaced apart from the second drain region DA2.

[0178] In an embodiment, the second charge layer CL2 may be disposed such that the second charge layer CL2 is spaced apart from the second oxide semiconductor layer ACT2. For example, the second charge layer CL2 may be disposed such that the second charge layer CL2 is spaced apart from the second oxide semiconductor layer ACT2 and a portion of the third gate insulating layer GI3 is interposed between the second charge layer CL2 and the second oxide semiconductor layer ACT2. That is, the second charge layer CL2 may not be in contact with the second oxide semiconductor layer ACT2.

[0179] In an embodiment, a width L4 of the second charge layer CL2 in the first direction DR1 may be less than half of a width L3 of the second channel region CH2 of the second oxide semiconductor layer ACT2 in the first direction DR. In another embodiment (not shown), a width L4 of the second charge layer CL2 in the first direction DR may be substantially the same as half of a width L3 of the second channel region CH2 of the second oxide semiconductor layer ACT2 in the first direction DR.

[0180] refer to Fig.11 In another embodiment, the width L4 ′ of the second charge layer CL2 ′ may be greater than half the width L3 of the second channel region CH2 of the second oxide semiconductor layer ACT2 .

[0181] Return to reference Figure 7 and Fig.10 , the second charge layer CL2 may include particles PC2. In an embodiment, the second oxide semiconductor layer ACT2 may be an N-type semiconductor. In this case, each of the second source region SA2 and the second drain region DA2 may be doped with N-type impurity ions.

[0182] In this case, the particle PC2 may include a negatively charged particle. For example, the particle PC2 may include an electron. However, the embodiment of the present disclosure is not limited thereto, and the particle PC2 may include an electron and other particles.

[0183] Since the second charge layer CL2 is disposed between the second oxide semiconductor layer ACT2 and the second upper gate electrode GE3B, the threshold voltage of the third transistor T3 can be shifted in the positive direction. Therefore, the embodiment of the present disclosure supports preventing a phenomenon in which the third transistor T3 is turned on when a signal value lower than a specific value is provided to the second upper gate electrode GE3B of the third transistor T3. Therefore, the pixel circuit (for example, Figure 3 The reliability of the pixel circuit PXC).

[0184] Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16 is a diagram illustrating a method of manufacturing a Figure 2 A cross-sectional view of a method of including a gate driver and / or an emission driver in a display device.

[0185] In the description of methods and processes herein, operations may be performed in an order different from that shown and / or described, or operations may be performed in a different order or at a different time. Specific operations may also be excluded from methods and processes, one or more operations may be repeated, or other operations may be added. Descriptions of elements "may be set" and "may be formed", etc. include methods, processes and techniques for setting, forming, positioning and modifying elements, etc. according to the example aspects described herein.

[0186] refer to Fig.12, the method may include forming a barrier layer BAR on a substrate SUB. In some aspects, the method may further include forming a buffer layer BUF on the barrier layer BAR. In some aspects, the method may further include forming a first silicon semiconductor layer PACT1 on the buffer layer BUF. The first silicon semiconductor layer PACT1 may include a first source region PSA1, a first drain region PDA1, and a first channel region PCH1. The first channel region PCH1 may be disposed between the first source region PSA1 and the first drain region PDA1.

[0187] The method may further include forming a first gate insulating layer GI1 on the buffer layer BUF. The first gate insulating layer GI1 may be formed such that the first gate insulating layer GI1 covers the first silicon semiconductor layer PACT1.

[0188] The method may further include forming a first lower gate electrode GE1A on the first gate insulating layer GI1. The first lower gate electrode GE1A may be formed such that the first lower gate electrode GE1A overlaps the first channel region PCH1 of the first silicon semiconductor layer PACT1 in a plan view.

[0189] The method may further include forming a second gate insulating layer GI2 on the first gate insulating layer GI1. The second gate insulating layer GI2 may be formed such that the second gate insulating layer GI2 covers the first lower gate electrode GE1A.

[0190] The method may further include forming a first lower metal layer BML1 on the second gate insulating layer GI2. The method may further include forming a first interlayer insulating layer ILD1 on the second gate insulating layer GI2. The first interlayer insulating layer ILD1 may be formed such that the first interlayer insulating layer ILD1 covers the first lower metal layer BML1.

[0191] refer to Fig.13 , the method may further include forming a first oxide semiconductor layer ACT1 on the first interlayer insulating layer ILD1. The first oxide semiconductor layer ACT1 may be formed so that the first oxide semiconductor layer ACT1 overlaps the first lower metal layer BML1 in a plan view. The first oxide semiconductor layer ACT1 may include a first source region SA1, a first drain region DA1, and a first channel region CH1. The first channel region CH1 may be disposed between the first source region SA1 and the first drain region DA1. That is, the first drain region DA1 may be spaced apart from the first source region SA1 in the first direction DR1, and the first channel region CH1 is between the first drain region DA1 and the first source region SA1.

[0192] The method may further include forming a third gate insulating layer GI3 on ​​the first interlayer insulating layer ILD1. The third gate insulating layer GI3 may be formed such that the third gate insulating layer GI3 covers the first oxide semiconductor layer ACT1.

[0193] refer to Fig.14 , the method may further include implanting ions into the third gate insulating layer GI3 by using a mask MK. For example, the mask MK may define a hole H, and the method may further include implanting ions into a portion of the third gate insulating layer GI3 that overlaps the hole H in a plan view. Thus, a first charge layer CL1 may be formed.

[0194] In an embodiment, in a plan view, the hole H may overlap with at least a portion of the first channel region CH1 of the first oxide semiconductor layer ACT1. In some aspects, the hole H may be adjacent to (e.g., adjacent to in a plan view) the first source region SA1 of the first oxide semiconductor layer ACT1. Thus, the method may include selectively injecting ions into a portion of the third gate insulating layer GI3 that overlaps with at least a portion of the first channel region CH1 of the first oxide semiconductor layer ACT1. In some aspects, the method may include selectively injecting ions into a portion of the third gate insulating layer GI3 that is adjacent to the first source region SA1 of the first oxide semiconductor layer ACT1. Thus, the method may include forming the first charge layer CL1 so that the first charge layer CL1 overlaps with at least a portion of the first channel region CH1 of the first oxide semiconductor layer ACT1. In some aspects, the first charge layer CL1 may be formed so that the first charge layer CL1 is disposed adjacent to the first source region SA1 of the first oxide semiconductor layer ACT1.

[0195] In an embodiment, the method may further include forming the first charge layer CL1 so that the first charge layer CL1 is spaced apart from the first oxide semiconductor layer ACT1. For example, the method may further include forming the first charge layer CL1 so that the first charge layer CL1 is spaced apart from the first oxide semiconductor layer ACT1 and the third gate insulating layer GI3 is interposed between the first charge layer CL and the first oxide semiconductor layer ACT1.

[0196] For example, the method may include adjusting the position where the first charge layer CL1 is formed by adjusting the energy of ions injected into the third gate insulating layer GI3 through the hole H, by adjusting the injection amount of ions injected into the third gate insulating layer GI3 through the hole H, and adjusting a combination of the energy and the injection amount, etc. Therefore, the method may include adjusting the position where the first charge layer CL1 is formed so that the first charge layer CL1 is not formed until the first oxide semiconductor layer ACT1.

[0197] For example, the energy of the ions injected into the third gate insulating layer GI3 through the hole H may be about 5 kV or more and 10 kV or less. For example, the energy of the ions may range from about 5 kV to about 10 kV. However, the embodiments of the present disclosure are not limited to the example range, and the energy of the ions may be appropriately changed.

[0198] In some aspects, the amount of ions implanted into the third gate insulating layer GI3 through the hole H may be about 3e11 ions / cm 2 Above and about 3e12 ions / cm 2 For example, the implant volume can range from about 3e11 ions / cm 2 to about 3e12 ions / cm 2 However, the embodiments of the present disclosure are not limited to the exemplary range, and the implantation amount of ions may be appropriately changed.

[0199] refer to Fig.15 The method may further include forming a first upper gate electrode GE3A on the third gate insulating layer GI3. The method may further include forming the first upper gate electrode GE3A so that the first upper gate electrode GE3A overlaps the first channel region CH1 of the first oxide semiconductor layer ACT1 in a plan view.

[0200] refer to Fig.16 , the method may further include forming a 1-1 source electrode PSE1 , a 1-1 drain electrode PDE1 , a 1-2 source electrode SE1 , and a 1-2 drain electrode DE1 on the second interlayer insulating layer ILD2 .

[0201] refer to Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16 A method of manufacturing a gate driver and / or an emission driver according to one or more embodiments of the present disclosure is described, but the embodiments of the present disclosure are not limited thereto, and the method of manufacturing a gate driver and / or an emission driver according to one or more embodiments of the present disclosure is described. Figure 7 The method of manufacturing a pixel of the embodiment of the present invention may be substantially the same as the method of manufacturing a gate driver and / or an emission driver described above.

[0202] The present disclosure can be applied to various display devices. For example, the present disclosure can be applied to various display devices such as display devices for vehicles, ships and aircraft, portable communication devices, display devices for exhibitions or information transmission, and medical display devices.

[0203] Terms such as, for example, "first" and "second" may be used to describe various components, but these components should not be limited by these terms. The terms used herein may distinguish one component from other components, and the components will not be limited by the terms. For example, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component without departing from the scope of the present disclosure. Terms in the singular may include plural forms unless otherwise specified.

[0204] The terms used herein are only for the purpose of describing specific embodiments and are not intended to be limited. As used herein, "one", "the" and "at least one" do not represent the limitation of quantity, and are intended to include both the singular and the plural, unless the context clearly indicates otherwise. For example, "an element" has the same meaning as "at least one element", unless the context clearly indicates otherwise. "At least one" will not be interpreted as being limited to "one". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more of the items listed in association. It will be further understood that when used in this specification, the term "comprising" and / or "including" indicates the existence of stated features, regions, wholes, steps, operations, elements and / or parts, but does not exclude the existence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and / or their groups.

[0205] The terms "about" or "approximately" as used herein include the stated value and include an appropriate deviation range for the specific value determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0206] As used herein, the term "substantially equal" means approximately equal or substantially equal (e.g., within a threshold percentage of being equal). As used herein, the term "substantially simultaneous" means approximately simultaneous or substantially simultaneous (e.g., within a threshold percentage of being simultaneous). As used herein, the term "substantially identical" means approximately identical or substantially identical (e.g., within a threshold difference).

[0207] For ease of description, spatially relative terms such as "below," "below," "down," "above," "upper," etc. may be used herein to describe the relationship of one element or feature relative to another (or some) element or feature as illustrated in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the accompanying drawings, the spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the accompanying drawings is turned over, the elements described as being "below" or "below" other elements or features will then be oriented to be "above" the other elements or features. Therefore, the term "below" can cover both above and below. The device can be oriented in other ways (rotated 90 degrees or oriented in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0208] In this article, embodiments are described with reference to schematically illustrated cross-sectional diagrams of idealized embodiments. In this way, variations in the shapes of the diagrams due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the embodiments described herein should not be interpreted as being limited to the specific shapes of the zones illustrated herein, but should include deviations in shapes due to, for example, manufacturing. For example, a zone illustrated or described as flat may typically have rough and / or nonlinear features. In addition, the illustrated sharp corners may be rounded. Therefore, the zones illustrated in the drawings are schematic in nature, and the shapes of the zones illustrated in the drawings are not intended to illustrate the precise shapes of the zones and are not intended to limit the scope of the claims.

[0209] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense, unless specifically defined as such herein.

[0210] It should be understood that the various embodiments of the present disclosure and the terms used in the various embodiments are not intended to limit the technical features set forth herein to specific embodiments, but include various changes, equivalents or replacements of the corresponding embodiments. Regarding the description of the accompanying drawings, similar figure numerals may be used to refer to similar or related elements. It will be understood that the singular form of the noun corresponding to the project may include one or more of the things, unless the relevant context clearly indicates otherwise. As used herein, each of the phrases such as "A or B", "at least one of A and B", "A, B or C", and "at least one of A, B, and C" may include any one or all possible combinations of the items listed together in the corresponding one in the phrase.

[0211] It will be understood that if an element (e.g., a first element) is referred to as being “coupled with”, “coupled to”, “connected with” or “connected to” another element (e.g., a second element), regardless of whether the terms “operably” or “communicatively” are used, this means that the element can be coupled to the other element directly (e.g., wired), wirelessly, or via a third element.

[0212] The foregoing is illustrative of example embodiments and will not be construed as limiting the example embodiments. Although some embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications to the embodiments are possible without substantially departing from the novel teachings and advantages of the aspects and features supported by the present disclosure. Therefore, all such modifications are intended to be included within the scope of the aspects and features supported by the present disclosure as defined in the claims. Therefore, it will be understood that the foregoing is illustrative of various example embodiments and will not be construed as being limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the claims.

Claims

1. A display device, comprising: Pixels; and driver, electrically connected to the pixel, Wherein, the driver comprises: a first oxide semiconductor layer including a first source region, a first drain region, and a first channel region disposed between the first source region and the first drain region; a first gate electrode provided on the first oxide semiconductor layer and overlapping with the first channel region of the first oxide semiconductor layer in a plan view; and A first charge layer is provided between the first gate electrode and the first oxide semiconductor layer and overlaps at least a portion of the first channel region in the plan view.

2. The display device according to claim 1, wherein: The first charge layer is disposed adjacent to the first source region of the first oxide semiconductor layer.

3. The display device according to claim 1, further comprising: a first insulating layer covering the first oxide semiconductor layer, Wherein, the first charge layer is arranged in the first insulating layer.

4. The display device according to claim 3, wherein: The first charge layer is disposed such that the first charge layer is spaced apart from the first oxide semiconductor layer and a portion of the first insulating layer is interposed between the first charge layer and the first oxide semiconductor layer.

5. The display device according to claim 1, wherein: The first source region of the first oxide semiconductor layer and the first drain region of the first oxide semiconductor layer are spaced apart from each other in a first direction, and the first channel region of the first oxide semiconductor layer is interposed between the first source region and the first drain region, and A width of the first charge layer in the first direction is less than or equal to half a width of the first channel region of the first oxide semiconductor layer in the first direction.

6. The display device according to claim 1, wherein: The first oxide semiconductor layer includes an N-type semiconductor.

7. The display device according to any one of claims 1 to 6, wherein: The pixel comprises a pixel circuit, and The pixel circuit comprises: a second oxide semiconductor layer including a second source region, a second drain region, and a second channel region disposed between the second source region and the second drain region; a second gate electrode provided on the second oxide semiconductor layer and overlapping with the second channel region of the second oxide semiconductor layer in the plan view; and A second charge layer is provided between the second gate electrode and the second oxide semiconductor layer and overlaps at least a portion of the second channel region of the second oxide semiconductor layer in the plan view.

8. A method for manufacturing a display device, the method comprising: forming a driver electrically connected to the pixel, Wherein, forming the driver comprises: forming an oxide semiconductor layer including a source region, a drain region, and a channel region disposed between the source region and the drain region on a substrate; forming an insulating layer covering the oxide semiconductor layer; forming a charge layer in the insulating layer that overlaps with at least a portion of the channel region of the oxide semiconductor layer in a plan view; and A gate electrode is formed which is provided on the insulating layer and overlaps with the channel region of the oxide semiconductor layer in the plan view.

9. The method according to claim 8, wherein: Forming the charge layer includes implanting ions into the insulating layer using a mask.

10. The method according to claim 9, wherein: Implanting the ions includes selectively implanting the ions into a portion of the insulating layer overlapping the channel region of the oxide semiconductor layer and adjacent to the source region of the oxide semiconductor layer in the plan view using the mask.

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