Display panel and display device

Abstract

The invention provides a display panel and a display device, the display panel comprises a substrate, and a shading layer, a first semiconductor layer and a second semiconductor layer which are arranged on the substrate, the first semiconductor layer is provided with a first active part of a driving transistor, and the second semiconductor layer is provided with a second active part of a driving transistor; a third active part of the compensation transistor and a fourth active part of the first initialization transistor are formed on the second semiconductor layer, the light shielding layer comprises a first light shielding pattern, a second light shielding pattern and a third light shielding pattern which are arranged at intervals in the first direction, and a first light shielding part on the first light shielding pattern can shield the first active part; a second shading part on the second shading pattern can shade the third active part, and a third shading part on the third shading pattern can shade the fourth active part, so that the third active part of the compensation transistor and the fourth active part of the first initialization transistor are prevented from being influenced by light; therefore, the photosensitivity and the electrical property of the compensation transistor and the first initialization transistor are improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display devices, the requirements for power consumption and screen-to-body ratio of existing display devices are getting higher and higher. In order to reduce power consumption and increase screen-to-body ratio, existing display devices will use low-temperature polysilicon oxide (LTPO) technology. LTPO technology refers to the simultaneous use of low-temperature polysilicon thin-film transistors and oxide thin-film transistors, so that the driving circuit takes into account the advantages of low-temperature polysilicon thin-film transistors and oxide thin-film transistors, thereby reducing power consumption and leakage current.

[0003] Existing display devices using LTPO technology have a large number of film layers, and the corresponding number of mask plates required is large, resulting in a complex process and high cost. In order to reduce the number of mask plates, existing display devices will remove some gate layers and insulating layers, but this will result in the loss of the bottom gate of the oxide thin film transistor, and the photosensitivity and electrical properties of the thin film transistor will deteriorate.

[0004] Therefore, existing display devices using LTPO technology have technical problems such as poor photosensitivity and electrical properties caused by the absence of the bottom gate of the oxide thin film transistor. Summary of the invention

[0005] The present application provides a display panel and a display device to alleviate the technical problem of poor photosensitivity and electrical properties caused by the bottom gate loss of oxide thin film transistors in existing display devices using LTPO technology.

[0006] To solve the above problems, the technical solutions provided by this application are as follows:

[0007] In a first aspect, an embodiment of the present application provides a display panel, comprising a substrate and a plurality of sub-pixels arranged on the substrate, each of the sub-pixels comprising a driving transistor, a switching transistor, a compensation transistor and a first initialization transistor, the switching transistor and the driving transistor are connected to a first node; an electrode of the compensation transistor, an electrode of the first initialization transistor and the driving transistor are connected to a second node, another electrode of the compensation transistor and the driving transistor are connected to a third node, a gate of the compensation transistor is connected to a first scanning signal line, and a gate of the first initialization transistor is connected to a second scanning signal line; the display panel further comprises:

[0008] A light shielding layer, disposed on one side of the substrate;

[0009] A first semiconductor layer, disposed on a side of the light shielding layer away from the substrate, the first semiconductor layer comprising a first active portion of the driving transistor and a second active portion of the switching transistor;

[0010] a second semiconductor layer, disposed on a side of the first semiconductor layer away from the substrate, the second semiconductor layer comprising a third active portion of the compensation transistor and a fourth active portion of the first initialization transistor;

[0011] Among them, the light shading layer includes a first light shading pattern, a second light shading pattern and a third light shading pattern which are arranged at intervals in a first direction, the first light shading pattern, the second light shading pattern and the third light shading pattern all extend along a second direction, the second direction is different from the first direction, the second light shading pattern is connected to the first scanning signal line, the third light shading pattern is connected to the second scanning signal line, the first light shading pattern includes a first light shading portion arranged corresponding to the first active portion, the second light shading pattern includes a second light shading portion arranged corresponding to the third active portion, and the third light shading pattern includes a third light shading portion arranged corresponding to the fourth active portion.

[0012] In a second aspect, an embodiment of the present application further provides a display device, which includes a display panel as described in one of the aforementioned embodiments.

[0013] The beneficial effects of the present application are as follows: in the display panel and the display device provided by the present application, the display panel includes a substrate and a light shielding layer, a first semiconductor layer, and a second semiconductor layer arranged on the substrate, the first semiconductor layer forms a first active part of a driving transistor, the second semiconductor layer forms a third active part of a compensation transistor and a fourth active part of a first initialization transistor, the gate of the compensation transistor is connected to the first scanning signal line, the gate of the first initialization transistor is connected to the second scanning signal line, the light shielding layer includes a first light shielding pattern, a second light shielding pattern, and a third light shielding pattern spaced apart in a first direction, the first light shielding part on the first light shielding pattern can shield the first active part, the second light shielding part on the second light shielding pattern can shield the third active part, and the third light shielding part on the third light shielding pattern can shield the fourth active part, so as to avoid the compensation transistor from being blocked. The third active portion of the body tube and the fourth active portion of the first initialization transistor are affected by light, thereby improving the photosensitivity and electrical properties of the compensation transistor and the first initialization transistor, so as to improve the problem of poor photosensitivity and electrical properties caused by the missing bottom gate of the oxide thin film transistor in the display device using LTPO technology; and the second shading pattern is connected to the first scanning signal line, and the third shading pattern is connected to the second scanning signal line, so that the second shading pattern and the third shading pattern can respectively serve as the bottom gate of the compensation transistor and the first initialization transistor while realizing the shading function, thereby improving the gate control capability of the transistor. At the same time, the second shading pattern is connected to the first scanning signal line, and the third shading pattern is connected to the second scanning signal line, which can improve the problem of threshold voltage offset compared to connecting other signal lines (such as high-potential power lines). BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0015] Figure 1 A schematic diagram of a first comparative display device provided in an embodiment of the present application.

[0016] Figure 2 A schematic diagram of a second comparative display device provided in an embodiment of the present application.

[0017] Figure 3 A schematic diagram of a third comparative display device provided in an embodiment of the present application.

[0018] Figure 4 A schematic diagram of a film layer of a display panel provided in an embodiment of the present application.

[0019] Figure 5 A circuit diagram of a sub-pixel of a display panel provided in an embodiment of the present application.

[0020] Figure 6 A first stacking diagram of a portion of film layers of a display panel provided in an embodiment of the present application.

[0021] Figure 7 for Figure 6 Exploded view of the light shielding layer of the display panel.

[0022] Figure 8 for Figure 6 An exploded view of the first semiconductor layer of the display panel in FIG.

[0023] Fig. 9 for Figure 8 The first semiconductor layer and Figure 7 Schematic diagram of the stacking of the middle light-shielding layer.

[0024] Fig.10 for Figure 6 An exploded view of the first gate layer of the display panel in FIG.

[0025] Fig.11 for Fig.10 The first gate layer and Fig. 9 Schematic diagram of the stacking of the structure.

[0026] Fig.12 for Figure 6 An exploded view of the second semiconductor layer of the display panel in FIG.

[0027] Fig.13 for Fig.12 The second semiconductor layer Fig.11 Schematic diagram of the stacking of the structure.

[0028] Fig.14 for Figure 6 An exploded view of the second gate layer of the display panel in FIG.

[0029] Fig.15 for Fig.14 The second gate layer and Fig.13 Schematic diagram of the stacking of the structure.

[0030] Fig.16 for Figure 6 An exploded view of the first source-drain layer of the display panel in FIG.

[0031] Fig.17 for Fig.16 The first source and drain layer Fig.15 Schematic diagram of the stacking of the structure.

[0032] Fig.18 for Figure 6 An exploded view of the second source-drain layer of the display panel in FIG. DETAILED DESCRIPTION

[0033] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be implemented in. The directional terms mentioned in the present application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present application, rather than to limit the present application. In the figures, units with similar structures are represented by the same reference numerals. In the accompanying drawings, the thickness of some layers and regions is exaggerated for clear understanding and ease of description. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited to this.

[0034] Please refer to Figures 1 to 3 As an introduction to the embodiments of the present application, some comparative display devices are provided. Figure 1 A schematic diagram of a first comparative display device provided in an embodiment of the present application, Figure 2 A schematic diagram of a second comparative display device provided in an embodiment of the present application, Figure 3 This is a schematic diagram of a third comparative display device provided in an embodiment of the present application. Figure 1 A comparative display device using LTPO technology includes a substrate 101, a light shielding film 102, a barrier film 103, a buffer film 104, a low-temperature polysilicon film 105, a first gate insulating film 106, a first gate film 107, a second gate insulating film 108, a second gate film 109, a first interlayer insulating film 111, an oxide semiconductor film 112, a third gate insulating film 113, a third gate film 114, a second interlayer insulating film 115, a first source-drain film 116, a first planarizing film 117, a second source-drain film 118, a second planarizing film 119, a third source-drain film 121, a third planarizing film 122, an anode film 123, a pixel definition film 124, and a support film 125. Figure 1 It can be seen that the comparative display device includes three layers of source and drain films and three layers of gate films, so that the comparative display device needs to be formed using 16 mask plates, the process is relatively complex and the cost is relatively high.

[0035] In order to solve the problem of complex process of the comparative display device, another comparative display device removes one layer of the gate film and the insulating film, such as Figure 2 As shown, it can be seen that the second gate film 109 and the second gate insulating film 108 are removed from the comparative display device, so that the number of mask plates can be reduced to 14, but there are still problems such as a large number of mask plates, a complex process, and a high cost.

[0036] In order to solve the problem of complex process of the comparative display device, another comparative display device further removes a layer of source and drain film and insulating film, such as Figure 3 As shown in FIG. 1 , by removing the third source-drain film 121 and the third planarization film 122, the number of mask plates can be reduced to 13; Figure 2 , Figure 3 It can be seen that there is no shielding under the oxide semiconductor film 112, resulting in the missing bottom gate of the oxide thin film transistor, and the photosensitivity and electrical properties of the thin film transistor are deteriorated.

[0037] To this end, the present application provides a display panel and a display device, please refer to Figures 1 to 14 , Figure 4 A schematic diagram of a film layer of a display panel provided in an embodiment of the present application. Figure 5 A circuit diagram of a sub-pixel of a display panel provided in an embodiment of the present application. Figure 6 A first stacking diagram of a portion of film layers of a display panel provided in an embodiment of the present application. Figure 7 for Figure 6 Exploded view of the light shielding layer of the display panel. Figure 8 for Figure 6 An exploded view of the first semiconductor layer of the display panel in FIG. Fig. 9 for Figure 8 The first semiconductor layer and Figure 7 Schematic diagram of the stacking of the middle light-shielding layer. Fig.10 for Figure 6 An exploded view of the first gate layer of the display panel in FIG. Fig.11 for Fig.10 The first gate layer and Fig. 9 Schematic diagram of the stacking of the structure. Fig.12 for Figure 6 An exploded view of the second semiconductor layer of the display panel in FIG. Fig.13 for Fig.12 The second semiconductor layer Fig.11 Schematic diagram of the stacking of the structure. Fig.14 for Figure 6 An exploded view of the second gate layer of the display panel in FIG. Fig.15 for Fig.14 The second gate layer and Fig.13 Schematic diagram of the stacking of the structure. Fig.16 for Figure 6 An exploded view of the first source-drain layer of the display panel in FIG. Fig.17 for Fig.16 The first source and drain layer Fig.15 Schematic diagram of the stacking of the structure. Fig.18 for Figure 6 An exploded view of the second source-drain layer of the display panel in FIG.

[0038] Reference Figures 4 to 18The display panel 2 includes a substrate 201 and a plurality of sub-pixels 31 disposed on the substrate 201. Each sub-pixel 31 includes a switch transistor T2, a drive transistor T1, a compensation transistor T3 and a first initialization transistor T4. The switch transistor T2 and the drive transistor T1 are connected to a first node A. One electrode of the compensation transistor T3, one electrode of the first initialization transistor T4 and the drive transistor T1 are connected to a second node Q. The other electrode of the compensation transistor T3 and the drive transistor T1 are connected to a third node B. The gate of the compensation transistor T3 is connected to the first scan signal line Nscan1, and the gate of the first initialization transistor T4 is connected to the second scan signal line Nscan2.

[0039] The display panel 2 further includes a light shielding layer 202 , a first semiconductor layer 207 and a second semiconductor layer 212 disposed on the substrate 201 . The light shielding layer 202 is disposed between the substrate 201 and the first semiconductor layer 207 , and the first semiconductor layer 207 is disposed between the light shielding layer 202 and the second semiconductor layer 212 .

[0040] The first semiconductor layer 207 is disposed on a side of the light shielding layer 202 away from the substrate 201 . The first semiconductor layer 207 includes a first active portion T1A of the driving transistor T1 and a second active portion T2A of the switching transistor T2 .

[0041] The second semiconductor layer 212 is disposed on a side of the first semiconductor layer 207 away from the substrate 201 , and the second semiconductor layer 212 includes a third active portion T3A of the compensation transistor T3 and a fourth active portion T4A of the first initialization transistor T4 .

[0042] The light shielding layer 202 includes a first light shielding pattern 202a, a second light shielding pattern 202b, and a third light shielding pattern 202c that are spaced apart in the first direction Y, and the first light shielding pattern 202a, the second light shielding pattern 202b, and the third light shielding pattern 202c all extend along the second direction X. The second light shielding pattern 202b is connected to the first scan signal line Nscan1, and the third light shielding pattern 202c is connected to the second scan signal line Nscan2. The first light shielding pattern 202a includes a first light shielding portion 311 disposed corresponding to the first active portion T1A, the second light shielding pattern 202b includes a second light shielding portion 313 disposed corresponding to the third active portion T3A, and the third light shielding pattern 202c includes a third light shielding portion 315 disposed corresponding to the fourth active portion T4A. The first direction Y and the second direction X are different. For example, the first direction Y is a vertical direction and the second direction X is a horizontal direction, that is, the first direction Y is a column direction and the second direction X is a row direction. Of course, the present application is not limited thereto. In the present application, the first direction Y and the second direction X may also be at other angles, such as an angle greater than 0 degrees and less than 90 degrees.

[0043] In the display panel 2 provided in the embodiment of the present application, the display panel 2 includes a substrate 201 and a light shielding layer 202, a first semiconductor layer 207, and a second semiconductor layer 212 arranged on the substrate 201. The first semiconductor layer 207 forms a first active portion T1A of a driving transistor T1, and the second semiconductor layer 212 forms a third active portion T3A of a compensation transistor T3 and a fourth active portion T4A of a first initialization transistor T4. The light shielding layer 202 includes a first light shielding pattern 202a, a second light shielding pattern 202b, and a third light shielding pattern 202c arranged at intervals along a first direction Y. The first light shielding pattern 202a has a first active portion T1A of a driving transistor T1, and the second semiconductor layer 212 has a third active portion T3A of a compensation transistor T3 and a fourth active portion T4A of a first initialization transistor T4. The light shielding layer 202 includes a first light shielding pattern 202a, a second light shielding pattern 202b, and a third light shielding pattern 202c. The shading portion 311 can shield the first active portion T1A, the second shading portion 313 on the second shading pattern 202b can shield the third active portion T3A, and the third shading portion 315 on the third shading pattern 202c can shield the fourth active portion T4A, thereby preventing the third active portion T3A of the compensation transistor T3 and the fourth active portion T4A of the first initialization transistor T4 from being affected by light, thereby improving the photosensitivity and electrical properties of the compensation transistor T3 and the first initialization transistor T4, so as to improve the problem of poor photosensitivity and electrical properties caused by the bottom gate missing of the oxide thin film transistor in the display device using LTPO technology.

[0044] Specifically, in the embodiment of the present application, the light-shielding portion on the light-shielding pattern formed by the light-shielding layer 202 is arranged corresponding to the active portion of the transistor, which means that the light-shielding portion is at least arranged corresponding to the channel portion of the active portion of the transistor, and the projection of the light-shielding portion on the substrate 201 overlaps with the projection of the channel portion of the transistor on the substrate 201. It can be understood that the active portion of each transistor includes a doping portion and a channel portion, and the channel portion is easily affected by light and causes performance changes. Therefore, the light-shielding portion can be arranged corresponding to the channel portion of the transistor. Specifically, for example, the second light-shielding portion 313 is arranged corresponding to the third active portion T3A of the compensation transistor T3, which means that the second light-shielding portion 313 is at least arranged corresponding to the third channel portion of the compensation transistor T3.

[0045] The first light shielding portion 311 is disposed corresponding to the first active portion T1A of the driving transistor T1 , the second light shielding portion 313 is disposed corresponding to the third active portion T3A of the compensation transistor T3 , and the third light shielding portion 315 is disposed corresponding to the fourth active portion T4A of the first initialization transistor T4 .

[0046] Specifically, the orthographic projection of the first active portion T1A of the driving transistor T1 on the substrate 201 is located within the orthographic projection of the first light shielding portion 311 on the substrate 201, the orthographic projection of the third active portion T3A of the compensation transistor T3 on the substrate 201 is located within the orthographic projection of the second light shielding portion 313 on the substrate 201, and the orthographic projection of the fourth active portion T4A of the first initialization transistor T4 on the substrate 201 is located within the orthographic projection of the third light shielding portion 315 on the substrate 201, thereby preventing light from irradiating the first active portion T1A of the driving transistor T1, the third active portion T3A of the compensation transistor T3, and the fourth active portion T4A of the first initialization transistor T4, thereby improving the electrical properties and photosensitivity of the driving transistor T1, the compensation transistor T3, and the first initialization transistor T4.

[0047] Specifically, the area of ​​the first light-shielding portion 311 can be greater than or equal to the area of ​​the first active portion T1A of the driving transistor T1, the area of ​​the second light-shielding portion 313 can be greater than or equal to the area of ​​the third active portion T3A of the compensation transistor T3, and the area of ​​the third light-shielding portion 315 can be greater than or equal to the area of ​​the fourth active portion T4A of the first initialization transistor T4.

[0048] Reference Figure 6 , Figure 7 and Figure 8 , a plurality of first light shielding portions 311 are arranged at intervals in the second direction X, a plurality of second light shielding portions 313 are arranged at intervals in the second direction X, and a plurality of third light shielding portions 315 are arranged at intervals in the second direction X. The first light shielding pattern 202a further includes first connecting lines 312a and 312b connected between two adjacent first light shielding portions 311, the second light shielding pattern 202b further includes a second connecting line 314a connected between two adjacent second light shielding portions 313, and the third light shielding pattern 202c further includes a third connecting line 316a connected between two adjacent third light shielding portions 315. The first connecting lines 312a and 312b, the second connecting line 314a and the third connecting line 316a are sequentially arranged at intervals in the first direction Y.

[0049] The display panel 2 also includes a plurality of repeating units 30 arranged in an array on the substrate 201, each repeating unit 30 includes two mirror-symmetrical sub-pixels 31, two mirror-symmetrical first light-shielding portions 311, two mirror-symmetrical second light-shielding portions 313, and two mirror-symmetrical third light-shielding portions 315; within the same repeating unit 30, the first connecting line connecting the two first light-shielding portions 311 is a first-type first connecting line 312a, the second connecting line connecting the two second light-shielding portions 313 is a first-type second connecting line, and the third connecting line connecting the two third light-shielding portions 315 is a first-type third connecting line. In the second direction X, the length of the first-type first connecting line 312a is less than the length of the first-type second connecting line 314a, and the length of the first-type first connecting line 312a is less than the length of the first-type third connecting line 316a.

[0050] The first connecting line connecting the first shading parts 311 in two adjacent repeating units 30 is the second type first connecting line 312b. Of course, the second connecting line 314a and the third connecting line 316a are also divided into connecting lines connecting two adjacent repeating units 30. For example, the second connecting line connecting the second shading parts 313 in two adjacent repeating units 30 is the second type second connecting line, and the third connecting line connecting the third shading parts 315 in two adjacent repeating units 30 is the second type third connecting line. In the second direction X, the second type first connecting line 312b is staggered with the first type first connecting line 312a. The first type second connecting line 314a includes a recessed portion 321 arranged near the first type first connecting line 312a, and the recessed portion 321 is arranged corresponding to the gap between the two adjacent first shading parts 311.

[0051] The adjacent second light shielding portions 313 and the third light shielding portions 315 overlap in the first direction Y. In the repeating unit 30, the first light shielding portion 311 is arranged corresponding to the gap between two adjacent second light shielding portions 313, and in the first direction Y, the first light shielding portion 311 partially overlaps with the second light shielding portion 313, and the first light shielding portion 311 partially overlaps with the third light shielding portion 315.

[0052] The gate of the compensation transistor T3 is connected to the first scanning signal line Nscan1, the gate of the first initialization transistor T4 is connected to the second scanning signal line Nscan2, the second shading pattern 202b is connected to the first scanning signal line Nscan1, the third shading pattern 202c is connected to the second scanning signal line Nscan2, and the first shading pattern 202a is connected to the high potential power line VDD. In this way, by arranging the first light shading pattern 202a, the second light shading pattern 202b and the third light shading pattern 202c at intervals in the first direction Y, the first light shading pattern 202a, the second light shading pattern 202b and the third light shading pattern 202c are insulated from each other, so that different signals can be connected to the first light shading pattern 202a, the second light shading pattern 202b and the third light shading pattern 202c, thereby avoiding the negative threshold voltage bias of the compensation transistor T3 and the first initialization transistor T4 when the second light shading pattern 202b and the third light shading pattern 202c are connected to the same high-potential power supply signal as the first light shading pattern 202a.

[0053] Specifically, it can be understood that the display panel 2 includes a plurality of repeating units 30 arranged in an array, and the sub-pixels 31 in each repeating unit 30 can refer to the design in a repeating unit 30 in the embodiment of the present application.

[0054] In some embodiments, Figure 5 As shown, the gate of the switch transistor T2 is connected to the third scan signal line Pscan, the first electrode of the switch transistor T2 is connected to the data line DATA, and the second electrode of the switch transistor T2 is connected to the first electrode of the driving transistor T1 at the first node A; the gate of the compensation transistor T3 is connected to the first scan signal line Nscan1, the first electrode of the compensation transistor T3 is connected to the gate of the driving transistor T1 at the second node Q, and the second electrode of the compensation transistor T3 is connected to the second electrode of the driving transistor T1; the gate of the first initialization transistor T4 is connected to the second scan signal line Nscan2, the first electrode of the first initialization transistor T4 is connected to the first initialization signal line VI-G, and the second electrode of the first initialization transistor T4 is connected to the gate of the driving transistor T1 at the second node B; the sub-pixel 31 also includes:

[0055] A first light emitting control transistor T5, wherein a gate of the first light emitting control transistor T5 is connected to the light emitting control signal line EM, a first electrode of the first light emitting control transistor T5 is connected to the high potential power line VDD, and a second electrode of the first light emitting control transistor T5 is connected to the first electrode of the driving transistor T1 to the first node A;

[0056] A second light emission control transistor T6, wherein a gate of the second light emission control transistor T6 is connected to the light emission control signal line EM, and a first electrode of the second light emission control transistor T6 and a second electrode of the driving transistor T1 are connected to a third node B;

[0057] a second initialization transistor T7, wherein a gate of the second initialization transistor T7 is connected to the fourth scan signal line Pscan2, a first electrode of the second initialization transistor T7 is connected to the second initialization signal line VI-ANO, and a second electrode of the second initialization transistor T7 is connected to the second electrode of the second light emission control transistor T6 to a fourth node C;

[0058] a third initialization transistor T8, wherein the gate of the third initialization transistor T8 is connected to the fourth scan signal line Pscan2, the first electrode of the third initialization transistor T8 is connected to the third initialization signal line VI3, and the second electrode of the third initialization transistor T8 is connected to the first electrode of the driving transistor T1 to the first node A;

[0059] A storage capacitor Cst, one plate of the storage capacitor Cst is connected to the high potential power line VDD, and the other plate of the storage capacitor Cst is connected to the gate of the driving transistor T1 at the second node Q;

[0060] A boost capacitor Cboost, one plate of the boost capacitor Cboost is connected to the third scan signal line Pscan, and the other plate of the boost capacitor Cboost is connected to the second electrode of the first initialization transistor T4.

[0061] Specifically, Figure 4 , Figure 5 As shown, the display panel 2 further includes a light emitting layer 23, which includes a light emitting device LED, whose anode is connected to the second electrode of the second initialization transistor T7, and whose cathode is connected to the low potential power line VSS.

[0062] In some embodiments, Figure 4 As shown, the display panel 2 further includes a first gate layer 209, a second gate layer 214, a first source-drain electrode layer 216, and a second source-drain electrode layer 218. The first gate layer 209 is disposed between the first semiconductor layer 207 and the second semiconductor layer 212, the second gate layer 214 is disposed between the second semiconductor layer 212 and the first source-drain electrode layer 216, and the first source-drain electrode layer 216 is disposed between the second gate layer 214 and the second source-drain electrode layer 218. By making the display panel include the first gate layer 209, the second gate layer 214, the first source-drain electrode layer 216, and the second source-drain electrode layer 218, the process steps of the display panel can be reduced, and the mask plates required to form the display panel can be reduced.

[0063] In some embodiments, Figures 4 to 6 , Figure 8 , Fig. 9 As shown, the first semiconductor layer 207 includes a first active portion T1A of the driving transistor T1, a second active portion T2A of the switching transistor T2, a fifth active portion T5A of the first light emission control transistor T5, a sixth active portion T6A of the second light emission control transistor T6, a seventh active portion T7A of the second initialization transistor T7, and an eighth active portion T8A of the third initialization transistor T8. The first light shielding portion 311 on the first light shielding pattern 202a is arranged corresponding to the first active portion T1A, as shown in FIG. Fig. 9 The first active portion T1A of the driving transistor T1 is arranged along the second direction X, and the first active portion T1A of the driving transistor T1 is connected to the second active portion T2A of the switching transistor T2, the fifth active portion T5A of the first light emission control transistor T5, and the sixth active portion T6A of the second light emission control transistor T6. The second active portion T2A of the switching transistor T2 and the fifth active portion T5A of the first light emission control transistor T5 are arranged along the first direction Y, and the sixth active portion T6A of the second light emission control transistor T6 and the second initialization transistor T7 are connected to each other. The seventh active portion T7A is arranged along the first direction Y, and the sixth active portion T6A of the second light emitting control transistor T6 is connected to the seventh active portion T7A of the second initialization transistor T7, and the eighth active portion T8A of the third initialization transistor T8 is arranged at intervals with the first active portion T1A of the driving transistor T1, the second active portion T2A of the switching transistor T2, the fifth active portion T5A of the first light emitting control transistor T5, the sixth active portion T6A of the second light emitting control transistor T6 and the seventh active portion T7A of the second initialization transistor T7.

[0064] Specifically, it can be seen that within a repeating unit 30 , the fifth active portions T5A of two adjacent first light emission control transistors T5 are connected.

[0065] In some embodiments, Figures 4 to 6 , Fig.10 , Fig.11 As shown, the first gate layer 209 includes a first initialization signal line VI-G, a third scanning signal line Pscan, a light-emitting control signal line EM, a fourth scanning signal line Pscan2, a gate T1G of a driving transistor T1, a gate T2G of a switching transistor T2, a gate T5G of a first light-emitting control transistor T5, a gate T6G of a second light-emitting control transistor T6, a gate T7G of a second initialization transistor T7, a gate T8G of a third initialization transistor T8 and a first electrode Cst1 of a storage capacitor Cst. The first initialization signal line VI-G, the third scanning signal line Pscan, the first electrode Cst1 of the storage capacitor Cst, the light-emitting control signal line EM and the fourth scanning signal line Pscan2 are arranged in sequence along the first direction Y.

[0066] Specifically, from Fig.10 It can be seen that the gate T2G of the switch transistor T2 is a part of the third scan signal line Pscan. It can be understood that since the gates T2G of all the switch transistors T2 in a row of sub-pixels 31 are connected to the same third scan signal line Pscan, when the third scan signal line Pscan is formed, the portion of the channel of the switch transistor T2 of each sub-pixel 31 of the third scan signal line Pscan serves as the gate of the switch transistor T2 of each pixel unit. Therefore, two reference numerals are used to identify the same structure. Similarly, the gate T1G of the drive transistor T1 serves as both the gate and the storage capacitor Cs. t's first electrode Cst1, the portion of the channel of the first light-emitting control transistor T5 corresponding to the light-emitting control signal line EM serves as the gate T5G of the first light-emitting control transistor T5, the portion of the channel of the second light-emitting control transistor T6 corresponding to the light-emitting control signal line EM serves as the gate T6G of the second light-emitting control transistor T6, the portion of the channel of the second initialization transistor T7 corresponding to the fourth scanning signal line Pscan2 serves as the gate T7G of the second initialization transistor T7, and the portion of the channel of the third initialization transistor T8 corresponding to the fourth scanning signal line Pscan2 serves as the gate T8G of the third initialization transistor T8.

[0067] Among them, refer to Fig.10 and Fig.11 The position where the gate of each transistor overlaps with the first semiconductor layer 207 is the channel portion of the corresponding transistor, for example, the position where the gate T2G of the switch transistor T2 overlaps with the first semiconductor layer 207 is the channel portion of the switch transistor T2; the position where the gate T1G of the driving transistor T1 overlaps with the first semiconductor layer 207 is the channel portion of the driving transistor T1; the position where the gate T5G of the first light-emitting control transistor T5 overlaps with the first semiconductor layer 207 is the channel portion of the first light-emitting control transistor T5; the position where the gate T6G of the second light-emitting control transistor T6 overlaps with the first semiconductor layer 207 is the channel portion of the second light-emitting control transistor T6; the position where the gate T7G of the second initialization transistor T7 overlaps with the first semiconductor layer 207 is the channel portion of the second initialization transistor T7; the position where the gate T8G of the third initialization transistor T8 overlaps with the first semiconductor layer 207 is the channel portion of the third initialization transistor T8.

[0068] In some embodiments, Figures 4 to 6 , Fig.12 , Fig.13As shown, the second semiconductor layer 212 includes a third active portion T3A of the compensation transistor T3, a fourth active portion T4A of the first initialization transistor T4, and a second plate Cst2 of the storage capacitor Cst, the third active portion T3A of the compensation transistor T3 is connected to the fourth active portion T4A of the first initialization transistor T4, and the third active portion T3A and the fourth active portion T4A both extend along the first direction Y. The second plate Cst2 of the storage capacitor Cst is arranged on one side of the third active portion T3A of the compensation transistor T3 along the first direction Y, and the second plate Cst2 of the storage capacitor Cst is arranged corresponding to the gap between two adjacent third active portions T3A. The second plate Cst2 is arranged corresponding to the first light shielding portion 311, and the first plate Cst2 is connected to the high potential power line VDD. A through hole 331 is provided on the second plate Cst of the storage capacitor Cst. By making the second semiconductor layer 212 form the second plate Cst2 of the storage capacitor Cst, the storage capacitor Cst can be set in the sub-pixel 31, and a through hole is provided on the second plate Cst2 of the storage capacitor Cst, so that the first electrode of the compensation transistor T3 can be normally connected to the gate of the driving transistor T1.

[0069] Specifically, it can be understood that the second semiconductor layer 212 forms the second plate of the storage capacitor Cst. Therefore, it is necessary to make the second plate of the storage capacitor Cst have better electrical properties. The second plate of the storage capacitor Cst can be doped to keep the electrical properties of the second plate of the storage capacitor Cst consistent with or even higher than the electrical properties of the doped part of the active part, so that the electrical properties of the storage capacitor Cst are better.

[0070] Specifically, by providing a through hole on the second plate of the storage capacitor Cst, the first electrode of the compensation transistor T3 can pass through the second plate of the storage capacitor Cst and be connected to the gate of the driving transistor T1, so that the sub-pixel 31 works normally.

[0071] Specifically, Fig.10 , Fig.12 , Fig.13 As shown, the first gate layer 209 also includes a first plate Cboost1 of the boost capacitor Cboost, the second semiconductor layer 212 also includes a second plate Cboost2 of the boost capacitor Cboost, the overlapping portion of the third scanning signal line Pscan and the fourth active portion T4A of the first initialization transistor T4 is the first plate Cboost1 of the boost capacitor Cboost, and the overlapping portion of the fourth active portion T4A of the first initialization transistor T4 and the third scanning signal line Pscan is the second plate Cboost2 of the boost capacitor Cboost.

[0072] In some embodiments, Figures 4 to 6 , Fig.14 and Fig.15 As shown, the second gate layer 214 includes the second scan signal line Nscan2, the first scan signal line Nscan1, the third initialization signal line VI3, the gate T3G of the compensation transistor T3, and the gate T4G of the first initialization transistor T4. The position where the gate T3G of the compensation transistor T3 overlaps with the second semiconductor layer 212 is the channel portion of the compensation transistor T3, and the position where the gate T4G of the first initialization transistor T4 overlaps with the second semiconductor layer 212 is the channel portion of the first initialization transistor T4.

[0073] Reference Fig.14 and Fig.15 , the second scan signal line Nscan2, the first scan signal line Nscan1 and the third initialization signal line VI3 are sequentially arranged along the first direction Y. The orthographic projection of the first scan signal line Nscan1 on the substrate 201 at least partially overlaps with the orthographic projection of the second light shielding pattern 202b on the substrate 201, and / or the orthographic projection of the second scan signal line Nscan2 on the substrate 201 at least partially overlaps with the orthographic projection of the third light shielding pattern 202c on the substrate 201. Specifically, the projection of the second light shading pattern 202b on the substrate 201 can overlap with the projection of the first scanning signal line Nscan1 on the substrate 201, thereby reducing the coupling capacitance between the second light shading pattern 202b and other signal lines, and even if the second light shading pattern 202b is coupled with the first scanning signal line Nscan1, since the second light shading portion 313 blocks the third active portion T3A of the compensation transistor T3, the potential of the second light shading pattern 202b is the same as the potential of the second light shading portion 313, which can be the potential of the first scanning signal line Nscan1, and the gate control capability of the compensation transistor T3 can be improved.

[0074] Specifically, the projection of the second light shading pattern 202b on the substrate 201 can overlap with the projection of the first scanning signal line Nscan1 on the substrate 201, and the projection of the third light shading portion 315 on the substrate 201 can overlap with the projection of the second scanning signal line Nscan2 on the substrate 201, thereby reducing the overlapping area between the second light shading pattern 202b and the third light shading pattern 202c and other wirings, reducing the interference of the second light shading pattern 202b and the third light shading pattern 202c with other signals, and when the second light shading pattern 202b is coupled with the first scanning signal line Nscan1 and the third light shading pattern 202c is coupled with the second scanning signal line Nscan2, the second light shading portion 313 and the third light shading portion 315 can be used as the bottom gate of the compensation transistor T3 and the first initialization transistor T4, respectively, to improve the gate control capability of the compensation transistor T3 and the first initialization transistor T4.

[0075] In some embodiments, Figures 4 to 6 , Fig.16and Fig.17 As shown, the first source-drain layer 216 includes a first electrode T2S of the switching transistor T2, a first electrode T3S of the compensation transistor T3, a second electrode T3D of the compensation transistor T3, a first electrode T4S of the first initialization transistor T4, a second electrode T4D of the first initialization transistor T4, a first electrode T5S of the first light-emitting control transistor T5, a second electrode T5D of the first light-emitting control transistor T5, a first electrode T6S of the second light-emitting control transistor T6, a second electrode T6D of the second light-emitting control transistor T6, a first electrode T7S of the second initialization transistor T7, a second electrode T7D of the second initialization transistor T7, a first electrode T8S of the third initialization transistor T8, a second electrode T8D of the third initialization transistor T8, and a second initialization signal line VI-ANO, wherein at Fig.17 The second initialization signal line VI-ANO is not shown in the stack-up diagram in FIG.

[0076] Specifically, Fig.16 As shown, it can be understood that since the electrodes of each transistor are connected together, in order to improve the aperture ratio in actual design, the electrodes of each transistor share the same structure. Fig.16 In the figure, multiple reference numerals are used to identify the same structure. For example, a structure serves as both the first electrode T3S of the compensation transistor T3 and the second electrode T4D of the first initialization transistor T4. Figure 5 As can be seen in , this is the location where the second node Q is connected. Similarly, other structures can also serve as multiple electrodes, and the location of each node can be determined accordingly.

[0077] Specifically, Fig.11 , Fig.16 and Fig.17As shown, the first initialization signal line VI-G is connected to the first electrode T4S of the first initialization transistor T4 through the first connection terminal K1. In view of the small spacing between the projections of the first initialization signal line VI-G and the second scanning signal line Nscan2 on the substrate, directly forming a via hole in the region corresponding to the first electrode of the first initialization transistor to connect the first initialization signal line will cause the problem of the via hole being formed on the second scanning signal line Nscan2. Therefore, the first connection terminal K1 can be set on the first source-drain layer, and the first electrode of the first initialization transistor T4 can be connected through the first connection terminal K1. At the same time, a via hole is formed in the region corresponding to the first connection terminal K1, so that the first connection terminal K1 is connected to the first initialization signal line VI-G, thereby realizing the connection between the first initialization signal line VI-G and the first electrode T4S of the first initialization transistor T4. The first connection terminal K1 is set on the symmetry axis of the two symmetrically arranged sub-pixels 31, so that the first electrode of the first initialization transistor T4 in the two symmetrically arranged sub-pixels 31 can be connected to the first initialization signal line through the same first connection terminal K1, thereby reducing the number of via holes and improving the yield.

[0078] Specifically, Figures 6 to 16 As shown, the first electrode T3S of the compensation transistor T3 is connected to the gate T1G of the driving transistor T1. Therefore, a second connection terminal K2 can be set on the first source and drain layer. The second connection terminal K2 passes through the through hole 331 and is connected to the gate T1G of the driving transistor T1, thereby realizing the connection between the gate of the driving transistor T1 and the first electrode T3S of the compensation transistor T3.

[0079] The third initialization signal line VI3 is connected to the first electrode T8S of the third initialization transistor T8 via the third connection terminal K3.

[0080] In some embodiments, Figures 4 to 6 , Fig.18 As shown, in one repeating unit 30, the second source-drain layer 218 includes two data lines DATA and two high-potential power lines VDD, and the two data lines are arranged in a mirror-symmetrical manner, and the two high-potential power lines VDD are arranged in a mirror-symmetrical manner.

[0081] Specifically, it can be understood that due to the design of the sub-pixel 31 in the display area shown in the embodiment of the present application, the connection points of some routing lines are located in the non-display area. Therefore, some routing lines may not be connected together, but in fact, they will be connected. For example, in order to adopt the technology of setting the fan-out line in the display area (Fanout In AA, FIAA), a first data connection line set along the first direction Y and a second data connection line set along the second direction X will be set, and they will be connected to the data line outside the display area. However, the embodiment of the present application shows the design of the sub-pixel 31 in the display area, and therefore, its connection points are not shown, but in fact they will be connected.

[0082] At the same time, in order to realize the mesh structure design of the initialization signal line, the embodiment of the present application will set the initialization signal connection line, and the initialization signal connection line can realize the mesh structure design of at least one of the first initialization signal line VI-G, the second initialization signal line VI-ANO and the third initialization signal line VI3. Similarly, the initialization signal connection line will be connected to the initialization signal line.

[0083] For example, the first initialization signal line VI-G will be connected to the initialization signal connection line outside the display area, thereby realizing the mesh structure design of the first initialization signal line VI-G. Similarly, the mesh structure design of the second initialization signal line VI-ANO and the third initialization signal line VI3 can be realized. However, the embodiments of the present application are not limited to this. Some initialization signal connection lines can be connected to one of the first initialization signal line VI-G, the second initialization signal line VI-ANO and the third initialization signal line VI3, and some initialization signal connection lines can be connected to another one of the first initialization signal line VI-G, the second initialization signal line VI-ANO and the third initialization signal line VI3. Some initialization signal connection lines can also be connected to another one of the first initialization signal line VI-G, the second initialization signal line VI-ANO and the third initialization signal line VI3, thereby realizing the mesh structure design of each initialization signal line.

[0084] Specifically, Figure 4 As shown, the display panel 2 further includes a first barrier layer 203 , a second barrier layer 205 , a buffer layer 206 , a first gate insulating layer 208 , a first interlayer insulating layer 211 , a second gate insulating layer 213 , a second interlayer insulating layer 215 , a first planarizing layer 217 and a second planarizing layer 219 .

[0085] Specifically, Figure 4 As shown, the display panel 2 further includes a light-emitting layer 23 , and the light-emitting layer 23 includes a pixel electrode layer 221 , a pixel definition layer 222 , a light-emitting material layer, a common electrode layer and a support column 223 .

[0086] Specifically, the first electrode of the transistor in the above embodiment is a source, and the second electrode is a drain; or the first electrode of the transistor in the above embodiment is a drain, and the second electrode is a source.

[0087] Specifically, the third scan signal line Pscan, the first scan signal line Nscan1, the second scan signal line Nscan2, the fourth scan signal line Pscan2 and the light-emitting control signal line EM can be respectively connected to different gate drive circuits. Specifically, five groups of gate drive circuits can be used to output signals to the third scan signal line Pscan, the first scan signal line Nscan1, the second scan signal line Nscan2, the fourth scan signal line Pscan2 and the light-emitting control signal line EM, respectively. Among them, the gate drive circuit connected to the third scan signal line Pscan can adopt bilateral drive, and other gate drive circuits adopt unilateral drive.

[0088] Specifically, the material of the first semiconductor layer 207 includes silicon semiconductor material, and specifically may be low temperature polysilicon.

[0089] Specifically, the material of the second semiconductor layer 212 includes an oxide semiconductor material, specifically a metal oxide semiconductor material, and more specifically, indium gallium zinc oxide.

[0090] Specifically, the material of the light shielding layer 202 includes metal material.

[0091] Specifically, the driving transistor T1 , the switching transistor T2 , the first light emitting transistor, the second light emitting transistor, the second initialization transistor and the third initialization transistor are P-type transistors, and the first initialization transistor T4 and the compensation transistor T3 are N-type transistors.

[0092] Specifically, the above embodiments respectively describe the display panel in detail from the sub-pixel 31 structure, film layer structure, specific structure, material, and potential of each layer in the display panel 2. It can be understood that when there is no conflict between the embodiments, the embodiments can be combined.

[0093] Meanwhile, an embodiment of the present application provides a display device, which includes a display panel 2 as described in any of the above embodiments.

[0094] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0095] The embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solution and core idea of ​​the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: The invention comprises a plurality of sub-pixels, each of which comprises a driving transistor, a compensation transistor and a storage capacitor, wherein a first active portion of the driving transistor is located in a first semiconductor layer, a third active portion of the compensation transistor and a plate of the storage capacitor are both located in a second semiconductor layer, a gate of the driving transistor and another plate of the storage capacitor are both located in a first gate layer, and the first semiconductor layer, the second semiconductor layer and the first gate layer are all arranged in different layers; The display panel further includes a light shielding layer, which includes a first light shielding portion provided corresponding to the first active portion and a second light shielding portion provided corresponding to the third active portion, and electrical signals on the first light shielding portion are different from those on the second light shielding portion.

2. The display panel according to claim 1, characterized in that: The light-shielding layer also includes a first light-shielding pattern and a second light-shielding pattern that are arranged at intervals, the first light-shielding pattern and the second light-shielding pattern have the same extension direction, the first light-shielding pattern includes a plurality of the light-shielding portions, the second light-shielding pattern includes a plurality of the second light-shielding portions, the first light-shielding pattern is connected to a high-potential power line, and the second light-shielding pattern is connected to the gate of the compensation transistor.

3. The display panel according to claim 2, characterized in that: A gate of the compensation transistor is connected to a first scanning signal line, and an orthographic projection of the first scanning signal line on the substrate of the display panel at least partially overlaps with an orthographic projection of the second light shielding pattern on the substrate of the display panel.

4. The display panel according to claim 2, characterized in that: The first light shielding pattern and the second light shielding pattern are arranged at intervals in the first direction, the first light shielding pattern and the second light shielding pattern both extend along a second direction, the second direction is different from the first direction, and the high potential power line extends along the first direction and is arranged at intervals in the second direction; A plurality of the first light shielding portions are arranged at intervals in the second direction, and a plurality of the second light shielding portions are arranged at intervals in the second direction; The first shading pattern further includes a first connecting line connected between two adjacent first shading portions, and the second shading pattern further includes a second connecting line connected between two adjacent second shading portions, and the first connecting lines and the second connecting lines are arranged in sequence in the first direction.

5. The display panel according to claim 4, characterized in that: The display panel further includes a plurality of repeating units, each of the repeating units including two mirror-symmetrical sub-pixels, two mirror-symmetrical first light shielding portions, and two mirror-symmetrical second light shielding portions; In the same repeating unit, the first connecting line connecting the two first shading parts is a first type of first connecting line, and the second connecting line connecting the two second shading parts is a first type of second connecting line. In the second direction, the length of the first type of first connecting line is less than the length of the first type of second connecting line.

6. The display panel according to claim 5, characterized in that: The first connecting lines connecting the first light shielding portions in two adjacent repeating units are second-type first connecting lines. In the second direction, the second-type first connecting lines are staggered with the first-type first connecting lines.

7. The display panel according to claim 5, characterized in that: The first-type second connecting line includes a recessed portion disposed close to the first-type first connecting line, and the recessed portion is disposed corresponding to a gap between two adjacent first light shielding portions.

8. The display panel according to claim 5, characterized in that: In the repeating unit, the first light shielding portion is arranged corresponding to a gap between two adjacent second light shielding portions.

9. The display panel according to any one of claims 2 to 8, characterized in that: The sub-pixel also includes a first initialization transistor, a fourth active portion of the first initialization transistor is located in the second semiconductor layer, the shading layer also includes a third shading pattern located in the second shading pattern away from the first shading pattern, the third shading pattern includes a third shading portion arranged corresponding to the fourth active portion, and the electrical signal on the third shading portion is the same as that on the second shading portion.

10. The display panel according to claim 9, characterized in that: The third shading pattern is connected to the gate of the first initialization transistor, and the gate of the first initialization transistor is connected to the second scanning signal line; the orthographic projection of the second scanning signal line on the substrate of the display panel at least partially overlaps with the orthographic projection of the third shading pattern on the substrate of the display panel.

11. The display panel according to claim 10, characterized in that: The sub-pixel further includes a switch transistor, a gate of the switch transistor is connected to a third scan signal line, a first electrode of the switch transistor is connected to a data line, and a second electrode of the switch transistor is connected to a first node with a first electrode of the drive transistor; a first electrode of the compensation transistor is connected to a gate of the drive transistor at a second node, and a second electrode of the compensation transistor is connected to a second electrode of the drive transistor; a first electrode of the first initialization transistor is connected to a first initialization signal line, and a second electrode of the first initialization transistor is connected to a second node with a gate of the drive transistor; The sub-pixel further includes: a first light emission control transistor, wherein a gate of the first light emission control transistor is connected to a light emission control signal line, a first electrode of the first light emission control transistor is connected to the high potential power line, and a second electrode of the first light emission control transistor and a first electrode of the driving transistor are connected to a first node; a second light emission control transistor, wherein a gate of the second light emission control transistor is connected to the light emission control signal line, and a first electrode of the second light emission control transistor and a second electrode of the driving transistor are connected to a third node; a second initialization transistor, wherein a gate of the second initialization transistor is connected to a fourth scanning signal line, a first electrode of the second initialization transistor is connected to a second initialization signal line, and a second electrode of the second initialization transistor and a second electrode of the second light emission control transistor are connected to a fourth node; a third initialization transistor, wherein a gate of the third initialization transistor is connected to the fourth scanning signal line, a first electrode of the third initialization transistor is connected to the third initialization signal line, and a second electrode of the third initialization transistor is connected to the first electrode of the driving transistor at a first node; One plate of the storage capacitor is connected to the high potential power line, and the other plate of the storage capacitor is connected to the gate of the driving transistor at a second node; A boosting capacitor, one plate of the boosting capacitor is connected to the third scanning signal line, and the other plate of the boosting capacitor is connected to the second electrode of the first initialization transistor.

12. The display panel according to claim 11, characterized in that: The second semiconductor layer further includes a second electrode plate of the storage capacitor, the second electrode plate is arranged corresponding to the first light shielding portion, and the second electrode plate is connected to the high potential power line, and a through hole is arranged on the second electrode plate.

13. The display panel according to claim 12, characterized in that: The first semiconductor layer also includes a second active portion of the switching transistor, a fifth active portion of the first light-emitting control transistor, a sixth active portion of the second light-emitting control transistor, a seventh active portion of the second initialization transistor, and an eighth active portion of the third initialization transistor, the first active portion connecting the second active portion, the fifth active portion, and the sixth active portion, the sixth active portion connecting the seventh active portion, the eighth active portion being spaced apart from the first active portion, the second active portion, the fifth active portion, the sixth active portion, and the seventh active portion, and the eighth active portion being located between the fifth active portion and the seventh active portion.

14. The display panel according to claim 13, characterized in that: The first gate layer is arranged between the first semiconductor layer and the second semiconductor layer, and the first gate layer includes the first initialization signal line, the third scanning signal line, the light-emitting control signal line, the fourth scanning signal line, the gate of the driving transistor, the gate of the switching transistor, the gate of the first light-emitting control transistor, the gate of the second light-emitting control transistor, the gate of the second initialization transistor, the gate of the third initialization transistor and the first plate of the storage capacitor, and the first initialization signal line, the third scanning signal line, the first plate of the storage capacitor, the light-emitting control signal line and the fourth scanning signal line are arranged in sequence.

15. The display panel according to claim 14, characterized in that: The display panel also includes a second gate layer, which is arranged on a side of the second semiconductor layer away from the first gate layer, and the second gate layer includes the first scanning signal line, the second scanning signal line, the third initialization signal line, the gate of the compensation transistor and the gate of the first initialization transistor, and the third initialization signal line, the first scanning signal line and the second scanning signal line are arranged in sequence at intervals.

16. A display device, characterized in that: The invention comprises the display panel as claimed in any one of claims 1 to 15.

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