Chip and preparation method thereof, display device, electronic equipment, wafer and wafer lamination

Abstract

The embodiment of the invention provides a chip and a preparation method thereof, a display device, electronic equipment, a wafer and a wafer lamination, relates to the technical field of electronics, and is used for obtaining a low-cost and high-performance display chip. The three-primary-color light-emitting device in the chip can be obtained by pixelating an epitaxial wafer, and the epitaxial wafer is directly bonded with a driving back plate through a one-time bonding process, namely the three-primary-color light-emitting device is bonded with the driving back plate through the one-time bonding process. Colorful display can be realized through a one-time epitaxial process and a one-time bonding process, and the chip is high in integration level (small in film layer number and small in size), simple in structure, simple in process flow, low in cost and long in service life. Only one P-type semiconductor layer is arranged in the light-emitting device, the other semiconductor layers are all N-type semiconductor layers, and only one PN junction is arranged. The epitaxial wafer is simple, the epitaxial growth difficulty is low, the time is short, the quality is high, and the cost is low.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a chip and a preparation method thereof, a display device, an electronic device, a wafer, and a wafer stack. Background Art

[0002] With the development of micro-machining technology, light emitting diode (LED) devices have been gradually and widely used in lighting and display fields due to their advantages of high brightness, low power consumption, long life, high stability, and small size. Especially in some small-size and high-resolution scenes, the advantages of LED devices are more obvious.

[0003] However, one of the biggest challenges facing display chips based on LED devices is to achieve full-color pixel display of red, green and blue on the display chip. However, the methods currently used by those skilled in the art to achieve full-color pixel display have many problems such as complex processes, high costs and poor performance. Summary of the invention

[0004] The present application provides a chip and a preparation method thereof, a display device, an electronic device, a wafer, and a wafer stack, which are used to obtain a low-cost, high-performance display chip.

[0005] In a first aspect of an embodiment of the present application, a chip is provided, and the chip is used, for example, to realize full-color display. The chip includes: a driving backplane and a first primary color light-emitting device and a second primary color light-emitting device arranged at intervals on the same side of the driving backplane. The first primary color light-emitting device includes a first bonding layer, a first hole injection layer, a first active layer of the first primary color light-emitting device, and a first electron injection layer of the first primary color light-emitting device arranged in sequence, the first active layer of the first primary color light-emitting device includes a first sub-active layer, and the first sub-active layer includes a first barrier layer and a first multi-quantum well layer arranged in sequence on a side of the first hole injection layer away from the driving backplane; the first bonding layer is bonded to the driving backplane. The second primary color light emitting device includes a second bonding layer, a second hole injection layer, a first active layer of the second primary color light emitting device, a first electron injection layer of the second primary color light emitting device, a second active layer of the second primary color light emitting device, and a second electron injection layer of the second primary color light emitting device, which are arranged in sequence; the second active layer of the second primary color light emitting device includes a second sub-active layer, and the second sub-active layer includes a second barrier layer, a second quantum well protection layer, and a second multi-quantum well layer, which are arranged in sequence on the side of the first electron injection layer of the second primary color light emitting device away from the driving backplane; the second bonding layer is bonded to the driving backplane. The first bonding layer and the second bonding layer are of the same layer and the same material, and the first active layer of the first primary color light emitting device and the first active layer of the second primary color light emitting device are of the same layer and the same material.

[0006] The chip provided in the embodiment of the present application includes a first primary color light emitting device and a second primary color light emitting device, wherein the first primary color light emitting device only includes the first active layer of the first primary color light emitting device, and is used to emit the first primary color light. The second primary color light emitting device includes the first active layer of the second primary color light emitting device and the second active layer of the second primary color light emitting device. Since the second active layer of the second primary color light emitting device is arranged on the side of the first active layer of the second primary color light emitting device away from the driving backplane, and the second active layer of the second primary color light emitting device includes a second quantum well protection layer, the second quantum well protection layer increases the barrier height, prevents electrons from moving to the first active layer of the second primary color light emitting device, and holes can move to the second active layer of the second primary color light emitting device. Therefore, in the second primary color light emitting device, only the second active layer of the second primary color light emitting device emits light, and the first active layer of the second primary color light emitting device does not emit light, so that the second primary color light emitting device emits the second primary color light, thereby realizing that the chip emits multi-primary color light. On this basis, the first active layer of the second primary color light emitting device and the first active layer of the first primary color light emitting device are of the same layer and material, so a wafer emitting multiple colors of light can be formed on the same substrate through a single epitaxial process. And the first bonding layer and the second bonding layer are of the same layer and material, so the first primary color light emitting device and the second primary color light emitting device can be bonded to the driving backplane through a single bonding process, without the need for additional wafer bonding and other integration processes. Moreover, taking the second primary color light emitting device as an example, the semiconductor layer in the second primary color light emitting device only includes a P-type semiconductor layer (the second hole injection layer), and the rest are N-type semiconductor layers. The second primary color light emitting device only includes one PN junction, and the epitaxial structure is simple, and the epitaxial growth is less difficult, the time is short, the quality is high, and the cost is low. Similarly, the first primary color light emitting device also includes only one PN junction. A PN junction, an epitaxial process, and a bonding process can realize colorful display. There is no need for complex solutions such as quantum dot color conversion, three-color light combination, and multiple PN junction tunneling junctions. The chip has high integration (few film layers, small volume), simple structure, simple process flow, low cost, and long life. Furthermore, in the light-emitting device, each time it is mainly an active layer with a single primary color, the color of the sub-pixel is positive, the brightness and color are easy to adjust, and the luminous efficiency is high. The light-emitting device is a vertical structure light-emitting device. Compared with the flip-chip structure light-emitting device, the chip has a low driving voltage and low power consumption.

[0007] In a possible implementation, the chip also includes a third primary color light-emitting device arranged at intervals from the second primary color light-emitting device; the third primary color light-emitting device includes a third bonding layer, a third hole injection layer, a first active layer of the third primary color light-emitting device, a first electron injection layer of the third primary color light-emitting device, a second active layer of the third primary color light-emitting device, a second electron injection layer of the third primary color light-emitting device, a third active layer of the third primary color light-emitting device and a third electron injection layer of the third primary color light-emitting device arranged in sequence; the third active layer of the third primary color light-emitting device includes a third sub-active layer, and the third sub-active layer includes a third barrier layer, a third quantum well protection layer and a third multi-quantum well layer arranged in sequence on a side of the second electron injection layer of the third primary color light-emitting device away from the driving backplane; the third bonding layer is bonded to the driving backplane; the third bonding layer and the first bonding layer are of the same layer and material, the first active layer of the third primary color light-emitting device and the first active layer of the first primary color light-emitting device are of the same layer and material, and the second active layer of the second primary color light-emitting device and the second active layer of the third primary color light-emitting device are of the same layer and material. The chip may also include a third primary color light-emitting device that emits a third primary color light. The third primary color light-emitting device can be prepared in the same epitaxial process and bonding process as the first primary color light-emitting device and the second primary color light-emitting device, so that full-color display of the chip can be achieved through one epitaxial process and one bonding process.

[0008] In a possible implementation, the chip further includes a transparent electrode layer; the transparent electrode layer is coupled to the first electron injection layer of the first primary color light emitting device, the second electron injection layer of the second primary color light emitting device, and the third electron injection layer of the third primary color light emitting device, respectively. The first transparent electrode layer is coupled to all three light emitting devices, forming a common cathode structure. The anodes of the three light emitting devices are all located in the driving backplane, and are arranged opposite to the common cathode to form a vertical light emitting device structure. The light emitting device can be driven to emit light with a lower driving voltage, thereby reducing the power consumption of the chip and improving the heating and battery life problems of the electronic device including the chip.

[0009] In a possible implementation, the chip further includes a dielectric layer; the dielectric layer is arranged on the side of the transparent electrode layer facing the driving backplane; the dielectric layer includes a first opening, a second opening, and a third opening; the dielectric layer covers the edge of the first electron injection layer of the first primary color light emitting device; the dielectric layer covers the edge of the second electron injection layer of the second primary color light emitting device; the dielectric layer covers the edge of the third electron injection layer of the third primary color light emitting device; the transparent electrode layer is coupled to the first electron injection layer of the first primary color light emitting device through the first opening, coupled to the second electron injection layer of the second primary color light emitting device through the second opening, and coupled to the third electron injection layer of the third primary color light emitting device through the third opening. The first opening exposes the middle area of ​​the first electron injection layer of the first primary color light emitting device, which can prevent electrons from being injected from the edge of the first electron injection layer of the first primary color light emitting device, and reduce the possibility of affecting the light emitting effect due to damage to the edge of the first primary color light emitting device. Similarly, the second opening exposes the middle area of ​​the second electron injection layer of the second primary color light emitting device, which can prevent electrons from being injected from the edge of the second electron injection layer of the second primary color light emitting device, and reduce the possibility of affecting the light emitting effect due to damage to the edge of the second primary color light emitting device. Similarly, the third opening exposes the middle area of ​​the third electron injection layer of the third primary color light emitting device, which can prevent electrons from being injected from the edge of the third electron injection layer of the third primary color light emitting device, thereby reducing the possibility of affecting the light emitting effect due to edge damage of the third primary color light emitting device.

[0010] In a possible implementation, the first active layer of the first primary color light emitting device further includes a fourth sub-active layer; the fourth sub-active layer is arranged between the first hole injection layer and the first sub-active layer, and the fourth sub-active layer includes a fourth barrier layer, a fourth quantum well protection layer, and a fourth multi-quantum well layer, which are sequentially arranged on the side of the first hole injection layer toward the first sub-active layer. The fourth sub-active layer is arranged on the side of the first sub-active layer toward the first hole injection layer, and the fourth sub-active layer includes a fourth quantum well protection layer, which can prevent electrons from moving toward the driving backplane and reduce the leakage current of the chip.

[0011] In a possible implementation, the second active layer of the second primary color light emitting device further includes a fifth sub-active layer; the fifth sub-active layer is arranged between the second sub-active layer and the second electron injection layer of the second primary color light emitting device, and the fifth sub-active layer includes a fifth barrier layer and a fifth multi-quantum well layer sequentially arranged on the second sub-active layer facing the second electron injection layer of the second primary color light emitting device. The fifth sub-active layer is arranged in the second active layer of the second primary color light emitting device, which increases the number of light emitting units in the second active layer and can improve the light emitting brightness of the second active layer. In addition, the fifth sub-active layer does not include a quantum well protection layer, which will not affect the normal light emission of the second sub-active layer.

[0012] In a possible implementation, the third active layer of the third primary color light-emitting device further includes a sixth sub-active layer; the sixth sub-active layer is arranged between the third sub-active layer and the third electron injection layer of the third primary color light-emitting device, and the sixth sub-active layer includes a sixth barrier layer and a sixth multi-quantum well layer sequentially arranged on the side of the third sub-active layer facing the third electron injection layer of the third primary color light-emitting device. The sixth sub-active layer is arranged in the third active layer of the third primary color light-emitting device, which increases the number of light-emitting units in the third active layer and can improve the light-emitting brightness of the third active layer. In addition, the sixth sub-active layer does not include a quantum well protection layer, which will not affect the normal light emission of the third sub-active layer.

[0013] In a possible implementation, the chip further includes a reflective baffle disposed on the driving backplane, the reflective baffle comprising a first sub-reflective baffle, a second sub-reflective baffle and a third sub-reflective baffle; the first sub-reflective baffle is disposed on the side of the first primary color light emitting device, the top of the first sub-reflective baffle away from the driving backplane is higher than the top of the first multi-quantum well layer away from the driving backplane; the second sub-reflective baffle is disposed on the side of the second primary color light emitting device, the top of the second sub-reflective baffle away from the driving backplane is higher than the top of the second multi-quantum well layer away from the driving backplane; the third sub-reflective baffle is disposed on the side of the third primary color light emitting device, the top of the third sub-reflective baffle away from the driving backplane is higher than the top of the third multi-quantum well layer away from the driving backplane. By arranging the reflective baffle between the light emitting devices, the light radiated from the side of the light emitting device can be reflected and radiated in a direction perpendicular to the driving backplane, so that the light radiated from the side of the light emitting device can be utilized, avoiding the waste of photons caused by the side radiation, and improving the overall light extraction efficiency (photoelectric conversion efficiency) of the chip. Moreover, after a reflective baffle is set around the periphery of the light-emitting device, the light radiated by the light-emitting device will be reflected and blocked by the reflective baffle, narrowing the light output angle, preventing the light from entering the area where the adjacent light-emitting device is located, reducing the interference to the visual brightness of the adjacent light-emitting device (reducing crosstalk between light-emitting devices), and helping to improve the resolution of the chip.

[0014] In a possible implementation, the material of the reflective baffle includes metal, and the reflective baffle is coupled to the transparent electrode layer. The material of the transparent electrode layer is a transparent conductive material, and the material of the reflective baffle is metal. The conductivity of the metal is greater than that of the transparent conductive material. During the driving process of the light-emitting device, the current is transmitted through the reflective baffle, which can alleviate the voltage drop phenomenon in the light-emitting area.

[0015] In a possible implementation, the reflective baffle is disposed on the side of the transparent electrode layer away from the driving backplane, so that the transparent electrode layer does not need to cooperate with the structure of the reflective baffle, which can simplify the structure of the transparent electrode layer and reduce the requirements for the shape of the reflective baffle structure.

[0016] In a possible implementation, there is a gap between the first sub-reflective baffle and the first primary color light emitting device; there is a gap between the second sub-reflective baffle and the second primary color light emitting device; there is a gap between the third sub-reflective baffle and the third primary color light emitting device. In the case where the spacing between adjacent light emitting devices is relatively large, by reserving a gap between the reflective baffle and the light emitting device, the gap is used as a tolerance area for process errors, which can reduce the requirements for process accuracy on the one hand, and reduce the weight of the reflective baffle on the other hand.

[0017] In a possible implementation, the chip further includes a first via hole and a second via hole; the first primary color light emitting device further includes a second active layer of the first primary color light emitting device, a second electron injection layer of the first primary color light emitting device, a third active layer of the first primary color light emitting device, and a third electron injection layer of the first primary color light emitting device, which are sequentially arranged on the side where the first electron injection layer of the first primary color light emitting device is away from the driving backplane; the second primary color light emitting device further includes a third active layer of the second primary color light emitting device, a third electron injection layer of the second primary color light emitting device, and a third electron injection layer of the second primary color light emitting device, which are sequentially arranged on the side where the second electron injection layer of the second primary color light emitting device is away from the driving backplane; the second active layer of the first primary color light emitting device and the second primary color light emitting device are connected to each other. The second active layer of the first primary color light emitting device is made of the same material, and the third active layer of the first primary color light emitting device, the third active layer of the second primary color light emitting device and the third active layer of the third primary color light emitting device are made of the same material; the first via hole penetrates the third electron injection layer of the first primary color light emitting device, the third active layer of the first primary color light emitting device, the second electron injection layer of the first primary color light emitting device and the second active layer of the first primary color light emitting device; the second via hole penetrates the third electron injection layer of the second primary color light emitting device and the third active layer of the second primary color light emitting device; the transparent electrode layer is coupled to the first electron injection layer of the first primary color light emitting device through the first via hole, and is coupled to the second electron injection layer of the second primary color light emitting device through the second via hole. The surfaces of the first primary color light emitting device, the second primary color light emitting device and the third primary color light emitting device are flush, and the transparent electrode layer is coupled to the first electron injection layer of the first primary color light emitting device through the first via hole, and is coupled to the second electron injection layer of the second primary color light emitting device through the second via hole. The top layer of the chip finally formed has a relatively high flatness, which can subsequently support the platformization of the top of the chip to facilitate the subsequent production of other processes such as microlenses on the top of the chip.

[0018] In a possible implementation, the chip further includes a first conductive column and a second conductive column; the first conductive column is disposed in the first via hole, and is coupled to the transparent electrode layer and the first electron injection layer of the first primary color light emitting device, respectively; the second conductive column is disposed in the second via hole, and is coupled to the transparent electrode layer and the second electron injection layer of the second primary color light emitting device, respectively. By arranging the first conductive column in the first via hole, the ohmic contact effect between the transparent conductive layer and the first electron injection layer of the first primary color light emitting device can be improved, the resistance can be reduced, and the electron injection effect can be improved. Similarly, by arranging the second conductive column in the second via hole, the ohmic contact effect between the transparent conductive layer and the second electron injection layer of the second primary color light emitting device can be improved, the resistance can be reduced, and the electron injection effect can be improved.

[0019] In a possible implementation, the third primary color light emitting device further includes a stress release layer, which is disposed on the surface of the third electron injection layer of the third primary color light emitting device away from the driving backplane. Since the lattice mismatch between the substrate and the subsequently formed active layer will cause a large stress, this part of the stress can be released by providing a stress release layer. The quality of the epitaxial growth of the active layer is improved, the influence of the defects of the active layer on the luminous efficiency is reduced, and the stability of the visible light wavelength changing with the current is improved, so that the luminous color is more correct.

[0020] In a possible implementation, the third primary color light emitting device further includes an N-type semiconductor layer, which is disposed on a side of the stress release layer away from the third electron injection layer of the third primary color light emitting device, and the thickness of the N-type semiconductor layer is greater than the thickness of the third electron injection layer of the third primary color light emitting device. By providing a thicker N-type semiconductor layer, the epitaxial quality of the third electron injection layer of the third primary color light emitting device can be improved, and the electron transmission effect can be improved.

[0021] In a possible implementation, the first primary color light emitting device further includes a first ohmic contact layer, which is disposed between the first bonding layer and the first hole injection layer. The second primary color light emitting device further includes a second ohmic contact layer, which is disposed between the second bonding layer and the second hole injection layer. The first primary color light emitting device further includes a third ohmic contact layer, which is disposed between the third bonding layer and the third hole injection layer. The first ohmic contact layer, the second ohmic contact layer and the third ohmic contact layer are of the same layer and the same material. By setting the ohmic contact layer for impedance transition, the ohmic contact effect between the hole injection layer and the bonding layer can be improved, and the hole transmission quality can be improved.

[0022] In a possible implementation, the first primary color light emitting device further includes a first electron blocking layer, which is disposed between the first hole injection layer and the first active layer of the first primary color light emitting device. The second primary color light emitting device further includes a second electron blocking layer, which is disposed between the second hole injection layer and the first active layer of the second primary color light emitting device. The first primary color light emitting device further includes a third electron blocking layer, which is disposed between the third hole injection layer and the first active layer of the third primary color light emitting device. The first electron blocking layer, the second electron blocking layer and the third electron blocking layer are of the same layer and the same material. By providing the electron blocking layer, electrons can be blocked from moving toward the driving backplane side, thereby reducing the leakage current of the light emitting device.

[0023] According to a second aspect of an embodiment of the present application, a display device is provided, comprising a chip and a lens, wherein the lens is arranged on a light output side of the chip; the chip comprises the chip of any one of the first aspects.

[0024] According to a third aspect of the embodiments of the present application, an electronic device includes an optical waveguide and a display device, wherein the optical waveguide is used to receive image light emitted by the display device; the display device includes the display device of the second aspect.

[0025] In a fourth aspect of the embodiments of the present application, a wafer is provided, the wafer comprising a hole injection film layer; a first primary color active film layer, a first electron injection film layer, a second primary color active film layer, a second electron injection film layer, a third primary color active film layer and a third electron injection film layer sequentially arranged on one side of the hole injection film layer. The first primary color active film layer comprises a first sub-active film layer, the first sub-active film layer comprises a first barrier film layer and a first multi-quantum well film layer sequentially arranged on the side of the hole injection film layer facing the first electron injection film layer. The second primary color active film layer comprises a second sub-active film layer, the second sub-active film layer comprises a second barrier film layer, a second quantum well protection film layer and a second multi-quantum well film layer sequentially arranged on the side of the first electron injection film layer facing the second electron injection film layer. The third primary color active film layer comprises a third sub-active film layer, the third sub-active film layer comprises a third barrier film layer, a third quantum well protection film layer and a third multi-quantum well film layer sequentially arranged on the side of the second electron injection film layer facing the third electron injection film layer. The wafer provided in the embodiment of the present application comprises a second quantum well protection film layer in the second primary color active film layer, and a third quantum well protection film layer in the third primary color active film layer. Based on this special design, a light-emitting device emitting three primary colors of light can be prepared from one wafer, with simple process and low cost.

[0026] In a possible implementation, the first primary color active film layer also includes a fourth sub-active film layer; the fourth sub-active film layer is arranged between the hole injection film layer and the first sub-active film layer, and the fourth sub-active film layer includes a fourth barrier film layer, a fourth quantum well protection film layer and a fourth multi-quantum well film layer which are sequentially arranged on the side of the hole injection film layer facing the first sub-active film layer.

[0027] In a possible implementation, the second primary color active film layer also includes a fifth sub-active film layer; the fifth sub-active film layer is arranged between the second sub-active film layer and the second electron injection film layer, and the fifth sub-active film layer includes a fifth barrier film layer and a fifth multi-quantum well film layer which are sequentially arranged on the side of the second sub-active film layer facing the second electron injection film layer.

[0028] In a possible implementation, the third primary color active film layer also includes a sixth sub-active film layer; the sixth sub-active film layer is arranged between the third sub-active film layer and the third electron injection film layer, and the sixth sub-active film layer includes a sixth barrier film layer and a sixth multi-quantum well film layer which are sequentially arranged on the side of the third sub-active film layer facing the third electron injection film layer.

[0029] In a possible implementation, the wafer further includes an electron blocking film layer, and the electron blocking film layer is disposed between the hole injection film layer and the first primary color active film layer.

[0030] In a possible implementation, the wafer further includes an ohmic contact film layer and a bonding film layer, and the ohmic contact film layer and the bonding film layer are sequentially arranged on a side of the hole injection film layer away from the first primary color active film layer.

[0031] In a possible implementation, the wafer further includes a stress release film layer, and the stress release film layer is arranged on a side of the third electron injection film layer away from the third primary color active film layer.

[0032] In a possible implementation, the wafer further includes an N-type semiconductor film layer, and the N-type semiconductor film layer is arranged on a side of the stress release film layer away from the third electron injection film layer.

[0033] In a possible implementation, the wafer further includes a buffer film layer, which is disposed on a side of the third electron injection film layer away from the third primary color active film layer and located on the surface of the wafer.

[0034] In a possible implementation, the wafer further includes a buffer film layer and a substrate, the substrate is located on the surface of the wafer, and the buffer film layer is arranged on the surface of the substrate facing the third electron injection film layer.

[0035] According to a fifth aspect of an embodiment of the present application, a wafer stack is provided, comprising a wafer and a driving substrate, wherein the wafer comprises any one of the wafers of the fourth aspect; the wafer is bonded to the driving substrate.

[0036] According to a sixth aspect of the embodiments of the present application, a method for preparing a chip is provided, and the method for preparing a wafer comprises: providing a wafer stack, and the wafer stack comprises the wafer stack of the fifth aspect. The wafers in the wafer stack are pixelated to form a first primary color light-emitting device, a second primary color light-emitting device, and a third primary color light-emitting device which are spaced apart on a driving substrate in the wafer stack; the first primary color light-emitting device comprises a first hole injection layer, a first active layer of the first primary color light-emitting device, and a first electron injection layer of the first primary color light-emitting device which are sequentially arranged, and the first active layer of the first primary color light-emitting device comprises a first sub-active layer, and the first sub-active layer comprises a first barrier layer and a first multi-quantum well layer which are sequentially arranged on a side of the first hole injection layer away from the driving backplane; the second primary color light-emitting device comprises a second hole injection layer, a first active layer of the second primary color light-emitting device, a first electron injection layer of the second primary color light-emitting device, a second active layer of the second primary color light-emitting device, and a second electron injection layer of the second primary color light-emitting device which are sequentially arranged; the second primary color light-emitting device The second active layer of the second primary color light emitting device includes a second sub-active layer, which includes a second barrier layer, a second quantum well protection layer, and a second multi-quantum well layer, which are sequentially arranged on the side of the first electron injection layer of the second primary color light emitting device away from the driving backplane; the third primary color light emitting device includes a third hole injection layer, a first active layer of the third primary color light emitting device, a first electron injection layer of the third primary color light emitting device, a second active layer of the third primary color light emitting device, a second electron injection layer of the third primary color light emitting device, a third active layer of the third primary color light emitting device, and a third electron injection layer of the third primary color light emitting device, which are sequentially arranged; the third active layer of the third primary color light emitting device includes a third sub-active layer, which includes a third barrier layer, a third quantum well protection layer, and a third multi-quantum well layer, which are sequentially arranged on the side of the second electron injection layer of the third primary color light emitting device away from the driving backplane. A transparent electrode layer is formed, which is coupled to the first electron injection layer of the first primary color light emitting device, the second electron injection layer of the second primary color light emitting device, and the third electron injection layer of the third primary color light emitting device, respectively.

[0037] The chip preparation method provided in the embodiment of the present application can obtain a light-emitting device that emits three colors of light by pixelating a wafer. Moreover, the wafer is bonded to the driving backplane through a one-time bonding process, that is, the light-emitting device that emits three colors of light is bonded to the driving backplane through a one-time bonding process. The process flow is simple and the cost is low.

[0038] In a possible implementation, wafers in a wafer stack are pixelated to form first primary color light-emitting devices, second primary color light-emitting devices, and third primary color light-emitting devices that are spaced apart on a drive substrate in the wafer stack, including: cutting the wafer to form a first primary color device stack, a second primary color device stack, and a third primary color light-emitting device that are spaced apart; the first primary color device stack includes a first hole injection layer, a first active layer of the first primary color light-emitting device, a first electron injection layer of the first primary color light-emitting device, a second active layer of the first primary color light-emitting device, a second electron injection layer of the first primary color light-emitting device, a third active layer of the first primary color light-emitting device, and a third electron injection layer of the first primary color light-emitting device; the second primary color device The stack includes a second hole injection layer, a first active layer of a second primary color light emitting device, a first electron injection layer of a second primary color light emitting device, a second active layer of a second primary color light emitting device, a second electron injection layer of a second primary color light emitting device, a third active layer of a second primary color light emitting device, and a third electron injection layer of a second primary color light emitting device; the third active layer of the second primary color light emitting device, the third electron injection layer of the second primary color light emitting device, the third active layer of the first primary color light emitting device, and the third electron injection layer of the first primary color light emitting device are removed to form a stack of second primary color light emitting devices and first primary color devices; the second active layer of the first primary color light emitting device and the second electron injection layer of the first primary color light emitting device are removed to form a first primary color light emitting device. The transparent electrode layer prepared in this way has a large contact area with the electron injection layer in each light emitting device, and a good electron transmission effect.

[0039] In a possible implementation, the first primary color light-emitting device further includes a second active layer of the first primary color light-emitting device, a second electron injection layer of the first primary color light-emitting device, a third active layer of the first primary color light-emitting device, and a third electron injection layer of the first primary color light-emitting device, which are sequentially arranged at a side where the first electron injection layer of the first primary color light-emitting device is away from the driving backplane; the second primary color light-emitting device further includes a third active layer of the second primary color light-emitting device, a third electron injection layer of the second primary color light-emitting device, and a third electron injection layer of the second primary color light-emitting device, which are sequentially arranged at a side where the second electron injection layer of the second primary color light-emitting device is away from the driving backplane; before forming the transparent electrode layer, the preparation method further includes: forming a first via hole and a second via hole; the first via hole penetrates the third electron injection layer of the first primary color light-emitting device, the third active layer of the first primary color light-emitting device, the second electron injection layer of the first primary color light-emitting device, and the second active layer of the first primary color light-emitting device, and the second via hole penetrates the third electron injection layer of the second primary color light-emitting device and the third active layer of the second primary color light-emitting device; wherein the transparent electrode layer is coupled to the first electron injection layer of the first primary color light-emitting device through the first via hole, and is coupled to the second electron injection layer of the second primary color light-emitting device through the second via hole. The top layer of the chip finally formed in this way has a relatively high flatness, which can subsequently support the platformization of the top of the chip to facilitate the subsequent production of other processes such as microlenses on the top of the chip.

[0040] In a possible implementation, the preparation method also includes: forming a reflective baffle; the reflective baffle includes a first sub-reflective baffle, a second sub-reflective baffle and a third sub-reflective baffle; the first sub-reflective baffle is arranged on the side of the first primary color light-emitting device, and the top of the first sub-reflective baffle away from the driving back plate is higher than the top of the first multi-quantum well layer away from the driving back plate; the second sub-reflective baffle is arranged on the side of the second primary color light-emitting device, and the top of the second sub-reflective baffle away from the driving back plate is higher than the top of the second multi-quantum well layer away from the driving back plate; the third sub-reflective baffle is arranged on the side of the third primary color light-emitting device, and the top of the third sub-reflective baffle away from the driving back plate is higher than the top of the third multi-quantum well layer away from the driving back plate. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A schematic diagram of an AR glasses provided in an embodiment of the present application;

[0042] Figure 2A A full-color display diagram of a chip according to an embodiment of the present application;

[0043] Figure 2B A schematic diagram of a product structure of a process for preparing an epitaxial stack provided in an embodiment of the present application;

[0044] Figure 3 A schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0045] Figure 4 A schematic diagram of a light-emitting principle provided in an embodiment of the present application;

[0046] Figure 5 A schematic diagram of the structure of another chip provided in an embodiment of the present application;

[0047] Fig. 6A and Figure 6B A schematic diagram of the structure of another chip provided in an embodiment of the present application;

[0048] Fig. 7A and Figure 7B A schematic diagram of the structure of another chip provided in an embodiment of the present application;

[0049] Fig. 8A and Figure 8B A schematic diagram of the structure of another chip provided in an embodiment of the present application;

[0050] Fig. 9 A schematic diagram of the structure of another chip provided in an embodiment of the present application;

[0051] Fig.10 A schematic diagram of the structure of another chip provided in an embodiment of the present application;

[0052] Fig.11A and Fig. 11B A flowchart of a chip preparation method provided in an embodiment of the present application;

[0053] Fig. 12A and Fig. 12B A schematic diagram of the structure of a wafer provided in an embodiment of the present application;

[0054] Fig. 12C A schematic diagram of the structure of a third primary color active film layer provided in an embodiment of the present application;

[0055] Fig.13 A schematic diagram of the structure of a wafer stack provided in an embodiment of the present application;

[0056] Figure 14A-14E A schematic diagram of the product structure of a chip manufacturing process provided in an embodiment of the present application;

[0057] Fig.15 A schematic diagram of the product structure of a chip manufacturing process provided in an embodiment of the present application;

[0058] Fig.16 A schematic diagram of the product structure of a chip manufacturing process provided in an embodiment of the present application;

[0059] Fig.17A and Fig. 17B A schematic diagram of the structure of another chip provided in an embodiment of the present application;

[0060] Fig.18 A schematic diagram of a product structure of an intermediate state of preparation of a chip provided in an embodiment of the present application;

[0061] Fig.19 A schematic diagram of the structure of another chip provided in an embodiment of the present application;

[0062] Fig. 20 A schematic diagram of the structure of another chip provided in an embodiment of the present application;

[0063] Fig.21 A schematic diagram of the structure of another chip provided in an embodiment of the present application;

[0064] Fig. 22 A flow chart of the preparation of a chip provided in an embodiment of the present application;

[0065] Fig.23 and Fig.24 A schematic diagram of the product structure of a chip manufacturing process provided in an embodiment of the present application;

[0066] Fig.25 A schematic diagram of an arrangement of light-emitting devices provided in an embodiment of the present application. DETAILED DESCRIPTION

[0067] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0068] In the following, the terms "second", "first", etc. are used only for convenience of description and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, features defined as "second", "first", etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "multiple" means two or more. In the embodiments of the present application, unless otherwise clearly specified and limited, the term "coupling" may be a direct electrical connection or an indirect electrical connection through an intermediate medium.

[0069] In the embodiments of the present application, "and / or" describes the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B may be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0070] An embodiment of the present application provides an electronic device, which may be, for example, a virtual reality (VR) electronic device, an augmented reality (AR) electronic device, a mixed reality (MR) device, a watch, a bracelet, a mobile phone, a tablet, a television, a projector, a micro-projector, a car pixel headlight, a front window augmented reality head up display (AR-HUD), or other electronic devices with a pixel display function.

[0071] Taking the electronic device as an AR head-mounted display device as an example, the AR head-mounted display device may include AR glasses or an AR helmet, etc. For the sake of convenience of explanation, the electronic device is taken as an example of AR glasses.

[0072] Figure 1 A schematic diagram of an AR glasses provided in an embodiment of the present application.

[0073] Figure 1As shown, the AR glasses include a frame 101, temples 102 and lenses 103. The lenses 103 are mounted on the frame 101. The temples 102 are connected to the frame 101. The temples 102 and the frame 101 can wear the AR glasses in front of the user's eyes. The temples 102 are provided with a display device 200 (such as an optical machine) that can display images or other content.

[0074] The lens 103 may be a prism-shaped eyeglass lens based on an aspherical surface, a free-form surface or its corresponding Fresnel surface. The lens 103 may include a lens body and an optical waveguide sheet, wherein the optical waveguide sheet is disposed on the lens body, and the lens body is used to receive the image light (optical signal) emitted by the display device 200, and transmit the received image light to the optical waveguide sheet, and the optical waveguide sheet is used to reflect the received effective image light to a preset position to form a virtual image, thereby forming an image in front of the user's eyes. For example, the optical signal emitted by the display device 200 enters the lens body from the vicinity of the temple 102, and is totally reflected and propagated in the lens body, and then reflected by the optical waveguide sheet, and coupled out to enter the retina of the user's eye to form a virtual image on the retina, thereby enabling the user to view the virtual image.

[0075] Micro displays (micro-display) such as micro light emitting diode (Micro LED), mini light emitting diode (Mini LED), communication and display light emitting diode (light emitting diode, LED) have shown great potential in the display market with their advantages of high brightness, low power consumption, long life, high stability and small size, and can meet the needs of small size and high resolution scenes.

[0076] The display device 200 in the temple 102 can display images or other content through, for example, a Micro LED chip, a Mini LED chip, or an LED chip.

[0077] In some embodiments, the display device 200 includes a chip and a lens, the chip includes a micro display chip and a lens, and the lens is arranged on the light output side of the chip. The lens includes, for example, a convex lens (group), a Fresnel lens (group), a super lens (group) and other optical elements, and the lens projects and magnifies the image on the chip and then outputs it to the optical waveguide.

[0078] Figure 2A This is a diagram of a full-color display mode of a chip according to an embodiment of the present application.

[0079] In some technologies, blue-green epitaxial wafers based on gallium nitride (GaN)-based materials, or red epitaxial wafers based on aluminum gallium indium phosphide (AlGaInP)-based materials, can only obtain chips with three monochrome displays of red (R), green (G), and blue (B), and then use various light combination solutions. Figure 2A As shown, three monochromatic sub-chips of R, G, and B and a light-combining prism (X-cube) are used to combine three colors.

[0080] However, these light combining methods lead to problems such as complicated manufacturing process, increased process cost, larger size of the display device 200, loss of light combining efficiency, etc. If a high-performance R, G, B full-color micro-display (MD) chip can be obtained, the size of the display device 200 will be greatly reduced, the manufacturing cost will be reduced, and the brightness of the display device 200 will be increased.

[0081] At present, there are three main technical solutions for realizing MD chips: 1) Blue light Micro LED + red and green quantum dot color conversion solution. 2) Stacking and bonding of 3 R, G, B single-color epitaxial wafers, and then device processing. 3) Epitaxial side integration to realize R, G, B luminescent epitaxial wafers. For example, color-changing multiple quantum well (MQW) LED based on porous GaN solution, tunnel junction full-color LED based on R, G, B three-color multiple quantum well stacking (LED structure that requires vertical stacking and growth of 3 tunnel junctions).

[0082] The quantum dot color conversion solution faces problems such as complex quantum dot integration process, insufficient quantum dot color conversion brightness, quantum dot reliability and lifespan. The R, G, B monochrome epitaxial wafer stacking and bonding integration solution faces problems such as extremely high alignment accuracy requirements, overly complex device process flow, and high cost. The epitaxial side integration solution also faces problems such as complex epitaxial stacking structure, difficult epitaxial growth process, and complex matching device process. The full-color chips finally obtained often face limitations such as incorrect color, low efficiency, inconvenient brightness and color adjustment, and excessive operating voltage.

[0083] Figure 2B A schematic diagram of the product structure of a process for preparing an epitaxial stack provided in an embodiment of the present application.

[0084] For example, in the process of preparing the epitaxial stack, a tunnel junction full-color LED chip based on a stack of R, G, and B three-color multi-quantum wells is Figure 2BAs shown, an epitaxial stack is first formed, and the epitaxial stack includes a substrate, a buffer layer, a first electron injection layer, a blue multi-quantum well layer, a first hole injection layer, a first tunnel junction, a second electron injection layer, a green multi-quantum well layer, a second hole injection layer, a second tunnel junction, a third electron injection layer, a red multi-quantum well layer, and a third hole injection layer. Then, the epitaxial stack is patterned to form an epitaxial structure including a blue LED, a green LED, and a red LED.

[0085] The epitaxial stack includes three complete PN junction LED structures (including electron injection layer, multi-quantum well, hole injection layer), which emit red, green and blue light respectively. The three complete LEDs are connected by two tunneling junctions (the third tunneling junction can also be set on the surface of the third hole injection layer). When making LED devices, the electron injection layer above the tunneling junction in the corresponding LED is etched respectively, and then the tunneling principle of the tunneling junction is used to realize the hole injection of the lower LED. When the epitaxial structure is bonded to the driving backplane to form a chip, the chip can realize RGB full-color light emission.

[0086] However, the RGB full-color epitaxial structure based on the tunneling junction contains 3 complete PN junction LED structures and 2-3 tunneling junctions from bottom to top. The epitaxial structure is complex, and the epitaxial growth is difficult, time-consuming, and costly. If it is grown on a silicon (Si) substrate, an overly thick epitaxial layer may lead to the deterioration of parameters such as edge cracking and bowing. In addition, since the remaining structures continue to grow after the hole injection layer is grown, the hole injection layer is wrapped in the middle of the remaining epitaxial layers. The complex formed by the hydrogen (H) element and the magnesium (Mg) dopant mixed during the growth is difficult to remove during the subsequent annealing, so the activation of the hole injection layer is more difficult. Furthermore, the process of the epitaxial structure is relatively complicated. Each LED needs to be accurately etched to the electron injection layer on the tunneling junction above the multi-quantum well layer in the LED and the electron injection layer under the tunneling junction below the multi-quantum well layer, respectively, to make P-type electrodes and N-type electrodes, respectively, to form a stepped inverted pixel structure, and the N-type electrode of the upper LED also serves as the P-type electrode of the lower LED. Therefore, based on the epitaxial structure, it is difficult to obtain a vertically structured light-emitting pixel. Finally, due to the introduction of the tunnel junction, an additional bias voltage is required to turn on the LED, so the turn-on voltage of the tunnel junction LED is usually greater than 4V, which is much greater than the turn-on voltage of a single PN junction LED (2-3V). Excessive voltage will reduce the wall plug efficiency (WPE) of the device, increase the heat and power consumption of the display device 200 based on the tunnel junction LED, and reduce the battery life and brightness of the entire device.

[0087] A chip provided in an embodiment of the present application can reduce power consumption, process difficulty, and cost, and improve chip performance.

[0088] Figure 3A schematic diagram of the structure of a chip provided in an embodiment of the present application.

[0089] In some embodiments, Figure 3 As shown, the chip includes a driving backplane and a first primary color light emitting device LED1 and a second primary color light emitting device LED2 arranged at intervals on the same side of the driving backplane. Then, the chip includes a first primary color sub-pixel P1 emitting a first primary color light and a second primary color sub-pixel P2 emitting a second primary color light. The first primary color light and the second primary color light include, for example, two of red light, green light and blue light.

[0090] The first primary color light emitting device LED1 includes a first bonding layer 26A, a first hole injection layer PA, a first active layer T1A of LED1 and a first electron injection layer N1A of LED1 which are arranged in sequence. The first active layer T1A of LED1 includes a first sub-active layer A1. The first sub-active layer A1 includes a first barrier layer L11A and a first multi-quantum well layer MQW11A which are arranged in sequence on the side of the first hole injection layer PA away from the driving backplane.

[0091] The second primary color light emitting device LED2 includes a second bonding layer 26B, a second hole injection layer PB, a first active layer T1B of LED2, a first electron injection layer N1B of LED2, a second active layer T2B of LED2 and a second electron injection layer N2B of LED2 which are arranged in sequence. The second active layer T2B of LED2 includes a second sub-active layer B2, and the second sub-active layer B2 includes a second barrier layer L21B, a second quantum well protection layer PQ2B and a second multi-quantum well layer MQW21B which are arranged in sequence on a side of the first electron injection layer N1B of LED2 away from the driving backplane.

[0092] For example, the first bonding layer 26A is bonded to the driving back plate, and the second bonding layer 26B is bonded to the driving back plate. The first bonding layer 26A and the second bonding layer 26B are of the same layer and the same material.

[0093] "Same layer" means that the film layer used to form a specific pattern is formed by the same film forming process, and then the layer structure of the specific pattern is formed by patterning (for example, by using a mask through a composition process). Depending on the specific pattern, the patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0094] Then, the first bonding layer 26A and the second bonding layer 26B are the same layer, which can be understood as the first bonding layer 26A and the second bonding layer 26B are prepared by the same bonding film layer. Then, the first primary color light emitting device LED1 and the second primary color light emitting device LED2 are bonded to the driving backplane in the same bonding process.

[0095] For example, the materials of the first bonding layer 26A and the second bonding layer 26B include metal materials such as chromium (Cr), titanium (Ti), nickel (Ni), platinum (Pt), gold (Au), copper (Cu), aluminum (Al), silver (Ag), titanium tungsten (TiW), tin (Sn), etc., conductive dielectric materials such as titanium nitride / tantalum nitride (TiN / TaN), a distributed Bragg reflector (DBR) with conductive through holes (dielectric stacks such as tantalum oxide / silicon oxide (Ta2O5 / SiO2), silicon oxide / titanium oxide (SiO2 / TiO2), etc.), or a stacked structure of the above film layers.

[0096] By setting the first bonding layer 26A and the second bonding layer 26B as conductive bonding layers with high reflection efficiency, each primary color light can be reflected on the basis of ensuring the conductive bonding effect, thereby improving the light extraction efficiency.

[0097] For example, the first hole injection layer PA and the second hole injection layer PB are made of the same layer and the same material. For example, the first hole injection layer PA and the second hole injection layer PB are obtained by pixelating the same hole injection film layer in the wafer.

[0098] For example, P-type doping can be performed in IIIV semiconductor materials (such as gallium oxide and other materials) to form a first hole injection layer PA and a second hole injection layer PB. The first hole injection layer PA and the second hole injection layer PB can transport holes.

[0099] For example, the first electron injection layer N1A of LED1 and the first electron injection layer N1B of LED2 are of the same layer and the same material. The first electron injection layer N1A of LED1 and the first electron injection layer N1B of LED2 are obtained by pixelating the same electron injection film layer in the wafer.

[0100] For example, N-type doping can be performed in IIIV semiconductor materials (such as gallium oxide) to form the first electron injection layer N1A of LED1 and the first electron injection layer N1B of LED2, and the first electron injection layer N1A of LED1 and the first electron injection layer N1B of LED2 can transmit electrons. The materials of the first electron injection layer N1A of LED1 and the first electron injection layer N1B of LED2 can include, for example, In x3 Ga 1-x3 N, GaN, aluminum gallium nitride (Al y3 Ga 1-y3 N) or a superlattice material composed of two of the above materials in alternating periods. <x3,y3≤1。

[0101] Optionally, the thickness of the first electron injection layer N1A of LED1 and the first electron injection layer N1B of LED2 is between 20nm-500nm. For example, the thickness of the first electron injection layer N1A of LED1 and the first electron injection layer N1B of LED2 is 20nm, 50nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, or 500nm. By setting the thickness of the first electron injection layer N1A of LED1 and the first electron injection layer N1B of LED2 between 20nm-500nm, the thickness of the wafer is reduced while satisfying electron transmission.

[0102] For example, the second electron injection layer N2B of LED2 can refer to the related description of the first electron injection layer N1B of LED2.

[0103] For example, the first active layer T1A of LED1 and the first active layer T1B of LED2 are made of the same layer and the same material. For example, the first active layer T1A of LED1 and the first active layer T1B of LED2 are prepared from the same active film layer.

[0104] For example, the first sub-active layer A1 of LED1 and the first sub-active layer B1 of LED2 are of the same layer and the same material. The first sub-active layer A1 of LED1 includes a first barrier layer L11A and a first multi-quantum well layer MQW11A sequentially arranged on a side of the first hole injection layer PA away from the driving backplane. The first sub-active layer B1 of LED2 includes a first barrier layer L11B and a first multi-quantum well layer MQW11B sequentially arranged on a side of the second hole injection layer PB away from the driving backplane. The first barrier layer L11A and the first barrier layer L11B are of the same layer and the same material. The first multi-quantum well layer MQW11A and the first multi-quantum well layer MQW11B are of the same layer and the same material.

[0105] For example, in the second active layer T2B of LED2, the material of the second multi-quantum well layer MQW21B in the second sub-active layer B2 includes In x1 Ga 1-x1 N, etc., the material of the second quantum well protection layer PQ2B includes aluminum nitride (AlN) or Al y1 Ga 1-y1 N, etc., and the material of the second barrier layer L21B includes In x2 Ga 1-x2 N, GaN or Al y2 Ga 1-y2 N, etc. Among them, 0<x1、x2≤1、x1> x2, x2>x3, 0<y1、y2≤1、y1> y2, y2>y3.

[0106] For example, the thickness of the second multi-quantum well layer MQW21B is between 1nm and 5nm. For example, the thickness of the second multi-quantum well layer MQW21B is 1nm, 1.5nm, 2nm, 2.5nm, 3nm, 3.5nm, 4nm, 4.5nm or 5nm. For example, the thickness of the second quantum well protection layer PQ2B is between 0.25nm and 5nm. For example, the thickness of the second quantum well protection layer PQ2B is 0.25nm, 0.5nm, 1nm, 1.5nm, 2nm, 2.5nm, 3nm, 3.5nm, 4nm, 4.5nm or 5nm. For example, the thickness of the second barrier layer L21B is between 2nm and 100nm. For example, the thickness of the second barrier layer L21B is 2nm, 20nm, 50nm, 100nm, 150nm or 200nm.

[0107] When the thickness of the multi-quantum well layer is fixed, the emission wavelength of the multi-quantum well layer can be adjusted by adjusting the component x1 of indium (In). The larger the x1, the longer the emission wavelength of the multi-quantum well layer. When the component x1 of In is fixed, the emission wavelength of the multi-quantum well layer can be adjusted by adjusting the thickness of the multi-quantum well layer. The thicker the thickness of the multi-quantum well layer, the longer the emission wavelength of the multi-quantum well layer.

[0108] In the second sub-active layer B2, the second quantum well protection layer PQ2B has the largest bandgap width, and the second multi-quantum well layer MQW21B has the smallest bandgap width. The second quantum well protection layer PQ2B provides a high potential barrier for the electrons trapped in the second multi-quantum well layer MQW21B, preventing the electrons from escaping from the second multi-quantum well layer MQW21B, so that the electrons and holes emit light in the second multi-quantum well layer MQW21B.

[0109] The second active layer T2B of LED2 may include one second sub-active layer B2, or may include a plurality of second sub-active layers B2.

[0110] The first barrier layer L11A and the first multi-quantum well layer MQW11A included in the first active layer T1A of LED1 may refer to the above description about the second barrier layer L21B and the second multi-quantum well layer MQW21B included in the second sub-active layer B2 in the second active layer T2B of LED2.

[0111] Figure 4 A schematic diagram of the light-emitting principle provided in an embodiment of the present application.

[0112] Figure 4 For the electron e - In general, after adding the quantum well protection layer, the limiting height of the barrier increases. -After falling into the quantum well, it becomes more difficult to escape from the quantum well along the direction of the arrow, making the electron e - It is difficult to move to the hole side, and it will only stay in the first active layer and will not move to the next active layer. However, for the hole h+, as long as it falls into the quantum well in the direction of the arrow, there is no obstacle and it can move directly to the electron side. Therefore, the hole can be transferred from the driving backplane to any active layer.

[0113] In the traditional GaN-based LED epitaxial structure, when the forward bias is injected, as the voltage increases, the hole injection layer recombines with the holes in the upper multi-quantum well layer. Therefore, when the forward bias is applied, the epitaxial structure mainly emits light in the multi-quantum well region close to the upper layer of the hole injection layer. In the chip provided in the embodiment of the present application, due to the unique design of the active layer, when the forward bias is injected, the electrons will be blocked by the high potential barrier of the quantum well protection layer in the active layer and cannot effectively move to the side close to the hole injection layer. When the holes are injected from one side of the hole injection layer, due to the higher bandgap width of the barrier layer itself, they can be smoothly injected into each layer of the active layer. Therefore, the electrons and holes in the chip recombine and emit light mainly in the active layer farthest from the driving backplane.

[0114] Therefore, in the chip provided in the embodiment of the present application, the second primary color sub-pixel P2 is used to emit the third primary color light, and the electrons are injected into the second active layer T2B of LED2 through the second electron injection layer N2B of LED2, and the holes are transmitted to the second active layer T2B of LED2 through the second hole injection layer PB. The electrons and holes are recombined in the second multi-quantum well layer MQW21B in the second active layer T2B of LED2 to emit the second primary color light. Since there is a second quantum well protection layer PQ2B in the second active layer T2B of LED2, and the band gap width of the second quantum well protection layer PQ2B is much larger than the band gap width of the second barrier layer L21B and the second multi-quantum well layer MQW21B, the electrons injected into the second multi-quantum well layer MQW21B by the second electron injection layer N2B of LED2 will be blocked by the high potential barrier and are difficult to move to the first electron injection layer N1B of LED2. However, the holes injected from the second hole injection layer PB can move to the second multi-quantum well layer MQW21B because there is no high potential barrier to block them. Therefore, in the second primary color sub-pixel P2, only the second active layer T2B of LED2 emits the second primary color light, and the first active layer T1B of LED2 does not emit light.

[0115] Similarly, the first primary color sub-pixel P1 is used to emit the first primary color light, electrons are injected into the first active layer T1A of LED1 through the first electron injection layer N1A of LED1, and holes are transmitted to the first active layer T1A of LED1 through the first hole injection layer PA. Electrons and holes are recombined in the first multi-quantum well layer MQW11A in the first active layer T1A of LED1 to emit the first primary color light.

[0116] The chip provided in the embodiment of the present application includes a first primary color light emitting device LED1 and a second primary color light emitting device LED2. The first primary color light emitting device LED1 only includes the first active layer T1A of LED1, which is used to emit the first primary color light. The second primary color light emitting device LED2 includes the first active layer T1B of LED2 and the second active layer T2B of LED2. Since the second active layer T2B of LED2 is arranged on the side of the first active layer T1B of LED2 away from the driving backplane, and the second active layer T2B of LED2 includes the second quantum well protection layer PQ2B, the second quantum well protection layer PQ2B will increase the barrier height, prevent electrons from moving to the first active layer T1B of LED2, and holes can move to the second active layer T2B of LED2. Therefore, in the second primary color light emitting device LED2, only the second active layer T2B of LED2 emits light, and the first active layer T1B of LED2 does not emit light, so that the second primary color light emitting device LED2 emits the second primary color light, thereby realizing that the chip emits multi-primary color light.

[0117] On this basis, the first primary color light emitting device LED1 and the second primary color light emitting device LED2 are of the same layer and material (for example, the first active layer T1A of LED1 and the first active layer T1B of LED2 are of the same layer and material), then a multi-primary color light emitting wafer can be formed on the same substrate through a single epitaxial process. And the first bonding layer 26A and the second bonding layer 26B are of the same layer and material, then the first primary color light emitting device LED1 and the second primary color light emitting device LED2 can be bonded to the driving backplane through a single bonding process, without the need for additional wafer bonding and other integration processes. Moreover, taking the second primary color light emitting device LED2 as an example, the semiconductor layer in the second primary color light emitting device LED2 only includes a P-type semiconductor layer (the second hole injection layer PB), and the rest are N-type semiconductor layers. The second primary color light emitting device LED2 only includes a PN junction, and the epitaxial structure is simple, and the epitaxial growth is less difficult, the time is short, the quality is high, and the cost is low. Similarly, the first primary color light emitting device LED1 also includes only a PN junction. Full-color display can be achieved with one PN junction, one epitaxial process, and one bonding process. There is no need for complex solutions such as quantum dot color conversion, three-color light combination, and multiple PN junction tunneling junctions. The chip has high integration (few film layers, small volume), simple structure, simple process flow, low cost, and long life. Furthermore, in the light-emitting device, each time it is mainly an active layer with a single primary color, the color of the sub-pixel is positive, the brightness and color are easy to adjust, and the luminous efficiency is high. The light-emitting device is a vertical structure light-emitting device. Compared with the flip-chip structure light-emitting device, the chip has a low driving voltage and low power consumption.

[0118] Figure 5 A schematic diagram of the structure of another chip provided in an embodiment of the present application.

[0119] In some embodiments, Figure 5 As shown, the chip further includes a third primary color light emitting device LED3 spaced apart from the second primary color light emitting device LED2. Then, the chip further includes a third primary color sub-pixel P3 emitting third primary color light. The third primary color light includes, for example, the remaining one of red light, green light and blue light.

[0120] The third primary color light emitting device LED3 includes a third bonding layer 26C, a third hole injection layer PC, a first active layer T1C of LED3, a first electron injection layer N1C of LED3, a second active layer T2C of LED3, a second electron injection layer N2C of LED3, a third active layer T3C of LED3 and a third electron injection layer of LED3 which are arranged in sequence.

[0121] For example, the third bonding layer 26C is bonded to the driving back plate, and the third bonding layer 26C and the first bonding layer 26A are made of the same layer and the same material.

[0122] For example, the first active layer T1C of the LED 3 includes a first sub-active layer C1, and the first sub-active layer C1 includes a first barrier layer L11C and a first multi-quantum well layer MQW11C which are sequentially arranged on a side of the third hole injection layer PC away from the driving backplane.

[0123] The first active layer T1C of LED3 and the first active layer T1A of LED1 are made of the same layer and material, the first barrier layer L11A and the first barrier layer L11C are made of the same layer and material, and the first multi-quantum well layer MQW11A and the first multi-quantum well layer MQW11C are made of the same layer and material.

[0124] For example, the second active layer T2C of LED3 includes a second sub-active layer C2, which includes a second barrier layer L21C, a second quantum well protection layer PQ2C and a second multi-quantum well layer MQW21C, which are sequentially arranged on the side of the first electron injection layer N1C of LED3 away from the driving backplane.

[0125] The second active layer T2C of LED3 and the second active layer T2B of LED2 are of the same layer and material, the second barrier layer L21B and the second barrier layer L21C are of the same layer and material, the second quantum well protection layer PQ2B and the second quantum well protection layer PQ2C are of the same layer and material, and the second multi-quantum well layer MQW21B and the second multi-quantum well layer MQW21C are of the same layer and material.

[0126] The third active layer T3C of LED3 includes a third sub-active layer C3, which includes a third barrier layer L31C, a third quantum well protection layer PQ3C and a third multi-quantum well layer MQW31C which are sequentially arranged on the side of the second electron injection layer N2C of LED3 away from the driving backplane.

[0127] The third primary color sub-pixel P3 is used to emit the third primary color light. Electrons are injected into the third active layer T3C of LED3 through the third electron injection layer N3C of LED3, and holes are transmitted to the third active layer T3C of LED3 through the third hole injection layer PC. Electrons and holes are recombined in the third multi-quantum well layer MQW31C in the third active layer T3C of LED3 to emit the third primary color light. Since there is a third quantum well protection layer PQ3C in the third active layer T3C of LED3, and the band gap width of the third quantum well protection layer PQ3C is much larger than the band gap width of the third barrier layer L31C and the third multi-quantum well layer MQW31C, the electrons injected into the third multi-quantum well layer MQW31C by the third electron injection layer N3C of LED3 will be blocked by the high potential barrier and are difficult to move to the second electron injection layer N2C. However, the holes injected from the third hole injection layer PC can move to the third multi-quantum well layer MQW31C because there is no high potential barrier. Therefore, in the third primary color sub-pixel P3, only the third active layer T3C of LED3 emits the third primary color light, and the second active layer T2C of LED3 and the first active layer T1C of LED2 do not emit light.

[0128] In the embodiment of the present application, the third active layer T3C, the second active layer T2C and the first active layer T1C may be a red active layer, a blue active layer, and a green active layer, respectively, or a red active layer, a green active layer, and a blue active layer, or a blue active layer, a red active layer, and a green active layer, or a blue active layer, a green active layer, and a red active layer, or a green active layer, a blue active layer, and a red active layer, or a green active layer, a red active layer, and a blue active layer.

[0129] The first primary color light emitting device LED1, the second primary color light emitting device LED2, and the third primary color light emitting device LED3 are of the same layer and material (for example, the first active layer T1A of LED1, the first active layer T1B of LED2, and the first active layer T1C of LED3 are of the same layer and material), then a wafer emitting red, green, and blue full-color light can be formed on the same substrate through a single epitaxial process. And the first bonding layer 26A, the second bonding layer 26B, and the third bonding layer 26C are of the same layer and material, then the first primary color light emitting device LED1, the second primary color light emitting device LED2, and the third primary color light emitting device LED3 can be bonded to the driving backplane through a single bonding process, without the need for additional wafer bonding and other integration processes. Moreover, the third primary color light emitting device LED3 also includes only one PN junction. Full-color display can be achieved with one PN junction, one epitaxial process, and one bonding process. There is no need for complex solutions such as quantum dot color conversion, three-color light combination, and multiple PN junctions and tunnel junctions. The chip has high integration (few film layers and small size), simple structure, simple process flow, low cost, and long life.

[0130] In some embodiments, the structure of the second primary color light emitting device in the chip provided in the embodiment of the present application is Figure 5 In other words, Figure 3 On the basis of, the second light emitting device LED2 may further include a third active layer of LED2 and a third electron injection layer of LED2 which are arranged on a side of the second electron injection layer N2B of LED2 away from the driving backplane.

[0131] In some embodiments, the structure of the first light-emitting device in the chip provided in the embodiment of the present application is Figure 5 In other words, Figure 3 On the basis of, the first primary color light emitting device LED1 further includes a second active layer of LED1 and a second electron injection layer of LED1 which are arranged on a side of the first electron injection layer N1A of LED1 away from the driving backplane.

[0132] Fig. 6A and Figure 6B A schematic diagram of the structure of another chip provided in an embodiment of the present application.

[0133] In some embodiments, Fig. 6A and Figure 6B As shown, the chip further includes a transparent electrode layer 29. The transparent electrode layer 29 is coupled to the first electron injection layer N1A of LED1, the second electron injection layer N2B of LED2, and the third electron injection layer N3C of LED3, respectively. It is used to inject electrons into the first primary color sub-pixel P1, the second primary color sub-pixel P2, and the third primary color sub-pixel P3. The first primary color sub-pixel P1 is used to emit the first primary color light, the second primary color sub-pixel P2 is used to emit the second primary color light, and the third primary color sub-pixel P3 is used to emit the third primary color light.

[0134] The driving backplane is also provided with a cathode pin, which is coupled to the transparent electrode layer 29 through a metal through hole to realize n-type current injection of each pixel and provide electrons for each light-emitting device.

[0135] The transparent electrode layer 29 in the third primary color light emitting device LED3 is directly coupled to the third electron injection layer N3C of LED3. The electrons provided by the transparent electrode layer 29 directly enter the third multi-quantum well layer MQW31C from the third electron injection layer N3C of LED3, which can reduce the number of film layers of the chip.

[0136] In some embodiments, the chip further includes a dielectric layer 27, which is disposed on the side of the transparent electrode layer 29 facing the driving backplane, and the transparent electrode layer 29 is coupled to the first electron injection layer N1A of LED1, the second electron injection layer N2B of LED2, and the third electron injection layer N3C of LED3 through the dielectric layer 27. The material of the dielectric layer 27 may include insulating dielectric materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), and aluminum oxide (Al2O3), and the dielectric layer 27 may be a single film layer structure or a stacked layer structure.

[0137] The dielectric layer 27 covers the portion of the driving backplane not covered by the three devices, the side surface of the third primary color light emitting device LED3 , the side surface of the second primary color light emitting device LED2 , and the side surface of the first primary color light emitting device LED1 .

[0138] By providing a dielectric layer 27 covering the side surfaces of the third primary color light emitting device LED3, the second primary color light emitting device LED2 and the first primary color light emitting device LED1, the side walls of the light emitting devices can be passivated and electrically isolated to reduce crosstalk.

[0139] For example, Fig. 6A As shown, the dielectric layer 27 does not cover the edges of the third electron injection layer N3C of LED3, the second electron injection layer N2B of LED2, and the first electron injection layer N1A of LED1, exposing the entire third N-type semiconductor layer 22C, the second electron injection layer N2B of LED2, and the first electron layer N1A of LED1.

[0140] Fig. 7A and Figure 7B A schematic diagram of the structure of another chip provided in an embodiment of the present application.

[0141] Or, for example, Fig. 7A As shown, the dielectric layer 27 includes a first opening, a second opening, and a third opening. The first opening exposes a portion (e.g., a middle region) of the first electron injection layer N1A of LED1, and the dielectric layer 27 covers the edge of the first electron injection layer N1A of LED1. The second opening exposes a portion of the second electron injection layer N2B of LED2, and the dielectric layer 27 covers the edge of the second electron injection layer N2B of LED2. The third opening exposes a portion of the third electron injection layer N3C of LED3, and the dielectric layer 27 covers the edge of the third electron injection layer N3C of LED3. The dielectric layer 27 also covers a portion of the third electron injection layer N3C of LED3, the second electron injection layer N2B of LED2, and the first electron injection layer N1A of LED1.

[0142] The transparent electrode layer 29 is coupled to the first electron injection layer N1A of LED1 through the first opening, coupled to the second electron injection layer N2B of LED2 through the second opening, and coupled to the third electron injection layer N3C of LED3 through the third opening.

[0143] The first opening exposes the middle area of ​​the first electron injection layer N1A of LED1, which can prevent electrons from being injected from the edge of the first electron injection layer N1A of LED1, and reduce the possibility that the light-emitting effect of the first primary color light-emitting device LED1 is affected by edge damage. Similarly, the second opening exposes the middle area of ​​the second electron injection layer N2B of LED2, which can prevent electrons from being injected from the edge of the second electron injection layer N2B of LED2, and reduce the possibility that the light-emitting effect of the second primary color light-emitting device LED2 is affected by edge damage. Similarly, the third opening exposes the middle area of ​​the third electron injection layer N3C of LED3, which can prevent electrons from being injected from the edge of the third electron injection layer N3C of LED3, and reduce the possibility that the light-emitting effect of the third primary color light-emitting device LED3 is affected by edge damage.

[0144] In some embodiments, Fig. 6A and Figure 6B As shown, the chip also includes a reflective baffle wall arranged on the driving backplane.

[0145] For example, the material of the reflective baffle wall can be a material with high reflectivity. For example, the material of the reflective baffle wall includes a metal material with high conductivity, such as Al, Ag, Pt, Cu, Au, etc. Or, for example, the reflective baffle wall can be a periodic dielectric stack material with high reflectivity, such as a DBR composed of SiO2 / TiO2, Ta2O5 / SiO2 stack, etc.

[0146] For example, the reflective blocking wall includes a first sub-reflective blocking wall 281 , a second sub-reflective blocking wall 282 and a third sub-reflective blocking wall 283 .

[0147] The first sub-reflective baffle 281 is disposed on the side of the first primary color light emitting device LED1. For example, the first sub-reflective baffle 281 is disposed between the first primary color light emitting device LED1 and the second primary color light emitting device LED2. Or for example, the first sub-reflective baffle 281 is disposed between the first primary color light emitting device LED1 and the third primary color light emitting device LED3. For example, the first sub-reflective baffle 281 is away from the top of the driving backplane, lower than or higher than or flush with the first multi-quantum well layer MQW11A away from the top of the driving backplane.

[0148] When the top of the first sub-reflective baffle 281 away from the driving backplane is higher than the top of the second multi-quantum well layer MQW21B away from the driving backplane, the light emitted by the first primary color light-emitting device LED1 and the second primary color light-emitting device LED2 can be completely isolated and blocked, thereby reducing the optical crosstalk between the first primary color light-emitting device LED1 and the second primary color light-emitting device LED2.

[0149] The second sub-reflective baffle 282 is disposed on the side of the second primary color light emitting device LED2, for example, the second sub-reflective baffle 282 is disposed between the second primary color light emitting device LED2 and the third primary color light emitting device LED3. Or for example, the second sub-reflective baffle 282 is disposed between the second primary color light emitting device LED2 and the first primary color light emitting device LED1. The second sub-reflective baffle 282 is away from the top of the driving backplane, higher than or flush with (or lower than), and the second multi-quantum well layer MQW21B is away from the top of the driving backplane.

[0150] The third sub-reflective baffle 283 is arranged on the side of the third primary color light emitting device LED3, for example, the third sub-reflective baffle 283 is arranged between the third primary color light emitting device LED3 and the first primary color light emitting device LED1. Or for example, the third sub-reflective baffle 283 is arranged between the third primary color light emitting device LED3 and the second primary color light emitting device LED2. The third sub-reflective baffle 283 is far away from the top of the driving backplane, higher than or flush with (can also be lower than), and the third multi-quantum well layer MQW31C is far away from the top of the driving backplane.

[0151] The cross-sectional shapes of the first sub-reflective blocking wall 281, the second sub-reflective blocking wall 282, and the third sub-reflective blocking wall 283 can be any shapes such as rectangle, regular trapezoid, inverted trapezoid, triangle, etc. Fig. 6A and Figure 6B The figure is for illustration only.

[0152] By setting up reflective baffles between light-emitting devices, the light radiated from the side of the light-emitting device can be reflected and radiated in a direction perpendicular to the driving backplane, so that the light radiated from the side of the light-emitting device can be utilized, avoiding the waste of photons caused by side radiation and improving the overall light extraction efficiency (photoelectric conversion efficiency) of the chip. Moreover, after the reflective baffles are set around the periphery of the light-emitting device, the light radiated by the light-emitting device will be reflected and blocked by the reflective baffles, reducing the light extraction angle, preventing the light from entering the area where the adjacent light-emitting device is located, reducing the interference with the visual brightness of the adjacent light-emitting device (reducing crosstalk between light-emitting devices), and helping to improve the resolution of the chip.

[0153] In some embodiments, the reflective baffle is made of metal, and the transparent electrode layer 29 is coupled to the reflective baffle. The transparent electrode layer 29 is made of a transparent conductive material, and the reflective baffle is made of metal. The conductivity of the metal is greater than that of the transparent conductive material. During the driving process of the light-emitting device, the current is transmitted through the reflective baffle, which can alleviate the voltage drop phenomenon in the light-emitting area.

[0154] In some embodiments, Fig. 6A and Figure 6B As shown, the reflective baffle is arranged on the side of the transparent electrode layer 29 close to the driving backplane.

[0155] In other embodiments, Fig. 7A and Figure 7B As shown, the reflective baffle 28 is arranged on the side of the transparent electrode layer 29 away from the driving backplane. In this way, the transparent electrode layer 29 does not need to cooperate with the structure of the reflective baffle 28, which can simplify the structure of the transparent electrode layer 29 and reduce the requirements on the structure shape of the reflective baffle 28.

[0156] Depending on the structure and position of the reflective baffle 28 , the structure of the transparent electrode layer 29 finally formed is also different. The embodiment of the present application does not limit the specific structure of the reflective baffle 28 and the transparent electrode layer 29 , and the two can be coupled.

[0157] In some embodiments, the transparent electrode layer 29 may be directly coupled to metal vias on the driving backplane.

[0158] In some other embodiments, the metal through hole is coupled to the reflective blocking wall 28 , and the transparent electrode layer 29 is coupled to the metal through hole through the reflective blocking wall 28 .

[0159] Fig. 8A and Figure 8B A schematic diagram of the structure of another chip provided in an embodiment of the present application.

[0160] In some embodiments, Fig. 8A and Figure 8B As shown, there is a gap between the first sub-reflective blocking wall 281 and the first primary color light emitting device in the first primary color sub-pixel P1, and when the first sub-reflective blocking wall 281 is adjacent to the second primary color light emitting device in the second primary color sub-pixel P2, there may also be a gap between the two.

[0161] There is a gap between the second sub-reflective blocking wall 282 and the second primary color light emitting device in the second primary color sub-pixel P2. When the second sub-reflective blocking wall 282 is adjacent to the third primary color light emitting device in the third primary color sub-pixel P3, there may also be a gap between the two.

[0162] There is a gap between the third sub-reflective blocking wall 283 and the third primary color light emitting device in the third primary color sub-pixel P3. When the third sub-reflective blocking wall 283 is adjacent to the first primary color light emitting device in the first primary color sub-pixel P1, there may also be a gap between the two.

[0163] The above gap can be an empty gap, or it can be filled with a conductive or insulating dielectric material. Fig. 8A and Figure 8B The figure is for illustration only.

[0164] like Fig. 8A As shown, when the reflective baffle is located on the side of the transparent electrode layer 29 close to the back plate of the driving board, the transparent electrode layer 29 is spread along the outline of the light-emitting device and covers the surface of the reflective baffle.

[0165] When the distance between adjacent light-emitting devices is relatively large, a gap is reserved between the reflective baffle and the light-emitting device. The gap serves as a tolerance area for process errors. On the one hand, it can reduce the requirements for process accuracy, and on the other hand, it can reduce the weight of the reflective baffle.

[0166] Fig. 9 A schematic diagram of the structure of another chip provided in an embodiment of the present application.

[0167] In some embodiments, Fig. 9 As shown, the third primary color light emitting device LED3 further includes a third stress release layer 23C, and the third stress release layer 23C is arranged on the surface of the third electron injection layer N3C of LED3 away from the driving backplane.

[0168] For example, the material of the third stress release layer 23C includes InGaN or a superlattice material composed of periodically overlapping InGaN / GaN.

[0169] By providing the third stress release layer 23C, since there is a large stress due to the lattice mismatch between the substrate and the subsequently formed active layer, this part of the stress can be released by providing the third stress release layer 23C, thereby improving the quality of epitaxial growth of the active layer, reducing the influence of active layer defects on luminous efficiency, improving the stability of the visible light wavelength changing with current, and making the luminous color more correct.

[0170] In some embodiments, the third primary color light emitting device LED3 further includes a third N-type semiconductor layer 22C, which is disposed on a side of the third stress release layer 23C away from the third electron injection layer N3C of LED3. For example, the thickness of the third N-type semiconductor layer 22C is greater than the thickness of the third electron injection layer N3C of LED3.

[0171] For example, N-type doping may be performed in a IIIV group semiconductor material (such as gallium oxide or other materials) to form a third N-type semiconductor layer 22C. The third N-type semiconductor layer 22C can transmit electrons.

[0172] For example, the thickness of the third N-type semiconductor layer 22C is between 1 um and 4 um. For example, the thickness of the third N-type semiconductor layer 22C is 1 um, 1.5 um, 2 um, 2.5 um, 3 um, 3.5 um or 4 um.

[0173] By providing a thicker third N-type semiconductor layer 22C, the epitaxial quality of the third electron injection layer N3C of the LED 3 can be improved, and the electron transmission effect can be improved.

[0174] In some embodiments, the third primary color light emitting device LED3 also includes a third electron blocking layer 24C, which is arranged between the third hole injection layer PC and the first active layer T1C of LED3, and is used to block electrons from moving toward the driving backplane side, thereby reducing the leakage current of the third primary color light emitting device LED3.

[0175] The second primary color light emitting device LED2 further includes a second electron blocking layer 24B, which is disposed between the second hole injection layer PB and the first active layer T1B of LED2. The second electron blocking layer 24B is used to block electrons from moving toward the driving backplane side, thereby reducing the leakage current of the second primary color light emitting device LED2 formed subsequently.

[0176] The first primary color light emitting device LED1 further includes a first electron blocking layer 24A, which is disposed between the first hole injection layer PA and the first active layer T1A of LED1. The first electron blocking layer 24A is used to block electrons from moving toward the driving backplane side, thereby reducing the leakage current of the first primary color light emitting device LED1 formed subsequently.

[0177] The third electron blocking layer 24C, the second electron blocking layer 24B and the first electron blocking layer 24A can be obtained by performing pixelation processing on the same electron blocking film layer in the wafer, and the three are made of the same layer and the same material.

[0178] In some embodiments, the third primary color light emitting device LED3 further includes a third ohmic contact layer 25C, which is disposed between the third bonding layer 26C and the third hole injection layer PC to improve the ohmic contact effect between the driving backplane and the third hole injection layer PC.

[0179] The second primary color light emitting device LED2 further comprises a second ohmic contact layer 25B, which is disposed between the second bonding layer 26B and the second hole injection layer PB. The second ohmic contact layer 25B is used to improve the ohmic contact effect between the driving backplane and the second hole injection layer PB.

[0180] The first primary color light emitting device LED1 further includes a first ohmic contact layer 25A, which is disposed between the first bonding layer 26A and the first hole injection layer PA. The first ohmic contact layer 25A is used to improve the ohmic contact effect between the driving backplane and the first hole injection layer PA.

[0181] The third ohmic contact layer 25C, the second ohmic contact layer 25B and the first ohmic contact layer 25A can be obtained by performing pixelation processing on the same ohmic contact film layer in the wafer, and the three are made of the same layer and the same material.

[0182] For example, the materials of the third ohmic contact layer 25C, the second ohmic contact layer 25B and the first ohmic contact layer 25A may include transparent conductive materials such as indium tin oxide (ITO), zinc oxide (IZO), aluminum-doped zinc oxide (ZnO:Al, AZO), and fluorine-doped tin oxide (SnO2:F, FTO). The thickness of the third ohmic contact layer 25C, the second ohmic contact layer 25B and the first ohmic contact layer 25A may be between 5nm and 500nm. For example, the thickness of the third ohmic contact layer 25C, the second ohmic contact layer 25B and the first ohmic contact layer 25A may be 5nm, 20nm, 50nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, or 500nm.

[0183] By providing the third ohmic contact layer 25C, the second ohmic contact layer 25B and the first ohmic contact layer 25A, after the wafer and the driving backplane are bonded, the electrical connection effect between the hole injection layer and the driving backplane can be improved and the signal loss can be reduced.

[0184] Fig.10 A schematic diagram of the structure of another chip provided in an embodiment of the present application.

[0185] In some embodiments, Fig.10As shown, the first active layer T1A of LED1 further includes a fourth sub-active layer A4, which is disposed between the first hole injection layer PA and the first sub-active layer A1. The fourth sub-active layer A4 includes a fourth barrier layer L12A, a fourth quantum well protection layer PQ1A, and a fourth multi-quantum well layer MQW12A, which are sequentially disposed on the side of the first hole injection layer PA facing the first sub-active layer A1. The fourth sub-active layer A4 and the first sub-active layer A1 are used to emit light of the same color.

[0186] The first active layer T1B of LED2 further includes a fourth sub-active layer B4, which is disposed between the second hole injection layer PB and the first sub-active layer B1. The fourth sub-active layer B4 includes a fourth barrier layer L12B, a fourth quantum well protection layer PQ1B, and a fourth multi-quantum well layer MQW12B, which are sequentially disposed on the second hole injection layer PB toward the first sub-active layer B1.

[0187] The first active layer T1C of LED3 further includes a fourth sub-active layer C4, which is disposed between the third hole injection layer PC and the first sub-active layer C1. The fourth sub-active layer C4 includes a fourth barrier layer L12C, a fourth quantum well protection layer PQ1C, and a fourth multi-quantum well layer MQW12C, which are sequentially disposed on the side of the third hole injection layer PC facing the first sub-active layer C1.

[0188] The fourth barrier layer L12A, the fourth barrier layer L12B and the fourth barrier layer L12C are obtained by pixelating the fourth barrier film layer L12 in the wafer, and the three are of the same layer and the same material.

[0189] The fourth quantum well protection layer PQ1A, the fourth quantum well protection layer PQ1B and the fourth quantum well protection layer PQ1C are obtained by pixelating the fourth quantum well protection film layer PQ1 in the wafer, and the three are of the same layer and the same material.

[0190] The fourth multi-quantum well layer MQW12A, the fourth multi-quantum well layer MQW12B and the fourth multi-quantum well layer MQW12C are obtained by pixelating the fourth multi-quantum well film layer MQW12 in the wafer, and the three are of the same layer and material.

[0191] The fourth sub-active layer is arranged on the side of the first sub-active layer facing the first hole injection layer. The fourth sub-active layer includes a fourth quantum well protection layer, which can prevent electrons from moving toward the driving backplane and reduce the leakage current of the chip.

[0192] In some embodiments, Fig.10As shown, the second active layer T2B of LED2 further includes a fifth sub-active layer B5, which is disposed between the second sub-active layer B2 and the second electron injection layer N2B of LED2. The fifth sub-active layer B5 includes a fifth barrier layer L22B and a fifth multi-quantum well layer MQW22B sequentially disposed on the second sub-active layer B2 facing the second electron injection layer N2B of LED2.

[0193] The fifth sub-active layer B5 and the second sub-active layer B2 are used to emit light of the same color.

[0194] The second active layer T2C of LED3 further includes a fifth sub-active layer C5, which is disposed between the second sub-active layer C2 and the second electron injection layer N2C of LED3. The fifth sub-active layer C5 includes a fifth barrier layer L22C and a fifth multi-quantum well layer MQW22C sequentially disposed on the second sub-active layer C2 on the side facing the second electron injection layer N2C of LED3.

[0195] The fifth barrier layer L22B and the fifth barrier layer L22C are obtained by pixelating the fifth barrier film layer L22 in the wafer, and the three are made of the same layer and material.

[0196] The fifth multi-quantum well layer MQW22B and the fifth multi-quantum well layer MQW22C are obtained by pixelating the fifth multi-quantum well film layer MQW22 in the wafer, and the three are of the same layer and material.

[0197] By providing the fifth sub-active layer, the number of light-emitting units in the second active layer is increased, and the light-emitting brightness of the second active layer can be improved. In addition, the fifth sub-active layer does not include a quantum well protection layer, which will not affect the normal light emission of the second sub-active layer.

[0198] In some embodiments, Fig.10 As shown, the third active layer T3C of LED3 further includes a sixth sub-active layer C6, which is disposed between the third sub-active layer C3 and the third electron injection layer N3C of LED3. The sixth sub-active layer C6 includes a sixth barrier layer L32C and a sixth multi-quantum well layer MQW32C which are sequentially disposed on the side of the third sub-active layer C3 facing the third electron injection layer N3C of LED3.

[0199] The sixth sub-active layer C6 and the third sub-active layer C3 are used to emit light of the same color.

[0200] The sixth sub-active layer C6 is provided in the third active layer T3C of LED3, which increases the number of light-emitting units in the third active layer T3C and can improve the light-emitting brightness of the third active layer T3C. The sixth sub-active layer C6 does not include a quantum well protection layer, which will not affect the normal light emission of the third sub-active layer C3.

[0201] Fig.10 The structures of the first active layer T1A of LED1, the first active layer T1B of LED2, the first active layer T1C of LED3, the second active layer T2A of LED1, the second active layer T2B of LED2, the second active layer T2C of LED3, the third active layer T3A of LED1, the third active layer T3B of LED2, and the third active layer T3C of LED3 shown in the figure can be applied to any of the above chip structures. The first active layer T1A of LED1 can include one or more fourth sub-active layers A4, the second active layer T2B of LED2 can include one or more fifth sub-active layers B5, and the third active layer T3C of LED3 can include one or more sixth sub-active layers C6.

[0202] Fig.11A and Fig. 11B A flowchart of a chip preparation method provided in an embodiment of the present application, Fig. 12A and Fig. 12B A schematic diagram of the structure of a wafer provided in an embodiment of the present application, Fig. 12C A schematic structural diagram of a third primary color active film layer provided in an embodiment of the present application.

[0203] The present application provides a method for preparing a chip. For example, any of the above chips can be prepared by the method. Fig.11A As shown, the preparation method comprises:

[0204] S1. Provide wafer stacking.

[0205] The wafer stack provided in the embodiment of the present application can be prepared, for example, by step S1. The wafer stack provided in the embodiment of the present application is schematically described below in conjunction with the method for preparing the wafer stack.

[0206] For example, step S1 includes:

[0207] S11, such as Fig. 12A As shown, a wafer is formed.

[0208] The wafer can be understood as an epitaxial stacked wafer, for example. The wafer provided in the embodiment of the present application can be prepared by step S11, for example. The wafer provided in the embodiment of the present application is schematically described below in conjunction with the wafer preparation method.

[0209] For example, step S11 includes:

[0210] S111 . Provide a substrate 20 .

[0211] For example, the substrate 20 may be a silicon substrate, a sapphire substrate, a GaN substrate, or a quartz glass substrate, etc. Here, the substrate 20 is mainly used as an epitaxial carrier.

[0212] S112 , forming a buffer film layer 21 on one side of the substrate 20 .

[0213] The buffer film layer 21 may be made of different materials according to the different materials selected for the substrate 20 and the target thickness and crystal quality requirements of the buffer film layer 21. For example, the material of the buffer film layer 21 includes aluminum nitride (AlN), aluminum gallium nitride (AlGaN), GaN, gallium indium nitride (InGaN), etc. The buffer film layer 21 may be a single-layer structure or a multi-layer structure.

[0214] S113 , forming an N-type semiconductor film layer 22 on a side of the buffer film layer 21 away from the substrate 20 .

[0215] S114 , forming a stress release film layer 23 on a side of the N-type semiconductor film layer 22 away from the substrate 20 .

[0216] Since the lattice mismatch between the substrate 20 and the subsequently formed active film layer will cause great stress, this part of the stress can be released by providing the stress release film layer 23. The quality of epitaxial growth of the active film layer is improved, the influence of active film layer defects on the luminous efficiency is reduced, and the stability of the visible light wavelength changing with the current is improved, so that the luminous color is more correct.

[0217] S115 , forming a third electron injection film layer N3 on a side of the stress release film layer 23 away from the substrate 20 .

[0218] S116 , forming a third primary color active film layer T3 on a side of the third electron injection film layer N3 away from the substrate 20 .

[0219] In some embodiments, Fig. 12A As shown, the third primary color active film layer T3 includes a third sub-active film layer T31 for emitting a third primary color light, and the third sub-active film layer T31 includes a third multi-quantum well film layer MQW31, a third quantum well protection film layer PQ3 and a third barrier film layer L31 which are sequentially arranged on the side of the third electron injection film layer N3 away from the substrate 20.

[0220] The third primary color active film layer T3 may include one third sub-active film layer T31 , or may include a plurality of third sub-active film layers T31 .

[0221] In other embodiments, Fig. 12B As shown, the third primary color active film layer T3 further includes a sixth sub-active film layer T32 , and both the third sub-active film layer T31 and the sixth sub-active film layer T32 are used to emit light of the third primary color.

[0222] The sixth sub-active film layer T32 is arranged between the third sub-active film layer T31 and the third electron injection film layer N3, and the sixth sub-active film layer T32 includes a sixth barrier film layer L32 and a sixth multi-quantum well film layer MQW32 which are sequentially arranged on the side of the third sub-active film layer T31 toward the third electron injection film layer N3.

[0223] like Fig. 12B As shown, the third primary color active film layer T3 may include the sixth sub-active film layer T32, as shown in FIG. Fig. 12C As shown, the third primary color active film layer T3 may include a plurality of stacked sixth sub-active film layers T32. On the basis of the third sub-active film layer T31, by further providing one or more sixth sub-active film layers T32 in the third primary color active film layer T3, the luminous brightness of the third primary color in the wafer can be improved.

[0224] S117 , forming a second electron injection film layer N2 on the side of the third primary color active film layer T3 away from the substrate 20 .

[0225] The structure of the second electron injection film layer N2 may refer to the related description of the third electron injection film layer N3, which will not be repeated here.

[0226] S118 , forming a second primary color active film layer T2 on a side of the second electron injection film layer N2 away from the substrate 20 .

[0227] In some embodiments, Fig. 12A As shown, the second primary color active film layer T2 includes a second sub-active film layer T21 for emitting second primary color light, and the second sub-active film layer T21 includes a second multi-quantum well film layer MQW21, a second quantum well protection film layer PQ2 and a second barrier film layer L21 which are sequentially arranged on the side of the second electron injection film layer N2 away from the substrate 20.

[0228] In other embodiments, Fig. 12B As shown, the second primary color active film layer T2 also includes a fifth sub-active film layer T22 for emitting second primary color light. The fifth sub-active film layer T22 is arranged between the second sub-active film layer T21 and the second electron injection film layer N2. The fifth sub-active film layer T22 includes a fifth barrier film layer L22 and a fifth multi-quantum well film layer MQW22 which are sequentially arranged on the side of the second sub-active film layer T21 toward the second electron injection film layer N2.

[0229] S119 , forming a first electron injection film layer N1 on the side of the second primary color active film layer T2 away from the substrate 20 .

[0230] S1110 , forming a first primary color active film layer T1 on a side of the first electron injection film layer N1 away from the substrate 20 .

[0231] In some embodiments, Fig. 12A As shown, the first primary color active film layer T1 includes a first sub-active film layer T11 for emitting first primary color light. The first sub-active film layer T11 includes a first multi-quantum well film layer MQW11 and a first barrier film layer L11 which are sequentially arranged on the side of the first electron injection film layer N1 away from the substrate 20.

[0232] In other embodiments, Fig. 12B As shown, the first primary color active film layer T1 also includes a fourth sub-active film layer T12 for emitting the first primary color light, and the fourth sub-active film layer T12 is arranged between the hole injection film layer P and the first sub-active film layer T11 (the first sub-active film layer T11 is away from the substrate 20 side), and the fourth sub-active film layer T12 includes a fourth multi-quantum well film layer MQW12, a fourth quantum well protection film layer PQ1 and a fourth barrier film layer L12 (the fourth barrier film layer L12, the fourth quantum well protection film layer PQ1 and the fourth multi-quantum well film layer MQW12 on the side of the hole injection film layer P facing the first sub-active film layer T11) which are sequentially arranged on the side of the first sub-active film layer T11 away from the substrate 20.

[0233] S1111 , forming an electron blocking film layer 24 on a side of the first primary color active film layer T1 away from the substrate 20 .

[0234] For example, the electron blocking film layer 24 is disposed between the hole injection film layer P and the first primary color active film layer T11 (the fourth sub-active film layer T12 ).

[0235] S1112 , forming a hole injection film layer P on the side of the electron blocking film layer 24 away from the substrate 20 .

[0236] S1113 , forming an ohmic contact film layer 25 on the side of the hole injection film layer P away from the substrate 20 (the first primary color active film layer T1 ).

[0237] S1114 , forming a first bonding film layer 26 on the side of the ohmic contact film layer 25 away from the substrate 20 (hole injection film layer P).

[0238] For example, the first bonding film layer 26 can be used to bond with the driving backplane, and the hole injection film layer P can be connected with the electrodes on the driving backplane through the first bonding film layer 26 and the ohmic contact film layer 25 .

[0239] By the above-mentioned method for forming a wafer provided in the embodiment of the present application (step S11), the wafer provided in the embodiment of the application can be formed. When executing step S11, only one of the above-mentioned step S113 and step S115 can be executed, or both of step S113 and step S115 can be executed. Or it can be understood that the wafer may include one or both of the N-type semiconductor film layer 22 and the third electron injection film layer N3. The above-mentioned step S114 can be executed or not. Or it can be understood that the wafer may include a stress release film layer 23, or the wafer may not include a stress release film layer 23. The above-mentioned step S1111 can be executed or not. Or it can be understood that the wafer may include an electron blocking film layer 24, or the wafer may not include an electron blocking film layer 24. The above-mentioned step S1113 can be executed or not. Or it can be understood that the wafer may include an ohmic contact film layer 25, or the wafer may not include an ohmic contact film layer 25. The above-mentioned step S1114 can be executed or not. Alternatively, it can be understood that the wafer may include the first bonding film layer 26 , or the wafer may not include the first bonding film layer 26 .

[0240] S12, forming a driving backplane.

[0241] For example, step S12 includes:

[0242] S121, forming a driving electrode substrate including a pixel circuit and a pixel electrode.

[0243] S122, forming a second bonding film layer on the driving electrode substrate.

[0244] For example, the second bonding film layer is formed on the surface of the driving electrode substrate by magnetron sputtering, electron beam evaporation or thermal evaporation. The material of the second bonding film layer can be the same as the material of the first bonding film layer 26 in the above wafer.

[0245] Fig.13 A schematic diagram of the structure of a wafer stack provided in an embodiment of the present application.

[0246] S13, such as Fig.13 As shown, the wafer is bonded to the driving backplane to form a wafer stack.

[0247] For example, the first bonding film layer 26 and the second bonding film layer are bonded to achieve bonding between the wafer and the drive backplane to form a wafer stack provided in an embodiment of the present application. For example, a bonding machine and an annealing furnace and other equipment can be used to bond the wafer and the drive backplane. At this time, the substrate 20 is located on the surface of the wafer (wafer stack).

[0248] In other embodiments, after bonding the wafer to the driving backplane, the substrate 20 is further removed. Then the wafer stack provided in the embodiment of the present application does not include the substrate 20, and the buffer film layer 21 is located on the surface of the wafer (wafer stack).

[0249] In some other embodiments, after bonding the wafer to the driving backplane, the substrate 20 and the buffer film layer 21 are removed. Then the wafer stack provided in the embodiment of the present application does not include the substrate 20 and the buffer film layer 21, and the N-type semiconductor film layer 22 is located on the surface of the wafer (wafer stack).

[0250] Figure 14A-14E A schematic diagram of the product structure of a chip preparation process provided in an embodiment of the present application.

[0251] S2, such as Fig.14A As shown, the wafers in the wafer stack are pixelated to form a first primary color light emitting device LED1, a second primary color light emitting device LED2 and a third primary color light emitting device LED3 which are spaced apart on the driving substrate.

[0252] That is to say, the first primary color light emitting device LED1, the second primary color light emitting device LED2 and the third primary color light emitting device LED3 in the embodiment of the present application are obtained by processing one wafer.

[0253] The driving backplane includes a pixel circuit and a pixel electrode. The surface of the driving backplane facing the wafer has a metal through-hole. The first primary color light-emitting device LED1, the second primary color light-emitting device LED2 and the third primary color light-emitting device LED3 are coupled to the corresponding pixel electrodes through the metal through-holes to realize the switching drive of the sub-pixels.

[0254] In the first implementation, Fig. 11B As shown, step S2 includes:

[0255] S21. Combination Fig. 14C As shown, the wafer is cut to form a first primary color device stack LED1', a second primary color device stack LED2' and a third primary color light emitting device LED3 which are arranged at intervals.

[0256] For example, the wafer may be cut by dry etching or the like to achieve isolation between sub-pixels (light-emitting devices).

[0257] In some embodiments, Fig.14A As shown, the wafer stack is Figure 5 In the case of wafer stacking shown, before executing step S21, step S20 is further included: removing the substrate 20 and the buffer film layer 21 to expose the N-type semiconductor film layer 22. Then, the light-emitting device finally formed includes an N-type semiconductor layer.

[0258] For example, the substrate 20 and the buffer film layer 21 are removed by mechanical grinding, chemical mechanical polishing (CMP), wet / dry etching, etc.

[0259] Optionally, when removing the substrate 20 and the buffer film layer 21, a certain thickness of the N-type semiconductor film layer 22 may be removed. In this way, it is not necessary to remove the buffer film layer 21 exactly, thereby reducing the requirement on process accuracy.

[0260] In other embodiments, Fig. 14B As shown, the wafer stack is Figure 5 In the case of wafer stacking shown in the figure, before executing step S21, step S20' is also included: removing the substrate 20, the buffer film layer 21, the N-type semiconductor film layer 22 and the stress release film layer 23 to expose the third electron injection film layer N3. Then, the light-emitting device finally formed does not include the N-type semiconductor layer.

[0261] In some other embodiments, the wafer stack itself does not include the substrate 20 and the buffer film layer 21, and step S21 can be directly performed, or step S20″ can be performed: the N-type semiconductor film layer 22 and the stress release film layer 23 are removed to expose the third electron injection film layer N3. In this way, the number of film layers in the wafer stack can be reduced, and the thickness of the chip finally formed can be reduced.

[0262] The following preparation process is schematically described by taking the wafer stack including the N-type semiconductor film layer 22 as an example before executing step S21 .

[0263] like Fig. 14C As shown, the third primary color light emitting device LED3 includes a third hole injection layer PC, a first active layer T1C of LED3, a first electron injection layer N1C of LED3, a second active layer T2C of LED3, a second electron injection layer N2C of LED3, a third active layer T3C of LED3 and a third electron injection layer N3C of LED3, which are sequentially arranged on one side of the driving backplane.

[0264] The second primary color device stack LED2' includes a second hole injection layer PB, a first active layer T1B of LED2, a first electron injection layer N1B of LED2, a second active layer T2B of LED2, a second electron injection layer N2B of LED2, a third active layer T3B of LED2 and a third electron injection layer N3B of LED2.

[0265] In the second primary color device stack LED2', the third active layer T3B of LED2 includes a third sub-active layer B3, and the third sub-active layer B3 includes a third barrier layer L31B, a third quantum well protection layer PQ3B and a third multi-quantum well layer MQW31B which are sequentially arranged on the side of the second electron injection layer N2B of LED2 away from the driving backplane.

[0266] In the second primary color device stack LED2', the second active layer T2B of LED2 includes a second sub-active layer B2, and the second sub-active layer B2 includes a second barrier layer L21B, a second quantum well protection layer PQ2B and a second multi-quantum well layer MQW21B which are sequentially arranged on the side of the first electron injection layer N1B of LED2 away from the driving backplane.

[0267] In the second primary color device stack LED2', the first active layer T1B of LED2 includes a first sub-active layer B1, which includes a first barrier layer L11B and a first multi-quantum well layer MQW11B sequentially arranged on the side of the second hole injection layer PB away from the driving backplane.

[0268] The first primary color device stack LED1' includes a first hole injection layer PA, a first active layer T1A of LED1, a first electron injection layer N1A of LED1, a second active layer T2A of LED1, a second electron injection layer N2A of LED1, a third active layer T3A of LED1 and a third electron injection layer N3A of LED1.

[0269] In the first primary color device stack LED1', the third active layer T3A of LED1 includes a third sub-active layer A3, which includes a third barrier layer L31A, a third quantum well protection layer PQ3A and a third multi-quantum well layer MQW31A, which are sequentially arranged on the side of the second electron injection layer N2A of LED1 away from the driving backplane.

[0270] In the first primary color device stack LED1', the second active layer T2A of LED1 includes a second sub-active layer A2, and the second sub-active layer A2 includes a second barrier layer L21A, a second quantum well protection layer PQ2A and a second multi-quantum well layer MQW21A which are sequentially arranged on the side of the first electron injection layer N1A of LED1 away from the driving backplane.

[0271] In the first primary color device stack LED1', the first active layer T1A of LED1 includes a first sub-active layer A1, which includes a first barrier layer L11A and a first multi-quantum well layer MQW11A sequentially arranged on the side of the second hole injection layer PA away from the driving backplane.

[0272] The third hole injection layer PC, the second hole injection layer PB, and the first hole injection layer PA are obtained by pixelating the hole injection film layer P in the wafer, and the three are of the same layer and material.

[0273] The first active layer T1C of LED3, the first active layer T1B of LED2, and the first active layer T1A of LED1 are obtained by pixelating the first primary color active film layer T1 in the wafer, and the three are made of the same layer and material.

[0274] For example, the first primary color active film layer T1 includes a first sub-active film layer T11, the first active layer T1C of LED3 includes a first sub-active layer C1, the first active layer T1B of LED2 includes a first sub-active layer B1, and the first active layer T1A of LED1 includes a first sub-active layer A1.

[0275] For example, the first sub-active film layer T11 includes a first barrier film layer L11 and a first multi-quantum well film layer MQW11 sequentially arranged on the side of the hole injection film layer P toward the first electron injection film layer N1. The first sub-active layer C1 formed includes a first barrier layer L11C and a first multi-quantum well layer MQW11C sequentially arranged on the side of the third hole injection layer PC away from the driving backplane. The first sub-active layer B1 formed includes a first barrier layer L11B and a first multi-quantum well layer MQW11B sequentially arranged on the side of the second hole injection layer PB away from the driving backplane. The first sub-active layer A1 formed includes a first barrier layer L11A and a first multi-quantum well layer MQW11A sequentially arranged on the side of the first hole injection layer PA away from the driving backplane.

[0276] The first electron injection layer N1C of LED3, the first electron injection layer N1B of LED2, and the first electron injection layer N1A of LED1 are obtained by pixelating the first electron injection film layer N1 in the wafer, and the three are of the same layer and material.

[0277] The second active layer T2C of LED3, the second active layer T2B of LED2, and the second active layer T2A of LED1 are obtained by pixelating the second primary color active film layer T2 in the wafer, and the three are made of the same layer and material.

[0278] For example, the second primary color active film layer T2 includes a second sub-active film layer T21, the second active layer T2C of LED3 includes a second sub-active layer C2, the second active layer T2B of LED2 includes a second sub-active layer B2, and the second active layer T2A of LED1 includes a second sub-active layer A2.

[0279] For example, the second sub-active film layer T21 includes a second barrier film layer L21, a second quantum well protection film layer PQ2, and a second multi-quantum well film layer MQW21, which are sequentially arranged on the side of the first electron injection film layer N1 toward the second electron injection film layer N2. The second sub-active layer C2 formed includes a second barrier layer L21C, a second quantum well protection layer PQ2C, and a second multi-quantum well layer MQW21C, which are sequentially arranged on the side of the first electron injection layer N1C of LED3 toward the second electron injection layer N2C of LED3. The second sub-active layer B2 formed includes a second barrier layer L21B, a second quantum well protection layer PQ2B, and a second multi-quantum well layer MQW21B, which are sequentially arranged on the side of the first electron injection layer N1B of LED2 toward the second electron injection layer N2B of LED2. The second sub-active layer A2 formed includes a second barrier layer L21A, a second quantum well protection layer PQ2A, and a second multi-quantum well layer MQW21A, which are sequentially arranged on the side of the first electron injection layer N1A of LED1 toward the second electron injection layer N2A of LED1.

[0280] The second electron injection layer N2C of LED3, the second electron injection layer N2B of LED2, and the second electron injection layer N2A of LED1 are obtained by pixelating the second electron injection film layer N2 in the wafer, and the three are of the same layer and material.

[0281] The third active layer T3C of LED3, the third active layer T3B of LED2, and the third active layer T3A of LED1 are obtained by pixelating the third primary color active film layer T3 in the wafer, and the three are made of the same layer and material.

[0282] For example, the third primary color active film layer T3 includes a third sub-active film layer T31, the third active layer T3C of LED3 includes a third sub-active layer C3, the third active layer T3B of LED2 includes a third sub-active layer B3, and the third active layer T3A of LED1 includes a third sub-active layer A3.

[0283] For example, the third sub-active film layer T31 includes a third barrier film layer L31, a third quantum well protection film layer PQ3, and a third multi-quantum well film layer MQW31, which are sequentially arranged on the side of the second electron injection film layer N2 toward the third electron injection film layer N3. The formed third sub-active layer C3 includes a third barrier layer L31C, a third quantum well protection layer PQ3C, and a third multi-quantum well layer MQW31C, which are sequentially arranged on the side of the second electron injection layer N2C of LED3 toward the third electron injection layer N3C of LED3. The formed third sub-active layer B3 includes a third barrier layer L31B, a third quantum well protection layer PQ3B, and a third multi-quantum well layer MQW31B, which are sequentially arranged on the side of the second electron injection layer N2B of LED2 toward the third electron injection layer N3B of LED2. The formed third sub-active layer A3 includes a third barrier layer L31A, a third quantum well protection layer PQ3A and a third multi-quantum well layer MQW31A which are sequentially arranged on the side of the second electron injection layer N2A of LED1 toward the third electron injection layer N3A of LED1.

[0284] The third electron injection layer N3C of LED3, the third electron injection layer N3B of LED2, and the third electron injection layer N3A of LED1 are obtained by pixelating the third electron injection film layer N3 in the wafer, and the three are made of the same layer and material.

[0285] In some embodiments, Fig. 14C As shown, the third primary color light emitting device LED3 further includes a third electron blocking layer 24C, the second primary color device stack LED2' further includes a second electron blocking layer 24B, and the first primary color device stack LED1' further includes a first electron blocking layer 24A.

[0286] The third electron blocking layer 24C, the second electron blocking layer 24B and the first electron blocking layer 24A can be obtained by pixelating the electron blocking film layer 24 in the wafer, and the three are made of the same layer and the same material.

[0287] In some embodiments, Fig. 14C As shown, the third primary color light emitting device LED3 further includes a third bonding layer 26C, and the third bonding layer 26C is bonded to the driving backplane. The second primary color device stack LED2' further includes a second bonding layer 26B, and the second bonding layer 26B is bonded to the driving backplane. The first primary color device stack LED1' further includes a first bonding layer 26A, and the first bonding layer 26A is bonded to the driving backplane.

[0288] The third bonding layer 26C, the second bonding layer 26B and the first bonding layer 26A can be obtained by performing pixelation processing on the first bonding film layer 26 in the wafer, and the three are of the same layer and the same material.

[0289] In some embodiments, Fig. 14CAs shown, the third primary color light emitting device LED3 further includes a third ohmic contact layer 25C, the second primary color device stack LED2' further includes a second ohmic contact layer 25B, and the first primary color device stack LED1' further includes a first ohmic contact layer 25A.

[0290] The third ohmic contact layer 25C, the second ohmic contact layer 25B and the first ohmic contact layer 25A can be obtained by pixelating the ohmic contact film layer 25 in the wafer, and the three are made of the same layer and the same material.

[0291] In some embodiments, Fig. 14C As shown, the third primary color light emitting device LED3 further includes a third stress release layer 23C, and the third stress release layer 23C is arranged on the surface of the third electron injection layer N3C of LED3 away from the driving backplane.

[0292] The second primary color device stack LED2 ′ further includes a second stress release layer 23B. The second stress release layer 23B is disposed on a surface of the third electron injection layer N3B of the LED2 away from the driving backplane.

[0293] The first primary color device stack LED1 ′ further includes a first stress release layer 23A. The first stress release layer 23A is disposed on a surface of the third electron injection layer N3A of the LED1 away from the driving backplane.

[0294] The third stress release layer 23C, the second stress release layer 23B and the first stress release layer 23A can be obtained by pixelating the stress release film layer 23 in the wafer, and the three are made of the same layer and material.

[0295] In some embodiments, the third primary color light emitting device LED3 further includes a third N-type semiconductor layer 22C, and the third N-type semiconductor layer 22C is disposed on a side of the third stress release layer 23C away from the third electron injection layer N3C of LED3.

[0296] The second primary color device stack LED2' further includes a second N-type semiconductor layer 22B, which is disposed on the side of the second stress release layer 23B away from the third electron injection layer N3B of LED2. For example, the thickness of the second N-type semiconductor layer 22B is greater than the thickness of the third electron injection layer N3B of LED2.

[0297] The first primary color device stack LED1' further includes a first N-type semiconductor layer 22A, which is disposed on the side of the first stress release layer 23A away from the third electron injection layer N3A of LED1. For example, the thickness of the first N-type semiconductor layer 22A is greater than the thickness of the third electron injection layer N3A of LED1.

[0298] The third N-type semiconductor layer 22C, the second N-type semiconductor layer 22B and the first N-type semiconductor layer 22A can be obtained by pixelating the N-type semiconductor film layer 22 in the wafer, and the three are made of the same layer and the same material.

[0299] In some embodiments, the third primary color light emitting device does not include the third N-type semiconductor layer 22C and the third stress release layer 23C, and the transparent electrode layer 29 is directly coupled to the third electron injection layer N3C of LED3.

[0300] In other embodiments, the third primary color light emitting device may not include the third electron injection layer N3C of LED3, but only include the third N-type semiconductor layer 22C, and the transparent electrode layer 29 is coupled to the third N-type semiconductor layer 22C. In this case, the third N-type semiconductor layer 22C serves as the third electron injection layer of LED3 in the third primary color light emitting device, and the electrons provided by the transparent electrode layer 29 directly enter the third multi-quantum well layer MQW31C from the third N-type semiconductor layer 22C, which can reduce the number of film layers of the chip.

[0301] In the case where the third primary color light emitting device only includes the third N-type semiconductor layer 22C, the third N-type semiconductor layer 22C can also be understood as the third electron injection layer N3C of LED3 in the third primary color light emitting device.

[0302] The pixelation process of multiple film layers in the above-mentioned wafer may be performed once or multiple times, which is not limited in the embodiment of the present application.

[0303] S22, Combination Fig.14D As shown, the third active layer T3B of LED2, the third electron injection layer N3B of LED2, the third active layer T3A of LED1 and the third electron injection layer N3A of LED1 in the second primary color device stack LED2' are removed to form a second primary color light emitting device LED2 and a first primary color device stack LED1'.

[0304] In the case where the second primary color device stack LED2' further includes a second N-type semiconductor layer 22B and a second stress release layer 23B, step S22 further includes removing the second N-type semiconductor layer 22B and the second stress release layer 23B. Alternatively, it can be understood that the purpose of step S22 is to remove the film layer located above the second electron injection layer N2B of LED2 to expose the second electron injection layer N2B of LED2.

[0305] In the case where the first primary color device process stack LED1" also includes a first N-type semiconductor layer 22A and a first stress release layer 23A, step S22 also includes removing the first N-type semiconductor layer 22A and the first stress release layer 23A. Alternatively, it can be understood that the purpose of step S22 is to remove the film layer above the second electron injection layer N2A of LED1 to expose the second electron injection layer N2A of LED1.

[0306] The second primary color light emitting device LED2 includes a second hole injection layer PB, a first active layer T1B of LED2, a first electron injection layer N1B of LED2, a second active layer T2B of LED2, and a second electron injection layer N2B of LED2, which are sequentially arranged on one side of the driving backplane. The second primary color light emitting device LED2 may also include a second bonding layer 26B, a second ohmic contact layer 25B, a second electron blocking layer 24B, etc.

[0307] The first primary color device stack LED1″ includes a first hole injection layer PA, a first active layer T1A of LED1, a first electron injection layer N1A of LED1, a second active layer T2A of LED1 and a second electron injection layer N2A of LED1.

[0308] The process of removing the third active layer T3A of LED1 and the third electron injection layer N3A of LED1 may be performed in step S22 or in the subsequent step S23 . The embodiment of the present application is only for illustration.

[0309] S23, such as Fig.14E As shown, the second active layer T2A of LED1 and the second electron injection layer N2A of LED1 in the first primary color device process stack LED1″ are removed to form the first primary color light emitting device LED1.

[0310] The first primary color light emitting device LED1 includes a first hole injection layer PA, a first active layer T1A of LED1 and a first electron injection layer N1A of LED1 which are sequentially arranged on one side of the driving backplane. The first primary color light emitting device LED1 may also include a first bonding layer 26A, a first ohmic contact layer 25A, a first electron blocking layer 24A, etc.

[0311] Fig.15 and Fig.16 A schematic diagram of the product structure of a chip preparation process provided in an embodiment of the present application.

[0312] S3, such as Fig.15 As shown, a dielectric layer 27 is formed.

[0313] For example, step S3 includes:

[0314] S31. Forming a dielectric film layer.

[0315] S32 , forming a first opening, a second opening and a third opening on the dielectric film layer to form a dielectric layer 27 .

[0316] S4, such as Fig.16 As shown, a reflective baffle is formed. The reflective baffle includes a first sub-reflective baffle 281, a second sub-reflective baffle 282 and a third sub-reflective baffle 283. The cross-sectional shape of the reflective baffle can be various shapes.

[0317] Fig.17A and Fig. 17B A schematic diagram of the structure of another chip provided in an embodiment of the present application.

[0318] S5, such as Fig.17A and Fig. 17B As shown, a transparent electrode layer 29 is formed to obtain the first primary color sub-pixel P1, the second primary color sub-pixel P2, and the third primary color sub-pixel P3 that are independently driven.

[0319] For example, the transparent electrode layer 29 is coupled to the first electron injection layer N1A of LED1 through the first opening, coupled to the second electron injection layer N2B of LED2 through the second opening, and coupled to the third N-type semiconductor layer 22C through the third opening.

[0320] In some other embodiments, step S5 is performed first and then step S4 , and the reflective blocking wall 28 is located on a side of the transparent electrode layer 29 away from the dielectric layer 27 .

[0321] In some embodiments, the chip preparation method further comprises:

[0322] S6. Form a light collimator on the top of the chip.

[0323] For example, the light collimator includes a micro-lens structure such as a hemispherical convex lens structure. The material of the lens includes but is not limited to silicon carbonitride (SiCN), silicon nitride (SiN), aluminum oxide (Al2O3), titanium oxide (TiO2), niobium pentoxide (Nb2O5), tantalum pentoxide (Ta2O5), aluminum nitride (AlN), yttrium trioxide (Y2O3), hafnium dioxide (HfO2), silicon oxide (SiO2), polyester fiber (polyster resin, PR), polyolefin acid, etc.

[0324] A light collimator is formed on the top of the chip, which optimizes the multi-angle light it receives into light that is emitted perpendicular to the driving backplane, so that the side light that was originally unusable can be used, further improving the light output efficiency (photoelectric conversion efficiency) of the chip.

[0325] The above steps do not limit the steps of the chip preparation method provided in the embodiment of the present application. The preparation method can add steps, reduce steps, or adjust the order of steps based on the above steps. The above is only an illustration.

[0326] Fig.18 A schematic diagram of a product structure of an intermediate state of preparation of a chip provided in an embodiment of the present application.

[0327] In some embodiments, Fig. 12B As shown, the first primary color active film layer T1 also includes a fourth sub-active film layer T12 for emitting the first primary color light, the second primary color active film layer T2 also includes a fifth sub-active film layer T22 for emitting the second primary color light, and the third primary color active film layer T3 also includes a sixth sub-active film layer T32 for emitting the third primary color light.

[0328] For example, Fig.18 As shown, the first active layer T1A of LED1 in the first primary color device stack LED1' further includes a fourth sub-active layer A4, the first active layer T1B of LED2 in the second primary color device stack LED2' further includes a fourth sub-active layer B4, and the first active layer T1C of LED3 further includes a fourth sub-active layer C4.

[0329] The fourth barrier layer L12A, the fourth barrier layer L12B and the fourth barrier layer L12C are obtained by pixelating the fourth barrier film layer L12 in the wafer, and the three are of the same layer and the same material.

[0330] The fourth quantum well protection layer PQ1A, the fourth quantum well protection layer PQ1B and the fourth quantum well protection layer PQ1C are obtained by pixelating the fourth quantum well protection film layer PQ1 in the wafer, and the three are of the same layer and the same material.

[0331] The fourth multi-quantum well layer MQW12A, the fourth multi-quantum well layer MQW12B and the fourth multi-quantum well layer MQW12C are obtained by pixelating the fourth multi-quantum well film layer MQW12 in the wafer, and the three are of the same layer and material.

[0332] For example, Fig.18 As shown, the second active layer T2A of LED1 in the first primary color device stack LED1' further includes a fifth sub-active layer A5, the second active layer T2B of LED2 in the second primary color device stack LED2' further includes a fifth sub-active layer B5, and the second active layer T2C of LED3 further includes a fifth sub-active layer C5.

[0333] The fifth barrier layer L22A, the fifth barrier layer L22B and the fifth barrier layer L22C are obtained by pixelating the fifth barrier film layer L22 in the wafer, and the three are of the same layer and material.

[0334] The fifth multi-quantum well layer MQW22A, the fifth multi-quantum well layer MQW22B and the fifth multi-quantum well layer MQW22C are obtained by pixelating the fifth multi-quantum well film layer MQW22 in the wafer, and the three are of the same layer and material.

[0335] For example, Fig.18 As shown, the third active layer T3A of LED1 in the first primary color device stack LED1' further includes a sixth sub-active layer A6, the third active layer T3B of LED2 in the second primary color device stack LED2' further includes a sixth sub-active layer B6, and the third active layer T3C of LED3 further includes a sixth sub-active layer C6.

[0336] The sixth barrier layer L32A, the sixth barrier layer L32B and the sixth barrier layer L32C are obtained by pixelating the sixth barrier film layer L32 in the wafer, and the three are of the same layer and material.

[0337] The sixth multi-quantum well layer MQW32A, the sixth multi-quantum well layer MQW32B and the sixth multi-quantum well layer MQW32C are obtained by pixelating the sixth multi-quantum well film layer MQW32 in the wafer, and the three are of the same layer and material.

[0338] Fig.18 The structures of the first active layer T1A of LED1, the first active layer T1B of LED2, the first active layer T1C of LED3, the second active layer T2B of LED2, the second active layer T2C of LED3 and the third active layer T3C of LED3 shown can be applied to any of the above chip structures.

[0339] Fig.19 A schematic diagram of the structure of another chip provided in an embodiment of the present application.

[0340] like Fig.19 As shown, the first active layer T1A of LED1 in the finally formed first primary color light emitting device further includes a fourth sub-active layer A4. The first active layer T1B of LED2 in the second primary color light emitting device further includes a fourth sub-active layer B4, and the second active layer T2B of LED2 further includes a fifth sub-active layer B5. The first active layer T1C of LED3 in the third primary color light emitting device further includes a fourth sub-active layer C4, the second active layer T2C of LED3 further includes a fifth sub-active layer C5, and the third active layer T3C of LED3 further includes a sixth sub-active layer C6.

[0341] Fig. 20 A schematic diagram of the structure of another chip provided in an embodiment of the present application.

[0342] In some embodiments, Fig. 20As shown, the first primary color light emitting device LED1 includes a first hole injection layer PA, a first active layer T1A of LED1, a first electron injection layer N1A of LED1, a second active layer T2A of LED1, a second electron injection layer N2A of LED1, a third active layer T3A of LED1, and a third electron injection layer N3A of LED1. The first primary color light emitting device LED1' may also include one or more of a first bonding layer 26A, a first ohmic contact layer 25A, a first electron blocking layer 24A, a first stress release layer 23A, and a first N-type semiconductor layer 22A.

[0343] The first N-type semiconductor layer 22A, the first stress release layer 23A, the third electron injection layer N3A of LED1, the third active layer T3A of LED1, the second electron injection layer N2A of LED1 and the second active layer T2A of LED1 respectively have first sub-vias, and the first sub-vias on each film layer are connected to form a first via.

[0344] The second primary color light emitting device LED2 includes a second hole injection layer PB, a first active layer T1B of LED2, a first electron injection layer N1B of LED2, a second active layer T2B of LED2, a second electron injection layer N2B of LED2, a third active layer T3B of LED2, and a third electron injection layer N3B of LED2. The second primary color light emitting device LED2 may further include one or more of a second bonding layer 26B, a second ohmic contact layer 25B, a second electron blocking layer 24B, a second stress release layer 23B, and a second N-type semiconductor layer 22B.

[0345] The second N-type semiconductor layer 22B, the second stress release layer 23B, the third active layer T3B of LED2 and the third electron injection layer N3B of LED2 respectively have second sub-vias, and the second sub-vias on each film layer are connected to form a second via.

[0346] The third primary color light emitting device LED3 includes a third hole injection layer PC, a first active layer T1C of LED3, a first electron injection layer N1C of LED3, a second active layer T2C of LED3, a second electron injection layer N2C of LED3, a third active layer T3C of LED3 and a third electron injection layer N3C of LED3, which are sequentially arranged on one side of the driving backplane. The third primary color light emitting device LED3 may also include one or more of a third bonding layer 26C, a third ohmic contact layer 25C, a third electron blocking layer 24C, a third stress release layer 23C and a third N-type semiconductor layer 22C.

[0347] The second active layer T2A of LED1, the second active layer T2B of LED2 and the second active layer T2C of LED3 are of the same layer and material, and the third active layer T3A of LED1, the third active layer T3B of LED2 and the third active layer T3C of LED3 are of the same layer and material.

[0348] The first via hole penetrates the third electron injection layer N3A of LED1, the third active layer T3A of LED1, the second electron injection layer N2A of LED1, and the second active layer T2A of LED1, exposing the first electron injection layer N1A of LED1. When the first primary color light emitting device LED1 further includes the first stress release layer 23A and the first N-type semiconductor layer 22A, the first via hole also penetrates the first stress release layer 23A and the first N-type semiconductor layer 22A.

[0349] The first via hole may just penetrate the second active layer T2A of the second LED 1 and terminate at the surface of the first electron injection layer N1A of LED 1. The first via hole may also extend into the first electron injection layer N1A of LED 1 to reduce the requirement on process accuracy.

[0350] The second via hole penetrates the third electron injection layer N3B of LED2 and the third active layer T3B of LED2, exposing the second electron injection layer N2B of LED2. When the second primary color light emitting device LED2 further includes a second stress release layer 23B and a second N-type semiconductor layer 22B, the second via hole also penetrates the second stress release layer 23B and the second N-type semiconductor layer 22B.

[0351] The second via hole can just penetrate the third active layer T3B of LED 2 and terminate at the surface of the second electron injection layer N2B of LED 2. The second via hole can also extend to the second electron injection layer N2B of LED 2 to reduce the requirement on process accuracy.

[0352] The embodiment of the present application does not limit the contour shape of the first via hole, which can be a hole of any closed shape such as a round hole or a square hole. In addition, the chip may include one or more first via holes and one or more second via holes. Fig. 20 The example in which a chip includes a first via hole and a second via hole is used for illustration.

[0353] The transparent electrode layer 29 is coupled to the first electron injection layer N1A of LED1 through the first via hole, and is coupled to the second electron injection layer N2B of LED2 through the second via hole. At this time, the dielectric layer 27 also covers the sidewalls of the first via hole and the second via hole to achieve electrical isolation between the transparent electrode layer 29 and the third electron injection layer N3B of LED2, the third electron injection layer N3A of LED1, and the second electron injection layer N2A of LED1.

[0354] Fig.21A schematic diagram of the structure of another chip provided in an embodiment of the present application.

[0355] In some embodiments, Fig.21 As shown, the chip further includes a first conductive pillar 291 and a second conductive pillar 292. The first conductive pillar 291 is disposed in the first via hole, and the second conductive pillar 292 is disposed in the second via hole.

[0356] The first conductive pillar 291 is coupled to the transparent electrode layer 29 and the first electron injection layer N1A of LED1, respectively, to achieve the coupling between the transparent electrode layer 29 and the first electron injection layer N1A of LED1. The second conductive pillar 292 is coupled to the transparent electrode layer 29 and the second electron injection layer N2B of LED2, respectively, to achieve the coupling between the transparent electrode layer 29 and the second electron injection layer N2B of LED2.

[0357] By providing the first conductive column 291 in the first via hole, the ohmic contact effect between the transparent conductive layer 29 and the first electron injection layer N1A of LED1 can be improved, the resistance can be reduced, and the electron injection effect can be improved. Similarly, by providing the second conductive column 292 in the second via hole, the ohmic contact effect between the transparent conductive layer 29 and the second electron injection layer N2B of LED2 can be improved, the resistance can be reduced, and the electron injection effect can be improved.

[0358] Fig. 22 A flow chart of a chip preparation method provided in the embodiment of the present application, combined with Fig.23 and Fig.24 A schematic diagram of a chip manufacturing process product structure provided in an embodiment of the present application introduces the chip manufacturing process.

[0359] In the second implementation, Fig. 22 As shown, step S2 includes:

[0360] S21', such as Fig.23 As shown, the wafer is cut to form a first primary color device stack LED1', a second primary color device stack LED2' and a third primary color light emitting device LED3 which are arranged at intervals.

[0361] S22', such as Fig.24 As shown, a first via hole and a second via hole are formed, wherein the first via hole exposes the first electron injection layer N1A of LED1, and the second via hole exposes the second electron injection layer N2B of LED2, so as to form a first primary color light emitting device LED1, a second primary color light emitting device LED2 and a third primary color light emitting device LED3.

[0362] S3', such as Fig. 20 As shown, a dielectric layer 27, a reflective retaining wall 28 and a transparent electrode layer 29 are formed.

[0363] In some embodiments, Fig. 20 As shown, the transparent electrode layer 29 is coupled to the first electron injection layer N1A of LED1 through a first via hole, and is coupled to the second electron injection layer N2B of LED2 through a second via hole.

[0364] In other embodiments, Fig.21 As shown, before forming the transparent electrode layer 29, the chip preparation method further includes:

[0365] A first conductive column 291 and a second conductive column 292 are formed, the first conductive column 291 is disposed in the first via hole, and the second conductive column 292 is disposed in the second via hole. The transparent electrode layer 29 is coupled to the first electron injection layer N1A of LED1 through the first conductive column 291, and the transparent electrode layer 29 is coupled to the second electron injection layer N2B of LED2 through the second conductive column 292.

[0366] The positional structural relationship among the dielectric layer 27 , the reflective baffle 28 and the transparent electrode layer 29 may refer to the above-mentioned related description, which will not be repeated here.

[0367] In the above chip preparation method, the first primary color sub-pixel P1 and the second primary color sub-pixel P2 do not completely remove the redundant active layer and electron injection layer on the top layer by etching or other methods, but form a first via hole and a second via hole by etching or other methods, and realize electron injection of the first primary color sub-pixel P1 through the first via hole, and realize electron injection of the second primary color sub-pixel P2 through the second via hole, thereby realizing R, G, B single-chip full-color pixels. In this way, the top layer of the chip has a relatively high flatness, and the platformization of the top of the chip can be supported in the future, so as to facilitate the subsequent production of other processes such as micro-lenses on the top of the chip.

[0368] Fig.25 A schematic diagram of an arrangement of light-emitting devices provided in an embodiment of the present application.

[0369] like Fig.25 As shown, in the embodiment of the present application, the shape of the first primary color light emitting device LED1, the second primary color light emitting device LED2, and the third primary color light emitting device LED3 of the chip can be rectangular, and the shape of the first primary color light emitting device LED1, the second primary color light emitting device LED2, and the third primary color light emitting device LED3 can also be any closed shape such as circular, triangular, hexagonal, etc. The first primary color light emitting device LED1, the second primary color light emitting device LED2, and the third primary color light emitting device LED3 can be arranged in any layout such as four-room arrangement of pixels, triangle arrangement of pixels, diamond arrangement of pixels, etc. Fig.25 This is just an illustrative example.

[0370] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip, characterized in that: The chip comprises: Driver backplane; A first primary color light emitting device and a second primary color light emitting device are arranged at intervals on the same side of the driving backplane; The first primary color light emitting device comprises a first bonding layer, a first hole injection layer, a first active layer of the first primary color light emitting device and a first electron injection layer of the first primary color light emitting device which are arranged in sequence, the first active layer of the first primary color light emitting device comprises a first sub-active layer, the first sub-active layer comprises a first barrier layer and a first multi-quantum well layer which are arranged in sequence on a side of the first hole injection layer away from the driving backplane; the first bonding layer is bonded to the driving backplane; The second primary color light emitting device comprises a second bonding layer, a second hole injection layer, a first active layer of the second primary color light emitting device, a first electron injection layer of the second primary color light emitting device, a second active layer of the second primary color light emitting device and a second electron injection layer of the second primary color light emitting device, which are arranged in sequence; the second active layer of the second primary color light emitting device comprises a second sub-active layer, and the second sub-active layer comprises a second barrier layer, a second quantum well protection layer and a second multi-quantum well layer, which are arranged in sequence on a side of the first electron injection layer of the second primary color light emitting device away from the driving backplane; the second bonding layer is bonded to the driving backplane; The first bonding layer and the second bonding layer are formed of the same layer and the same material, and the first active layer of the first primary color light emitting device and the first active layer of the second primary color light emitting device are formed of the same layer and the same material.

2. The chip according to claim 1, characterized in that: The chip further comprises a third primary color light emitting device spaced apart from the second primary color light emitting device; The third primary color light emitting device comprises a third bonding layer, a third hole injection layer, a first active layer of the third primary color light emitting device, a first electron injection layer of the third primary color light emitting device, a second active layer of the third primary color light emitting device, a second electron injection layer of the third primary color light emitting device, a third active layer of the third primary color light emitting device and a third electron injection layer of the third primary color light emitting device, which are arranged in sequence; the third active layer of the third primary color light emitting device comprises a third sub-active layer, and the third sub-active layer comprises a third barrier layer, a third quantum well protection layer and a third multi-quantum well layer, which are arranged in sequence on a side of the second electron injection layer of the third primary color light emitting device away from the driving backplane; the third bonding layer is bonded to the driving backplane; The third bonding layer and the first bonding layer are of the same layer and the same material, the first active layer of the third primary color light emitting device and the first active layer of the first primary color light emitting device are of the same layer and the same material, and the second active layer of the third primary color light emitting device and the second active layer of the second primary color light emitting device are of the same layer and the same material.

3. The chip according to claim 2, characterized in that: The chip also includes a transparent electrode layer; The transparent electrode layer is coupled to the first electron injection layer of the first primary color light emitting device, the second electron injection layer of the second primary color light emitting device, and the third electron injection layer of the third primary color light emitting device, respectively.

4. The chip according to claim 3, characterized in that: The chip further comprises a dielectric layer; the dielectric layer is arranged on the side of the transparent electrode layer facing the driving backplane; the dielectric layer comprises a first opening, a second opening and a third opening; The dielectric layer covers the edge of the first electron injection layer of the first primary color light emitting device, covers the edge of the second electron injection layer of the second primary color light emitting device, and covers the edge of the third electron injection layer of the third primary color light emitting device; The transparent electrode layer is coupled to the first electron injection layer of the first primary color light emitting device through the first opening, is coupled to the second electron injection layer of the second primary color light emitting device through the second opening, and is coupled to the third electron injection layer of the third primary color light emitting device through the third opening.

5. The chip according to any one of claims 1 to 4, characterized in that: The first active layer of the first primary color light emitting device further includes a fourth sub-active layer; the fourth sub-active layer is arranged between the first hole injection layer and the first sub-active layer, and the fourth sub-active layer includes a fourth barrier layer, a fourth quantum well protection layer and a fourth multi-quantum well layer which are sequentially arranged on a side of the first hole injection layer facing the first sub-active layer; or, The second active layer of the second primary color light-emitting device also includes a fifth sub-active layer; the fifth sub-active layer is arranged between the second sub-active layer and the second electron injection layer of the second primary color light-emitting device, and the fifth sub-active layer includes a fifth barrier layer and a fifth multi-quantum well layer which are sequentially arranged on the side of the second sub-active layer facing the second electron injection layer of the second primary color light-emitting device.

6. The chip according to any one of claims 2 to 4, characterized in that: The third active layer of the third primary color light-emitting device also includes a sixth sub-active layer; the sixth sub-active layer is arranged between the third sub-active layer and the third electron injection layer of the third primary color light-emitting device, and the sixth sub-active layer includes a sixth barrier layer and a sixth multi-quantum well layer which are sequentially arranged on the side of the third sub-active layer toward the third electron injection layer of the third primary color light-emitting device.

7. The chip according to any one of claims 2 to 6, characterized in that: The chip further comprises a reflective baffle wall arranged on the driving backplane, wherein the reflective baffle wall comprises a first sub-reflective baffle wall, a second sub-reflective baffle wall and a third sub-reflective baffle wall; The first sub-reflective baffle is arranged on the side of the first primary color light emitting device, and the top of the first sub-reflective baffle away from the driving backplane is higher than the top of the first multi-quantum well layer away from the driving backplane; The second sub-reflective baffle is arranged on the side of the second primary color light emitting device, and the top of the second sub-reflective baffle away from the driving backplane is higher than the top of the second multi-quantum well layer away from the driving backplane; The third sub-reflective baffle is arranged on the side of the third primary color light emitting device, and the top of the third sub-reflective baffle away from the driving backplane is higher than the top of the third multi-quantum well layer away from the driving backplane.

8. The chip according to claim 7, characterized in that: The material of the reflective blocking wall includes metal, and the reflective blocking wall is coupled to the transparent electrode layer.

9. The chip according to claim 7 or 8, characterized in that: The reflective baffle is arranged on a side of the transparent electrode layer away from the driving backplane.

10. The chip according to any one of claims 7 to 9, characterized in that: There is a gap between the first sub-reflective baffle and the first primary color light emitting device; There is a gap between the second sub-reflective baffle and the second primary color light emitting device; There is a gap between the third sub-reflective blocking wall and the third primary color light emitting device.

11. The chip according to any one of claims 3 to 10, characterized in that: The chip further includes a first via and a second via; The first primary color light emitting device further comprises a second active layer of the first primary color light emitting device, a second electron injection layer of the first primary color light emitting device, a third active layer of the first primary color light emitting device and a third electron injection layer of the first primary color light emitting device, which are sequentially arranged on a side of the first electron injection layer of the first primary color light emitting device away from the driving backplane; The second primary color light emitting device further comprises a third active layer of the second primary color light emitting device and a third electron injection layer of the second primary color light emitting device which are sequentially arranged on a side of the second electron injection layer of the second primary color light emitting device away from the driving backplane; The second active layer of the first primary color light emitting device and the second active layer of the second primary color light emitting device are of the same layer and material, and the third active layer of the first primary color light emitting device, the third active layer of the second primary color light emitting device and the third active layer of the third primary color light emitting device are of the same layer and material; The first via hole penetrates the third electron injection layer of the first primary color light emitting device, the third active layer of the first primary color light emitting device, the second electron injection layer of the first primary color light emitting device, and the second active layer of the first primary color light emitting device; The second via hole penetrates the third electron injection layer of the second primary color light emitting device and the third active layer of the second primary color light emitting device; The transparent electrode layer is coupled to the first electron injection layer of the first primary color light emitting device through the first via hole, and is coupled to the second electron injection layer of the second primary color light emitting device through the second via hole.

12. The chip according to claim 11, characterized in that: The chip further includes a first conductive column and a second conductive column; The first conductive column is disposed in the first via hole and is respectively coupled to the transparent electrode layer and the first electron injection layer of the first primary color light emitting device; The second conductive column is disposed in the second via hole and is respectively coupled to the transparent electrode layer and the second electron injection layer of the second primary color light emitting device.

13. The chip according to any one of claims 2 to 12, characterized in that: The third primary color light emitting device further comprises a stress release layer, and the stress release layer is arranged on a surface of the third electron injection layer of the third primary color light emitting device away from the driving backplane.

14. The chip according to claim 13, characterized in that: The third primary color light emitting device further comprises an N-type semiconductor layer, which is arranged on a side of the stress release layer away from the third electron injection layer of the third primary color light emitting device, and a thickness of the N-type semiconductor layer is greater than a thickness of the third electron injection layer of the third primary color light emitting device.

15. The chip according to any one of claims 2 to 14, characterized in that: The first primary color light emitting device further includes a first ohmic contact layer, and the first ohmic contact layer is arranged between the first bonding layer and the first hole injection layer; The second primary color light emitting device further comprises a second ohmic contact layer, wherein the second ohmic contact layer is arranged between the second bonding layer and the second hole injection layer; The first primary color light emitting device further includes a third ohmic contact layer, and the third ohmic contact layer is arranged between the third bonding layer and the third hole injection layer; The first ohmic contact layer, the second ohmic contact layer and the third ohmic contact layer are in the same layer and made of the same material.

16. The chip according to any one of claims 2 to 15, characterized in that: The first primary color light emitting device further comprises a first electron blocking layer, wherein the first electron blocking layer is disposed between the first hole injection layer and the first active layer of the first primary color light emitting device; The second primary color light emitting device further comprises a second electron blocking layer, wherein the second electron blocking layer is disposed between the second hole injection layer and the first active layer of the second primary color light emitting device; The first primary color light emitting device further comprises a third electron blocking layer, wherein the third electron blocking layer is arranged between the third hole injection layer and the first active layer of the third primary color light emitting device; The first electron blocking layer, the second electron blocking layer and the third electron blocking layer are formed in the same layer and made of the same material.

17. A display device, characterized in that: It comprises a chip and a lens, wherein the lens is arranged on the light output side of the chip; the chip comprises the chip according to any one of claims 1 to 16.

18. An electronic device, characterized in that: It comprises an optical waveguide sheet and a display device, wherein the optical waveguide sheet is used to receive image light emitted by the display device; the display device comprises the display device according to claim 17.

19. A wafer, characterized in that: The wafer comprises: Hole injection into the film layer; A first primary color active film layer, a first electron injection film layer, a second primary color active film layer, a second electron injection film layer, a third primary color active film layer and a third electron injection film layer are sequentially arranged on one side of the hole injection film layer; The first primary color active film layer includes a first sub-active film layer, and the first sub-active film layer includes a first barrier film layer and a first multi-quantum well film layer sequentially arranged on a side of the hole injection film layer facing the first electron injection film layer; The second primary color active film layer includes a second sub-active film layer, and the second sub-active film layer includes a second barrier film layer, a second quantum well protection film layer, and a second multi-quantum well film layer, which are sequentially arranged on a side of the first electron injection film layer facing the second electron injection film layer; The third primary color active film layer includes a third sub-active film layer, and the third sub-active film layer includes a third barrier film layer, a third quantum well protection film layer and a third multi-quantum well film layer which are sequentially arranged on the side of the second electron injection film layer facing the third electron injection film layer.

20. The wafer according to claim 19, characterized in that The first primary color active film layer further includes a fourth sub-active film layer; the fourth sub-active film layer is arranged between the hole injection film layer and the first sub-active film layer, and the fourth sub-active film layer includes a fourth barrier film layer, a fourth quantum well protection film layer and a fourth multi-quantum well film layer which are sequentially arranged on the side of the hole injection film layer facing the first sub-active film layer; or, The second primary color active film layer further includes a fifth sub-active film layer; the fifth sub-active film layer is arranged between the second sub-active film layer and the second electron injection film layer, and the fifth sub-active film layer includes a fifth barrier film layer and a fifth multi-quantum well film layer which are sequentially arranged on a side of the second sub-active film layer facing the second electron injection film layer; or, The third primary color active film layer also includes a sixth sub-active film layer; the sixth sub-active film layer is arranged between the third sub-active film layer and the third electron injection film layer, and the sixth sub-active film layer includes a sixth barrier film layer and a sixth multi-quantum well film layer which are sequentially arranged on the side of the third sub-active film layer facing the third electron injection film layer.

21. The wafer according to claim 19 or 20, characterized in that: The wafer further includes an electron blocking film layer, and the electron blocking film layer is arranged between the hole injection film layer and the first primary color active film layer.

22. The wafer according to any one of claims 19 to 21, characterized in that: The wafer further includes an ohmic contact film layer and a bonding film layer, and the ohmic contact film layer and the bonding film layer are sequentially arranged on a side of the hole injection film layer away from the first primary color active film layer.

23. The wafer according to any one of claims 19 to 22, characterized in that: The wafer further comprises a stress release film layer, and the stress release film layer is arranged on a side of the third electron injection film layer away from the third primary color active film layer.

24. The wafer according to claim 23, characterized in that The wafer further includes an N-type semiconductor film layer, and the N-type semiconductor film layer is arranged on a side of the stress release film layer away from the third electron injection film layer.

25. The wafer according to any one of claims 19 to 24, characterized in that: The wafer further comprises a buffer film layer, which is arranged on a side of the third electron injection film layer away from the third primary color active film layer and located on the surface of the wafer; or, The wafer further includes a buffer film layer and a substrate. The substrate is located on a surface of the wafer, and the buffer film layer is arranged on a surface of the substrate facing the third electron injection film layer.

26. A wafer stack, characterized in that: It comprises a wafer and a driving substrate, wherein the wafer comprises the wafer described in any one of claims 19 to 25; and the wafer is bonded to the driving substrate.

27. A method for preparing a chip, characterized in that: The wafer preparation method comprises: providing a wafer stack, the wafer stack comprising the wafer stack of claim 26; The wafers in the wafer stack are pixelated to form a first primary color light emitting device, a second primary color light emitting device and a third primary color light emitting device which are arranged on a driving substrate in the wafer stack at intervals; the first primary color light emitting device comprises a first hole injection layer, a first active layer of the first primary color light emitting device and a first electron injection layer of the first primary color light emitting device which are arranged in sequence, the first active layer of the first primary color light emitting device comprises a first sub-active layer, and the first sub-active layer comprises a first barrier layer and a first multi-quantum well layer which are arranged in sequence on a side of the first hole injection layer away from the driving backplane; the second primary color light emitting device comprises a second hole injection layer, a first active layer of the second primary color light emitting device, a first electron injection layer of the second primary color light emitting device, a second active layer of the second primary color light emitting device and a second electron injection layer of the second primary color light emitting device which are arranged in sequence; The second active layer of the device includes a second sub-active layer, and the second sub-active layer includes a second barrier layer, a second quantum well protection layer, and a second multi-quantum well layer, which are sequentially arranged on the side of the first electron injection layer of the second primary color light-emitting device away from the driving backplane; the third primary color light-emitting device includes a third hole injection layer, a first active layer of the third primary color light-emitting device, a first electron injection layer of the third primary color light-emitting device, a second active layer of the third primary color light-emitting device, a second electron injection layer of the third primary color light-emitting device, a third active layer of the third primary color light-emitting device, and a third electron injection layer of the third primary color light-emitting device, which are sequentially arranged; the third active layer of the third primary color light-emitting device includes a third sub-active layer, and the third sub-active layer includes a third barrier layer, a third quantum well protection layer, and a third multi-quantum well layer, which are sequentially arranged on the side of the second electron injection layer of the third primary color light-emitting device away from the driving backplane; A transparent electrode layer is formed, and the transparent electrode layer is coupled to the first electron injection layer of the first primary color light emitting device, the second electron injection layer of the second primary color light emitting device, and the third electron injection layer of the third primary color light emitting device, respectively.

28. The preparation method according to claim 27, characterized in that: The wafers in the wafer stack are pixelated to form a first primary color light emitting device, a second primary color light emitting device and a third primary color light emitting device which are arranged on a driving substrate in the wafer stack at intervals, including: The wafer is cut to form a first primary color device stack, a second primary color device stack and the third primary color light-emitting device which are arranged at intervals; the first primary color device stack includes the first hole injection layer, the first active layer of the first primary color light-emitting device, the first electron injection layer of the first primary color light-emitting device, the second active layer of the first primary color light-emitting device, the second electron injection layer of the first primary color light-emitting device, the third active layer of the first primary color light-emitting device and the third electron injection layer of the first primary color light-emitting device; the second primary color device stack includes the second hole injection layer, the first active layer of the second primary color light-emitting device, the first electron injection layer of the second primary color light-emitting device, the second active layer of the second primary color light-emitting device, the second electron injection layer of the second primary color light-emitting device, the third active layer of the second primary color light-emitting device and the third electron injection layer of the second primary color light-emitting device; removing the third active layer of the second primary color light emitting device, the third electron injection layer of the second primary color light emitting device, the third active layer of the first primary color light emitting device and the third electron injection layer of the first primary color light emitting device to form a stack of the second primary color light emitting device and the first primary color device; The second active layer of the first primary color light emitting device and the second electron injection layer of the first primary color light emitting device are removed to form the first primary color light emitting device.

29. The preparation method according to claim 27, characterized in that: The first primary color light emitting device further comprises a second active layer of the first primary color light emitting device, a second electron injection layer of the first primary color light emitting device, a third active layer of the first primary color light emitting device and a third electron injection layer of the first primary color light emitting device, which are sequentially arranged at a side where the first electron injection layer of the first primary color light emitting device is away from the driving backplane; the second primary color light emitting device further comprises a third active layer of the second primary color light emitting device and a third electron injection layer of the second primary color light emitting device, which are sequentially arranged at a side where the second electron injection layer of the second primary color light emitting device is away from the driving backplane; Before forming the transparent electrode layer, the preparation method further includes: forming a first via hole and a second via hole; the first via hole penetrates the third electron injection layer of the first primary color light-emitting device, the third active layer of the first primary color light-emitting device, the second electron injection layer of the first primary color light-emitting device and the second active layer of the first primary color light-emitting device, and the second via hole penetrates the third electron injection layer of the second primary color light-emitting device and the third active layer of the second primary color light-emitting device; The transparent electrode layer is coupled to the first electron injection layer of the first primary color light emitting device through the first via hole, and is coupled to the second electron injection layer of the second primary color light emitting device through the second via hole.

30. The preparation method according to any one of claims 27 to 29, characterized in that: The preparation method further comprises: forming a reflective baffle wall; the reflective baffle wall comprises a first sub-reflective baffle wall, a second sub-reflective baffle wall and a third sub-reflective baffle wall; The first sub-reflective baffle is arranged on the side of the first primary color light emitting device, and the top of the first sub-reflective baffle away from the driving backplane is higher than the top of the first multi-quantum well layer away from the driving backplane; The second sub-reflective baffle is arranged on the side of the second primary color light emitting device, and the top of the second sub-reflective baffle away from the driving backplane is higher than the top of the second multi-quantum well layer away from the driving backplane; The third sub-reflective baffle is arranged on the side of the third primary color light emitting device, and the top of the third sub-reflective baffle away from the driving backplane is higher than the top of the third multi-quantum well layer away from the driving backplane.

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