Light-emitting unit and preparation method thereof, light-emitting panel and display device

Abstract

The embodiment of the invention provides a light-emitting unit and a preparation method thereof, a light-emitting panel and a display device. The light emitting unit includes: a first semiconductor layer; an active layer; the first columnar structures are located on the side, away from the first semiconductor layer, of the active layer and comprise second semiconductor layers, a first groove is formed between every two adjacent first columnar structures, and the distance between the bottom wall of each first groove and the surface, facing one side of the corresponding first columnar structure, of the active layer is larger than or equal to 0; the first passivation layer is located on the plurality of first columnar structures and is provided with a first via hole, and the first via hole is located on the second semiconductor layer; a first electrode coupled to the second semiconductor layer through the first via hole; the second electrode layer is located on the side, away from the active layer, of the first semiconductor layer, and the second electrode layer is coupled with the first semiconductor layer. According to the invention, the influence of etching damage on light emission can be avoided, and the light extraction efficiency is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a light-emitting unit and a preparation method thereof, a light-emitting panel and a display device. Background Art

[0002] Light-emitting diodes (LEDs) can include sub-millimeter light-emitting diodes (Mini Light Emitting Diode, referred to as Mini LED) and micro light-emitting diodes (Micro Light Emitting Diode, referred to as Micro LED). MicroLED chip size is usually a few microns to tens of microns, and has a very broad application scenario in wearable devices, augmented reality (AR), virtual reality (VR), smart car lights, and visible light communications.

[0003] As the size of LED chips decreases, the ratio of the chip sidewall to the light-emitting surface area continues to increase. As a result, during the device preparation process, sidewall damage caused by dry etching makes it difficult to improve LED efficiency. In addition, as the chip size decreases, the chip table area decreases, making table roughening more difficult, affecting light extraction. Therefore, how to avoid sidewall damage and increase light extraction is an important issue facing LEDs. Summary of the invention

[0004] The embodiments of the present disclosure provide a light-emitting unit and a method for manufacturing the same, a light-emitting panel and a display device to solve or alleviate one or more technical problems in the prior art.

[0005] As a first aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a light emitting unit, including:

[0006] a first semiconductor layer;

[0007] An active layer, located on one side of the first semiconductor layer;

[0008] A plurality of first columnar structures separated from each other are located on a side of the active layer away from the first semiconductor layer, the first columnar structures include a second semiconductor layer, first grooves are provided between adjacent first columnar structures, and a distance between a bottom wall of the first groove and a surface of the active layer facing the first columnar structure is greater than or equal to 0;

[0009] A first passivation layer is located on a side of the plurality of first columnar structures away from the first semiconductor layer, the first passivation layer is provided with a first via hole, and an orthographic projection of the first via hole on the active layer is located within an orthographic projection of the second semiconductor layer on the active layer;

[0010] A first electrode coupled to the second semiconductor layer through a first via hole;

[0011] The second electrode layer is located at a side of the first semiconductor layer away from the active layer, and the second electrode layer is coupled to the first semiconductor layer.

[0012] In some embodiments, a first insulating passivation layer is further included. The first insulating passivation layer is located on a surface of the first trench and extends from the surface of the first trench toward an inner side of the corresponding film layer by a first preset dimension.

[0013] In some embodiments, the first insulating passivation layer includes at least a portion of the active layer located within a first projection area, and the first projection area includes an orthographic projection area of ​​a bottom wall of the first trench on the active layer.

[0014] In some embodiments, the method further includes a second semiconductor connection portion located between the active layer and the plurality of first columnar structures, wherein the second semiconductor connection portion and the second semiconductor layer are an integral structure.

[0015] In some embodiments, the first insulating passivation layer includes a portion of the second semiconductor connection portion located within a first projection area, and the first projection area includes an orthographic projection area of ​​a bottom wall of the first trench on the active layer.

[0016] In some embodiments, the first passivation layer fills the first groove, the surface of the first passivation layer facing away from the active layer is a flat surface, the first electrode is located in the first via hole, and the distance between the surface of the first electrode facing away from the active layer and the active layer is smaller than the distance between the surface of the first passivation layer facing away from the active layer and the active layer.

[0017] In some embodiments, the first columnar structure further includes an auxiliary electrode layer and a reflective layer stacked in sequence on a side of the second semiconductor layer away from the active layer, the first via hole penetrates the reflective layer, and the first electrode is coupled to the auxiliary electrode layer.

[0018] In some embodiments,

[0019] The color of the light emitted by the light emitting unit includes blue or green, and the material of the reflective layer includes silver; or,

[0020] The color of the light emitted by the light emitting unit includes red, and the material of the reflective layer includes gold.

[0021] In some embodiments, the second electrode layer is provided with a hollow area corresponding to the first columnar structure, the orthographic projection of the second electrode layer on the active layer at least partially overlaps with the orthographic projection of the bottom wall of the corresponding first groove on the active layer, and the surface of the first semiconductor layer located in the hollow area has a preset roughness.

[0022] In some embodiments, the second electrode layer is provided with a hollow area corresponding to the first columnar structure, the light-emitting unit also includes a second groove, the second groove penetrates the first semiconductor layer and the active layer, the orthographic projection of the second groove on the active layer is located within the orthographic projection of the bottom wall of the first groove on the active layer, the second electrode layer includes a shielding portion and a partition portion, the shielding portion is located on the surface of the first semiconductor layer, and the partition portion is located in the second groove.

[0023] As a second aspect of the embodiment of the present disclosure, the embodiment of the present disclosure provides a method for preparing a light-emitting unit, including:

[0024] growing an active layer on one side of the first semiconductor layer;

[0025] forming a structural layer on a side of the active layer facing away from the first semiconductor layer;

[0026] Etching the structural layer to form a first groove, wherein the first groove defines a plurality of first columnar structures separated from each other, wherein the first columnar structure includes a second semiconductor layer, wherein the second semiconductor layer is located on a side of the active layer away from the first semiconductor layer, and a distance between a bottom wall of the first groove and a surface of the active layer facing the first columnar structure is greater than or equal to 0;

[0027] A first passivation layer is formed on a side of the plurality of first columnar structures away from the first semiconductor layer, the first passivation layer is provided with a first via hole, and an orthographic projection of the first via hole on the active layer is located within an orthographic projection of the second semiconductor layer on the active layer;

[0028] forming a first electrode, wherein the first electrode is coupled to the second semiconductor layer through a first via hole;

[0029] A second electrode layer is formed on a side of the first semiconductor layer facing away from the active layer, and the second electrode layer is coupled to the first semiconductor layer.

[0030] In some embodiments, before forming a first passivation layer on a side of the plurality of first columnar structures away from the first semiconductor layer, the method further includes:

[0031] The surface of the first trench is passivated to passivate a first preset dimension from the surface of the first trench toward the inner side of the corresponding film layer to form a first insulating passivation layer.

[0032] In some embodiments, before forming the second electrode layer on the side of the first semiconductor layer facing away from the active layer, the method further comprises:

[0033] A driving backplane is provided, wherein a second passivation layer is disposed on one side surface of the driving backplane, the surface of the second passivation layer is a flat surface, a second via hole is opened in the second passivation layer, and a bonding electrode is located in the second via hole;

[0034] The surface of the first passivation layer is bonded to the surface of the second passivation layer, and the bonding is performed by hybrid alignment bonding, so that the first electrode and / or the bonding electrode are connected after expansion.

[0035] In some embodiments, forming a second electrode layer on a side of the first semiconductor layer away from the active layer includes:

[0036] A second trench is formed on a side of the first semiconductor layer away from the active layer, the second trench penetrates the first semiconductor layer and the active layer, and an orthographic projection of the second trench on the active layer is located within an orthographic projection of a bottom wall of the first trench on the active layer;

[0037] A second electrode layer is formed on a side of the first semiconductor layer away from the active layer. The second electrode layer includes a shielding portion and a partition portion. The shielding portion is located on the surface of the first semiconductor layer, the partition portion is located in the second groove, and the second electrode layer is provided with a hollow area corresponding to the first columnar structure.

[0038] In some embodiments, the second electrode layer is provided with a hollow region corresponding to the first columnar structure, and the method further comprises:

[0039] The second electrode layer is used as a shielding layer, and the surface of the first semiconductor layer in the hollow area is roughened.

[0040] As a third aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a light-emitting panel, including:

[0041] A driving back plate provided with bonding electrodes;

[0042] In any light-emitting unit of the present disclosure, the first electrode of the light-emitting unit is bonded to the bonding electrode.

[0043] In some embodiments, the driving backplane includes a driving structure layer and a second passivation layer located on one side of the driving structure layer, the surface of the second passivation layer is a flat surface, the second passivation layer is provided with a second via hole, and the bonding electrode is located in the second via hole;

[0044] The surface of the first passivation layer in the light-emitting unit that is away from the active layer is a flat surface, the surface of the second passivation layer is in contact with the surface of the first passivation layer, and the first electrode is bonded to the bonding electrode in alignment.

[0045] As a fourth aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display device, including the light-emitting panel in the embodiments of the present disclosure.

[0046] In the light-emitting unit of the embodiment of the present disclosure, the active layer is located on one side of the first semiconductor layer, and a plurality of first columnar structures separated from each other are arranged on the side of the active layer facing away from the first semiconductor layer, and the adjacent first columnar structures are separated by the first groove, so that the light-emitting unit includes a plurality of light-emitting bodies, and each light-emitting body is separated by the first groove. The distance between the bottom wall of the first groove and the surface of the active layer facing the first columnar structure is greater than or equal to 0, so that when the first groove is etched by an etching process, the active layer will not be etched, thereby avoiding damage to the active layer by the etching process, and further avoiding the influence of etching loss on the light-emitting body, which can improve the internal quantum efficiency of the light-emitting body, and further improve the external quantum efficiency of the light-emitting body, thereby improving the light extraction efficiency.

[0047] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present disclosure will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments according to the present disclosure and should not be regarded as limiting the scope of the present disclosure.

[0049] Figure 1 is a cross-sectional schematic diagram of a light-emitting panel in an embodiment of the present disclosure;

[0050] Figure 2 is a schematic plan view of a light-emitting panel in an embodiment of the present disclosure;

[0051] Figure 3 It is a cross-sectional schematic diagram after a structural layer is formed in a process of preparing a light-emitting unit according to an embodiment of the present disclosure;

[0052] Figure 4 It is a cross-sectional schematic diagram after the first groove is formed in the process of preparing the light-emitting unit according to one embodiment of the present disclosure;

[0053] Figure 5 It is a cross-sectional schematic diagram of a light-emitting unit after a first insulating passivation layer is formed in a process of preparing the light-emitting unit according to an embodiment of the present disclosure;

[0054] Figure 6 It is a cross-sectional schematic diagram after the first passivation layer is formed in the process of preparing the light-emitting unit according to one embodiment of the present disclosure;

[0055] Figure 7 It is a cross-sectional schematic diagram after forming the first electrode in the process of preparing the light-emitting unit according to one embodiment of the present disclosure;

[0056] Figure 8 It is a cross-sectional schematic diagram of a light-emitting unit after being attached to a driving backplane during the preparation process of the light-emitting unit according to an embodiment of the present disclosure;

[0057] Fig. 9 It is a cross-sectional schematic diagram after the second groove is formed in the process of preparing the light-emitting unit according to one embodiment of the present disclosure;

[0058] Fig.10 FIG. 4 is a cross-sectional schematic diagram of a light-emitting panel in another embodiment of the present disclosure.

[0059] Description of reference numerals:

[0060] 100, light-emitting unit; 10, light-emitting body; 101, columnar structure; 11, first semiconductor layer; 111, first semiconductor part; 12, active layer; 121, active part; 13, second semiconductor film; 131, second semiconductor layer; 132, second semiconductor connection part; 14, auxiliary electrode film; 141, auxiliary electrode layer; 15, reflective film; 151, reflective layer; 152, first groove; 153, first insulating passivation layer; 16, first passivation layer;

[0061] 200, driving backplane; 21, driving structure layer; 22, second passivation layer; 23, bonding electrode;

[0062] 300, substrate; 301, buffer layer;

[0063] 31. First electrode; 32. Second electrode layer; 321. Shielding portion; 322. Partitioning portion; 323. Hollow region. DETAILED DESCRIPTION

[0064] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure, and different embodiments may be combined arbitrarily without conflict. Therefore, the drawings and descriptions are considered to be illustrative in nature and not restrictive.

[0065] Figure 1 is a cross-sectional schematic diagram of a light-emitting panel in an embodiment of the present disclosure, Figure 2 is a plan view of a light emitting panel in an embodiment of the present disclosure, Figure 1 Can be Figure 2 AA cross-section diagram in Figure 2. Figure 1 and Figure 2As shown, the light-emitting panel includes a driving backplane 200 and a light-emitting unit 100 arranged on one side of the driving backplane 200. The light-emitting unit 100 includes a first semiconductor layer 11 and an active layer 12, and the active layer 12 is located on one side of the first semiconductor layer 11. The active layer 12 is located on the side of the first semiconductor layer 11 facing the driving backplane 200. The light-emitting unit 100 also includes a plurality of first columnar structures 101 separated from each other, and the plurality of first columnar structures 101 are located on the side of the active layer 12 away from the first semiconductor layer 11. The first columnar structure 101 includes a second semiconductor layer 131. First grooves 152 are arranged between adjacent first columnar structures 101, and the arrangement of the first grooves 152 separates the plurality of first columnar structures 101 from each other. Exemplarily, as Figure 2 As shown, the first grooves 152 may be arranged along the circumference of the first columnar structure 101 , so that each first columnar structure 101 is isolated as an independent structure by the first grooves 152 . Figure 2 The boundary of the first trench 152 is shown by arrows.

[0066] like Figure 2 As shown, the distance between the bottom wall of the first groove 152 and the surface of the active layer 12 facing the first columnar structure 101 is greater than or equal to 0, that is, the distance between the upper surface of the first groove 152 and the lower surface of the active layer 12 is greater than or equal to 0. Therefore, when the first groove 152 is formed by an etching process, the active layer 12 will not be etched. The specific value of the distance between the bottom wall of the first groove 152 and the surface of the active layer 12 facing the first columnar structure 101 can be set as needed. In one embodiment, the distance between the two can be 40nm to 60nm.

[0067] The light-emitting unit 100 may further include a first passivation layer 16, which is located on a side of the plurality of first columnar structures 101 away from the first semiconductor layer 11, and the first passivation layer 16 is provided with a first via hole K1, and the orthographic projection of the first via hole K1 on the active layer 12 is located within the orthographic projection of the second semiconductor layer 131 on the active layer 12. The first passivation layer 16 is insulating, and the first passivation layer 16 can protect the light-emitting unit 100.

[0068] The light emitting unit 100 further includes a first electrode 31 and a second electrode layer 32. The first electrode 31 is coupled to the second semiconductor layer 131 through a first via hole K1. At least a portion of the first electrode 31 is located in the first via hole K1, so that the first electrode 31 is coupled to the second semiconductor layer 131. The second electrode layer 32 is located on a side of the first semiconductor layer 11 away from the active layer 12, and the second electrode layer 32 is coupled to the first semiconductor layer 11.

[0069] It can be understood that in the light-emitting unit 100, the active layer 12 and the first semiconductor layer 11 located in the region where the first columnar structure 101 is located form a light-emitting body 10 with the first columnar structure 101. For example, the portion of the active layer 12 located in the region where the first columnar structure 101 is located is the active portion 121, and the portion of the first semiconductor layer 11 located in the region where the first columnar structure 101 is located is the first semiconductor portion 111, then, the light-emitting body 10 includes the first semiconductor portion 111, the active portion 121 and the first columnar structure 101 which are stacked.

[0070] The luminous body 10 emits light under the drive of the first electrode 31 and the second electrode layer 32. A light-emitting unit 100 includes a plurality of luminous bodies 10, and the first semiconductor parts 111 of the plurality of luminous bodies 10 are connected to each other through the second electrode layer 32. A luminous body 10 can be regarded as a pixel, and a light-emitting unit 100 includes a plurality of pixels.

[0071] Herein, "plurality" should be understood as two or more.

[0072] In the light-emitting unit 100 of the embodiment of the present disclosure, the active layer 12 is located on one side of the first semiconductor layer 11, and a plurality of first columnar structures 101 separated from each other are arranged on the side of the active layer 12 facing away from the first semiconductor layer 11, and adjacent first columnar structures 101 are separated by first grooves 152, so that the light-emitting unit 100 includes a plurality of light-emitting bodies 10, and each light-emitting body 10 is separated by the first grooves 152. The distance between the bottom wall of the first groove 152 and the surface of the active layer 12 facing the first columnar structure 101 is greater than or equal to 0, so that when the first groove 152 is formed by an etching process, the active layer 12 will not be etched, thereby avoiding damage to the active layer 12 by the etching process, and further avoiding the influence of etching loss on the light-emitting body 10, which can improve the internal quantum efficiency of the light-emitting body 10, and further improve the external quantum efficiency of the light-emitting body 10, thereby improving the light extraction efficiency.

[0073] Fig.10 FIG. 2 is a cross-sectional schematic diagram of a light-emitting panel in another embodiment of the present disclosure. Fig.10 As shown, the light-emitting unit 100 may further include a first insulating passivation layer 153, which is located on the surface of the first groove 152 and extends from the surface of the first groove 152 toward the inner side of the corresponding film layer by a first preset size. It can be understood that the first insulating passivation layer 153 is insulating and non-conductive. Exemplarily, the first insulating passivation layer 153 may be formed by passivating the surface of the first groove 152, for example, the surface of the first groove 152 is passivated, and the first insulating passivation layer 153 is passivated from the surface of the first groove 152 toward the inner side of the corresponding film layer by a first preset size. The specific value of the first preset size can be set as needed.

[0074] It should be noted that the surface of the first groove 152 may include the side surface and the bottom surface of the first groove 152. The first insulating passivation layer 153 includes a first portion 1531 located on the side surface of the first groove 152 and a second portion 1532 located on the bottom surface of the first groove 152. The first portion 1531 extends from the side surface of the first groove 152 toward the inside of the corresponding film layer by a first preset dimension, and the second portion 1532 extends from the bottom surface of the first groove 152 toward the inside of the corresponding film layer by a first preset dimension.

[0075] A first insulating passivation layer 153 is provided on the surface of the first groove 152, and the first insulating passivation layer 153 extends from the surface of the first groove 152 toward the inner side of the corresponding film layer by a first preset dimension. Since the first insulating passivation layer 153 is insulating, it will not affect the luminescence of the light-emitting body 10 during the luminescence process of the light-emitting body 10. Therefore, the morphology of the surface of the first groove 152 will not affect the luminescence of the light-emitting body 10, which can avoid the influence of the side wall damage of the first groove 152 on the light-emitting body 10 during the etching process, further improve the internal quantum efficiency of the light-emitting body 10, and then improve the external quantum efficiency of the light-emitting body 10, thereby improving the light extraction efficiency.

[0076] One of the first semiconductor layer 11 and the second semiconductor layer 131 may be a P-type doped semiconductor layer, and the other may be an N-type doped semiconductor layer. The P-type doped semiconductor layer may include In x Al y Ga 1-x-y N (0≤x<1, 0≤y<1, 0≤x+y<1) component p-type nitride semiconductor layer, the p-type impurity can be magnesium. For example, the material of the P-type doped semiconductor layer can include P-type doped gallium nitride (GaN). The N-type doped semiconductor layer can include In x Al y Ga 1-x-y The n-type nitride semiconductor layer may be N (0≤x<1, 0≤y<1, 0≤x+y<1), and the n-type impurity may be silicon. For example, the material of the N-type doped semiconductor layer may include N-type doped gallium nitride (GaN).

[0077] The second semiconductor layer 131 may be a single-layer structure, but may have a multi-layer structure including different components as in some example embodiments.

[0078] The active layer 12 may have a multi-quantum well (MQW) structure, in which quantum well layers and quantum barrier layers are alternately stacked. For example, the quantum well layers and the quantum barrier layers may include In x Al y Ga 1-x-y N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). In one example, the quantum well layer may include Inx Ga 1-x For the composition of GaN(0 < x ≤ 1), the quantum barrier layer may include GaN or AlGaN. The active layer 12 is not limited to the MQW structure and may have a single quantum well (SQW) structure.

[0079] As Figure 1 shown, the bottom wall of the first trench 152 is the wall of the first trench 152 parallel to the active layer 12. The first projection region includes the positive projection region of the bottom wall of the first trench 152 on the active layer 12. To prevent crosstalk between adjacent light emitters 10 in the light emitting unit 100, the first insulating passivation layer 153 may include at least a part of the active layer 12 located within the first projection region. Exemplarily, the first insulating passivation layer 153 may include the part of the active layer 12 located within the first projection region, that is, when the surface of the first trench 152 is passivated, the part of the active layer 12 located within the first projection region is also passivated and insulated to form an insulating isolation portion. Thus, the active layers 12 in adjacent light emitters 10 are isolated from each other by the insulating isolation portion, and crosstalk between adjacent light emitters 10 can be avoided.

[0080] The light emitting unit 100 may further include a second semiconductor connection portion 132, and the second semiconductor connection portion 132 may be located between the active layer 12 and the plurality of first columnar structures 101. The setting of the second semiconductor connection portion 132 enables a certain distance between the bottom wall of the first trench 152 and the active layer 12, so that when the first trench 152 is etched, the active layer 12 will not be etched, avoiding damage to the active layer 12 caused by etching. Exemplarily, the thickness of the second semiconductor connection portion 132 may range from 40 nm to 60 nm. For example, the thickness of the second semiconductor connection portion 132 may be 40 nm, 50 nm, or 60 nm. Thus, a suitable distance can be provided between the bottom wall of the first trench 152 and the active layer 12, avoiding etching damage to the active layer 12.

[0081] The second semiconductor connection portion 132 may be an integral structure with the second semiconductor layer 131. That is, a second semiconductor thin film is grown on the surface of the active layer 12. After the first trench 152 is formed by an etching process, the second semiconductor thin film that is etched and separated by the first trench 152 forms the second semiconductor layer 131, and the second semiconductor thin film that is not etched forms the second semiconductor connection portion 132.

[0082] The first insulating passivation layer 153 may further include the part of the second semiconductor connection portion 132 located within the first projection region. That is, when the surface of the first trench 152 is passivated, the part of the second semiconductor connection portion 132 located within the first projection region is also passivated and insulated, thereby isolating the second semiconductor layers 131 in adjacent light emitters 10 and ensuring that the light emission of adjacent light emitters 10 is not interfered.

[0083] In one embodiment, the first columnar structure 101 may further include an auxiliary electrode layer 141 and a reflective layer 151. The auxiliary electrode layer 141 and the reflective layer 151 are sequentially stacked on the side of the second semiconductor layer 131 away from the active layer 12. For example, the auxiliary electrode layer 141 may be located on the side of the second semiconductor layer 131 away from the active layer 12, and the reflective layer 151 may be located on the side of the auxiliary electrode layer 141 away from the active layer 12. Figure 1 In the embodiment, the auxiliary electrode layer 141 is located on the lower surface of the second semiconductor layer 131, and the reflective layer 151 is located on the lower surface of the auxiliary electrode layer 141, so that the second semiconductor layer 131, the auxiliary electrode layer 141 and the reflective layer 151 are stacked in sequence from top to bottom. The first via hole K1 can penetrate the first passivation layer 16 and the reflective layer 151, so that the first electrode 31 can be coupled with the auxiliary electrode layer 141 to achieve coupling between the first electrode 31 and the second semiconductor layer 131. The aperture size of the first via hole K1 can be greater than or equal to 1μm, and the maximum size of the aperture of the first via hole K1 can be set as needed, as long as the first via hole K1 is set on the surface of the first passivation layer 16.

[0084] The material of the auxiliary electrode layer 141 may include a transparent conductive material, for example, the material of the auxiliary electrode layer 141 may include at least one of indium tin oxide (ITO) and indium zinc oxide (IZO). The auxiliary electrode layer 141 is conducive to the diffusion of holes, has the function of expanding current, and can improve the light extraction performance of the light emitting body 10.

[0085] The thickness of the auxiliary electrode layer 141 may be 80 nm to 200 nm. For example, the thickness of the auxiliary electrode layer 141 may be 80 nm, 100 nm, 120 nm, 180 nm or 200 nm.

[0086] The reflective layer 151 can reflect light, and then, Figure 1 As shown, when the light emitted by the light emitting body 10 is emitted from the lower side, the reflective layer 151 can reflect the light toward the upper side, thereby preventing the light from being emitted from the lower side and improving the light emission efficiency of the upper side.

[0087] In one embodiment, the reflective layer 151 may be a mirror reflective layer 151, and the thickness of the reflective layer 151 may be 100nn to 200nm. For example, the thickness of the reflective layer 151 may be 100nn, 150nm or 200nm. Exemplarily, when the color of the light emitted by the light-emitting unit 100 includes blue light or green light, the material of the reflective layer 151 may include silver. Such a reflective layer 151 can reflect more than 90% of the blue light or green light, thereby improving the light extraction efficiency. When the color of the light emitted by the light-emitting unit 100 includes red light, the material of the reflective layer 151 may include gold. Such a reflective layer 151 can reflect more than 90% of the red light, thereby improving the light extraction efficiency.

[0088] In another embodiment, the reflective layer 151 may include a distributed Bragg reflector (DBR), and the thickness of the reflective layer 151 may be 1 μm to 2 μm, for example, the thickness of the reflective layer 151 may be 1 μm, 1.5 μm or 2 μm. The DBR may be set according to the color of the light emitted by the light emitting unit 100, so that the DBR matches the color of the light emitted by the light emitting unit 100, and then the DBR may reflect the light emitted by the light emitting unit 100 toward the upper side, thereby improving the light extraction efficiency.

[0089] In one embodiment, Figure 1 and Figure 2 As shown, the second electrode layer 32 is provided with a hollow area 323, and the hollow area 323 corresponds to the first columnar structure 101. Such a second electrode layer 32 is a mesh structure, and each hollow area defines a light-emitting area. A light-emitting unit 100 includes multiple light-emitting areas, and the light-emitting areas correspond to the light-emitting bodies 10 one by one. The light emitted by the light-emitting bodies 10 is emitted from the corresponding hollow areas 323.

[0090] In one embodiment, the orthographic projection of the second electrode layer 32 on the active layer 12 at least partially overlaps with the orthographic projection of the bottom wall of the corresponding first groove 152 on the active layer 12. It can be understood that the bottom wall of the first groove 152 is non-luminous, and the orthographic projection of the second electrode layer 32 on the active layer 12 is set to at least partially overlap with the orthographic projection of the bottom wall of the corresponding first groove 152 on the active layer 12, which can reduce the area of ​​the light-emitting region occupied by the second electrode layer 32, which is conducive to improving the resolution of the display product.

[0091] Illustratively, after the second electrode layer 32 is formed on the upper surface of the first semiconductor layer 11, the first semiconductor layer 11 can be used as a shielding layer to roughen the entire surface of the first semiconductor layer 11 of the light-emitting unit 100 on the side facing away from the active layer 12. Under the shielding effect of the second electrode layer 32, the surface of the first semiconductor portion of the first semiconductor layer 11 located in the hollow area 323 has a preset roughness.

[0092] It can be understood that when the surface of the first semiconductor portion 111 in the hollow area 323 is a smooth surface, light will form a waveguide mode in the light emitting body 10 and cannot escape. In this embodiment, for each light emitting body 10, the surface of the first semiconductor portion 111 is a rough surface with a preset roughness. Such a rough surface can couple out the light in the waveguide mode, so that the light is scattered in a diffuse manner, which increases the light escape and improves the light extraction efficiency.

[0093] In the related art, as the size of the LED chip decreases, the roughening area decreases, making roughening difficult. In the embodiment of the present disclosure, after the second electrode layer 32 is provided on the surface of the first semiconductor portion 111 away from the active layer 12, the entire upper surface of the first semiconductor layer 11 can be roughened, which greatly increases the roughening area and improves the roughening efficiency. In addition, during the roughening process, the shielding effect of the second electrode layer 32 enables the surface of the first semiconductor layer 11 located in the hollow area to be roughened, while the area covered by the second electrode layer 32 will not be roughened.

[0094] Exemplarily, the roughening depth of the surface of the first semiconductor portion 111 in the hollow region may be in the range of 200nm to 400nm, for example, the roughening depth may be 200nm, 300nm or 400nm. Exemplarily, when the size of the roughening particles is 200 to 500nm and the corrosion depth (i.e., the roughening depth) is about 200nm to 400nm, the light extraction efficiency may be increased by more than 30% at an injection current of 20 mA, and the surface roughening will not affect the angular distribution of the luminous intensity of the light emitting body 10.

[0095] In one embodiment, Figure 1 As shown, the light emitting unit 100 may further include a second groove 112, which penetrates the first semiconductor layer 11 and the active layer 12. The orthographic projection of the second groove 112 on the active layer 12 is located within the orthographic projection of the bottom wall of the first groove 152 on the active layer 12. The second electrode layer 32 includes a shielding portion 321 and a partition portion 322, the shielding portion 321 is located on the surface of the first semiconductor layer 11, and the partition portion 322 is located in the second groove 112. Exemplarily, the material of the second electrode layer 32 may include an opaque conductive material.

[0096] The partition part 322 located in the second groove 112 can isolate two adjacent light emitters 10, and can effectively reduce the light crosstalk between adjacent light emitters 10. One light emitter 10 is equivalent to one pixel, and the partition part 322 can be used as a partition between adjacent pixels.

[0097] In addition, the bottom wall of the first groove 152 is non-luminous, and the orthographic projection of the second groove 112 on the active layer 12 is set to be located within the orthographic projection of the bottom wall of the first groove 152 on the active layer 12. This makes the second groove 112 and the partition portion 322 located in the non-luminous area of ​​the light-emitting unit 100, which can avoid the second groove 112 occupying the area of ​​the light-emitting area and avoid the second groove 112 affecting the light-emitting area.

[0098] Exemplarily, the second trench 112 may also penetrate the second semiconductor connection portion 132 , or the second trench 112 may also enter the first passivation layer 16 in the first trench 152 , both of which will not affect the light emitting unit 100 .

[0099] An embodiment of the present disclosure further provides a method for preparing a light emitting unit 100 , comprising steps S21 to S27 .

[0100] In step S21 , an active layer 12 is grown on one side of the first semiconductor layer 11 .

[0101] In step S22 , a structure layer is formed on a side of the active layer 12 facing away from the first semiconductor layer 11 .

[0102] In step S23 , the structural layer is etched to form a first trench 152 . The first trench 152 defines a plurality of first columnar structures 101 separated from each other. The first columnar structures 101 include a second semiconductor layer 131 . The second semiconductor layer 131 is located on a side of the active layer 12 away from the first semiconductor layer 11 .

[0103] In step S24 , a first passivation layer 16 is formed on the side of the plurality of first columnar structures 101 away from the first semiconductor layer 11 . The first passivation layer 16 is provided with a first via hole K1 . The orthographic projection of the first via hole K1 on the active layer 12 is located within the orthographic projection of the second semiconductor layer 131 on the active layer 12 .

[0104] In step S25 , the first electrode 31 is formed, and the first electrode 31 is coupled to the second semiconductor layer 131 through the first via hole K1 .

[0105] In step S26 , a second electrode layer 32 is formed on a side of the first semiconductor layer 11 facing away from the active layer 12 , and the second electrode layer 32 is coupled to the first semiconductor layer 11 .

[0106] In one embodiment, before forming the first passivation layer 16 on the side of the multiple first columnar structures 101 facing away from the first semiconductor layer 11, the method further includes: passivating the surface of the first groove 152 to passivate a first preset dimension from the surface of the first groove 152 toward the inner side of the corresponding film layer to form a first insulating passivation layer 153.

[0107] In one embodiment, the first passivation layer 16 may fill the first groove 152. For example, the first passivation layer 16 fills the first groove 152 completely. The surface of the first passivation layer 16 on the side away from the active layer 12 is a flat surface. The first electrode 31 is located in the first via hole K1, and the distance d3 between the surface of the first electrode 31 on the side away from the active layer 12 and the active layer 12 is less than the distance d4 between the surface of the first passivation layer 16 on the side away from the active layer 12 and the active layer 12. The difference between the distances d3 and d4 can be set as needed, for example, the difference between the distances d3 and d4 can be 2nm to 3nm. Before step S27, the preparation method may further include: providing a driving backplane 200, wherein a second passivation layer 22 is disposed on a surface of one side of the driving backplane 200, wherein the surface of the second passivation layer 22 is a flat surface, and a second via hole K2 is opened in the second passivation layer 22, wherein the bonding electrode 23 is located in the second via hole K2; and the surface of the first passivation layer 16 is bonded to the surface of the second passivation layer 22, and a mixed alignment bonding method is used for bonding, so that the first electrode 31 and / or the bonding electrode 23 are connected after expansion.

[0108] In one embodiment, step S26 may include: forming a second groove 112 on the side of the first semiconductor layer 11 away from the active layer 12, the second groove 112 penetrates the first semiconductor layer 11 and the active layer 12, and the orthographic projection of the second groove 112 on the active layer 12 is located within the orthographic projection of the bottom wall of the first groove 152 on the active layer 12; forming a second electrode layer 32 on the side of the first semiconductor layer 11 away from the active layer 12, the second electrode layer 32 includes a shielding portion 321 and a partition portion 322, the shielding portion 321 is located on the surface of the first semiconductor layer 11, the partition portion 322 is located in the second groove 112, and the second electrode layer 32 is provided with a hollow area 323 corresponding to the first columnar structure 101.

[0109] In one embodiment, the second electrode layer 32 is provided with a hollow region 323 corresponding to the first columnar structure 101. The preparation method may further include: using the second electrode layer 32 as a shielding layer, and roughening the surface of the first semiconductor layer 11 in the hollow region 323.

[0110] Below Fig.10 Taking the light-emitting panel shown as an example, the technical solution of the embodiment of the present disclosure is further explained through the preparation process of the light-emitting unit 100 in one embodiment of the present disclosure. It can be understood that the "patterning" mentioned in this article includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist when the patterned material is an inorganic material or metal, and includes processes such as mask exposure and development when the patterned material is an organic material. The evaporation, deposition, coating, and coating mentioned in this article are all mature preparation processes in the relevant technology.

[0111] A first semiconductor layer 11 is grown on one side of the substrate 300, an active layer 12 is grown on the side of the first semiconductor layer 11 facing away from the substrate 300; a structural layer is formed on the side of the active layer 12 facing away from the first semiconductor layer 11, such as Figure 3 As shown, Figure 3 It is a cross-sectional schematic diagram after a structural layer is formed in a process of preparing a light-emitting unit according to an embodiment of the present disclosure.

[0112] Exemplarily, the substrate 300 may be a sapphire substrate, and may also be a substrate of other materials, such as a silicon substrate, an aluminum oxide substrate, a diamond substrate, etc. The structural layer may include a stacked second semiconductor film 13, an auxiliary electrode film 14, and a reflective film 15. Before growing the first semiconductor layer 11, a buffer layer 301 is grown on the surface of the substrate 300, and the first semiconductor layer 11 is grown on the buffer layer 301.

[0113] The structural layer is etched to form a first groove 152, such as Figure 4 As shown, Figure 4 This is a cross-sectional diagram of a light-emitting unit after forming a first groove in the process of preparing the light-emitting unit according to an embodiment of the present disclosure. For example, the structural layer is etched by an etching process, and the second semiconductor film 13 is not etched through, and a portion of the second semiconductor film is retained to form a second semiconductor connection portion 132. The second semiconductor connection portion 132 can prevent etching damage to the active layer 12. The first groove 152 defines a plurality of first columnar structures 101 separated from each other, Figure 4 Two first columnar structures 101 are shown in FIG. The first columnar structure 101 includes a second semiconductor layer 131 , and the second semiconductor layer 131 is located on a side of the active layer 12 away from the first semiconductor layer 11 . Figure 4 In the embodiment, the first columnar structure 101 may further include an auxiliary electrode layer 141 and a reflective layer 151, and the second semiconductor layer 131, the auxiliary electrode layer 141 and the reflective layer 151 are stacked in sequence.

[0114] like Figure 4 As shown, the surface of the first groove 152 includes a side surface and a bottom surface of the first groove 152. The first columnar structure 101 includes a second semiconductor layer 131, an auxiliary electrode layer 141 and a reflective layer 151 which are stacked, so the side surface of the first groove 152 includes a first surface portion 1521, a second surface portion 1522 and a third surface portion 1523. The first surface portion 1521 is formed by the side surface of the second semiconductor layer 131, the second surface portion 1522 is formed by the side surface of the auxiliary electrode layer 141, and the third surface portion 1523 is formed by the side surface of the reflective layer 151. Figure 4 In the embodiment, the bottom surface of the first trench 152 is formed by the surface of the second semiconductor connection portion 132 exposed in the first trench 152 .

[0115] The process of forming the first groove 152 may include: depositing an insulating film on the side of the structure away from the active layer 12, and the material of the insulating film may include at least one of silicon nitride, silicon oxide, and silicon oxynitride; patterning the insulating film to form a hard mask, and the hard mask is provided with a hollow, and the hollow corresponds to the first groove 152; using the hard mask as a mask, etching the structural layer at the hollow position to form the first groove 152, and the first groove 152 may surround the first columnar structure 101. When etching to form the first groove 152, in order to prevent etching to the active layer 12, the second semiconductor film 13 should not be etched through, and a part of the thickness of the second semiconductor film may be retained to form the second semiconductor connection portion 132. The distance between the bottom wall of the first groove 152 and the active layer 12 can be set as needed, as long as it is ensured that the active layer 12 corresponding to the first groove 152 can be passivated in the subsequent passivation process. The shape surrounded by the first groove 152 can be one of polygonal, circular, elliptical and other shapes, and thus, the shape of the first columnar structure 101 can be one of polygonal, circular, elliptical and other shapes.

[0116] The surface of the first trench 152 is passivated to form a first insulating passivation layer 153. The first insulating passivation layer 153 is formed by passivating a first preset dimension from the surface of the first trench 152 toward the inner side of the corresponding film layer. Figure 5 As shown, Figure 5 1 is a cross-sectional schematic diagram after the first insulating passivation layer is formed in the process of preparing the light-emitting unit according to an embodiment of the present disclosure. The first insulating passivation layer 153 includes a first portion 1531 located on the side surface of the first groove 152 and a second portion 1532 located on the bottom surface of the first groove 152. The first portion 1531 extends from the side surface of the first groove 152 toward the inner side of the film layer corresponding to the first columnar structure 101, and the second portion 1532 extends from the bottom surface of the first groove 152 toward the inner side of the corresponding film layer.

[0117] Exemplarily, the surface of the first groove 152 may be passivated, and passivation may be performed along the surface of the first groove 152 toward the inner side of the corresponding film layer. For example, the side surface of the first groove 152 includes a first surface portion 1521, a second surface portion 1522, and a third surface portion 1523. For the first surface portion 1521, a first preset dimension is passivated along the first surface portion 1521 toward the inside of the second semiconductor layer 131; for the second surface portion 1522, a first preset dimension is passivated along the second surface portion 1522 toward the inside of the auxiliary electrode layer 141; for the third surface portion 1523, a first preset dimension is passivated along the third surface portion 1523 toward the inside of the reflective layer 151, thereby forming a continuous insulating passivation film on the side surfaces of the second semiconductor layer 131, the auxiliary electrode layer 141, and the reflective layer 151, that is, forming a first portion 1531 of the first insulating passivation layer 153, and the first portion 1531 is located on the side surface of the first groove 152.

[0118] For the bottom surface of the first trench 152, Figure 4 and Figure 5 , a first preset dimension is passivated toward the lower side along the exposed surface of the second semiconductor connection portion 132. Exemplarily, the first preset dimension is greater than or equal to the sum of the thickness of the second semiconductor connection portion 132 and the thickness of the active layer 12, so that the second semiconductor connection portion 132 corresponding to the first groove 152 and the active layer 12 are both passivated. Figure 5 The first insulating passivation layer 153 is illustrated in gray shaded areas.

[0119] It is understandable that the material composition of the first insulating passivation layer 153 is different from the material composition of the corresponding film layer. For example, the material composition of the passivated portion and the non-passivated portion of the second semiconductor layer 131 is different, the material composition of the passivated portion and the non-passivated portion of the auxiliary electrode layer 141 is different, and the material composition of the passivated portion and the non-passivated portion of the reflective layer 151 is different.

[0120] Three passivation methods may be used to passivate the surface of the first trench 152 to form the first insulating passivation layer 153 .

[0121] The first method is to place the entire structure forming the first trench 152 in a high temperature environment and in a passivation atmosphere filled with oxygen, and expose the surface of the first trench 152 to the passivation atmosphere. By controlling the time, the portion of the first trench 152 from the surface to the inner side of the corresponding film layer with a first preset thickness can be oxidized and passivated and insulated, thereby forming a first insulating passivation layer 153 with a first preset thickness passivated from the surface of the first trench 152 to the inner side of the corresponding film layer. Figure 5 FIG. 1 schematically shows the boundary line of the first insulating passivation layer 153 .

[0122] The second method: the surface of the first groove 152 can be passivated by oxygen ion implantation. For example, oxygen ions are implanted along the surface of the first groove 152. By controlling the implantation time, the depth of the oxygen ion implantation can be made a first preset size, thereby forming a first insulating passivation layer 153.

[0123] The third method: passivation treatment is performed on the surface of the first groove 152 by electrochemical etching. For example, the entire structure forming the first groove 152 is placed in a corrosion solution, and by controlling the reaction time, ions in the first preset thickness film layer from the surface of the first groove 152 toward the inner side of the corresponding film layer can be released into the corrosion solution to form a porous structure. Therefore, the first insulating passivation layer 153 formed by this method is a passivation insulating layer with a porous structure. For example, the corrosion solution can include an oxalic acid solution.

[0124] The first insulating passivation layer 153 formed by the first method and the second method contains a relatively high concentration of oxygen, and the first insulating passivation layer 153 formed by the third method has a porous structure.

[0125] Three methods of passivating the surface of the first groove 152 are listed above. It is understandable that the passivation treatment on the surface of the first groove 152 is not limited to the above three methods. Other methods can also be used to passivate the surface of the first groove 152 to form a first insulating passivation layer 153.

[0126] In order to prevent light crosstalk between adjacent light emitters, the portion of the active layer 12 located at the first groove 152 is also passivated, thereby isolating the connection between the active parts 121 in different light emitters.

[0127] It can be understood that when the first groove 152 is formed by the etching process, there is etching damage on the surface of the first groove 152. By passivating the surface of the first groove 152, an insulating film can be formed on the etched damaged surface. The insulating film is non-conductive, and thus, the insulating film does not affect the luminescence. This avoids the influence of etching loss on luminescence, improves the internal quantum efficiency, and then improves the external quantum efficiency, thereby improving the luminescence performance.

[0128] A first passivation layer 16 is formed on one side of the plurality of first columnar structures 101 away from the first semiconductor layer 11. The first passivation layer 16 is provided with a first via hole K1. The orthographic projection of the first via hole K1 on the active layer 12 is located within the orthographic projection of the second semiconductor layer 131 on the active layer 12. Figure 6 As shown, Figure 6It is a cross-sectional schematic diagram after the first passivation layer is formed in the process of preparing the light-emitting unit of one embodiment of the present disclosure. For example, a passivation film can be deposited on the side of the multiple first columnar structures 101 away from the first semiconductor layer 11. For example, the passivation film can fill the first groove 152; the passivation film is subjected to chemical mechanical polishing (CMP polishing) to make the surface of the passivation film a flat surface; the passivation film is patterned to form a first via K1, and the first via K1 penetrates the passivation film and the reflective layer 151, so that part of the surface of the auxiliary electrode layer 141 is exposed through the first via K1. The first via K1 corresponds to the first columnar structure 101. The shape of the first via K1 can be an inverted trapezoid, such as Figure 6 As shown, that is to say, the aperture of the first via hole K1 gradually increases from bottom to top.

[0129] The first electrode 31 is formed, and the first electrode 31 is coupled to the second semiconductor layer 131 through the first via hole K1. Figure 7 As shown, Figure 7 It is a cross-sectional schematic diagram after the first electrode is formed in the process of preparing the light-emitting unit of one embodiment of the present disclosure. Exemplarily, the first electrode 31 can be formed in the first via hole K1, and the material of the first electrode 31 can be a conductive metal, and the material of the first electrode 31 can include at least one of metals such as copper (Cu), gold (Au), and tin (Sn). The distance between the surface of the first electrode 31 facing away from the active layer 12 and the active layer 12 is less than the distance between the surface of the first passivation layer 16 facing away from the active layer 12 and the active layer 12, that is, the upper surface of the first electrode 31 is lower than the upper surface of the first passivation layer 16, and a first preset distance d1 can be set between the upper surface of the first electrode 31 and the upper surface of the first passivation layer 16. The specific value of the first preset distance d1 can be set as needed, for example, the value range of the first preset distance d1 can be 0 to 3nm or 0 to 2nm. For example, the first electrode 31 may be formed in the first via hole K1 by electroplating, and the first electrode 31 is coupled to the auxiliary electrode layer 141 , thereby achieving coupling between the first electrode 31 and the second semiconductor layer 131 .

[0130] A driving backplane 200 is provided. A second passivation layer 22 is disposed on one side of the driving backplane 200. The surface of the second passivation layer 22 is a flat surface. The second passivation layer 22 is provided with a second via hole K2. A bonding electrode 23 is disposed in the second via hole K2. Figure 8 As shown, Figure 8 This is a cross-sectional schematic diagram of a light-emitting unit after being attached to a driving backplane during the preparation process of a light-emitting unit according to an embodiment of the present disclosure. Figure 8 The first electrode 31 is not bonded to the bonding electrode 23. For example, the shape of the second via hole K2 may be an inverted trapezoid, such as Figure 8As shown, the aperture of the second via hole K2 gradually increases from bottom to top, that is, the aperture of the second via hole K2 gradually increases in the direction close to the light-emitting unit 100, and the closer to the first passivation layer 16, the larger the aperture of the second via hole K2. Exemplarily, a second preset distance d2 is set between the upper surface of the bonding electrode 23 and the surface of the second passivation layer 22 in the driving backplane 200, and the specific value of the second preset distance d2 can be set as needed, for example, the value range of the second preset distance d2 can be 0 to 3nm or 0 to 2nm.

[0131] The surface of the first passivation layer 16 is bonded to the surface of the second passivation layer 22, and hybrid alignment bonding is used to bond the first electrode 31 and the bonding electrode 23. The hybrid alignment bonding process may include: activating the first passivation layer 16 and the second passivation layer 22 respectively, and then cleaning them; bonding the surface of the first passivation layer 16 to the surface of the second passivation layer 22, so that the first electrode 31 and the bonding electrode 23 are aligned; performing an annealing process to expand the first electrode 31 and the bonding electrode 23, so as to achieve a bonding connection between the first electrode 31 and the bonding electrode 23.

[0132] In this embodiment, Figure 8 As shown, the aperture of the second via hole K2 gradually increases from bottom to top, and the aperture of the first via hole K1 gradually increases from top to bottom, which is beneficial to the alignment of the first electrode 31 in the first via hole K1 and the bonding electrode 23 in the second via hole K2, and can reduce the alignment accuracy.

[0133] In other embodiments, other bonding methods may be used to achieve the connection between the first electrode 31 and the bonding electrode 23. For example, the material of the first electrode 31 may include a gold-tin alloy, and the material of the bonding electrode 23 may include a gold-tin alloy, so that the first electrode 31 and the bonding electrode 23 may be connected by a gold-tin (AuSn) eutectic bonding method. In another embodiment, the material of the first electrode 31 may include indium tin oxide (ITO), and the material of the bonding electrode 23 may include indium tin oxide, so that the first electrode 32 and the bonding electrode 23 may be connected by ITO bonding.

[0134] The substrate 300 is peeled off. After the first electrode 31 and the bonding electrode 23 are bonded, the substrate 300 can be peeled off by laser peeling, chemical peeling or etching peeling; the upper side of the first semiconductor layer 11 is thinned by an epitaxial thinning process to prevent the film layer from being too thick. The thinning process may include thinning by an etching process, thinning by chemical mechanical polishing (CMP), and the like. It can be understood that before growing the first semiconductor layer 11 on the substrate 300, a film layer such as a buffer layer 301 can be grown on the substrate 300, and then the first semiconductor layer 11 is grown. The buffer layer 301 may include a stacked aluminum nitride layer and an undoped gallium nitride layer, and the undoped gallium nitride layer is located between the aluminum nitride layer and the first semiconductor layer 11. The thinning process is mainly to reduce the thickness of the buffer layer 301.

[0135] A second trench 112 is formed on the side of the first semiconductor layer 11 away from the active layer 12. The second trench 112 penetrates the first semiconductor layer 11 and the active layer 12. The orthographic projection of the second trench 112 on the active layer 12 is located within the orthographic projection of the bottom wall of the first trench 152 on the active layer 12. Fig. 9 As shown, Fig. 9 1 is a cross-sectional schematic diagram after the second groove is formed in the process of preparing the light-emitting unit according to an embodiment of the present disclosure. For example, a photoresist can be coated on the side of the first semiconductor layer 11 away from the active layer 12, the photoresist is exposed and developed through a mask, and the first semiconductor layer 11 and the active layer 12 at the position of the second groove 112 are etched away, thereby forming the second groove 112. The first semiconductor layer 11 is isolated into a plurality of first semiconductor portions 111 by the second groove 112, and the active layer 12 is isolated into a plurality of active portions 121 by the second groove 112.

[0136] In one embodiment, the minimum depth of the second groove 112 is the sum of the thicknesses of the first semiconductor layer 11 and the active layer 12, and the maximum depth of the second groove 112 is the distance between the upper surface of the first semiconductor layer 11 and the lower surface of the first passivation layer 16. In other words, the bottom of the second groove 112 is located between the surface of the second semiconductor layer 131 facing the active layer 12 (i.e., the upper surface of the second semiconductor layer 131) and the surface of the first passivation layer 16 facing the driving backplane 200 (i.e., the lower surface of the first passivation layer 16).

[0137] A second electrode film is deposited on the side of the first semiconductor layer 11 away from the active layer 12, and the second electrode film is patterned to form a second electrode layer 32. The second electrode layer 32 is provided with a hollow region 323 corresponding to the first columnar structure 101. Fig.10 and Figure 2As shown. The second electrode layer 32 includes a shielding portion 321 and a partition portion 322, wherein the shielding portion 321 is located on the surface of the first semiconductor layer 11, and the partition portion 322 is located in the second groove 112. The first semiconductor layer 11 and the active layer 12 in two adjacent light-emitting bodies 10 are separated by the partition portion 322, and the partition portion 322 is opaque to prevent crosstalk between the light-emitting bodies 10. Exemplarily, the material of the second electrode layer 32 may be a conductive metal, and the conductive metal may include at least one of metals such as gold (Au), platinum (Pt), and titanium (Ti).

[0138] The preparation method may also include: using the second electrode layer 32 as a shielding layer to roughen the surface of the first semiconductor layer 11 in the hollow area 323. Due to the shielding effect of the second electrode layer 32, the entire upper surface of the first semiconductor layer 11 can be roughened. Since the second electrode layer 32 shields part of the surface, only the surface in the hollow area 323 is roughened. During the roughening process, the roughening area is the surface of the entire first semiconductor layer 11, which greatly increases the roughening area, reduces the difficulty of roughening, and improves the roughening efficiency. The roughening treatment can be performed by solution roughening, metal roughening, etc., which are not limited here.

[0139] Exemplarily, the roughening depth may range from 200 nm to 400 nm.

[0140] One hollow area 323 corresponds to one luminous body 10, one luminous body 10 is equivalent to one pixel, and the partition part 322 partitions the adjacent pixels. When the surface of the first semiconductor layer 11 is roughened, although the entire surface of the first semiconductor layer 11 is exposed to the roughening process, under the shielding effect of the second electrode layer 32, the surface of the first semiconductor part 111 in each hollow area is roughened, which is equivalent to roughening a single pixel, ensuring the uniformity of light emission of each pixel, and multiple pixels in a light-emitting unit 100 are roughened at the same time, ensuring the uniformity of light emission in a light-emitting unit 100 area.

[0141] It can be seen from the preparation process of the light-emitting unit 100 above that a light-emitting panel is also prepared in the process of preparing the light-emitting unit 100. Therefore, the preparation method of the light-emitting unit 100 can also be called the preparation method of the light-emitting panel. In this article, the light-emitting unit 100 and the preparation and the preparation of the light-emitting panel are not strictly distinguished.

[0142] The present disclosure also provides a light-emitting panel. Figure 1 As shown, it includes a driving backplane 200 and a light emitting unit 100 in any embodiment of the present disclosure. The driving backplane 200 is provided with a bonding electrode 23, and the first electrode 31 of the light emitting unit 100 is bonded to the bonding electrode 23.

[0143] The driving backplane 200 includes a driving structure layer 21 and a second passivation layer 22 located on one side of the driving structure layer 21. The surface of the second passivation layer 22 is a flat surface, and the second passivation layer 22 is provided with a second via hole K2, and the bonding electrode 23 is located in the second via hole K2.

[0144] The surface of the first passivation layer 16 in the light-emitting unit 100 facing away from the active layer 12 is a flat surface, the surface of the second passivation layer 22 is in contact with the surface of the first passivation layer 16 , and the first electrode 31 is bonded to the bonding electrode 23 .

[0145] Exemplarily, there is a second preset distance between the surface of the bonding electrode 23 and the surface of the second passivation layer 22. The specific value of the second preset distance can be set as needed, as long as the first electrode 31 and the bonding electrode 23 can be bonded when the light-emitting unit 100 is bonded to the driving backplane 200.

[0146] In an exemplary embodiment, the first passivation layer 16 and the second passivation layer 22 may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer.

[0147] Based on the inventive concept of the foregoing embodiments, an embodiment of the present disclosure further provides a display device, which includes the light-emitting panel of the embodiment of the present disclosure.

[0148] The light-emitting panel in the embodiment of the present disclosure can be assembled in a display device as a display panel, or can be assembled in a display device as a light source. The display device can be: electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, navigators, wearable display devices, and any other products or components with display functions.

[0149] The light-emitting panel in the embodiment of the present disclosure can also be used as a light source in lighting products.

[0150] In the drawings of the specification of the present disclosure, various film layers are schematically shown. It should be understood that the thickness of each film layer is only for the purpose of illustrating the film layer and does not constitute a limitation on the thickness of the film layer, nor does it constitute a limitation on the size relationship of the film layer thickness.

[0151] In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0152] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0153] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0154] In the present disclosure, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being “above”, “above”, and “above” a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0155] The disclosure above provides many different embodiments or examples to implement different structures of the present disclosure. In order to simplify the present disclosure, the components and settings of specific examples are described above. Of course, they are only examples, and the purpose is not to limit the present disclosure. In addition, the present disclosure can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed.

[0156] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of various changes or replacements within the technical scope disclosed in the present disclosure. Different parts in different embodiments can be combined with each other without conflict, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A light emitting unit, characterized in that: include: a first semiconductor layer; An active layer, located on one side of the first semiconductor layer; A plurality of first columnar structures separated from each other are located on a side of the active layer away from the first semiconductor layer, the first columnar structures include a second semiconductor layer, first grooves are provided between adjacent first columnar structures, and a distance between a bottom wall of the first groove and a surface of the active layer facing the first columnar structure is greater than or equal to 0; A first passivation layer is located on a side of the plurality of first columnar structures away from the first semiconductor layer, the first passivation layer is provided with a first via hole, and an orthographic projection of the first via hole on the active layer is located within an orthographic projection of the second semiconductor layer on the active layer; a first electrode coupled to the second semiconductor layer through the first via hole; The second electrode layer is located at a side of the first semiconductor layer away from the active layer, and the second electrode layer is coupled to the first semiconductor layer.

2. The light emitting unit according to claim 1, characterized in that: The invention also includes a first insulating passivation layer, which is located on the surface of the first trench and extends from the surface of the first trench toward the inner side of the corresponding film layer by a first preset dimension.

3. The light emitting unit according to claim 2, characterized in that: The first insulating passivation layer includes at least a portion of the active layer located within a first projection area, and the first projection area includes an orthographic projection area of ​​a bottom wall of the first trench on the active layer.

4. The light emitting unit according to claim 2, characterized in that: It also includes a second semiconductor connection portion located between the active layer and the plurality of first columnar structures, wherein the second semiconductor connection portion and the second semiconductor layer are an integral structure.

5. The light emitting unit according to claim 4, characterized in that: The first insulating passivation layer includes a portion of the second semiconductor connection portion located within a first projection area, and the first projection area includes an orthographic projection area of ​​the bottom wall of the first trench on the active layer.

6. The light emitting unit according to claim 1, characterized in that: The first passivation layer fills the first groove, the surface of the first passivation layer facing away from the active layer is a flat surface, the first electrode is located in the first via hole, and the distance between the surface of the first electrode facing away from the active layer and the active layer is smaller than the distance between the surface of the first passivation layer facing away from the active layer and the active layer.

7. The light emitting unit according to claim 1, characterized in that: The first columnar structure further includes an auxiliary electrode layer and a reflective layer stacked in sequence on a side of the second semiconductor layer away from the active layer, the first via hole penetrates the reflective layer, and the first electrode is coupled to the auxiliary electrode layer.

8. The light emitting unit according to claim 7, characterized in that: The color of the light emitted by the light emitting unit includes blue or green, and the material of the reflective layer includes silver; or The color of the light emitted by the light emitting unit includes red, and the material of the reflective layer includes gold.

9. The light emitting unit according to any one of claims 1 to 8, characterized in that: The second electrode layer is provided with a hollow area corresponding to the first columnar structure, the orthographic projection of the second electrode layer on the active layer at least partially overlaps with the orthographic projection of the bottom wall of the corresponding first groove on the active layer, and the surface of the first semiconductor layer located in the hollow area has a preset roughness.

10. The light emitting unit according to any one of claims 1 to 8, characterized in that: The second electrode layer is provided with a hollow area corresponding to the first columnar structure, and the light-emitting unit also includes a second groove, which runs through the first semiconductor layer and the active layer, and the orthographic projection of the second groove on the active layer is located within the orthographic projection of the bottom wall of the first groove on the active layer, and the second electrode layer includes a shielding portion and a partition portion, the shielding portion is located on the surface of the first semiconductor layer, and the partition portion is located in the second groove.

11. A method for preparing a light-emitting unit, characterized in that: include: growing an active layer on one side of the first semiconductor layer; forming a structural layer on a side of the active layer away from the first semiconductor layer; Etching the structural layer to form a first groove, wherein the first groove defines a plurality of first columnar structures separated from each other, the first columnar structure includes a second semiconductor layer, the second semiconductor layer is located on a side of the active layer away from the first semiconductor layer, and a distance between a bottom wall of the first groove and a surface of the active layer facing the first columnar structure is greater than or equal to 0; A first passivation layer is formed on a side of the plurality of first columnar structures away from the first semiconductor layer, the first passivation layer is provided with a first via hole, and an orthographic projection of the first via hole on the active layer is located within an orthographic projection of the second semiconductor layer on the active layer; forming a first electrode, wherein the first electrode is coupled to the second semiconductor layer through the first via hole; A second electrode layer is formed on a side of the first semiconductor layer facing away from the active layer, and the second electrode layer is coupled to the first semiconductor layer.

12. The method according to claim 11, characterized in that Before forming a first passivation layer on a side of the plurality of first columnar structures away from the first semiconductor layer, the method further includes: The surface of the first trench is passivated to passivate a first preset dimension from the surface of the first trench toward the inner side of the corresponding film layer to form a first insulating passivation layer.

13. The method according to claim 11, characterized in that Before forming a second electrode layer on a side of the first semiconductor layer away from the active layer, the method further comprises: A driving backplane is provided, wherein a second passivation layer is disposed on a surface of one side of the driving backplane, the surface of the second passivation layer is a flat surface, a second via hole is opened in the second passivation layer, and the bonding electrode is located in the second via hole; The surface of the first passivation layer is bonded to the surface of the second passivation layer, and a hybrid alignment bonding method is used to bond the first electrode and / or the bonding electrode so that the first electrode and / or the bonding electrode are connected after expansion.

14. The method according to claim 11, characterized in that The forming of a second electrode layer on a side of the first semiconductor layer away from the active layer comprises: A second groove is formed on a side of the first semiconductor layer away from the active layer, the second groove penetrates the first semiconductor layer and the active layer, and an orthographic projection of the second groove on the active layer is located within an orthographic projection of a bottom wall of the first groove on the active layer; The second electrode layer is formed on the side of the first semiconductor layer away from the active layer, the second electrode layer includes a shielding portion and a partition portion, the shielding portion is located on the surface of the first semiconductor layer, the partition portion is located in the second groove, and the second electrode layer is provided with a hollow area corresponding to the first columnar structure.

15. The method according to claim 11, characterized in that The second electrode layer is provided with a hollow region corresponding to the first columnar structure, and the method further includes: The second electrode layer is used as a shielding layer, and the surface of the first semiconductor layer in the hollow area is roughened.

16. A light-emitting panel, characterized in that: include: A driving back plate provided with bonding electrodes; The light-emitting unit according to any one of claims 1 to 10, wherein the first electrode of the light-emitting unit is bonded to the bonding electrode.

17. The light emitting panel according to claim 16, characterized in that: The driving backplane includes a driving structure layer and a second passivation layer located on one side of the driving structure layer, the surface of the second passivation layer is a flat surface, the second passivation layer is provided with a second via hole, and the bonding electrode is located in the second via hole; The surface of the first passivation layer in the light-emitting unit that is away from the active layer is a flat surface, the surface of the second passivation layer is in contact with the surface of the first passivation layer, and the first electrode is bonded to the bonding electrode in alignment.

18. A display device, characterized in that: Comprising the light-emitting panel according to claim 16 or 17.

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