Display substrate, intermediate display substrate and display device

Abstract

The invention discloses a display substrate, an intermediate display substrate and a display device. The display substrate comprises a substrate, the substrate comprises a display area and a peripheral area surrounding the display area, and the peripheral area comprises a binding area located on one side of the display area; the plurality of sub-pixels are located in the display area; the plurality of power supply pins are located in the binding area and electrically connected with the plurality of sub-pixels, and the plurality of power supply pins are configured to transmit power supply signals to the plurality of sub-pixels; the display substrate comprises a plurality of power supply pins and a plurality of power supply test connecting lines, the power supply test connecting lines are located on the sides, away from the display area, of the power supply pins and connected with the power supply pins, at least one power supply test connecting line in the power supply test connecting lines is made of at least one of titanium and aluminum, and the display substrate can be prevented from being burnt.

Description

Technical Field

[0001] The present invention relates to but is not limited to the field of display technology, and in particular to a display substrate, an intermediate display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) is an active light-emitting display device with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, and extremely high response speed. With the continuous development of display technology, display devices using OLED as the light-emitting element and thin film transistor (TFT) for signal control have become the mainstream products in the current display field.

[0003] Currently, there is a problem that a local area of ​​the binding area of ​​the display substrate is burned. Summary of the invention

[0004] The embodiments of the present disclosure provide a display substrate, an intermediate display substrate and a display device, which can solve the problem of local area burns in the binding area of ​​the existing display substrate.

[0005] In one aspect, an embodiment of the present disclosure provides a display substrate, comprising:

[0006] A substrate, comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area comprises a binding area located at one side of the display area;

[0007] A plurality of sub-pixels are located in the display area; a plurality of power pins are located in the binding area and are electrically connected to the plurality of sub-pixels, and the plurality of power pins are configured to transmit power signals to the plurality of sub-pixels;

[0008] A plurality of power test connection lines are located on a side of the plurality of power pins away from the display area and connected to the plurality of power pins. The material of at least one of the plurality of power test connection lines includes at least one of titanium and aluminum.

[0009] In some exemplary embodiments, the plurality of power supply test connection lines are connected to the plurality of power supply pins in a one-to-one correspondence.

[0010] In some exemplary embodiments, the at least one power supply test connection line includes a first sub-portion and a second sub-portion which are stacked, and the first sub-portion and the second sub-portion are located in different layers, and the first sub-portion is closer to the substrate than the second sub-portion.

[0011] In some exemplary embodiments, the orthographic projection of the second sub-portion on the plane where the substrate is located includes the orthographic projection of the first sub-portion on the plane where the substrate is located, and the orthographic projection area of ​​the second sub-portion on the plane where the substrate is located is larger than the orthographic projection area of ​​the first sub-portion on the plane where the substrate is located.

[0012] In some exemplary embodiments, the first sub-section includes a plurality of first connection portions arranged at intervals, and at least a portion of the surface of the plurality of first connection portions away from the substrate side contacts the second sub-section; or, the second sub-section includes a plurality of second connection portions arranged at intervals, and at least a portion of the surface of the plurality of second connection portions close to the substrate side contacts the first sub-section; or, the first sub-section includes a plurality of first connection portions arranged at intervals, and the second sub-section includes a plurality of second connection portions arranged at intervals, and at least a portion of the surface of the first connection portions away from the substrate side contacts at least a portion of the surface of the second connection portions close to the substrate side.

[0013] In some exemplary embodiments, at least a portion of at least one of the plurality of first connection portions has a straight line projection on the plane where the substrate is located; or, at least a portion of at least one of the plurality of first connection portions has a curved line projection on the plane where the substrate is located.

[0014] In some exemplary embodiments, at least one of the plurality of first connecting portions comprises at least one of a protruding portion and a recessed portion; the protruding portion protrudes in a direction away from the substrate, and the recessed portion is recessed in a direction close to the substrate.

[0015] In some exemplary embodiments, the at least one first connection portion includes a plurality of protrusions and a plurality of recesses; the plurality of protrusions and the plurality of recesses are alternately arranged in sequence.

[0016] In some exemplary embodiments, in a direction perpendicular to the plane where the substrate is located, the binding region includes a first source-drain metal layer, a first planar layer, a second source-drain metal layer, and a second planar layer stacked in sequence, the first sub-portion is located in the first source-drain metal layer, and the second sub-portion is located in the second source-drain metal layer;

[0017] The first flat layer has at least one groove, which exposes at least a portion of the surface of the first sub-portion away from the substrate, and at least a portion of the second sub-portion is located in the groove and in contact with the first sub-portion; the orthographic projection of the second flat layer on the plane where the substrate is located includes the orthographic projections of the first sub-portion and the second sub-portion on the plane where the substrate is located.

[0018] In some exemplary embodiments, the first sub-portion includes a plurality of first connecting portions arranged at intervals, the first connecting portions including a top wall, a bottom wall and a side wall connected to each other; the top wall is farther away from the substrate than the bottom wall, and the side wall is located between the top wall and the bottom wall; the second sub-portion is in contact with the top wall, the bottom wall and the side wall of at least one of the first connecting portions.

[0019] In some exemplary embodiments, the binding area further includes at least one binding pin group and at least one first aging pin group; the binding pin group and the first aging pin group are arranged side by side along a first direction, and the first direction is parallel to the plane where the substrate is located.

[0020] In some exemplary embodiments, at least one of the plurality of sub-pixels includes a transistor, a first planar layer, a switching electrode, a second planar layer, and a light-emitting device, wherein the first planar layer is located on a side of the transistor away from the substrate and covers the transistor, the switching electrode is located on a side of the first planar layer away from the substrate; the light-emitting device is located on a side of the second planar layer away from the substrate;

[0021] The transistor comprises an active layer located on the substrate, a gate located on a side of the active layer away from the substrate, and a source and a drain located on a side of the gate away from the substrate, and one of the source and the drain is electrically connected to the switching electrode through a via hole provided in the first flat layer, and the light emitting device is electrically connected to the switching electrode through a via hole provided in the second flat layer;

[0022] The first sub-portion and the source or the drain are located in the same layer, and the second sub-portion and the transfer electrode are located in the same layer.

[0023] In some exemplary embodiments, a plurality of first power lines are further included, the plurality of first power lines are located in the display area and are electrically connected to the plurality of sub-pixels, and the plurality of first power lines are configured to provide a first voltage signal to the plurality of sub-pixels;

[0024] a first power bus located in the binding area and electrically connected to the plurality of first power lines;

[0025] A second power line, located in the peripheral area and partially surrounding the display area;

[0026] The multiple power pins include at least a first power pin and a second power pin, the first power pin is connected to the first power bus and is configured to transmit the first voltage signal to the first power bus, and the second power pin is connected to the second power line and is configured to transmit the second voltage signal to the second power line.

[0027] In some exemplary embodiments, the plurality of power test connection lines include a first power test connection line and a second power test connection line, the first power pin is connected to the first power test connection line, and the second power pin is connected to the second power test connection line.

[0028] On the other hand, an embodiment of the present disclosure provides an intermediate display substrate, comprising the display substrate described in any one of the above embodiments and a plurality of power test pins located on a side of the plurality of power pins away from the display area; the intermediate display substrate comprises a substrate area and a first cutting area located on one side of the substrate area, the first cutting area is located on a side of the binding area away from the display area, the display substrate is located in the substrate area, and the plurality of power test pins are located in the first cutting area;

[0029] The plurality of power supply test connection lines are located between the plurality of power supply pins and the plurality of power supply test pins and connect the plurality of power supply pins and the plurality of power supply test pins.

[0030] In some exemplary embodiments, the plurality of power test connection lines are connected to the plurality of power test pins in a one-to-one correspondence; the plurality of power test connection lines include a first power test connection line and a second power test connection line, and the plurality of power pins include a first power pin and a second power pin;

[0031] The multiple power test pins include a first power test pin and a second power test pin, the first power pin is connected to the first power test pin through the first power test connection line; the second power pin is connected to the second power test pin through the second power test connection line.

[0032] In some exemplary embodiments, at least one second aging pin group is further included, the second aging pin group is located in the first cutting area, the second aging pin group includes at least one second aging pin, the second aging pin and the power test pin are arranged side by side along a first direction, and the first direction is parallel to the plane where the substrate is located.

[0033] On the other hand, an embodiment of the present disclosure provides a display device, comprising the display substrate described in any one of the aforementioned embodiments.

[0034] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0036] Figure 1 is a schematic structural diagram of a display device according to an embodiment of the present disclosure;

[0037] Figure 2 is a schematic plan view of a display substrate according to an embodiment of the present disclosure;

[0038] Figure 3 A display motherboard according to an embodiment of the present disclosure includes a schematic diagram of the arrangement of multiple display substrates;

[0039] Figure 4A is a schematic plan view of an intermediate display substrate according to an embodiment of the present disclosure;

[0040] Figure 4B is a schematic plan view of a display substrate according to an embodiment of the present disclosure;

[0041] Figure 5 is a partial cross-sectional schematic diagram of a sub-pixel in a display area according to an embodiment of the present disclosure;

[0042] Figure 6 for Figure 4A A local enlarged schematic diagram of the mark A in the middle;

[0043] Figure 7 for Figure 6 A partial enlarged schematic diagram of an embodiment at the position marked B in FIG.

[0044] Figure 8 for Figure 6 A partial enlarged schematic diagram of another embodiment at the mark B in FIG.

[0045] Fig. 9 for Figure 6 A partial enlarged schematic diagram of another embodiment at the mark B in FIG.

[0046] Fig.10 for Figure 7 A cross-sectional schematic diagram of an embodiment at the position marked CC in FIG.

[0047] Fig.11 for Figure 7 A cross-sectional schematic diagram of another embodiment at the position marked CC in FIG.

[0048] Fig.12 for Figure 8 A schematic cross-sectional view of an embodiment at the position marked DD in FIG. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a plurality of different forms. A person of ordinary skill in the art can easily understand the fact that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0050] In the drawings, the size of one or more components, the thickness of a layer, or an area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0051] The ordinal numbers such as "first", "second", and "third" in the present disclosure are provided to avoid confusion of constituent elements, rather than to limit the quantity. The "plurality" in the present disclosure includes two and more than two.

[0052] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the constituent elements are described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0053] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in the present disclosure can be understood according to the circumstances.

[0054] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region where current mainly flows.

[0055] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.

[0056] In the present disclosure, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit electrical signals between connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0057] In the present disclosure, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, a state where the angle is greater than -5° and less than 5° may be included. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, a state where the angle is greater than 85° and less than 95° may be included.

[0058] In the present disclosure, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film" in some cases. Similarly, "insulating film" may be replaced with "insulating layer" in some cases.

[0059] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0060] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device according to an embodiment of the present disclosure. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array, the timing controller is respectively connected to the data driver, the scan driver and the light emitting driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting unit, the circuit unit may include at least a pixel driving circuit, the pixel driving circuit is respectively connected to the scan signal line, the light emitting signal line and the data signal line, the light emitting unit may include a light emitting device, and the light emitting device is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specification of the data driver to the data driver, may provide a clock signal suitable for the specification of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specification of the light emitting driver, an emission stop signal, etc. to the light emitting driver. The data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ... and Dn using grayscale values ​​and control signals received from the timing controller. For example, the data driver can sample grayscale values ​​using a clock signal, and apply data voltages corresponding to grayscale values ​​to data signal lines D1 to Dn in units of pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ... and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with conduction level pulses to scan signal lines S1 to Sm. For example, the scan driver can be constructed in the form of a shift register, and can sequentially transmit scan start signals provided in the form of conduction level pulses to the next level circuit under the control of the clock signal to generate scan signals, where m can be a natural number. The light-emitting driver can generate emission signals to be provided to light-emitting signal lines E1, E2, E3, ... and Eo by receiving clock signals, emission stop signals, etc. from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having a cut-off level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register, and may generate an emission signal in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal, and o may be a natural number. In an exemplary embodiment, a pixel array may be provided on a display substrate.

[0061] Figure 2 FIG. 1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure. Figure 2As shown, the display substrate may include a substrate, a display area 100 located on the substrate, and a peripheral area 300 located on the substrate and surrounding the display area 100. The peripheral area 300 may include a binding area 200 located on one side of the display area 100 and a frame area located on the other side of the display area 100. For example, the binding area 200 may be a lower frame of the display substrate, and the frame area may include an upper frame, a left frame, and a right frame of the display substrate. In some examples, the display area 100 may be a flat area, and the display area 100 may include a plurality of sub-pixels Pxij constituting a pixel array, and the plurality of sub-pixels Pxij are configured to display dynamic pictures or still images. In some examples, the display substrate may be a flexible substrate, so that the display substrate may be deformable, such as curling, bending, folding, or rolling up.

[0062] In some exemplary embodiments, Figure 2 As shown, the display area 100 may include at least a plurality of scan signal lines (S1 to Sm) and a plurality of data signal lines (D1 to Dn). The plurality of scan signal lines may extend along a first direction X, and the plurality of data signal lines may extend along a second direction Y. The first direction X and the second direction Y may intersect, and the plane formed by the first direction X and the second direction Y is parallel to the plane where the substrate is located. For example, the first direction X and the second direction Y may be perpendicular to each other. The positive projections of the plurality of scan signal lines and the plurality of data signal lines on the plane where the substrate is located intersect to form a plurality of sub-pixel regions, and a sub-pixel is arranged in each sub-pixel region. The plurality of data signal lines are electrically connected to the plurality of sub-pixels, and the plurality of data signal lines may be configured to provide data signals to the plurality of sub-pixels. For example, portions of the plurality of data signal lines may extend to the binding area 200. The plurality of scan signal lines are electrically connected to the plurality of sub-pixels, and the plurality of scan signal lines may be configured to provide gate control signals to the plurality of sub-pixels. In some examples, the gate control signal may include a scan signal and a light emitting control signal.

[0063] In some exemplary embodiments, the display area 100 itself may be symmetrical along a center line O extending in the second direction Y. For example, the binding area 200 may be symmetrical along the center line O. For example, the frame area may be symmetrical along the center line O. For example, the display substrate may be symmetrical along the center line O. The center line O may be a straight line that bisects the display area in the first direction X and extends along the second direction Y.

[0064] In some exemplary embodiments, the display area 100 includes a plurality of pixel units, and one pixel unit may include three sub-pixels, which are red sub-pixels, green sub-pixels, and blue sub-pixels. However, the embodiments of the present disclosure are not limited to this. In some examples, one pixel unit may include four sub-pixels, which are red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels.

[0065] In some exemplary embodiments, the shape of the sub-pixel may be a rectangle, a rhombus, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the three sub-pixels may be arranged horizontally, vertically, or in a triangular pattern. When a pixel unit includes four sub-pixels, the four sub-pixels may be arranged horizontally, vertically, or in a square pattern. However, the embodiments of the present disclosure are not limited thereto.

[0066] In some exemplary embodiments, the sub-pixel may include a circuit unit and a light-emitting unit, the circuit unit may include at least a pixel driving circuit, the pixel driving circuit is respectively connected to the scanning signal line, the light-emitting signal line and the data signal line, the light-emitting unit may include a light-emitting device, and the light-emitting device is connected to the pixel driving circuit of the circuit unit. The pixel driving circuit may include a plurality of transistors and at least one capacitor, for example, the pixel driving circuit may be a 3T1C structure, a 7T1C structure or a 5T1C structure, etc., the number before T represents the number of transistors in the pixel driving circuit, and the number before C represents the number of capacitors in the pixel driving circuit.

[0067] In some exemplary embodiments, the light emitting device may be any one of a light emitting diode, an organic light emitting diode, a quantum dot light emitting diode, a micro LED (including: mini-LED or micro-LED), etc. For example, the light emitting device may be an OLED, and the light emitting device may emit red light, green light, blue light, or white light, etc., when driven by its corresponding pixel driving circuit. In some examples, the light emitting device may include: an anode, a cathode, and an organic light emitting layer located between the anode and the cathode. The anode of the light emitting device may be electrically connected to the corresponding pixel driving circuit.

[0068] In some exemplary embodiments, the frame area may include a circuit area, a power line area, a crack dam area, and a cutting area that are sequentially arranged along the direction of the display area 100. The circuit area may be connected to the display area 100, and the circuit area may include at least a gate driving circuit (for example, including a plurality of cascaded shift registers), and the plurality of shift registers may be electrically connected to a plurality of scanning signal lines in the display area 100. The power line area is connected to the circuit area, and the power line area may include at least a low-level power line, and the low-level power line may extend in a direction parallel to the edge of the display area and may be connected to a cathode located in the display area 100. The crack dam area may be connected to the power line area, and the crack dam area may include at least a plurality of cracks arranged on the composite insulating layer. The cutting area may be connected to the crack dam area, and may include at least a cutting groove arranged on the composite insulating layer, and the cutting groove may be configured such that after all the film layers of the display substrate are prepared, the cutting arrangement may be cut along the cutting groove respectively.

[0069] In some exemplary embodiments, a first isolation dam and a second isolation dam may be provided in the binding area 200 and the border area. The first isolation dam and the second isolation dam may extend in a direction parallel to the edge of the display area and form an annular structure surrounding the display area 100. The edge of the display area is the edge of the display area close to the binding area and the border area.

[0070] Figure 3 FIG. 1 is a schematic diagram showing the arrangement of a display motherboard including a plurality of display substrates. Figure 3 As shown, the display motherboard may include a plurality of substrate regions 400 arranged in a periodic and regular manner and a cutting region 500 located outside the substrate region 400. The substrate region 400 includes at least a display substrate, and a first cutting path 501 and a second cutting path 502 may be provided in the cutting region 500. After all the film layers of the display motherboard are prepared, the cutting equipment may perform rough cutting and fine cutting along the first cutting path 501 and the second cutting path 502, respectively, and the fine cutting may also be referred to as module cutting.

[0071] In some possible exemplary embodiments, for a display motherboard, a cutting process may be first performed along the EAC (Even After Cell, cutting after evaporation) cutting line, that is, a rough cutting may be performed to cut the display motherboard into multiple intermediate display substrates (for example, an intermediate display substrate may include a substrate area, a first cutting area, and a second cutting area), and then, each intermediate display substrate may be subjected to a lighting test and an aging stage. After the test and aging stages are completed, the intermediate display substrate may be cut along the module (Module, MDL) cutting line, that is, a fine cutting may be performed, and then, a circuit board may be bound to the intermediate display substrate. In one example, the intermediate display substrate that has completed the circuit board binding may be edge cut to obtain a display substrate.

[0072] In some implementations, multiple tests are required during the preparation process of the display substrate, one of the important tests is the cell test (CT) light-on, which can also be called ET light-on test. ET light-on test is to input a test signal to the display substrate before the display substrate is bound to the circuit board, so that its sub-pixels show color, and check whether each sub-pixel is good through a defect detection device to confirm whether the display substrate has defects. Since the prepared light-emitting device has unstable interface (interface not stable) and other conditions, another important process for the display substrate is the aging process, which can also be called the aging stage. It is a necessary process before the display device is shipped. By lighting the light-emitting device with a certain current for a period of time, the interface instability can be aged out, the brightness attenuation of the light-emitting device can be reduced, and the life of the light-emitting device can be increased.

[0073] During the aging stage, the detection current will pass through the source-drain metal layer and the gate metal layer. Since the test current of the first power supply voltage (VDD) and the second power supply voltage (VSS) of the medium and large-sized display substrate is relatively large, when the large current flows through the gate metal layer with a large resistance, since the material of the gate metal layer has a high resistance, the material of the gate metal layer is usually molybdenum, and a high heat is generated at the gate metal layer of the display substrate, thereby causing burning loss to the display substrate.

[0074] The present disclosure provides a display substrate, comprising:

[0075] A substrate, comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area comprises a binding area located at one side of the display area;

[0076] A plurality of sub-pixels are located in the display area;

[0077] a plurality of power pins, located in the binding area and electrically connected to the plurality of sub-pixels, the plurality of power pins being configured to transmit power signals to the plurality of sub-pixels;

[0078] A plurality of power test connection lines are located on a side of the plurality of power pins away from the display area and connected to the plurality of power pins. The material of at least one of the plurality of power test connection lines includes at least one of titanium and aluminum.

[0079] In the embodiment of the present disclosure, by setting the material of at least one of the multiple power test connection lines to include at least one of titanium and aluminum, since titanium and aluminum have lower resistance, it is possible to avoid generating more heat during the test of the power pin and avoid burning the display substrate.

[0080] Figure 4A FIG. 1 is a schematic plan view of an intermediate display substrate according to an embodiment of the present disclosure. Figure 4A As shown, only one substrate area 400 is illustrated. The substrate area 400 may include a display substrate. The display substrate may include a substrate. The substrate includes a display area 100 and a peripheral area 300 surrounding the display area 100. The peripheral area 300 may include a binding area 200 located on one side of the display area 100. The cutting area 500 may be located outside the substrate area 400. For example, the cutting area 500 may include a first cutting area 50a located on the side of the binding area 200 away from the display area 100. The embodiment of the present disclosure omits illustrating the cutting areas on the other sides of the substrate area. The intermediate display substrate is a structure before cutting during the preparation process of the display substrate. After completing the lighting detection and aging procedures, the first cutting area 50a of the intermediate display substrate may be cut off along the cutting line L1 to obtain the display substrate, as shown in FIG. Figure 4B shown.

[0081] The display substrate can be a flexible substrate or a rigid substrate. Taking the display substrate as a flexible substrate as an example, along the direction away from the display area 100, the binding area 200 may include a sub-frame area 201 and a binding pin area 202. The binding pin area 202 may be located on the side of the sub-frame area 201 away from the display area 100. The sub-frame area 201 may include a first fan-out area 201a, a bending area 201b, a second fan-out area 201c, a first circuit area 201d, a third fan-out area 201e and a driver chip area 201f arranged in sequence. The first fan-out area 201a can be connected to the display area 100, and may at least include a first power bus 70, a portion of the second power line and a plurality of data signal lines (D1 to Dn), and the plurality of data signal lines (D1 to Dn) are configured to extend from the data signal lines of the display area in a fan-out routing manner. The first power bus 70 of the first fan-out area 201a can be configured to connect the first power line 71 of the display area 100, the first power line 71 is a high-level power line or a positive voltage power line, and the second power line is a low-level power line or a negative voltage power line, and the second power line is located in the peripheral area 300 and partially surrounds the display area 100. The bending area 201b can be connected to the second fan-out area 201c, and may include a composite insulating layer provided with a groove, and the groove can be configured to bend the binding area 200 to the back of the display area 100. The second fan-out area 201c may include a plurality of fan-out traces. The first circuit area 201d may include at least an electrostatic circuit 16, and the electrostatic circuit 16 may be configured to prevent electrostatic damage to the display substrate by eliminating static electricity. The third fan-out area 201e may include a plurality of fan-out traces. The driver chip area 201f may be provided with a driver chip 17 (Integrated Circuit, IC), which may be electrically connected to the data signal lines (D1 to Dn) of the display area 100 through fan-out wiring, and the driver chip 17 may be configured to generate a driving signal required for driving the sub-pixel Pxij, and provide different driving signals to multiple sub-pixels Pxij in the display area 100, for example, the driving signal may be a data signal transmitted through the data signal lines (D1 to Dn) or a clock signal transmitted by the clock signal line of GOA. The binding pin area 202 may be provided with a plurality of pins, which may include a plurality of access pins, a plurality of first aging pins, and a plurality of power pins.

[0082] In some exemplary embodiments, the gate driving circuit may include a plurality of cascaded shift registers GOA0, GOA1, ... GOAn, and the plurality of shift registers may be electrically connected to a plurality of scan signal lines (S1 to Sm) in the display area 100. A plurality of gate driving signal lines GSTV, GCK, GCB are electrically connected to the gate driving circuit, and each shift register is electrically connected to one scan signal line.

[0083] Figure 5 FIG. 4 is a partial cross-sectional schematic diagram of a sub-pixel in a display area according to an embodiment of the present disclosure. Figure 5 for Figure 4A The cross-sectional view at the position marked PP is shown in the figure. Figure 5 The structure of a sub-pixel in the display area is taken as an example for illustration. Figure 5 In the figure, a pixel driving circuit of each sub-pixel includes a transistor 21 and a capacitor 22 as an example for illustration. The transistor 21 may be a low temperature polysilicon thin film transistor.

[0084] like Figure 5 As shown, in a direction perpendicular to the display substrate, the display area of ​​the display substrate may include at least a circuit structure layer 12, a light emitting structure layer 13, and a packaging structure layer 14 sequentially arranged on the substrate 11. The circuit structure layer 12 may include at least a pixel driving circuit for a plurality of sub-pixels, and the pixel driving circuit for each sub-pixel may include a plurality of transistors and at least one capacitor. For example, the transistor may be a thin film transistor. The light emitting structure layer 13 may include at least a light emitting device for a plurality of sub-pixels. In other examples, a touch structure layer 15 may be provided on the side of the packaging structure layer 14 away from the substrate 11 to integrate a touch function.

[0085] In some exemplary embodiments, the circuit structure layer 12 may include a semiconductor layer, a first insulating layer 121, a first gate metal layer, a second insulating layer 122, a second gate metal layer, a third insulating layer 123 (interlayer insulating layer), a first source-drain metal layer 51, a first planar layer 61, a second source-drain metal layer 52, and a second planar layer 62, which are stacked in sequence. The semiconductor layer in the display area may include: an active layer 210 of a transistor 21 of a pixel driving circuit. The active layer 210 of the transistor 21 may include: a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer in the display area may include: a gate 213 of the transistor 21 and a first electrode 221 of the capacitor 22. The orthographic projection of the gate 213 of the transistor 21 on the plane where the substrate 11 is located may cover the orthographic projection of the channel region 2100 of the active layer 210 on the plane where the substrate 11 is located. The second gate metal layer may include a second electrode 222 of the capacitor 22. The orthographic projections of the second plate 222 and the first plate 221 of the capacitor 22 on the plane where the substrate 11 is located may at least partially overlap, and for example, the two may overlap. The first source-drain metal layer 51 of the display area may include a source 211 and a drain 212 of the transistor 21. The source 211 of the transistor 21 may be electrically connected to the first area 2101 of the active layer 210, and the drain 212 may be electrically connected to the second area 2102 of the first active layer 210. The second source-drain metal layer 52 of the display area may include a switching electrode 214, and one of the source 211 and the drain 212 is electrically connected to the switching electrode 214 through a via provided in the first flat layer 61, and for example, the drain 212 is electrically connected to the switching electrode 214 through a via provided in the first flat layer 61. The switching electrode 214 is configured to be electrically connected to the light-emitting device to achieve electrical connection between the light-emitting device and the pixel driving circuit.

[0086] The light emitting structure layer 13 may include a pixel definition layer 134 and a plurality of light emitting devices. Each light emitting device may include: a stacked first electrode 131, an organic light emitting layer 132, and a second electrode 133. The first electrode 131 of the light emitting device may be electrically connected to the transfer electrode 214 through a via hole provided in the second flat layer 62. The pixel definition layer 134 is provided on a side of the first electrode 131 away from the substrate 11, and the pixel definition layer 134 may be provided with a plurality of pixel openings, and a pixel opening may expose at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light emitting layer 132 may be provided in a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be provided on a side of the organic light emitting layer 132 away from the substrate 11, and connected to the organic light emitting layer 132. The organic light emitting layer 132 may emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133.

[0087] In some exemplary embodiments, the organic light-emitting layer 132 of the light-emitting device may include at least one light-emitting layer (EML), and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting characteristics of the organic material can be used to emit light according to the required grayscale.

[0088] In some exemplary embodiments, the light-emitting layers of light-emitting devices of different colors may be different. For example, a red light-emitting device includes a red light-emitting layer, a green light-emitting device includes a green light-emitting layer, and a blue light-emitting device includes a blue light-emitting layer. In order to reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may use a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may use a common layer. In some examples, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer can be made by a single process (a single evaporation process or a single inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment. For example, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels may be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (Fine Metal Mask, FMM) or an open mask (Open Mask), or by inkjet technology.

[0089] In some exemplary embodiments, the encapsulation structure layer 14 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked. The first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, silicon oxynitride, etc. The inorganic material has high density and can prevent the intrusion of water, oxygen, etc., so as to ensure that external water vapor cannot enter the light-emitting device. The second encapsulation layer 142 may be arranged between the first encapsulation layer 141 and the third encapsulation layer 143. The second encapsulation layer 142 may be made of organic materials, for example, a polymer material containing a desiccant or a polymer material that can block water vapor, or a polymer resin, etc. to flatten the surface of the display substrate, and can relieve the stress of the first encapsulation layer 141 and the third encapsulation layer 143, and may also include a desiccant and other water-absorbing materials to absorb water, oxygen, etc. that invade the interior. However, the embodiments of the present disclosure are not limited to this. In one example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0090] Figure 6 for Figure 4A A local enlarged schematic diagram of the area marked A. Figure 4A and Figure 6 As shown, the intermediate display substrate may include at least one substrate region 400. The substrate region 400 may include a display substrate, and the display substrate may include a display region 100 and a binding region 200 located on one side of the display region 100. The cutting region 500 may be located outside the substrate region 400. For example, the cutting region 500 may include a first cutting region 50a located on the side of the binding region 200 away from the display region 100. The embodiment of the present disclosure omits the cutting regions on the other sides of the substrate region, and only illustrates the first cutting region 50a. The intermediate display substrate is a structure before cutting in the process of preparing the display substrate. After completing the lighting detection and aging procedures, the first cutting region 50a of the intermediate display substrate may be cut off along the cutting line L1 to obtain the display substrate.

[0091] In some examples, for a display motherboard, it can be cut along the EAC cutting line to cut the display motherboard into multiple intermediate display substrates. For example, an intermediate display substrate may include a substrate area and a first cutting area. Then, each intermediate display substrate is subjected to a lighting test and an aging procedure. After the test and aging procedure are completed, it can be cut along the module cutting line of the intermediate display substrate, and then the circuit board can be bound to the cut display substrate. Figure 6 The cutting line L1 in FIG. 5 is the aforementioned module cutting line. After the lighting test and the aging procedure are completed, the first cutting area 50 a can be cut off along the cutting line L1 .

[0092] In some exemplary embodiments, Figure 6As shown, the first cutting area 50a may be provided with a plurality of test pin groups 10. Each test pin group may include a plurality of test pins arranged along the first direction X. The test pins may be configured as pins for signal transmission during the lighting test phase. The plurality of test pins may include at least a plurality of power test pins, and the plurality of power test pins may include at least a first power test pin 101 and a second power test pin 102.

[0093] The first cutting area 50a may also be provided with at least one second aging pin group, and the second aging pin group may include at least one second aging pin 20. For example, the first cutting area 50a may also be provided with four second aging pin groups, and the four second aging pin groups are respectively a second aging pin group 20a, a second aging pin group 20b, a second aging pin group 20c, and a second aging pin group 20d. The second aging pin group 20a, the second aging pin group 20b, the second aging pin group 20c, and the second aging pin group 20d may be arranged in sequence along the first direction X. For example, the second aging pin group 20a may include two second aging pins 20, the second aging pin group 20b and the second aging pin group 20c may each include one second aging pin 20, and the second aging pin group 20d may include four second aging pins 20, however, the present disclosure is not limited thereto.

[0094] In some exemplary embodiments, the first power supply test pin 101 , the second power supply test pin 102 , and a plurality of second aging pin groups may be arranged side by side along the first direction X, and the pin layout may be optimized.

[0095] In some exemplary embodiments, the first cutting area 50a may further include a plurality of power test connection lines 40, and the plurality of power test connection lines 40 are configured to be connected to a plurality of power test pins, and the material of at least one of the plurality of power test connection lines 40 includes at least one of titanium and aluminum, which can reduce resistance, reduce the heat generated by the power test connection lines during the test process, and prevent the display substrate from being burned. For example, the plurality of power test connection lines may include a titanium-aluminum-titanium three-layer structure.

[0096] In some exemplary embodiments, the plurality of power test connection lines 40 are connected to the plurality of power test pins in a one-to-one correspondence. The plurality of power test connection lines 40 may include a first power test connection line 41 and a second power test connection line 42, wherein the first power test connection line 41 is connected to the first power test pin 101, and the second power test connection line 42 is connected to the second power test pin 102.

[0097] In some exemplary embodiments, along the direction away from the display area 100, the binding area 200 may include a sub-frame area 201 and a binding pin area 202. The binding pin area 202 may be located on a side of the sub-frame area 201 away from the display area 100. The binding pin area 202 may be provided with a plurality of binding pin groups 30, a plurality of first aging pin groups, and a plurality of power pins, and the plurality of power pins may include a plurality of first power pins 111 and a plurality of second power pins 112. The plurality of binding pin groups 30 and the plurality of first aging pin groups may be arranged side by side along the first direction X. The first power pin 111 is connected to the first power bus 70 and is configured to transmit a first voltage signal to the first power bus 70, and the second power pin 112 is connected to the second power line 72 and is configured to transmit a second voltage signal to the second power line 72. Multiple power pins are arranged in one-to-one correspondence with multiple power test connection lines 40 , the first power pin 111 is connected to the first power test pin 101 through the first power test connection line 41 , and the second power pin 112 is connected to the second power test pin 102 through the second power test connection line 42 .

[0098] The binding pin group 30 may include a plurality of access pins 31. Taking one binding pin group 30 as an example, the binding pin group 30 may include twenty-eight access pins 31. Each binding pin group may be configured to be bound and connected to at least one corresponding circuit board, for example, a flexible printed circuit (FPC). The binding pin area 202 may include four first aging pin groups, and the four first aging pin groups are respectively the first aging pin group 20e, the first aging pin group 20f, the first aging pin group 20g and the first aging pin group 20h. The first aging pin group 20e may include two first aging pins 20-1, the first aging pin group 20f and the first aging pin group 20g may respectively include one first aging pin 20-1, and the first aging pin group 20h may include four first aging pins 20-1. The first aging pin group and the second aging pin group may be configured to be used in the aging stage or the test stage. After the aging stage and the test stage are ended and the binding pin group 30 is bound and connected to the circuit board, the first aging pin group may be retained in the binding pin area 202 as an invalid pin. The first aging pin group 20e, the first aging pin group 20f, the first aging pin group 20g and the first aging pin group 20h are arranged in sequence along the first direction X. In the embodiment of the present disclosure, the pins in the first aging pin group, the second aging pin group and the binding pin group can extend substantially along the second direction Y and be arranged along the first direction X.

[0099] In some exemplary embodiments, the plurality of first aging pins 20-1 in the first aging pin group, the plurality of access pins 31 in the binding pin group 30, and the plurality of second aging pins 20 in the second aging pin group can be arranged in the same layer, for example, they can all be located in the first source-drain metal layer. In other examples, the plurality of first aging pins 20-1, the plurality of second aging pins 20, and the plurality of access pins 31 can be a double-layer stacked structure, for example, a stacked structure of a first gate metal layer and a first source-drain metal layer, or a stacked structure of a second gate metal layer and a first source-drain metal layer, or a stacked structure of a second gate metal layer and a second source-drain metal layer. In one example, the plurality of access pins 31 can be connected to a touch line (not shown) for transmitting a touch signal.

[0100] In some exemplary embodiments, the first power pin 111 and the second power pin 112 may both be located in the source-drain metal layer. For example, the first power pin 111 and the second power pin 112 may both be a double-layer stacked structure, for example, the first power pin 111 and the second power pin 112 may both be a double-layer stacked structure of the first source-drain metal layer and the second source-drain metal layer. Since the material of the source-drain metal layer has a relatively small resistance, for example, the source-drain metal layer adopts a titanium-aluminum-titanium stacked structure, and since the test current of the first power supply voltage (VDD) and the second power supply voltage (VSS) of the display substrate of medium and large sizes is relatively large, when a large current flows through the source-drain metal layer with a relatively small resistance, due to the low resistance, the heat generated at the first power pin and the second power pin can be reduced, and the risk of burning the display substrate can be avoided.

[0101] In some exemplary embodiments, within a plane perpendicular to the display substrate, the binding pin area 202 may include a first insulating layer 121, a second insulating layer 122, a third insulating layer 123, a first source-drain metal layer (SD1) 51, a first planarization layer (Planarization layer, PLN1) layer 61, a second source-drain metal layer (SD2) 52, and a second planarization layer (Planarization layer, PLN2) layer 62, which are sequentially stacked on the substrate 11.

[0102] The substrate 11 may be a flexible substrate, and the substrate may include a first flexible material layer, a first inorganic material layer, and a second flexible material layer stacked on a glass substrate. The first and second flexible material layers may be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the first inorganic material layer may be made of silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the entire display substrate, and the first inorganic material layer may also be referred to as a first barrier layer.

[0103] In an exemplary embodiment, the materials of the first planar layer 61 and the second planar layer 62 may include any one or more of epoxy resin, phenolic resin, urea-formaldehyde resin, melamine-formaldehyde resin, furan resin, silicone resin, polyester resin, polyamide resin, acrylic resin, polyurethane, vinyl resin, hydrocarbon resin, polyether resin, etc., and may be a single layer, multiple layers, or a composite layer. The materials of the first insulating layer 121, the second insulating layer 122, and the third insulating layer 123 may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc., or aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), etc., and may be a single layer, multiple layers, or a composite layer.

[0104] In an exemplary embodiment, the display substrate may further include a protective layer (over coating, referred to as OC). The protective layer is farther away from the substrate 11 than the second flat layer 62. The orthographic projection of the protective layer on the plane where the substrate 11 is located includes the orthographic projection of the plurality of binding pin groups 30 on the plane where the substrate 11 is located. The protective layer can protect the plurality of binding pin groups 30 and improve the ability of the display substrate to resist water and oxygen.

[0105] Figure 7 for Figure 6 A partial enlarged schematic diagram of an embodiment of the position marked B in FIG. Figure 7 As shown, the first power supply test connection line 41 may include a first sub-portion 411 and a second sub-portion 412 that are stacked. The first sub-portion 411 is closer to the substrate 11 than the second sub-portion 412. For example, the first sub-portion 411 may be located in the first source-drain metal layer (SD1) 51, and the second sub-portion 412 may be located in the second source-drain metal layer (SD2) 52. The orthographic projection of the second sub-portion 412 on the plane where the substrate 11 is located at least partially overlaps with the orthographic projection of the first sub-portion 411 on the plane where the substrate 11 is located. For example, the orthographic projection of the second sub-portion 412 on the plane where the substrate 11 is located includes the orthographic projection of the first sub-portion 411 on the plane where the substrate 11 is located. Figure 7 In the figure, the second sub-portion 412 is not filled with color to facilitate identification of the first sub-portion 411.

[0106] The first sub-section 411 may include a plurality of first connection portions 411a disposed at intervals, and at least a portion of the surface of the plurality of first connection portions 411a away from the substrate 11 is in contact with the second sub-section 412. In the embodiment of the present disclosure, by configuring the first sub-section to include a plurality of first connection portions disposed at intervals, the contact interface between the first sub-section and the second sub-section is divided into a plurality of contact interfaces, so that water, oxygen, etc. can be prevented from invading the binding area and the display area along the contact interface between the first sub-section and the second sub-section through the cutting line, and the reliability of the display substrate can be improved.

[0107] like Figure 7As shown, the first connection portion 411a may be in the shape of a straight line extending along the first direction X, and a plurality of first connection portions 411a may be arranged at intervals along the second direction Y. Alternatively, the first connection portion 411a may be in the shape of a curve extending along the first direction X, and a plurality of first connection portions 411a may be arranged at intervals along the second direction Y. Alternatively, the first connection portion 411a may be in the shape of a straight line extending along the second direction Y, and a plurality of first connection portions 411a may be arranged at intervals along the first direction X. Alternatively, the first connection portion 411a may be in the shape of a curve extending along the second direction Y, and a plurality of first connection portions 411a may be arranged at intervals along the first direction X. Alternatively, the first connection portion 411a may be in the shape of a straight line extending along a direction different from the first direction X and the second direction Y, and for example, the first connection portion 411a may be in the shape of a straight line extending along a direction forming an angle of 45 degrees with the first direction X. Alternatively, the first connection portion 411a may be in the shape of a curve extending along a direction different from the first direction X and the second direction Y.

[0108] In an exemplary embodiment, the plurality of first connection portions 411 a may be arranged in an array, for example, in a rectangular array or a circular array.

[0109] In an exemplary embodiment, the orthographic projection of the first connection portion 411 a on the plane where the substrate is located may be a rectangle, a square, a rhombus, a hexagon, or the like.

[0110] Figure 8 for Figure 6 A partial enlarged schematic diagram of another embodiment at the mark B in FIG. Figure 8 As shown, at least one first connection portion 411a may include at least one protrusion 411b or at least one recess 411c. Figure 8 As shown, a plurality of protrusions 411b and a plurality of recesses 411c may be arranged alternately in sequence along the first direction X. For example, one protrusion 411b and one recess 411c are arranged alternately in sequence. Alternatively, two protrusions 411b and two recesses 411c are arranged alternately in sequence. Alternatively, one protrusion 411b and two recesses 411c are arranged alternately in sequence, etc. Figure 8 In the figure, the second sub-portion 412 is not filled with color to facilitate identification of the first connecting portion 411a.

[0111] The protruding portion 411b protrudes in a direction away from the substrate 11, and the recessed portion 411c is recessed in a direction close to the substrate 11. In the embodiment of the present disclosure, by providing the protruding portion or the recessed portion, the irregularity of the contact interface between the first sub-section and the second sub-section can be improved, and water, oxygen, etc. can be prevented from invading the binding area and the display area along the contact interface between the first sub-section and the second sub-section through the cutting line, thereby improving the reliability of the display substrate.

[0112] Fig. 9 for Figure 6 A partial enlarged schematic diagram of another embodiment at the mark B in FIG. Fig. 9 As shown, the second sub-section 412 may include a plurality of second connecting portions 412a disposed at intervals, and at least a portion of the surface of the plurality of second connecting portions 412a close to the substrate 11 is in contact with the first connecting portion 411a of the first sub-section 411. Fig. 9 In the figure, the second sub-portion 412 is not filled with color to facilitate identification of the first sub-portion 411. The structure of the second connecting portion 412a can refer to the above description of the first connecting portion 411a, which will not be repeated here.

[0113] Fig.10 for Figure 7 A cross-sectional view of an embodiment at the position marked CC in FIG. Fig.10 As shown, in a plane perpendicular to the display substrate, in the embodiment of the present disclosure, the direction of the plane perpendicular to the substrate 11 is marked as a third direction Z, and the binding pin area 202 may include a first insulating layer 121, a second insulating layer 122, a third insulating layer 123, a first source-drain metal layer 51, a first planarizing layer 61, a second source-drain metal layer 52 and a second planarizing layer 62 arranged on the substrate 11.

[0114] like Fig.10 As shown, the first flat layer 61 has at least one groove K, the groove K exposes part of the first sub-portion 411, and at least part of the second sub-portion 412 is located in the groove K and in contact with the first sub-portion 411. For example, the orthographic projection of the groove K on the plane where the substrate 11 is located includes the orthographic projection of the first sub-portion 411 on the plane where the substrate 11 is located. The groove K includes a groove bottom K1 and a groove wall K2 connected to each other, and the groove bottom K1 is closer to the substrate 11 than the groove wall K2. Part of the first flat layer 61 constitutes the groove wall K2, and part of the first flat layer 61 and part of the first sub-portion 411 together constitute the groove bottom K1. In the embodiment of the present disclosure, by using the provided groove, the contact interface between the first sub-portion and the second sub-portion can be protected, the ability of the first power supply test connection line and the second power supply test connection line to resist water and oxygen intrusion can be improved, and the reliability of the display substrate can be improved.

[0115] like Fig.10 As shown, the orthographic projection of the second planar layer 62 on the plane where the substrate 11 is located includes the orthographic projections of the first planar layer 61, the first source-drain metal layer 51, and the second source-drain metal layer 52 on the plane where the substrate 11 is located. In the embodiment of the present disclosure, the first planar layer and the second planar layer can jointly enhance the ability of the first power supply test connection line and the second power supply test connection line to block water and oxygen.

[0116] Fig.11 for Figure 7A cross-sectional view of another embodiment at the position marked CC in FIG. Fig.11 As shown, the first flat layer 61 has at least one groove K, the groove K exposes part of the first sub-section 411, and at least part of the second sub-section 412 is located in the groove K and contacts the first sub-section 411. The groove K is a through hole extending along the third direction Z. In the embodiment of the present disclosure, the contact interface between the first sub-section and the second sub-section can be protected by the provided groove, the ability of the first power supply test connection line and the second power supply test connection line to resist water and oxygen intrusion can be improved, and the reliability of the display substrate can be improved.

[0117] In an exemplary embodiment, if Fig.11 As shown, the first sub-portion 411 may include a plurality of first connecting portions 411a arranged at intervals, and the first connecting portion 411a may include a top wall 411d, a bottom wall 411e and a side wall 411f connected to each other. The top wall 411d is farther away from the substrate 11 than the bottom wall 411e, and the side wall 411f is located between the top wall 411d and the bottom wall 411e. The second sub-portion 412 is in contact with the top wall 411d, the bottom wall 411e and the side wall 411f, which can increase the contact area between the first sub-portion 411 and the second sub-portion 412, and improve the reliability of the contact between the first sub-portion 411 and the second sub-portion 412.

[0118] In an exemplary embodiment, the orthographic projection of the groove K on the plane where the substrate is located can be a square, a rectangle, a circle, a hexagon, etc.

[0119] Fig.12 for Figure 8 A cross-sectional view of an embodiment at the position marked DD in FIG. Fig.12 As shown, at least one first connection portion 411a may include at least one protrusion 411b and at least one recess 411c. Fig.12 As shown, the plurality of protrusions 411 b and the plurality of recesses 411 c may be arranged alternately in sequence along the first direction X. As shown in FIG.

[0120] For example, the binding pin area 202 can have multiple avoidance holes K11, the first insulating layer 121 and the second insulating layer 122 located within the avoidance holes K11 are etched away, the recessed portion 411c is arranged one-to-one with the avoidance holes K11, and the recessed portion 411c is located within the avoidance holes K11, and the protruding portion 411b and the avoidance holes K11 do not overlap in their orthographic projection on the plane where the substrate 11 is located.

[0121] In an exemplary embodiment, the display substrate may further include at least one circuit board, and the circuit board is configured to be bound and connected to at least one binding pin group of the display substrate. For example, the circuit board may be a flexible printed circuit (FPC).

[0122] The present disclosure also provides a display device, including the display substrate described in any of the above embodiments. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame or a navigator.

[0123] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted for facilitating understanding of the present invention and are not intended to limit the present invention. It should be noted that the above embodiments or embodiments are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the contents specifically shown and described herein. Various modifications, substitutions or omissions may be made to the forms and details of implementation without departing from the scope of the present disclosure.

Claims

1. A display substrate, characterized in that: include: A substrate, comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area comprises a binding area located at one side of the display area; A plurality of sub-pixels are located in the display area; a plurality of power pins, located in the binding area and electrically connected to the plurality of sub-pixels, the plurality of power pins being configured to transmit power signals to the plurality of sub-pixels; A plurality of power test connection lines are located on a side of the plurality of power pins away from the display area and connected to the plurality of power pins. The material of at least one of the plurality of power test connection lines includes at least one of titanium and aluminum.

2. The display substrate according to claim 1, wherein: The plurality of power supply test connection lines are connected to the plurality of power supply pins in a one-to-one correspondence.

3. The display substrate according to claim 1, wherein: The at least one power supply test connection line includes a first sub-portion and a second sub-portion which are stacked, wherein the first sub-portion and the second sub-portion are located in different layers, and the first sub-portion is closer to the substrate than the second sub-portion.

4. The display substrate according to claim 3, wherein: The orthographic projection of the second sub-portion on the plane where the substrate is located includes the orthographic projection of the first sub-portion on the plane where the substrate is located, and the orthographic projection area of ​​the second sub-portion on the plane where the substrate is located is larger than the orthographic projection area of ​​the first sub-portion on the plane where the substrate is located.

5. The display substrate according to claim 3, wherein: The first sub-section includes a plurality of first connection portions arranged at intervals, and at least a portion of the surface of the plurality of first connection portions away from the substrate is in contact with the second sub-section; or, the second sub-section includes a plurality of second connection portions arranged at intervals, and at least a portion of the surface of the plurality of second connection portions close to the substrate is in contact with the first sub-section; or, the first sub-section includes a plurality of first connection portions arranged at intervals, and the second sub-section includes a plurality of second connection portions arranged at intervals, and at least a portion of the surface of the first connection portions away from the substrate is in contact with at least a portion of the surface of the second connection portions close to the substrate.

6. The display substrate according to claim 5, wherein: At least part of at least one of the plurality of first connection portions has a straight line projection on the plane where the substrate is located; or, at least part of at least one of the plurality of first connection portions has a curved line projection on the plane where the substrate is located.

7. The display substrate according to claim 5, wherein: At least one of the plurality of first connection portions includes at least one of a protruding portion and a recessed portion; the protruding portion protrudes in a direction away from the substrate, and the recessed portion is recessed in a direction approaching the substrate.

8. The display substrate according to claim 7, wherein: The at least one first connection portion includes a plurality of protrusions and a plurality of recesses; the plurality of protrusions and the plurality of recesses are alternately arranged in sequence.

9. The display substrate according to any one of claims 3 to 8, characterized in that: In a direction perpendicular to the plane where the substrate is located, the binding area includes a first source-drain metal layer, a first planar layer, a second source-drain metal layer and a second planar layer stacked in sequence, the first sub-portion is located in the first source-drain metal layer, and the second sub-portion is located in the second source-drain metal layer; The first flat layer has at least one groove, which exposes at least a portion of the surface of the first sub-portion away from the substrate, and at least a portion of the second sub-portion is located in the groove and in contact with the first sub-portion; the orthographic projection of the second flat layer on the plane where the substrate is located includes the orthographic projections of the first sub-portion and the second sub-portion on the plane where the substrate is located.

10. The display substrate according to claim 9, wherein: The first sub-section includes a plurality of first connecting sections arranged at intervals, and the first connecting section includes a top wall, a bottom wall and a side wall connected to each other; the top wall is farther away from the substrate than the bottom wall, and the side wall is located between the top wall and the bottom wall; the second sub-section is in contact with the top wall, the bottom wall and the side wall of at least one of the first connecting sections.

11. The display substrate according to any one of claims 1 to 8, characterized in that: The binding area further includes at least one binding pin group and at least one first aging pin group; the binding pin group and the first aging pin group are arranged side by side along a first direction, and the first direction is parallel to the plane where the substrate is located.

12. The display substrate according to any one of claims 3 to 8, characterized in that: At least one of the plurality of sub-pixels comprises a transistor, a first planar layer, a switching electrode, a second planar layer and a light-emitting device, wherein the first planar layer is located on a side of the transistor away from the substrate and covers the transistor, the switching electrode is located on a side of the first planar layer away from the substrate; the light-emitting device is located on a side of the second planar layer away from the substrate; The transistor comprises an active layer located on the substrate, a gate located on a side of the active layer away from the substrate, and a source and a drain located on a side of the gate away from the substrate, and one of the source and the drain is electrically connected to the switching electrode through a via hole provided in the first flat layer, and the light emitting device is electrically connected to the switching electrode through a via hole provided in the second flat layer; The first sub-portion and the source or the drain are located in the same layer, and the second sub-portion and the transfer electrode are located in the same layer.

13. The display substrate according to any one of claims 1 to 8, characterized in that: Also comprising a plurality of first power lines, the plurality of first power lines are located in the display area and are electrically connected to the plurality of sub-pixels, the plurality of first power lines are configured to provide a first voltage signal to the plurality of sub-pixels; a first power bus located in the binding area and electrically connected to the plurality of first power lines; A second power line, located in the peripheral area and partially surrounding the display area; The multiple power pins include at least a first power pin and a second power pin, the first power pin is connected to the first power bus and is configured to transmit the first voltage signal to the first power bus, and the second power pin is connected to the second power line and is configured to transmit the second voltage signal to the second power line.

14. The display substrate according to claim 13, wherein: The plurality of power test connection lines include a first power test connection line and a second power test connection line, the first power pin is connected to the first power test connection line, and the second power pin is connected to the second power test connection line.

15. An intermediate display substrate, characterized in that: The display substrate comprises a display substrate as claimed in any one of claims 1 to 14 and a plurality of power test pins located on a side of the plurality of power pins away from the display area; the intermediate display substrate comprises a substrate area and a first cutting area located on one side of the substrate area, the first cutting area is located on a side of the binding area away from the display area, the display substrate is located in the substrate area, and the plurality of power test pins are located in the first cutting area; The plurality of power supply test connection lines are located between the plurality of power supply pins and the plurality of power supply test pins and connect the plurality of power supply pins and the plurality of power supply test pins.

16. The intermediate display substrate according to claim 15, characterized in that: The plurality of power test connection lines are connected to the plurality of power test pins in a one-to-one correspondence; the plurality of power test connection lines include a first power test connection line and a second power test connection line, and the plurality of power pins include a first power pin and a second power pin; The multiple power test pins include a first power test pin and a second power test pin, the first power pin is connected to the first power test pin through the first power test connection line; the second power pin is connected to the second power test pin through the second power test connection line.

17. The intermediate display substrate according to claim 15, characterized in that: It also includes at least one second aging pin group, which is located in the first cutting area. The second aging pin group includes at least one second aging pin, and the second aging pin and the power test pin are arranged side by side along a first direction, and the first direction is parallel to the plane where the substrate is located.

18. A display device, characterized in that: Comprising the display substrate according to any one of claims 1 to 14.

Images