Display panel and display device

Abstract

The invention discloses a display panel and a display device. A pixel circuit of the display panel comprises a driving transistor and a storage capacitor which are connected with each other, a shading layer in the display panel comprises a driving shading part corresponding to the driving transistor, a first active layer comprises an active part of the driving transistor, and a first gate layer comprises a gate of the driving transistor and a polar plate of the storage capacitor. The second active layer comprises another polar plate of the storage capacitor, the driving shading parts in the two adjacent sub-pixels in the first direction are connected, and the driving shading parts in the two adjacent sub-pixels in the second direction are electrically connected through an electric connecting wire; by arranging the electric connecting wire extending along the second direction, two adjacent driving shading parts in the second direction are electrically connected, namely, the driving shading parts in different sub-pixels are electrically connected with each other in the first direction and the second direction, so that the impedance of the driving shading parts is reduced, the potential difference of different areas of the shading layer is improved, and the display effect is improved. And the display effect of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) display technology is a new type of display technology. It has gradually attracted people's attention with its unique advantages such as low power consumption, high saturation, fast response time and wide viewing angle, and occupies a certain position in the field of panel display technology.

[0003] In the current display devices using LTPO (Low Temperature Polysilicon Oxide, LTPO) technology, the bottom gates of some transistors are prepared using a light-shielding layer. However, due to the large impedance of the light-shielding layer, when the light-shielding layer transmits the corresponding control signal, there is a potential difference between the middle area and the edge area of ​​the light-shielding layer. That is, the display panel has control signals with different potentials in different areas, resulting in abnormal display of the display panel. Summary of the invention

[0004] The present application provides a display panel and a display device to improve the technical problem of abnormal display of existing display panels.

[0005] To solve the above-mentioned problems, the technical solutions provided by this application are as follows:

[0006] In a first aspect, the present application provides a display panel, which includes a plurality of sub-pixels arranged in a first direction and a second direction, at least one of the sub-pixels includes a pixel circuit, and the pixel circuit includes a driving transistor and a storage capacitor connected to each other; wherein the display panel includes:

[0007] a light shielding layer, comprising a driving light shielding portion corresponding to the driving transistor, wherein the driving light shielding portions in two adjacent sub-pixels are connected in the first direction;

[0008] a first active layer including an active portion of the driving transistor;

[0009] A first gate layer, including a gate of the driving transistor and a plate of the storage capacitor;

[0010] A second active layer, comprising another plate of the storage capacitor;

[0011] The display panel further comprises an electrical connection line extending along the second direction, and in the second direction, the driving light shielding portions in two adjacent sub-pixels are electrically connected via the electrical connection line.

[0012] In a second aspect, the present application also proposes a display device, which includes the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0014] Figure 1 A simplified structural diagram of the display panel of this application;

[0015] Figure 2 An equivalent circuit diagram of a pixel circuit in a display panel of the present application;

[0016] Figure 3 This is a schematic diagram of the film layer in the display panel of this application;

[0017] Figure 4 A diagram showing the film layer stacking of a sub-pixel in the display panel of this application;

[0018] Figure 5 for Figure 4 A structural diagram of the first gate layer;

[0019] Figure 6 for Figure 4 Structural diagram of the first active layer in FIG.

[0020] Figure 7 for Figure 4 A stacking diagram of a first gate layer and a first active layer;

[0021] Figure 8 for Figure 4 Structural diagram of the middle shading layer;

[0022] Fig. 9 for Figure 4 A stacking diagram of the first gate layer and the light shielding layer;

[0023] Fig.10 for Figure 4 Structural diagram of the second active layer in FIG.

[0024] Fig.11 for Figure 4 A structural diagram of the second gate layer;

[0025] Fig.12 for Figure 4 A stacking diagram of a middle light shielding layer, a first gate layer, a first active layer, a second active layer and a second gate layer;

[0026] Fig.13 for Figure 4 A structural diagram of the first source and drain layer;

[0027] Fig.14 for Figure 4 A stacking diagram of a middle light shielding layer, a first gate layer, a first active layer, a second active layer, a second gate layer and a first source and drain layer;

[0028] Fig.15 for Figure 4 A structural diagram of the second source and drain layer;

[0029] Fig.16 for Figure 1 The film layer stacking diagram of the sub-pixel in the middle;

[0030] Fig.17 for Figure 4 and the stackup diagram of the anode layer. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; and "inside" and "outside" refer to the outline of the device.

[0032] See also Figures 1 to 17 The present application provides a display panel 100 , which may include a display unit 200 and a gate circuit 300 located at one side of the display unit 200 , and the gate circuit 300 is used to input a control signal to the display unit 200 .

[0033] In this example, see Figure 1 The display unit 200 includes a plurality of sub-pixels PX arranged along a first direction and a second direction. Each sub-pixel PX is provided with a light-emitting device EL and a pixel circuit PC connected to the light-emitting device EL. The gate circuit 300 is used to input a gate control signal to a transistor in the pixel circuit PC.

[0034] In this embodiment, the pixel circuit PC includes a driving transistor T1 and a storage capacitor Cst connected to each other, and the display panel 100 includes a light shielding layer 121 , a first active layer 123 , a first gate layer 125 and a second active layer 127 .

[0035] In this embodiment, the shading layer 121 includes a driving shading portion T1L corresponding to the driving transistor T1, and in the first direction X, the driving shading portions T1L in two adjacent sub-pixels PX are connected; the first active layer 123 includes the active portion of the driving transistor T1; the first gate layer 125 includes the gate of the driving transistor T1 and one plate of the storage capacitor Cst; the second active layer 127 includes the other plate of the storage capacitor Cst.

[0036] In this embodiment, the display panel 100 further includes an electrical connection line 50 extending along the second direction Y. In the second direction Y, the driving light shielding portions T1L in two adjacent sub-pixels PX are electrically connected via the electrical connection line 50 .

[0037] The present application electrically connects two adjacent driving light shielding portions T1L in the second direction Y by setting an electrical connection line 50 extending along the second direction Y, that is, the driving light shielding portions T1L in different sub-pixels PX are electrically connected to each other in the first direction X and the second direction Y, thereby reducing the impedance of the driving light shielding portion T1L, improving the potential difference between different areas of the light shielding layer 121, and improving the display effect of the display panel 100.

[0038] The technical solution of the present application is now described in conjunction with specific embodiments.

[0039] See also Figure 1 The display panel 100 includes a display area AA and a non-display area NA disposed adjacent to the display area AA, and a display unit 200 is disposed in the display area AA. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is surrounded by the non-display area NA. The display area AA is an area in the display panel 100 for performing a display function, and a plurality of sub-pixels PX are disposed therein to realize the display function. The non-display area NA may be a frame area of ​​the display panel 100, and a functional component that assists the sub-pixels PX in the display area AA to perform display may be disposed therein.

[0040] See also Figure 1 The lower side of the display area AA is provided with a binding terminal 400, which can be connected to an external circuit, and transmits the signal input by the external circuit to the data line, thereby driving the display panel 100 to display the picture. For example, the binding terminal 400 can be bound and connected to a chip or a flip chip film, etc., to provide power and driving signals for the display panel 100.

[0041] In this embodiment, the gate circuit 300 is arranged in the non-display area NA, and the gate circuit 300 can be arranged on both sides of the display area AA; the gate circuit 300 may include a plurality of cascaded gate driving units, and the structure of the gate driving unit is not specifically limited in this application.

[0042] In this embodiment, a plurality of light emitting devices EL and a pixel circuit PC for driving the light emitting devices EL may be arranged in an array in the display area AA. The pixel circuit PC may be a 7T1C, 7T2C, 8T1C, 8T2C, 8T3C, 8T4C or other pixel circuit PC. The following embodiment takes the 8T2C pixel circuit PC as an example for description.

[0043] See also Figure 2 The pixel circuit PC may include a switch transistor T2, a drive transistor T1, a compensation transistor T3, a first reset transistor T4, a second reset transistor T7, a first light-emitting transistor T5, a second light-emitting transistor T6, a storage capacitor Cst and a boost capacitor Cboost, and the storage capacitor Cst includes a first plate Cst1 and a second plate Cst2.

[0044] See also Figure 2, the drain of the switching transistor T2 is connected to the data line Data, the source of the switching transistor T2 is connected to the first node A, and the switch gate T2G of the switching transistor T2 is connected to the switch control line Pscan1; the drain of the driving transistor T1 is connected to the first node A, the source of the driving transistor T1 is connected to the second node B, and the drive gate T1G of the driving transistor T1 is connected to the third node Q; the drain of the compensation transistor T3 is connected to the third node Q, the source of the compensation transistor T3 is connected to the second node B, and the compensation gate T3G of the compensation transistor T3 is connected to the compensation control line Nscan1; the drain of the first reset transistor T4 is connected to the first reset signal line Vi1, the source of the first reset transistor T4 is connected to the third node Q, and the gate T4G of the first reset transistor T4 is connected to the first reset control line Nscan2; the drain of the second reset transistor T7 is connected to the second reset signal line Vi2, the source of the second reset transistor T7 is connected to the anode of the light emitting device EL, and the gate T7G of the second reset transistor T7 is connected to the second reset control line Pscan 2; the drain of the first light emitting transistor T5 is connected to the high potential line VDD, the source of the first light emitting transistor T5 is connected to the first node A, and the first light emitting gate T5G of the first light emitting transistor T5 is connected to the light emitting control line EM; the drain of the second light emitting transistor T6 is connected to the second node B, the source of the second light emitting transistor T6 is connected to the anode of the light emitting device EL, and the second light emitting gate T6G of the second light emitting transistor T6 is connected to the light emitting control line EM; the drain of the third reset transistor T8 is connected to the third reset signal line Vi3, the source of the third reset transistor T8 is connected to the first node A, and the third reset gate T8G of the third reset transistor T8 is connected to the second reset control line Pscan2; the first plate Cst1 of the storage capacitor Cst is connected to the third node Q, and the second plate Cst1 of the storage capacitor Cst is connected to the high potential line VDD; one plate of the boost capacitor Cboost is connected to the switch control line Pscan1, and the other plate of the boost capacitor Cboost is connected to the third node Q; the cathode of the light emitting device EL is connected to the low potential line VSS.

[0045] It should be noted that the switch transistors T2 in different sub-pixels PX are connected to different data signal lines, and the present application only takes one of them as an example for description.

[0046] It should be noted that the light-emitting device EL of the present application may be an organic light-emitting diode, Mini LED, MicroLED, LED of regular size or other light source.

[0047] In this embodiment, the high potential line VDD is used to provide a constant high voltage level to the pixel circuit PC, and the low potential line VSS is used to provide a constant low voltage level to the pixel circuit PC.

[0048] In this embodiment, the switch transistor T2, the drive transistor T1, the second reset transistor T7, the third reset transistor T8, the first light-emitting transistor T5, the second light-emitting transistor T6, the compensation transistor T3 and the first reset transistor T4 can be one of P-type transistors or N-type transistors; this application is explained by taking the switch transistor T2, the drive transistor T1, the second reset transistor T7, the third reset transistor T8, the first light-emitting transistor T5, the second light-emitting transistor T6 as P-type transistors, and the compensation transistor T3 and the first reset transistor T4 as N-type transistors as an example.

[0049] In this embodiment, the source is only the output end of the present application, and the drain is only the input end of the present application, and the two are only different in name.

[0050] In the following embodiments, the first direction is perpendicular to the extension direction of the data line, and the angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90°, for example, the first direction X is the horizontal direction and the second direction Y is the vertical direction.

[0051] The following is for Figure 2 The structure of the film layer structure of the pixel circuit PC of the present application is described.

[0052] See also Figure 3 The display area AA and the non-display area NA of the display panel 100 may be provided with a base substrate 110 and an array driving layer 120 provided on the base substrate 110; in the display area AA, the display panel 100 may also be provided with a pixel definition layer PDL provided on the array driving layer 120, a light emitting device layer provided on the same layer as the pixel definition layer PDL, and an encapsulation layer TFE provided on the pixel definition layer PDL. The following mainly describes the film layer structure in the display area AA.

[0053] In the present embodiment, the base substrate 110 supports various layers disposed on the base substrate 110. When the display panel 100 is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent base substrate is used. When the display panel 100 is a top-emitting light-emitting display device, a semi-transparent or opaque base substrate as well as a transparent base substrate may be used.

[0054] In the present embodiment, the base substrate 110 is used to support various film layers disposed on the base substrate 110, and the base substrate 110 may be made of an insulating material such as glass, quartz, or a polymer resin. The base substrate 110 may be a rigid substrate or a flexible substrate that can be bent, folded, curled, etc. Examples of flexible materials for the flexible substrate include polyimide (PI), but are not limited to polyimide (PI).

[0055] In this embodiment, the base substrate 110 may include a first flexible substrate 111, a first barrier layer 112, a second flexible substrate 113, and a second barrier layer 114 that are stacked. The first flexible substrate 111 and the second flexible substrate 113 may be formed of the same material such as polyimide, and the first barrier layer 112 and the second barrier layer 114 may be formed of an inorganic material including, for example, at least one of SiOx and SiNx.

[0056] See also Figure 3 , the array driving layer 120 may include a plurality of thin film transistors, the thin film transistors may be of an etching barrier type, a back channel etching type, or may be divided into a bottom gate thin film transistor, a top gate thin film transistor and the like structure according to the position of the gate and the active layer, or may be divided into an N-type thin film transistor, a P-type thin film transistor according to the performance of the thin film transistor; wherein, Figure 3 The thin film transistor does not represent Figure 2 The structural diagram of any transistor is merely a schematic diagram of each film layer of the display panel 100 of the present application.

[0057] See also Figure 3 The array driving layer 120 may include a blocking insulating layer BF disposed on the base substrate 110, a light shielding layer 121 embedded in the blocking insulating layer BF, a buffer layer 122 disposed on the blocking insulating layer BF, a first active layer 123 disposed on the buffer layer 122, a first insulating layer 124 disposed on the first active layer 123, a first gate layer 125 disposed on the first insulating layer 124, a second insulating layer 126 disposed on the first gate layer 125, a second active layer 127 disposed on the second insulating layer 126, and a first gate layer 125 disposed on the second active layer 127. Three insulating layers 128, a second gate layer 129 arranged on the third insulating layer 128, a fourth insulating layer 130 arranged on the second gate layer 129, a first source and drain layer 131 arranged on the fourth insulating layer 130, a first flat layer 132 arranged on the first source and drain layer 131, a second source and drain layer 133 arranged on the first flat layer 132, and a second flat layer 134 arranged on the second source and drain layer 133, a light-emitting device layer and a pixel definition layer PDL arranged on the second flat layer 134, and an encapsulation layer TFE arranged on the pixel definition layer PDL.

[0058] See also Figure 3 The light shielding layer 121 is disposed on the second barrier layer 114. The light shielding layer 121 is used to block external light from entering the thin film transistor from the bottom. The material of the light shielding layer 121 can be composed of a black light shielding material, such as a black light shielding metal or a black organic material.

[0059] See also Figure 3The buffer layer 122 is disposed on the light-shielding layer 121. The buffer layer 122 is used to isolate the light-shielding layer 121 from the upper metal material. The material of the buffer layer 122 may include a compound composed of nitrogen, silicon and oxygen, such as a single-layer silicon oxide film layer, or a silicon oxide-silicon nitride stacked structure.

[0060] In this embodiment, the light shielding layer 121 may also be embedded in the buffer layer 122 .

[0061] See also Figure 3 The first active layer 123 is arranged on the buffer layer 122, and the second active layer 127 is arranged on the second insulating layer 126. In the present application, the material of the first active layer 123 can be a silicon semiconductor, such as low-temperature polycrystalline silicon, and the material of the second active layer 127 can be an oxide semiconductor, such as metal oxide. The pixel circuit PC has N-type transistors and P-type transistors, so the display area AA of the present application is provided with metal oxide semiconductors and low-temperature polycrystalline silicon semiconductors.

[0062] See also Figure 3 The first insulating layer 124, the second insulating layer 126, the third insulating layer 128, and the fourth insulating layer 130 are respectively arranged on the corresponding metal layers or semiconductor layers, and are separated by different layers of metal layers or semiconductor layers; the materials of the first insulating layer 124, the second insulating layer 126, the third insulating layer 128, and the fourth insulating layer 130 can be an inorganic substance composed of at least two elements in silicon oxynitride or an organic material with flatness.

[0063] See also Figure 3 The first gate layer 125 and the second gate layer 129 are respectively disposed on corresponding insulating layers. The materials of the first gate layer 125 and the second gate layer 129 may be copper, molybdenum or molybdenum-titanium alloy.

[0064] See also Figure 3 The first source-drain electrode layer 131 is disposed on the fourth insulating layer 130 , and the second source-drain electrode layer 133 is disposed on the first planar layer 132 . The materials of the first source-drain electrode layer 131 and the second source-drain electrode layer 133 may be copper or molybdenum-titanium alloy, copper or titanium, etc.

[0065] See also Figure 3 The first flat layer 132 and the second flat layer 134 are laid in a whole layer to ensure the flatness of the film layer of the array driving layer 120. The materials of the first flat layer 132 and the second flat layer 134 can be inorganic substances composed of nitride oxide silicon or organic materials with flatness.

[0066] See also Figure 3 The light emitting device layer may include a plurality of light emitting devices EL, each of which has an anode AN connected to the pixel circuit, a light emitting unit, and a cathode CA.

[0067] according to Figure 3 It can be seen from the structure that the two plates of the storage capacitor Cst in the display area AA of the present application are respectively composed of the material of the first gate layer 125 and the material of the second active layer 127. For example, the first plate Cst1 is located in the first gate layer 125, and the second plate Cst2 is located in the second active layer 127. The metal layer and an insulating layer between the original second active layer 127 and the first gate layer 125 are removed, the number of film layers of the display panel 100 is reduced, the preparation process of the display panel 100 is simplified, and the cost of the display panel 100 is reduced.

[0068] See also Figure 1 and Fig.17 , the plurality of sub-pixels PX include a plurality of repeating units RU arranged along a first direction X and a second direction Y, each of the repeating units RU has two sub-pixels PX, and patterns of partial film layers in two pixel circuits PC in one repeating unit RU are symmetrically arranged with a center line of the repeating unit RU as an axis, and the center line may be parallel to the second direction Y; for example, patterns of the first active layer 123, the first gate layer 125, the second active layer 127, the second gate layer 129, and the first source and drain layer 131 in the repeating unit RU are symmetrically arranged with the center line as an axis, and partial patterns in the light shielding layer 121 and the second source and drain layer 133 in different pixel circuits PC have small differences.

[0069] It should be noted that due to limitations of process and equipment, there are slight differences in the film layer patterns in different pixel circuits PC of the present application in actual products. Therefore, the symmetrical setting of the present application is only a symmetrical setting within the error range; at the same time, in order to set the connection points with the upper structure, some structures widen the pattern in the area where the connection points are located, so that the pattern is asymmetrically set, which is also within the error range.

[0070] It should be noted that the structure and film layer structure of the above-mentioned pixel circuit PC of the present application are applicable to all sub-pixels PX of the present application.

[0071] In the following embodiments, the structure of each film layer in two pixel circuits PC in a repeating unit RU is taken as an example to describe the technical solution of the present application. For example, the repeating unit RU includes a first pixel circuit PC1 and a second pixel circuit PC2.

[0072] See also Figure 4 and Figure 5 , Figure 4 This is a film layer stacking diagram of a repeating unit RU in the display panel 100 of the present application. Figure 5 for Figure 4The structure diagram of the first gate layer 125 is shown in FIG. 1 , and the patterns in the first gate layer 125 within a repeating unit RU can be symmetrically arranged.

[0073] See also Figure 5 The first gate layer 125 includes a first reset signal line Vi1, a switch control line Pscan1, a light emitting control line EM and a second reset control line Pscan2 extending along the first direction X, and the first reset signal line Vi1, the switch control line Pscan1, the light emitting control line EM and the second reset control line Pscan2 are arranged in sequence along the second direction Y, and the first reset signal line Vi1, the switch control line Pscan1, the light emitting control line EM and the second reset control line Pscan2 in a repeating unit RU are connected to each other.

[0074] See also Figure 5 The first gate layer 125 also includes a first electrode plate Cst1 of a storage capacitor Cst arranged between the switch control line Pscan1 and the light-emitting control line EM, the first electrode plate Cst1 and the switch control line Pscan1 and the light-emitting control line EM are spaced apart, and the distance between the first electrode plate Cst1 and the switch control line Pscan1 is greater than the distance between the first electrode plate Cst1 and the light-emitting control line EM; at the same time, the two first electrode plates Cst1 in a repeating unit RU are spaced apart.

[0075] See also Figure 4 and Figure 6 , Figure 6 for Figure 4 , the patterns in the first active layer 123 within a repeating unit RU are symmetrically arranged.

[0076] See also Figure 6 The first active layer 123 includes a switch active portion T2A of the switch transistor T2, a first light emitting active portion T5A of the first light emitting transistor T5, a driving active portion T1A of the driving transistor T1, a second light emitting active portion T6A of the second light emitting transistor T6, a second reset active portion T7A of the second reset transistor T7, a third reset active portion T8A of the third reset transistor T8, a first extension segment ET1, and a second extension segment ET2.

[0077] See also Figure 6The switch active portion T2A, the first light emitting active portion T5A and the driving active portion T1A are connected to the first connection point N1, the driving active portion T1A and the second light emitting active portion T6A are connected to the second connection point N2, the first extension segment ET1, the second light emitting active portion T6A and the second reset active portion T7A are connected to the third connection point N3, the first extension segment ET1 extends from the third connection point N3 to the side close to the first light emitting active portion T5A, the third reset active portion T8A is spaced apart from the above active portions and is located between the first extension segment ET1 and the first light emitting active portion T5A, the second extension segment ET2 is connected to the first connection point N1, and is located between the driving active portion T1A and the first light emitting active portion T5A, and at the same time, the two first light emitting active portions T5A in a repeating unit RU are connected at the end away from the first node.

[0078] See also Figure 6 The switch active part T2A, the first light emitting active part T5A, the second light emitting active part T6A, the second reset active part T7A, and the third reset active part T8A extend along the second direction Y and are in a strip shape, the first extension segment ET1 extends along the first direction X and is in a strip shape, and the driving active part T1A can be U-shaped.

[0079] See also Figure 7 , Figure 7 for Figure 4 FIG. 1 is a stack diagram of the first gate layer 125 and the first active layer 123.

[0080] See also Figure 7 The light emitting control line EM and the first light emitting active part T5A have an overlapping part, and the light emitting control line EM in the overlapping part is multiplexed as the first light emitting gate T5G. The first light emitting active part T5A in the overlapping part is the channel of the first light emitting transistor T5. One end of the first light emitting active part T5A far from the first connection point N1 is multiplexed as the drain T5D of the first light emitting transistor T5, and one end of the first light emitting active part T5A close to the first connection point N1 is multiplexed as the source T5S of the first light emitting transistor T5, that is, the structure in the area where the first connection point N1 is located is the first node A in the pixel circuit PC.

[0081] See also Figure 7The light emitting control line EM and the second light emitting active portion T6A have an overlapping portion, and the light emitting control line EM in the overlapping portion is multiplexed as the second light emitting gate T6G. The second light emitting active portion T6A in the overlapping portion is the channel of the second light emitting transistor T6. One end of the second light emitting active portion T6A far from the second connection point N2 is multiplexed as the source T6S of the second light emitting transistor T6, and one end of the second light emitting active portion T6A close to the second connection point N2 is multiplexed as the drain T6D of the second light emitting transistor T6, that is, the structure of the area where the second connection point N2 is located is the second node B in the pixel circuit PC, and the structure of the area where the third connection point N3 is located is the position connected to the anode AN in the pixel circuit PC.

[0082] See also Figure 7 The second reset control line Pscan2 has an overlapping portion with the second reset active portion T7A, and the second reset control line Pscan2 of the overlapping portion is multiplexed as the second reset gate T7G. The second reset active portion T7A of the overlapping portion is the channel of the second reset transistor T7. One end of the second reset active portion T7A close to the third connection point N3 is multiplexed as the source T7S of the second reset transistor T7, and one end of the second reset active portion T7A far from the third connection point N3 is multiplexed as the drain T7D of the second reset transistor T7.

[0083] See also Figure 7 The second reset control line Pscan2 and the third reset active portion T8A have an overlapping portion, the second reset control line Pscan2 in the overlapping portion is multiplexed as the third reset gate T8G, the third reset active portion T8A in the overlapping portion is the channel of the third reset transistor T8, one end of the third reset active portion T8A close to the light emitting control line EM is multiplexed as the source T8S of the third reset transistor T8, and one end of the third reset active portion T8A far from the light emitting control line EM is multiplexed as the drain T8D of the third reset transistor T8.

[0084] See also Figure 7 The switch control line Pscan1 and the switch active part T2A have an overlapping part, and the switch control line Pscan1 in the overlapping part is multiplexed as the switch gate T2G. The switch active part T2A in the overlapping part is the channel of the switch transistor T2. One end of the switch active part T2A close to the first connection point N1 is multiplexed as the source T2S of the switch transistor T2, and one end of the switch active part T2A far from the first connection point N1 is multiplexed as the drain T2D of the switch transistor T2.

[0085] See also Figure 4 and Figure 8 , Figure 8 for Figure 4The structure of the light shielding layer 121 in the repeating unit RU can be symmetrically arranged or asymmetrically arranged. Figure 8 The patterns in the light shielding layer 121 are arranged asymmetrically.

[0086] See also Figure 8 The light-shielding layer 121 includes a reset light-shielding portion T4L, a compensation light-shielding portion T3L and a drive light-shielding portion T1L which are arranged at intervals along the second direction Y. The reset light-shielding portion T4L and the compensation light-shielding portion T3L both extend along the first direction X, and in the first direction X, the drive light-shielding portions T1L in two adjacent sub-pixels PX are connected, the reset light-shielding portions T4L in two adjacent sub-pixels PX are connected, and the compensation light-shielding portions T3L in two adjacent sub-pixels PX are connected.

[0087] exist Figure 8 In the structure, the shading layer 121 also includes a first connecting segment CT1 connected to the driving shading portion T1L, the first connecting segment CT1 is arranged between the driving shading portion T1L and the compensation shading portion T3L, and one end of the first connecting segment CT1 away from the driving shading portion T1L is spaced apart from the compensation shading portion T3L, and the electrical connector is electrically connected to the first connecting segment CT1.

[0088] It should be noted that in some repeating units RU, since no corresponding electrical connection line 50 is provided inside the pixel circuit PC, that is, the first connection segment CT1 may not be required in the repeating unit RU, the pattern in the light shielding layer 121 in the corresponding repeating unit RU may be symmetrically arranged.

[0089] See also Fig. 9 , Fig. 9 for Figure 4 FIG. 1 is a stacked diagram of the first gate layer 125 and the light shielding layer 121. FIG.

[0090] exist Fig. 9 In the structure, the reset shading portion T4L is arranged between the first reset signal line Vi1 and the switch control line Pscan1, the compensation shading portion T3L is arranged between the switch control line Pscan1 and the driving shading portion T1L, and the compensation shading portion T3L overlaps with a part of the switch control line Pscan1, and the driving shading portion T1L overlaps with the first electrode Cst1.

[0091] In this embodiment, since the driving light shielding portion T1L can also serve as a shielding structure, the outer contour area of ​​the driving light shielding portion T1L of the present application can be larger than the area of ​​the first electrode plate Cst1, and the orthographic projection of the first electrode plate Cst1 on the light shielding layer 121 can be located within the driving light shielding portion T1L.

[0092] See also Figures 10 to 12 , Fig.10 for Figure 4 The structure diagram of the second active layer 127, Fig.11 for Figure 4 The structure diagram of the second gate layer 129, Fig.12 for Figure 4 The stacking diagram of the first gate layer 125, the light shielding layer 121, the first active layer 123, the second active layer 127 and the second gate layer 129, and the pattern in the second active layer 127 within a repeating unit RU can be symmetrically arranged, and the pattern in the second gate layer 129 within a repeating unit RU can be symmetrically arranged.

[0093] exist Fig.10 In the structure, the second active layer 127 includes the first reset active portion T4A of the first reset transistor T4 and the compensation active portion T3A of the compensation transistor T3, the first reset active portion T4A and the compensation active portion T3A both extend along the second direction Y and are in the shape of long strips, and the first reset active portion T4A and the compensation active portion T3A are connected at a fourth connection point N4.

[0094] exist Fig.10 In the structure, the second active layer 127 also includes the second electrode plate Cst2 of the storage capacitor Cst, and the second electrode plate Cst2 in a repeating unit RU is connected, and the second electrode plate Cst2 is arranged opposite to the first electrode plate Cst1, the outer contour area of ​​the first electrode plate Cst1 can be smaller than the outer contour area of ​​the second electrode plate Cst2, and the outer contour area of ​​the second electrode plate Cst2 is smaller than the outer contour area of ​​the driving light shielding portion T1L.

[0095] exist Fig.11 In the structure, the second gate layer 129 includes a first reset control line Nscan2, a compensation control line Nscan1 and a third reset signal line Vi3 arranged at intervals along the second direction Y, and the first reset control line Nscan2 and the compensation control line Nscan1 both extend along the first direction X.

[0096] exist Fig.12In the structure, the first reset control line Nscan2 and the reset shading portion T4L both have an overlapping portion with the first reset active portion T4A, and the first reset control line Nscan2 of the overlapping portion is multiplexed as the first reset gate T4G, the first reset active portion T4A of the overlapping portion is the channel of the first reset transistor T4, an end of the first reset active portion T4A close to the fourth connection point N4 is multiplexed as the source T4S of the first reset transistor T4, and an end of the first reset active portion T4A far from the fourth connection point N4 is multiplexed as the drain T4D of the first reset transistor T4, that is, the structure of the area where the fourth connection point N4 is located is the third node Q in the pixel circuit PC, and the control signals transmitted by the first reset control line Nscan2 and the reset shading portion T4L are the same.

[0097] exist Fig.12 In the structure, the compensation shading portion T3L and the compensation control line Nscan1 both have an overlapping portion with the compensation active portion T3A of the compensation transistor T3, and the compensation control line Nscan1 in the overlapping portion is multiplexed as the compensation gate T3G, the compensation active portion T3A in the overlapping portion is the channel of the compensation transistor T3, an end of the compensation active portion T3A close to the fourth connection point N4 is multiplexed as the drain T3D of the compensation transistor T3, an end of the compensation active portion T3A far from the fourth connection point N4 is multiplexed as the source T3S of the compensation transistor T3, and the control signals transmitted by the compensation shading portion T3L and the compensation control line Nscan1 are the same.

[0098] exist Fig.12 In the structure, the first reset control line Nscan2 and the reset light shielding portion T4L have an overlapping portion, and the compensation control line Nscan1 and the compensation light shielding portion T3L have an overlapping portion. The area of ​​the overlapping portion between the first reset control line Nscan2 and the active portion of the first reset transistor T4 is larger than the area of ​​the overlapping portion between the reset light shielding portion T4L and the active portion of the first reset transistor T4; and the area of ​​the overlapping portion between the compensation light shielding portion T3L and the active portion of the compensation transistor T3 is larger than the area of ​​the overlapping portion between the compensation control line Nscan1 and the active portion of the compensation transistor T3.

[0099] See also Figure 4 , Fig.13 and Fig.14 , Fig.13 for Figure 4 For a structural diagram of the first source and drain electrode layer 131, please refer to Fig.14 , Fig.14 for Figure 41 and 12. In the stacking diagram of the first gate layer 125, the first active layer 123, the second active layer 127, the second gate layer 129 and the first source and drain electrode layer 131, the patterns in the first source and drain electrode layer 131 within a repeating unit RU can be symmetrically arranged.

[0100] See also Fig.13 and Fig.14 The first source-drain layer 131 includes a lateral fan-out line FIAH and a second reset signal line Vi2. The lateral fan-out line FIAH is arranged on a side of the first reset signal line Vi1 away from the switch control line Pscan1. The second reset signal line Vi2 is arranged between the third reset signal line Vi3 and the second reset control line Pscan2.

[0101] See also Fig.14 The first source-drain layer 131 further includes a third connection segment CT3, one end of the third connection segment CT3 is connected to the first reset signal line Vi1 through a via hole, and the other end of the third connection segment CT3 is connected to an end of the first reset active portion T4A away from the fourth connection point N4 through a via hole.

[0102] See also Fig.14 The first source-drain layer 131 further includes a fourth connection segment CT4, one end of the fourth connection segment CT4 is connected to the data line Data through a via hole, and the other end of the fourth connection segment CT4 is connected to an end of the switch active portion T2A away from the first connection point N1 through a via hole.

[0103] See also Fig.14 The first source-drain layer 131 further includes a fifth connection segment CT5, one end of the fifth connection segment CT5 is connected to one end of the fourth connection point N4 of the compensation active part T3A through a via hole, and the other end of the fifth connection segment CT5 is connected to the first electrode plate Cst1 through an avoidance hole HL0 in the second electrode plate Cst2.

[0104] See also Fig.14 The first source-drain layer 131 also includes a sixth connection segment CT6, one end of the sixth connection segment CT6 is connected to an end of the compensation active part T3A away from the fourth connection point N4 through a via hole, and the other end of the sixth connection segment CT6 is connected to an end of the second light-emitting active part T6A away from the third connection point N3 through a via hole.

[0105] See also Fig.14 The first source-drain layer 131 further includes a seventh connection segment CT7, one end of the seventh connection segment CT7 is connected to an end of the first extension segment ET1 away from the third connection point N3 through a via hole, and the other end of the seventh connection segment CT7 is connected to the upper metal layer through a via hole.

[0106] See also Fig.14The first source-drain layer 131 also includes an eighth connection segment CT8, one end of the eighth connection segment CT8 is connected to the second extension segment ET2 through a via hole, and the other end of the eighth connection segment CT8 is connected to an end of the third reset active portion T8A close to the light-emitting control line EM through a via hole.

[0107] In this embodiment, the third reset signal line Vi3 includes a reset transverse segment Vi3a and a reset extension segment Vi3b, the reset transverse segment Vi3a extends along the first direction X, the reset extension segment Vi3b extends along the second direction Y, and the reset extension segment Vi3b has an overlapping portion with the eighth connecting segment CT8, which is equivalent to the reset extension segment Vi3b overlapping with the area where the first node is located.

[0108] See also Fig.14 The first source-drain layer 131 also includes a ninth connection segment CT9, one end of the ninth connection segment CT9 is connected to the reset extension segment Vi3b through a via hole, the other end of the ninth connection segment CT9 is connected to an end of the third reset active portion T8A away from the light-emitting control line EM through a via hole, and the two ninth connection segments CT9 in a repeating unit RU are electrically connected at a position overlapping with the reset extension segment Vi3b.

[0109] See also Fig.13 and Fig.14 The first source-drain electrode layer 131 also includes a first sub-line 510 constituting the electrical connection line 50, the first sub-line 510 includes a first transverse segment 511 and a first longitudinal segment 512 connected to each other, the first transverse segment 511 is arranged along the first direction X, and the first longitudinal segment 512 is arranged along the second direction Y; the orthographic projection of the first transverse segment 511 on the shading layer 121 is located between the driving shading portion T1L and the compensating shading portion T3L, and has an overlapping portion with the first connecting segment CT1, and the first transverse segment 511 is electrically connected to the first connecting segment CT1 through the first via hole HL1.

[0110] In this embodiment, the first transverse segments 511 in a repeating unit RU are connected to each other, and the first longitudinal segments 512 in a repeating unit RU are shared; at the same time, the first longitudinal segment 512 includes a first part 512a close to the first transverse segment 511 and a second part 512b away from the first transverse segment 511, and one end of the first part 512a close to the second part 512b is electrically connected to the second electrode Cst2 through a via hole, and one end of the second part 512b away from the first part 512a is connected to the end of the first light-emitting active part T5A away from the first connection point N1 through a via hole.

[0111] In this embodiment, the line width of the first portion 512 a is greater than the line width of the second portion 512 b .

[0112] See also Figure 4 and Fig.15 , Fig.15 for Figure 4 1 , the pattern in the second source / drain electrode layer 133 within a repeating unit RU is asymmetrically arranged.

[0113] See also Figure 4 and Fig.15 The second source-drain layer 133 includes a high potential line VDD arranged along the first direction X, a second sub-line 520 and a data line Data constituting the electrical connection line 50, and the high potential line VDD, the second sub-line 520 and the data line Data all extend along the second direction Y.

[0114] In this embodiment, the second source-drain layer 133 also includes a second connection segment CT2, one end of the second connection segment CT2 is connected to the second sub-line 520, the other end of the second connection segment CT2 is connected to the high potential line VDD, and an end of the first transverse segment 511 away from the first longitudinal segment 512 has an overlapping portion with the high potential line VDD, and the high potential line VDD is electrically connected to the first transverse segment 511 through the second via HL2.

[0115] Please note that Fig.15 In a repeating unit RU, the pixel circuit PC on the left may include a high potential line VDD, a second sub-line 520 and a data line Data arranged along the first direction X, and the pixel circuit PC on the right may include a data line Data, a longitudinal fan-out line FIAZ and a high potential line VDD arranged along the first direction X, each column of sub-pixels PX corresponds to a high potential line VDD and a data line Data, and a sub-pixel PX in each repeating unit RU is provided with a longitudinal fan-out line FIAZ, which can be electrically connected to the transverse fan-out line FIAH.

[0116] It should be noted that the second sub-line 520 only exists in some repeating units RU, and in different repeating units RU, the position where the second sub-line 520 is located can be set with the first reset connection line Vi1c, the second reset connection line Vi2c and the third reset connection line Vi3c extending along the second direction Y.

[0117] See for example Fig.16 , Fig.16Two rows of sub-pixels PX are shown, and each row of sub-pixels PX includes 4 repeating units RU. In the two repeating units RU in the third column, the sub-pixels PX on the left are each provided with a first reset connection line Vi1c, and in the second direction Y, two adjacent first reset signal lines Vi1 are electrically connected through the first reset connection line Vi1c; in the two repeating units RU in the second column, the sub-pixels PX on the left are each provided with a second reset connection line Vi2c, and in the second direction Y, two adjacent second reset signal lines Vi2 are electrically connected through the second reset connection line Vi2c; in the two repeating units RU in the first column, the sub-pixels PX on the left are each provided with a third reset connection line Vi3c, and in the second direction Y, two adjacent third reset signal lines Vi3 are electrically connected through the third reset connection line Vi3c; in the two repeating units RU in the fourth column, the sub-pixels PX on the left are each provided with a second sub-line 520, and in the second direction Y, the high potential lines VDD, the first sub-line 510, the second electrode plate Cst2 and the driving light shielding portion T1L of two adjacent rows are connected to each other, and all transmit a high level.

[0118] exist Fig.16 In the structure of FIG. 5 , the first reset connection line Vi1c, the second reset connection line Vi2c, the third reset connection line Vi3c and the electrical connection line 50 are sequentially arranged in the first direction X at intervals.

[0119] It should be noted that the first reset connection line Vi1c, the second reset connection line Vi2c, the third reset connection line Vi3c and the electrical connection line 50 can be arranged with one repeating unit RU in between, or can be designed differently according to the difference in signals transmitted by different connection lines; for example, the number of repeating units RU between two adjacent first reset connection lines Vi1c is less than the number of repeating units RU between the other three connection lines.

[0120] It should be noted that, in the first direction X, the third reset connection line Vi3c, the second reset connection line Vi2c, the first reset connection line Vi1c and the electrical connection line 50 are sequentially arranged at intervals.

[0121] In this embodiment, the present application sets a longitudinal electrical connection line 50 to electrically connect the driving light shielding portion T1L located in the light shielding layer 121, the second electrode Cst2 of the storage capacitor Cst, and the high potential line VDD to each other, so that the structure for transmitting the high potential signal forms a horizontal and vertical mesh structure, thereby reducing the impedance of the driving light shielding portion T1L, improving the potential difference between different areas of the light shielding layer 121, and improving the display effect of the display panel 100.

[0122] See also Fig.17 , Fig.17For this application Figure 4 The pattern in and the stackup diagram of the anode layer.

[0123] See also Fig.17 The display panel 100 may include a first pixel circuit PC1 and a second pixel circuit PC2, and a first anode AN1 connected to the first pixel circuit PC1 and a second anode AN2 connected to the second pixel circuit PC2, the first anode overlaps with the first pixel circuit PC1 and the second pixel circuit PC2, and in order to avoid the influence of the high potential line VDD on the anode potential as much as possible, the first anode and the second anode AN2 of the present application are set to avoid the high potential line VDD as much as possible.

[0124] In this embodiment, the first pixel circuit PC1 may be one of the red sub-pixel PX, the green sub-pixel PX, and the blue sub-pixel PX, and the second pixel circuit PC2 may be the other one of the red sub-pixel PX, the green sub-pixel PX, and the blue sub-pixel PX.

[0125] It should be noted that the signal transmission wire of the present application extends along the first direction X or the second direction Y, which only means that the wire extends in this direction, and does not mean that the wire is a straight line. For example, the wire of the present application can be a bent curve or a broken line.

[0126] The present application also provides a display device, which includes the above-mentioned display panel. The display device can be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0127] The present application discloses a display panel and a display device; the pixel circuit of the display panel includes a driving transistor and a storage capacitor connected to each other, and the shading layer in the display panel includes a driving shading portion corresponding to the driving transistor, the first active layer includes the active portion of the driving transistor, the first gate layer includes the gate of the driving transistor and one electrode plate of the storage capacitor, the second active layer includes the other electrode plate of the storage capacitor, the driving shading portions in two adjacent sub-pixels in a first direction are connected, and the driving shading portions in two adjacent sub-pixels in a second direction are electrically connected through an electrical connection line; the present application electrically connects two adjacent driving shading portions in the second direction by setting an electrical connection line extending along the second direction, that is, the driving shading portions in different sub-pixels are electrically connected to each other in the first direction and the second direction, thereby reducing the impedance of the driving shading portion, improving the potential difference between different areas of the shading layer, and improving the display effect of the display panel.

[0128] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0129] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: The display panel comprises a plurality of sub-pixels arranged in a first direction and a second direction, at least one of the sub-pixels comprises a pixel circuit, and the pixel circuit comprises a driving transistor and a storage capacitor connected to each other; wherein the display panel comprises: a light shielding layer, comprising a driving light shielding portion corresponding to the driving transistor, wherein the driving light shielding portions in two adjacent sub-pixels are connected in the first direction; a first active layer including an active portion of the driving transistor; A first gate layer, including a gate of the driving transistor and a plate of the storage capacitor; A second active layer, comprising another plate of the storage capacitor; The display panel further comprises an electrical connection line extending along the second direction, and in the second direction, the driving light shielding portions in two adjacent sub-pixels are electrically connected via the electrical connection line.

2. The display panel according to claim 1, characterized in that: The pixel circuit further includes a switch transistor, a compensation transistor and a first reset transistor, wherein the switch transistor and the drive transistor are connected to a first node, the drive transistor and the compensation transistor are connected to a second node, and the first reset transistor, the drive transistor and the compensation transistor are connected to a third node; Among them, the shading portion also includes a reset shading portion corresponding to the reset transistor and a compensation shading portion corresponding to the compensation transistor, the reset shading portion, the compensation shading portion and the driving shading portion are arranged at intervals along the second direction, and in the first direction, the reset shading portions in two adjacent sub-pixels are connected, and the compensation shading portions in two adjacent sub-pixels are connected.

3. The display panel according to claim 2, characterized in that: The shading layer further includes a first connecting segment connected to the driving shading portion, the first connecting segment is arranged between the driving shading portion and the compensating shading portion, and an end of the first connecting segment away from the driving shading portion is spaced apart from the compensating shading portion.

4. The display panel according to claim 3, characterized in that: The display panel further includes: a first source-drain electrode layer, arranged on a side of the second active layer away from the first active layer, the first source-drain electrode layer comprising a first sub-line constituting the electrical connection line, the first sub-line comprising a first transverse segment and a first longitudinal segment connected to each other, the first transverse segment being arranged along the first direction, and the first longitudinal segment being arranged along the second direction; The orthographic projection of the first transverse segment on the shading layer is located between the driving shading portion and the compensating shading portion, and has an overlapping portion with the first connecting segment. The first transverse segment is electrically connected to the first connecting segment through a first via hole.

5. The display panel according to claim 4, characterized in that: The display panel further includes: A second source-drain electrode layer is provided on a side of the first source-drain electrode layer away from the second active layer, the second source-drain electrode layer comprises a high potential line arranged along the first direction, a second sub-line constituting the electrical connection line, and a data line, the high potential line, the second sub-line, and the data line all extending along the second direction; Wherein, the second sub-line is electrically connected to the first transverse segment.

6. The display panel according to claim 5, characterized in that: The second source-drain electrode layer further includes a second connecting segment, one end of the second connecting segment is connected to the second sub-line, and the other end of the second connecting segment is connected to the high potential line; An end of the first transverse segment away from the first longitudinal segment has an overlapping portion with the high potential line, and the high potential line passes through a second via hole and is electrically connected to the first transverse segment.

7. The display panel according to any one of claims 2 to 6, characterized in that: The display panel further includes: a second gate layer, disposed on a side of the second active layer away from the first active layer, the second gate layer comprising a first reset control line and a compensation control line arranged along the second direction, the first reset control line and the compensation control line both extending along the first direction; Among them, the first reset control line and the reset shading portion both have overlapping portions with the active portion of the first reset transistor, the compensation shading portion and the compensation control line both have overlapping portions with the active portion of the compensation transistor, and the control signals transmitted by the first reset control line and the reset shading portion are the same, and the control signals transmitted by the compensation shading portion and the compensation control line are the same.

8. The display panel according to claim 7, characterized in that: The area of ​​the overlapped portion between the first reset control line and the active portion of the first reset transistor is larger than the area of ​​the overlapped portion between the reset light shielding portion and the active portion of the first reset transistor; An area of ​​an overlapping portion of the compensation light shielding portion and the active portion of the compensation transistor is greater than an area of ​​an overlapping portion of the compensation control line and the active portion of the compensation transistor.

9. The display panel according to any one of claims 2 to 6, characterized in that: The first gate layer further includes a first reset signal line connected to the drain of the first reset transistor, and the first reset signal line extends along the first direction; The display panel further includes a first reset connection line extending along the second direction. In the second direction, two adjacent first reset signal lines are electrically connected through the first reset connection line, and the first reset connection line and the electrical connection line are arranged at intervals in the first direction.

10. The display panel according to claim 9, characterized in that: The pixel circuit further includes a second reset transistor and a third reset transistor, the drain of the second reset transistor is connected to the second reset signal line, the source of the second reset transistor is connected to the anode of the light emitting device, the drain of the third reset transistor is connected to the third reset signal line, and the source of the third reset transistor is connected to the switch transistor and the driving transistor; Among them, the display panel also includes a second reset connection line and a third reset connection line extending along the second direction, two adjacent second reset signal lines are electrically connected through the second reset connection line, two adjacent third reset signal lines are electrically connected through the third reset connection line, and the first reset connection line, the second reset connection line, the third reset connection line and the electrical connection line are arranged at intervals in the first direction.

11. A display device, characterized in that: The display device includes the display panel as described in any one of items 1 to 10 above.

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