Display device and manufacturing method thereof

Abstract

An embodiment of the invention discloses a display device and a method of manufacturing the same. The display device includes: a substrate including an opening area and a display area surrounding the opening area; the plurality of light emitting diodes are arranged in the display area; and a plurality of grooves in an intermediate region between the opening region and the display region, in which the plurality of grooves are defined in a multilayer film including a first organic insulating layer, a metal pattern layer on the first organic insulating layer, and a second organic insulating layer on the metal pattern layer, the second organic insulating layer covers an upper surface and a side surface of the metal pattern layer, and includes a substance having an etching selection ratio different from that of the first organic insulating layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device and a method for manufacturing the same. Background Art

[0002] Recently, the use of display devices is diversifying, and since display devices are thin and light, the range of use of display devices tends to be wide.

[0003] In display devices, various functions integrated into or associated with the display devices are being added while the area occupied by the display region is being expanded. As a technical solution for expanding the area while adding various functions, research is being conducted on display devices capable of arranging various components in the display region. Summary of the invention

[0004] Embodiments of the present invention may provide a display device having an opening area capable of arranging various kinds of components within the display area. However, such technical issues are exemplary, and the scope of the present invention is not limited thereto.

[0005] According to one aspect of the present invention, a display device is disclosed, comprising: a substrate, comprising an opening area and a display area surrounding the opening area; a plurality of light-emitting diodes arranged in the display area; and a plurality of grooves located in an intermediate area between the opening area and the display area, wherein the plurality of grooves are defined in a multilayer film, the multilayer film comprising a first organic insulating layer, a metal pattern layer on the first organic insulating layer, and a second organic insulating layer on the metal pattern layer, the second organic insulating layer covering the upper surface and side surfaces of the metal pattern layer and comprising a substance having an etching selectivity different from that of the first organic insulating layer.

[0006] In one embodiment, the metal pattern layer and the second organic insulating layer may be provided with a tip protruding from where a side surface of the first organic insulating layer intersects with a bottom surface of the metal pattern layer toward a center of the groove.

[0007] In one embodiment, the groove may be formed by overlapping the opening of the first organic insulating layer with the second organic insulating layer and the tip of the metal pattern layer.

[0008] In one embodiment, the second organic insulating layer may have a dielectric constant that is smaller than a dielectric constant of the first organic insulating layer.

[0009] In one embodiment, the second organic insulating layer may include a siloxane-based organic material having a cyclic or cage bonding structure.

[0010] In one embodiment, the bottom surface of the groove may be the upper surface of the lower layer made of an oxide-based semiconductor material.

[0011] In one embodiment, a metal dummy stack may be arranged around the groove, and the metal pattern layer may be in contact with the metal dummy stack through a hole provided in the first organic insulating layer.

[0012] In one embodiment, the metal dummy stack may include a plurality of stacked metal layers, and an insulating layer is interposed between adjacent metal layers.

[0013] In one embodiment, each of the plurality of light emitting diodes may be arranged on the substrate and may be respectively connected to a sub-pixel circuit portion, wherein the sub-pixel circuit portion includes a thin film transistor including a silicon-based semiconductor layer and a thin film transistor including an oxide-based semiconductor layer.

[0014] In one embodiment, the plurality of light emitting diodes may include: a first electrode and a second electrode; a light emitting layer between the first electrode and the second electrode; and a functional layer between the first electrode and the second electrode, wherein the functional layer and the second electrode may be disconnected or separated by the groove in the middle region.

[0015] Another aspect of the present invention discloses a method for manufacturing a display device, comprising the following steps: preparing a substrate including an opening area and a display area surrounding the opening area; forming a first organic insulating layer in an intermediate area between the opening area and the display area; forming a metal pattern layer on the first organic insulating layer in the intermediate area; forming a second organic insulating layer on the metal pattern layer in the intermediate area; forming a plurality of grooves by removing a portion of a multilayer film including the first organic insulating layer, the metal pattern layer and the second organic insulating layer; and forming a plurality of light-emitting diodes in the display area, wherein the second organic insulating layer covers the side surface and the upper surface of the metal pattern layer and includes a substance having an etching selectivity different from that of the first organic insulating layer.

[0016] In one embodiment, the step of forming the second organic insulating layer may include the following steps: forming a pre-second organic insulating layer on the first organic insulating layer and the metal pattern layer; positioning a mask on the pre-second organic insulating layer; and exposing and developing the pre-second organic insulating layer using the mask.

[0017] In one embodiment, the step of forming the plurality of grooves may include the step of using the second organic insulating layer as a mask to remove a portion of the first organic insulating layer to form an opening in the first organic insulating layer.

[0018] In an embodiment, the step of forming the opening of the first organic insulating layer may be performed by an etching process using a lower layer disposed under the first organic insulating layer as an etching stopper.

[0019] In one embodiment, the lower layer may include an oxide-based semiconductor material.

[0020] In one embodiment, the metal pattern layer and the second organic insulating layer may include a tip protruding toward the center of the groove from where a side surface of the first organic insulating layer defining the opening intersects with a bottom surface of the metal pattern layer.

[0021] In one embodiment, the second organic insulating layer may have a dielectric constant that is smaller than a dielectric constant of the first organic insulating layer.

[0022] In one embodiment, the second organic insulating layer may include a siloxane-based organic material having a cyclic or cage bonding structure.

[0023] In one embodiment, the method for manufacturing the display device may further include the step of forming a metal dummy stack arranged at the periphery of the groove, wherein the metal pattern layer may contact the metal dummy stack through a hole provided in the first organic insulating layer.

[0024] In one embodiment, the plurality of light emitting diodes may include: a first electrode and a second electrode; a light emitting layer between the first electrode and the second electrode; and a functional layer between the first electrode and the second electrode, wherein the functional layer and the second electrode may be disconnected or separated by the groove in the middle region.

[0025] The display device according to an embodiment of the present invention can reduce the number of masks used in the manufacturing process and improve productivity, while preventing external impurities such as moisture from flowing into the opening and damaging the display elements. Obviously, the scope of the present invention is not limited to this effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 FIG. 1 is a perspective view schematically showing an electronic device according to an embodiment of the present invention.

[0027] Figure 2 FIG. 1 is a schematic diagram of an electronic device according to an embodiment of the present invention. Figure 1 Cross-sectional view taken along line Ⅰ-Ⅰ'.

[0028] Figure 3 is a plan view schematically showing a display device according to an embodiment of the present invention.

[0029] Figure 4 FIG. 4 is an equivalent circuit diagram schematically showing a light emitting diode and a circuit connected to the light emitting diode according to an embodiment of the present invention.

[0030] Figure 5 FIG. 4 is an equivalent circuit diagram schematically showing a light emitting diode and a circuit connected to the light emitting diode according to an embodiment of the present invention.

[0031] Figure 6 is a plan view showing a portion of a display device according to an embodiment of the present invention.

[0032] Figure 7 is a cross-sectional view of a display device according to an embodiment of the present invention and is Figure 6 Cross-sectional view taken along line Ⅱ-Ⅱ'.

[0033] Figure 8 is a cross-sectional view of a display device according to an embodiment of the present invention and is Figure 6 Cross-sectional view taken along line III-III'.

[0034] Fig. 9 Is magnification Figure 8 Cross-sectional view of region VI.

[0035] Fig.10 is a cross-sectional view showing a portion of a display device according to an embodiment of the present invention and showing Fig. 9 A variation of .

[0036] Figures 11a to 11f is a cross-sectional view of a display device according to an embodiment of the present invention according to a manufacturing process.

[0037] Description of Reference Numerals OA: Opening area DA: Display area MA: Middle area PA: Outer area 1G: First slot 2G: Second slot 3G: Third slot 4G: Fourth slot PT: Tip PW1: First Wall PW2: second partition wall 211: first organic insulating layer 212: metal pattern layer 212s: side surface 213: Second organic insulating layer DETAILED DESCRIPTION

[0038] The present invention is susceptible to many variations and may have multiple embodiments, specific embodiments of which are illustrated in the drawings and described in detail in the detailed description. Figure 1The effects and features of the present invention and methods for achieving the effects and features can be clarified from the embodiments described in detail below. However, the present invention is not limited to the embodiments disclosed below, and can be implemented in various forms.

[0039] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. When describing with reference to the accompanying drawings, the same or corresponding components are denoted by the same reference numerals and their repeated description is omitted.

[0040] In the following embodiments, the terms "first" and "second" are not used in a limiting sense but are used for the purpose of distinguishing one constituent element from other constituent elements.

[0041] In the following embodiments, as long as other meanings are not clearly indicated in the context, expressions in the singular include expressions in the plural.

[0042] In the following embodiments, terms such as “including” or “having” indicate the presence of features or constituent elements described in the specification, and do not preclude the possibility of adding one or more other features or constituent elements.

[0043] In the following embodiments, when mentioning that a part of a film, region, component, etc. is located on or above another part, it includes not only the case where it is immediately above the other part, but also the case where other films, regions, components, etc. are interposed therebetween.

[0044] For the convenience of explanation, the size of the components in the drawings may be exaggerated or reduced. For example, for the convenience of explanation, the size and thickness of each component shown in the drawings are arbitrarily shown, and therefore the present invention is not necessarily limited to the contents shown in the drawings.

[0045] In the case where a certain embodiment can be implemented in different ways, a specific process sequence can be performed in a different order than described. For example, two processes described in succession can be performed substantially simultaneously, or in a reverse order to the described order.

[0046] In this specification, "A and / or B" means a case of A or B or A and B. Also, "at least one of A and B" means a case of A or B or A and B.

[0047] In the following embodiments, when mentioning that a film, region, component, etc. is connected, it includes not only the case where the film, region, component, etc. is directly connected, and / or the case where other films, regions, components, etc. are sandwiched between the film, region, component, and the case where they are indirectly connected. For example, in this specification, when mentioning that a film, region, component, etc. is electrically connected, it includes not only the case where the film, region, component, etc. is directly electrically connected, and / or the case where other films, regions, components, etc. are sandwiched between them and the case where they are indirectly electrically connected.

[0048] The x-axis, y-axis, and z-axis are not limited to the three axes on the rectangular coordinate system, and can be interpreted as including a broad meaning thereof. For example, the x-axis, y-axis, and z-axis can also be orthogonal, but can also refer to different directions that are not orthogonal to each other.

[0049] Figure 1 FIG. 1 is a perspective view schematically showing an electronic device according to an embodiment of the present invention.

[0050] Reference Figure 1 As a device for displaying moving images or still images, the electronic device 1 can be used not only as a display screen of portable electronic devices such as mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic notepads, electronic books, portable multimedia players (PMP: portable multimedia player), navigation devices, ultra mobile personal computers (UMPC: Ultra Mobile PC), etc., but also as a display screen of various products such as televisions, notebook computers, monitors, billboards, and Internet of Things (IOT: internet of things) devices. In addition, the electronic device 1 according to an embodiment can be used as a wearable device such as a smart watch, a watch phone, a glasses-type display, and a head mounted display (HMD: head mounted display). In addition, the electronic device 1 according to an embodiment can be used as a dashboard of a vehicle and a center fascia of a vehicle or a center information display (CID: Center Information Display) arranged on the dashboard, a room mirror display instead of a side mirror of a vehicle, and a display arranged on the back of a front seat as a rear seat entertainment for a vehicle. For ease of explanation, Figure 1 FIG. 4 shows a case where the electronic device 1 according to an embodiment is used as a smart phone.

[0051] The electronic device 1 may be formed in a rectangular shape on a plane. Figure 1 The plane shape of the electronic device 1 is a rectangle with short sides in the x direction and long sides in the y direction. The corner where the short side in the x direction intersects the long side in the y direction can be formed smoothly with a predetermined curvature, or can be formed as a right angle. The plane shape of the electronic device 1 is not limited to a rectangle, and can be formed into other polygonal, elliptical or irregular shapes.

[0052] The electronic device 1 may include an opening area OA and a display area DA at least surrounding the opening area OA. The electronic device 1 may include an intermediate area MA located between the opening area OA and the display area DA and an outer contour area PA surrounding the outside of the display area DA (e.g., the display area DA). The intermediate area MA may have a closed loop shape that surrounds the opening area OA as a whole on a plane.

[0053] The opening area OA may be located inside the display area DA. Figure 1 As shown, the opening area OA may be arranged in the middle of the upper side of the display area DA. Alternatively, the opening area OA may be arranged in various ways, for example, it may be arranged on the upper left side of the display area DA or on the upper right side of the display area DA. Figure 1 2 shows a case where one opening area OA is arranged, but as another embodiment, a plurality of opening areas OA may be provided.

[0054] Figure 2 FIG. 1 is a schematic diagram of an electronic device according to an embodiment of the present invention. Figure 1 Cross-sectional view taken along line Ⅰ-Ⅰ'.

[0055] Reference Figure 2 The electronic device 1 may include a display device 10 and a component 70 disposed in an opening area OA of the display device 10. The display device 10 and the component 70 may be accommodated in a housing HS.

[0056] The display device 10 may include an image generation layer 20 , an input sensing layer 40 , an optical function layer 50 , and a cover window 60 .

[0057] The image generation layer 20 may include a display element that emits light to display an image. The display element may include a light emitting diode, such as an organic light emitting diode including an organic light emitting layer. As another embodiment, the light emitting diode may be an inorganic light emitting diode including an inorganic substance. The inorganic light emitting diode may include a PN junction diode including an inorganic semiconductor material. If a forward voltage is applied to the PN junction diode, holes and electrons may be injected, and the energy generated by the recombination of holes and electrons may be converted into light energy, thereby emitting light of a predetermined color. The aforementioned inorganic light emitting diode may have a width of several micrometers to several hundred micrometers or several nanometers to several hundred nanometers. In some embodiments, the image generation layer 20 may include a quantum dot light emitting diode. For example, the light emitting layer of the image generation layer 20 may include organic matter, inorganic matter, quantum dots, organic matter and quantum dots, or inorganic matter and quantum dots.

[0058] The input sensing layer 40 may obtain coordinate information based on external input (e.g., a touch event). The input sensing layer 40 may include a touch electrode (sensing electrode or touch electrode) and a trace line connected to the touch electrode. The input sensing layer 40 may be arranged on the image generation layer 20. The input sensing layer 40 may sense external input in a mutual capacitance manner or / and a self-capacitance manner.

[0059] The input sensing layer 40 may be directly formed on the image generating layer 20, or may be formed separately and then bonded via an adhesive layer such as an optically transparent adhesive. For example, the input sensing layer 40 may be formed continuously after the process of forming the image generating layer 20, in which case the adhesive layer may not be interposed between the input sensing layer 40 and the image generating layer 20. Figure 2 A case where the input sensing layer 40 is interposed between the image generating layer 20 and the optical function layer 50 is shown, but as another embodiment, the input sensing layer 40 may be disposed on the optical function layer 50 .

[0060] The optical function layer 50 may include a reflection prevention layer. The reflection prevention layer may reduce the reflectivity of light (external light) incident from the outside to the display device 10 through the cover window 60. The reflection prevention layer may include a phase retarder and a polarizer. As another embodiment, the reflection prevention layer may include a black matrix and a color filter. The color filter may be arranged by considering the color of light emitted from each of the light emitting diodes of the image generation layer 20.

[0061] In order to improve the transmittance of the opening area OA, the display device 10 may include an opening 10OP that passes through a portion of the layers constituting the display device 10. The opening 10OP may include a first opening 20OP, a second opening 40OP, and a third opening 50OP that respectively pass through the image generation layer 20, the input sensing layer 40, and the optical function layer 50. The first opening 20OP of the image generation layer 20, the second opening 40OP of the input sensing layer 40, and the third opening 50OP of the optical function layer 50 may overlap to form the opening 10OP of the display device 10.

[0062] The cover window 60 may be disposed on the optical function layer 50. The cover window 60 may be bonded by an adhesive layer such as an optical clear adhesive (OCA) interposed between the cover window 60 and the optical function layer 50. The cover window 60 may cover the first opening 20OP of the image generation layer 20, the second opening 40OP of the input sensing layer 40, and the third opening 50OP of the optical function layer 50.

[0063] The cover window 60 may include a glass material or a plastic material. The glass material may include ultra-thin glass. The plastic material may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose acetate propionate, etc.

[0064] The opening area OA may be a component area (eg, a sensor area, a camera area, a speaker area, etc.) where a component 70 for imparting various functions to the electronic device 1 is located.

[0065] Component 70 may include an electronic element. For example, component 70 may be an electronic element that utilizes light or sound. For example, the electronic element may include a sensor that utilizes light, such as an infrared sensor, a camera that captures an image by receiving light, a sensor that measures distance or recognizes fingerprints by outputting and sensing light or sound, a small lamp that outputs light, or a speaker that outputs sound. The electronic element that utilizes light may utilize light of multiple wavelength bands, such as visible light, infrared light, and ultraviolet light. The opening area OA corresponds to an area that is output from component 70 to the outside, or corresponds to an area where light and / or sound traveling from the outside toward the electronic element can be transmitted.

[0066] Figure 3 is a plan view schematically showing a display device according to an embodiment of the present invention.

[0067] The display device 10 may include a plurality of sub-pixels PX arranged in the display area DA, and the display device 10 may display an image using light emitted from each sub-pixel PX. Each sub-pixel PX may emit red light, green light, or blue light using a light emitting diode. The light emitting diode of each sub-pixel PX may be electrically connected to the scan line SL and the data line DL.

[0068] In the outer contour area PA, a scan driver 2100 for providing scan signals to each sub-pixel PX, a data driver 2200 for providing data signals to each sub-pixel PX, a first main power wiring (not shown) and a second power wiring (not shown) for providing a first power voltage (e.g., a driving voltage) and a second power voltage (e.g., a common voltage) may be arranged. The scan driver 2100 may be arranged on both sides of the display area DA, respectively. In this case, the sub-pixel PX arranged on the left side with the opening area OA as the center is connected to the scan driver 2100 arranged on the left side, and the sub-pixel PX arranged on the right side with the opening area OA as the center is connected to the scan driver 2100 arranged on the right side.

[0069] The middle area MA may surround the opening area OA. The middle area MA is an area where display elements such as light-emitting diodes that emit light are not arranged, and signal lines that provide signals to sub-pixels PX provided around the opening area OA may pass through the middle area MA. For example, the data line DL and / or the scan line SL may cross the display area DA, and a portion of the data line DL and / or the scan line SL may meander in the middle area MA along the edge of the opening 10OP of the display device 10 formed in the opening area OA. As an embodiment, Figure 3 The data lines DL traverse the display area DA along the y direction and some of the data lines DL meander in the middle area MA in a manner partially surrounding the opening area OA. The scan lines SL may traverse the display area DA along the x direction and may be spaced apart from each other with the opening area OA interposed therebetween.

[0070] Despite Figure 3 , the data driver 2200 is arranged adjacent to one side of the substrate, but according to another embodiment, the data driver 2200 may be arranged on a circuit board (e.g., a printed circuit board) electrically connected to a pad arranged on one side of the display device 10. The circuit board may have flexibility, and a portion of the circuit board may be bent to be located below the rear surface of the substrate 100.

[0071] Figure 4 and Figure 5 FIG. 4 is an equivalent circuit diagram schematically showing a light emitting diode and a circuit connected to the light emitting diode according to an embodiment of the present invention.

[0072] Reference Figure 4 , one sub-pixel PX may include a sub-pixel circuit PC and an organic light emitting diode OLED as a display element electrically connected to the sub-pixel circuit PC.

[0073] As an example, the sub-pixel circuit PC may include a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, a seventh thin film transistor T7 and a first capacitor Cst. However, the present invention is not limited thereto.

[0074] The first thin film transistor T1 may be a driving transistor, the second thin film transistor T2 may be a switching transistor, the third thin film transistor T3 may be a compensation transistor, the fourth thin film transistor T4 may be a first initialization transistor, the fifth thin film transistor T5 may be a light emitting control transistor, the sixth thin film transistor T6 may be a light emitting control transistor, and the seventh thin film transistor T7 may be a second initialization transistor.

[0075] The organic light emitting diode OLED may include a sub-pixel electrode and a counter electrode, the sub-pixel electrode of the organic light emitting diode OLED may connect the sixth thin film transistor T6 to the first thin film transistor T1 as a medium to receive the driving current Ioled, and the counter electrode may receive the common voltage ELVSS. The organic light emitting diode OLED may generate light of brightness corresponding to the driving current Ioled.

[0076] In one embodiment, the first to seventh thin film transistors T1 to T7 may all be PMOS transistors. The first to seventh thin film transistors T1 to T7 may include amorphous silicon or polycrystalline silicon.

[0077] The signal line may include a first scan line SL1, a previous scan line SLp, a next scan line SLn, a light emitting control line EL, and a data line DL. However, the present invention is not limited thereto. Furthermore, the first scan line SL1 may transmit a first scan signal Sn. The previous scan line SLp may transmit a previous scan signal Sn-1 to a fourth thin film transistor T4. The next scan line SLn may transmit a next scan signal Sn+1 to a seventh thin film transistor T7. The light emitting control line EL may transmit a light emitting control signal EM to a fifth thin film transistor T5 and a sixth thin film transistor T6. The data line DL may output a data signal DATA.

[0078] The driving voltage line PL can transmit the driving voltage ELVDD to the first thin film transistor T1, and the initialization voltage line VIL can transmit the initialization voltage VINT for initializing the first thin film transistor T1 and the organic light emitting diode OLED to the sub-pixel PX. Specifically, the first initialization voltage line VIL1 can transmit the initialization voltage VINT to the fourth thin film transistor T4, and the second initialization voltage line VIL2 can transmit the initialization voltage VINT to the seventh thin film transistor T7.

[0079] The gate electrode of the first thin film transistor T1 may be connected to the first capacitor Cst, one of the source region and the drain region of the first thin film transistor T1 may be connected to the driving voltage line PL via the first node N1 via the fifth thin film transistor T5, and the other of the source region and the drain region of the first thin film transistor T1 may be electrically connected to the sub-pixel electrode of the organic light emitting diode OLED via the sixth thin film transistor T6. The first thin film transistor T1 may receive the data signal DATA according to the switching operation of the second thin film transistor T2 to supply the driving current Ioled to the organic light emitting diode OLED.

[0080] The gate electrode of the second thin film transistor T2 may be connected to the first scan line SL1 transmitting the first scan signal Sn, and one of the source region and the drain region of the second thin film transistor T2 may be connected to the data line DL, and the other of the source region and the drain region of the second thin film transistor T2 may be connected to the first thin film transistor T1 through the first node N1 and connected to the driving voltage line PL through the fifth thin film transistor T5. The second thin film transistor T2 may perform a switching operation of being turned on according to the first scan signal Sn received through the first scan line SL1 to transmit the data signal DATA transmitted to the data line DL to the first thin film transistor T1 through the first node N1.

[0081] The gate electrode of the third thin film transistor T3 may be connected to the first scan line SL1. One of the source region and the drain region of the third thin film transistor T3 may be connected to the sub-pixel electrode of the organic light emitting diode OLED via the sixth thin film transistor T6. The other of the source region and the drain region of the third thin film transistor T3 may be connected to the first capacitor Cst and the gate electrode of the first thin film transistor T1. The third thin film transistor T3 may be turned on according to the first scan signal Sn received through the first scan line SL1 to make the first thin film transistor T1 diode-connected.

[0082] The gate electrode of the fourth thin film transistor T4 may be connected to the previous scan line SLp. One of the source region and the drain region of the fourth thin film transistor T4 may be connected to the first initialization voltage line VIL1. The other of the source region and the drain region of the fourth thin film transistor T4 may be connected to the first capacitor electrode CE1 (refer to Figure 5 ) and the gate electrode of the first thin film transistor T1. The fourth thin film transistor T4 can be turned on according to the previous scan signal Sn-1 received through the previous scan line SLp to transmit the initialization voltage VINT to the gate electrode of the first thin film transistor T1, thereby performing an initialization operation of initializing the voltage of the gate electrode of the first thin film transistor T1.

[0083] The gate electrode of the fifth thin film transistor T5 can be connected to the light emitting control line EL, and one of the source and drain regions of the fifth thin film transistor T5 can be connected to the driving voltage line PL, and the other region can be connected to the first thin film transistor T1 and the second thin film transistor T2 through the first node N1.

[0084] The gate electrode of the sixth thin film transistor T6 can be connected to the light emitting control line EL, and one of the source region and the drain region of the sixth thin film transistor T6 can be connected to the first thin film transistor T1 and the third thin film transistor T3, and the other of the source region and the drain region of the sixth thin film transistor T6 can be electrically connected to the sub-pixel electrode of the organic light emitting diode OLED.

[0085] The fifth and sixth thin film transistors T5 and T6 may be turned on simultaneously according to the emission control signal EM received through the emission control line EL, so that the driving voltage ELVDD may be transmitted to the organic light emitting diode OLED and the driving current Ioled may flow through the organic light emitting diode OLED.

[0086] The gate electrode of the seventh thin film transistor T7 can be connected to the next scan line SLn, one of the source region and the drain region of the seventh thin film transistor T7 can be connected to the sub-pixel electrode of the organic light emitting diode OLED, and the other of the source region and the drain region of the seventh thin film transistor T7 can be connected to the second initialization voltage line VIL2 to receive the initialization voltage VINT. The seventh thin film transistor T7 can be turned on according to the next scan signal Sn+1 received through the next scan line SLn to initialize the sub-pixel electrode of the organic light emitting diode OLED. The next scan line SLn can be the same as the first scan line SL1. In this case, the relevant scan lines can transmit the same electrical signal at a time difference, so they can function as the first scan line SL1 or the next scan line SLn. In some embodiments, the seventh thin film transistor T7 can be omitted.

[0087] The first capacitor Cst may be connected to the driving voltage line PL and the gate electrode of the first thin film transistor T1 , and maintain a voltage applied to the gate electrode of the first thin film transistor T1 by storing and maintaining a voltage corresponding to a voltage difference between both ends.

[0088] The specific operations of the sub-pixel circuit PC and the organic light emitting diode OLED as a display element according to an embodiment are as follows.

[0089] During the initialization period, if a previous scan signal Sn-1 is supplied through the previous scan line SLp, the fourth thin film transistor T4 is turned on corresponding to the previous scan signal Sn-1, and the first thin film transistor T1 may be initialized by the initialization voltage VINT supplied from the first initialization voltage line VIL1.

[0090] During the data programming period, if the first scan signal Sn is supplied through the first scan line SL1, the second thin film transistor T2 and the third thin film transistor T3 may be turned on corresponding to the first scan signal Sn. At this time, the first thin film transistor T1 may be diode-connected through the turned-on third thin film transistor T3 and may be forward biased. In this way, a compensation voltage (DATA+Vth, Vth is a negative (-) value) obtained by subtracting the threshold voltage (Vth, Threshold voltage) of the first thin film transistor T1 from the data signal DATA supplied from the data line DL may be applied to the gate electrode of the first thin film transistor T1. The driving voltage ELVDD and the compensation voltage (DATA+Vth) may be applied to both ends of the first capacitor Cst, and charges corresponding to the voltage difference between the two ends may be stored in the first capacitor Cst.

[0091] During the light emission period, the fifth thin film transistor T5 and the sixth thin film transistor T6 may be turned on by the light emission control signal EM supplied from the light emission control line EL. A driving current Ioled according to a voltage difference between a voltage of the gate electrode of the first thin film transistor T1 and the driving voltage ELVDD is generated, and the driving current Ioled may be supplied to the organic light emitting diode OLED through the sixth thin film transistor T6.

[0092] Reference Figure 5 The sub-pixel PX may include a sub-pixel circuit PC and an organic light emitting diode OLED as a display element. The sub-pixel circuit PC may include first to seventh thin film transistors T1 to T7, a first capacitor Cst, and a second capacitor Cbt.

[0093] Some of the first to seventh thin film transistors T1 to T7 may be n-channel metal oxide semiconductor field effect (NMOS: n-channel MOSFET) transistors, and the remaining thin film transistors may be p-channel metal oxide semiconductor field effect (PMOS: p-channel MOSFET) transistors. Figure 5 As shown, the third thin film transistor T3 and the fourth thin film transistor T4 among the first thin film transistor T1 to the seventh thin film transistor T7 may be NMOS transistors, and the remaining thin film transistors may be PMOS transistors. Alternatively, the third thin film transistor T3, the fourth thin film transistor T4 and the seventh thin film transistor T7 among the first thin film transistor T1 to the seventh thin film transistor T7 may be NMOS transistors, and the remaining thin film transistors may be PMOS transistors. Alternatively, the first thin film transistor T1 to the seventh thin film transistor T7 may all be NMOS transistors.

[0094] The signal lines include a first scan line SL1 for transmitting a first scan signal Sn', a second scan line SL2 for transmitting a second scan signal Sn'', a previous scan line SLp for transmitting a previous scan signal Sn-1 to a fourth thin film transistor T4, a light emitting control line EL for transmitting a light emitting control signal EM to a fifth thin film transistor T5 and a sixth thin film transistor T6, a subsequent scan line SLn for transmitting a subsequent scan signal Sn+1 to a seventh thin film transistor T7, and a data line DL for transmitting a data signal DATA.

[0095] The first thin film transistor T1 may be connected to the driving voltage line PL via the fifth thin film transistor T5 and may be electrically connected to the organic light emitting diode OLED via the sixth thin film transistor T6. The first thin film transistor T1 may receive the data signal DATA according to the switching operation of the second thin film transistor T2 to supply the driving current Ioled to the organic light emitting diode OLED.

[0096] The second thin film transistor T2 may be connected to the first scan line SL1 and the data line DL, and may be connected to the driving voltage line PL via the fifth thin film transistor T5. The second thin film transistor T2 may be turned on according to the first scan signal Sn' received through the first scan line SL1 to transmit the data signal DATA transmitted from the data line DL to the first node N1.

[0097] The third thin film transistor T3 is connected to the second scan line SL2 and is connected to the organic light emitting diode OLED via the sixth thin film transistor T6. The third thin film transistor T3 can be turned on according to the second scan signal Sn'' received through the second scan line SL2 to compensate the threshold voltage of the first thin film transistor T1 by making the first thin film transistor T1 diode-connected.

[0098] The fourth thin film transistor T4 is connected to the previous scan line SLp and the first initialization voltage line VIL1, and is turned on according to the previous scan signal Sn-1 received through the previous scan line SLp to transmit the initialization voltage VINT from the first initialization voltage line VIL1 to the gate electrode of the first thin film transistor T1, thereby initializing the voltage of the gate electrode of the first thin film transistor T1.

[0099] The fifth thin film transistor T5 and the sixth thin film transistor T6 may be connected to the emission control line EL and may be simultaneously turned on according to the emission control signal EM received through the emission control line EL to form a current path for allowing the driving current Ioled to flow from the driving voltage line PL to the organic light emitting diode OLED.

[0100] The seventh thin film transistor T7 is connected to the subsequent scan line SLn and the second initialization voltage line VIL2, and is turned on by the subsequent scan signal Sn+1 received by the subsequent scan line SLn to transmit the initialization voltage VINT from the second initialization voltage line VIL2 to the organic light emitting diode OLED, thereby initializing the organic light emitting diode OLED. The seventh thin film transistor T7 may be omitted.

[0101] The first capacitor Cst includes a first capacitor electrode CE1 and a second capacitor electrode CE2. The first capacitor electrode CE1 may be connected to the gate electrode of the first thin film transistor T1, and the second capacitor electrode CE2 may be connected to the driving voltage line PL. The first capacitor Cst may maintain a voltage applied to the gate electrode of the first thin film transistor T1 by storing and maintaining a voltage corresponding to a voltage difference between the driving voltage line PL and the gate electrode of the first thin film transistor T1.

[0102] The second capacitor Cbt includes a third capacitor electrode CE3 and a fourth capacitor electrode CE4. The third capacitor electrode CE3 can be connected to the first scan line SL1 and the gate electrode of the second thin film transistor T2. The fourth capacitor electrode CE4 can be connected to the gate electrode of the first thin film transistor T1 and the first capacitor electrode CE1 of the first capacitor Cst. The second capacitor Cbt acts as a boost capacitor and can clearly present a black grayscale by increasing the voltage of the second node N2 when the first scan signal Sn' of the first scan line SL1 is a voltage that turns off the second thin film transistor T2.

[0103] In an embodiment, at least one of the first to seventh thin film transistors T1 to T7 may include a semiconductor layer including oxide, and the remaining thin film transistors may include a semiconductor layer including amorphous silicon or polycrystalline silicon.

[0104] Specifically, the first thin film transistor T1 as a driving transistor directly affecting the brightness of the display device 10 can be configured to include a semiconductor layer made of polycrystalline silicon with high reliability, thereby realizing a high-resolution display device.

[0105] In addition, since oxide semiconductors have high carrier mobility and low leakage current, voltage drop is not large even when driven for a long time. That is, even when driven at a low frequency, the color change of the image caused by voltage drop is not large, so low-frequency driving is possible.

[0106] Such an oxide semiconductor has the advantage of less leakage current. Therefore, an oxide semiconductor is used for at least one of the third thin film transistor T3 and the fourth thin film transistor T4 connected to the gate electrode of the first thin film transistor T1, thereby preventing leakage current from flowing to the gate electrode of the first thin film transistor T1 and reducing power consumption.

[0107] The sub-pixel circuit PC is not limited to the reference Figure 4 and Figure 5 The number of thin film transistors and capacitors and the circuit design described above can be variously changed.

[0108] Figure 6 is a plan view showing a portion of a display device according to an embodiment of the present invention.

[0109] Reference Figure 6 , the sub-pixels PX adjacent to the opening area OA can be arranged on a plane with the opening area OA as the center and spaced from each other. The sub-pixels PX can be arranged with the opening area OA as the center and spaced from each other up and down, or can be arranged with the opening area OA as the center and spaced from each other left and right. Each sub-pixel PX uses the red light, green light, and blue light emitted from the light emitting diode, Figure 6 The positions of the sub-pixels PX shown correspond to the positions of the respective light emitting diodes. Therefore, the sub-pixels PX are arranged spaced apart from each other on a plane with the opening area OA as the center, which can mean that the light emitting diodes are arranged spaced apart from each other on a plane with the opening area OA as the center. For example, on a plane, the light emitting diodes can be arranged spaced apart from each other up and down with the opening area OA as the center, or spaced apart from each other left and right with the opening area OA as the center.

[0110] In the signal line that supplies signals to the sub-pixel circuit of the light-emitting diode connected to each sub-pixel PX, the signal line adjacent to the opening area OA may detour the opening area OA and / or the opening 10OP. For example, the detour portion DL-C1 of at least one of the data lines DL may be formed on different layers from the extension portion DL-L1 that crosses the display area DA, and the detour portion DL-C1 and the extension portion DL-L1 of the data line DL may be connected through the contact hole CNT. The detour portion DL-C2 of at least one of the data lines DL may be located on the same layer as the extension portion DL-L2, and may be formed as one body with the extension portion DL-L2.

[0111] exist Figure 6 FIG. 4 shows a case where the scan line SL detours around the opening area OA and / or the opening 10OP in the middle area MA, but the present invention is not limited thereto. As another embodiment, the scan line SL may be separated or disconnected with the opening area OA as the center, as shown in FIG. Figure 3As described above, the scan line SL arranged on the left side with the opening area OA as the center can receive a signal from the scan driver 2100 arranged on the left side, and the scan line SL arranged on the right side of the opening area OA can receive a signal from the above Figure 3 The right scan driver 2100 of the display area DA is shown receiving the signal.

[0112] In the middle area MA, the partition wall PW may be located between the area where the data line DL meanders and the opening area OA. The partition wall PW may include a first partition wall PW1 and a second partition wall PW2 outside the first partition wall PW1. On a plane, each of the partition walls PW may be in a closed-loop shape surrounding the opening area OA, and the partition walls PW may be arranged to be spaced apart from each other.

[0113] Figure 7 is a cross-sectional view of a display device according to an embodiment of the present invention and is Figure 6 Cross-sectional view taken along line Ⅱ-Ⅱ'.

[0114] Reference Figure 7 The substrate 100 may include a glass material or a polymer resin. As an embodiment, the substrate 100 may have an alternating stacking structure of a base material layer including a polymer resin and a barrier layer including an inorganic insulator such as silicon oxide or silicon oxynitride. The polymer resin may include a polymer resin such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, etc.

[0115] A sub-pixel circuit PC may be formed on the substrate 100 , and a light emitting diode (eg, an organic light emitting diode OLED) may be arranged on the sub-pixel circuit PC.

[0116] Before forming the sub-pixel circuit PC, a buffer layer 201 for preventing impurities from penetrating into the sub-pixel circuit PC may be formed on the substrate 100. The buffer layer 201 may include inorganic insulators such as silicon nitride, silicon oxynitride, and silicon oxide, and may include a single layer or multilayer structure including the above inorganic insulators.

[0117] The sub-pixel circuit PC may include the Figure 5 The plurality of transistors and capacitors. In this regard, Figure 7 A first thin film transistor T1 , a third thin film transistor T3 , and a first capacitor Cst are shown.

[0118] The first thin film transistor T1 may include a semiconductor layer (hereinafter referred to as the first semiconductor layer) A1 on the buffer layer 201 and a gate electrode (hereinafter referred to as the first gate electrode) GE1 overlapping the channel region C1 of the first semiconductor layer A1. The first semiconductor layer A1 may include a silicon-based semiconductor material (e.g., polycrystalline silicon). The first semiconductor layer A1 may include a channel region C1 and a first region B1 and a second region D1 arranged on both sides of the channel region C1. The first region B1 and the second region D1 may be regions including impurities having a higher concentration than the channel region C1, one of the first region B1 and the second region D1 may correspond to a source region, and the other region may correspond to a drain region.

[0119] A first gate insulating layer 203 may be disposed between the first semiconductor layer A1 and the first gate electrode GE1. The first gate insulating layer 203 may include an inorganic insulator such as silicon oxide, silicon nitride, or silicon oxynitride, and may include a single layer or a multilayer structure including the inorganic insulator.

[0120] The first gate electrode GE1 may include a conductive substance including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single-layer or multi-layer structure including the above substances.

[0121] The first capacitor Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2 that overlap each other. The second capacitor electrode CE2 may be arranged on the first capacitor electrode CE1. As an embodiment, the first capacitor electrode CE1 of the first capacitor Cst may include a first gate electrode GE1. In other words, the first gate electrode GE1 may include the first capacitor electrode CE1 of the first capacitor Cst. For example, the first gate electrode GE1 and the first capacitor electrode CE1 of the first capacitor Cst may be formed as one body.

[0122] A first interlayer insulating layer 205 may be disposed between the first capacitor electrode CE1 and the second capacitor electrode CE2 of the first capacitor Cst. The first interlayer insulating layer 205 may include an inorganic insulator such as silicon oxide, silicon nitride, or silicon oxynitride, and may include a single layer or a multilayer structure including the inorganic insulator.

[0123] The second capacitor electrode CE2 of the first capacitor Cst may include a low-resistance conductive substance such as molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may include a single-layer or multi-layer structure composed of the above substances.

[0124] A second interlayer insulating layer 207 may be disposed on the first capacitor Cst. The second interlayer insulating layer 207 may include an inorganic insulator such as silicon oxide, silicon nitride, silicon oxynitride, and may include a single layer or multilayer structure including the inorganic insulator.

[0125] The semiconductor layer (hereinafter referred to as the third semiconductor layer) A3 of the third thin film transistor T3 may be arranged on the second interlayer insulating layer 207. The third semiconductor layer A3 may include an oxide-based semiconductor material. For example, the third semiconductor layer A3 may be formed using a Zn oxide-based material (e.g., Zn oxide, In-Zn oxide, Ga-In-Zn oxide, etc.). In some embodiments, the third semiconductor layer A3 may be an IGZO (In-Ga-Zn-O) semiconductor, an ITZO (In-Sn-Zn-O) semiconductor, or an IGTZO (In-Ga-Sn-Zn-O) semiconductor containing metals such as indium (In), gallium (Ga), and tin Sn in ZnO.

[0126] The third semiconductor layer A3 may include a channel region C3 and first and second regions B3 and D3 disposed on both sides of the channel region C3. One of the first and second regions B3 and D3 may correspond to a source region, and the other may correspond to a drain region.

[0127] The third thin film transistor T3 may include a gate electrode (hereinafter referred to as a third gate electrode) GE3 overlapping the channel region C3 of the third semiconductor layer A3. The third gate electrode GE3 may have a double gate structure including a lower gate electrode G3A disposed below the third semiconductor layer A3 and an upper gate electrode G3B disposed above the channel region C3.

[0128] The lower gate electrode G3A may be disposed on the same layer (eg, the first interlayer insulating layer 205 ) as the second capacitor electrode CE2 of the first capacitor Cst. The lower gate electrode G3A may include the same material as the second capacitor electrode CE2 of the first capacitor Cst.

[0129] The upper gate electrode G3B may be disposed on the third semiconductor layer A3 with the second gate insulating layer 209 interposed therebetween. The second gate insulating layer 209 may include an inorganic insulator such as silicon oxide, silicon nitride, silicon oxynitride, and may include a single layer or multilayer structure including the above inorganic insulator.

[0130] The third interlayer insulating layer 210 may be disposed on the upper gate electrode G3B. The third interlayer insulating layer 210 may include an inorganic insulator such as silicon oxynitride, and may include a single layer or a multilayer structure including the above-described inorganic insulator.

[0131] Figure 7 Shown is a reference Figure 5 The first thin film transistor T1 and the third thin film transistor T3 among the plurality of thin film transistors are described, and the first semiconductor layer A1 and the third semiconductor layer A3 are arranged on different layers from each other, but the present invention is not limited thereto.

[0132] Reference Figure 5 The second thin film transistor T2, the fifth thin film transistor T5, the sixth thin film transistor T6 and the seventh thin film transistor T7 described above may have the same Figure 7 For example, the second thin film transistor T2, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7 may include a semiconductor layer arranged on the same layer as the first semiconductor layer A1 of the first thin film transistor T1, and a gate electrode arranged on the same layer as the first gate electrode GE1 of the first thin film transistor T1.

[0133] Reference Figure 5 The fourth thin film transistor T4 described above may have the same Figure 7 For example, the fourth thin film transistor T4 may include a semiconductor layer arranged on the same layer as the third semiconductor layer A3 of the third thin film transistor T3 and a gate electrode formed on the same layer as the third gate electrode GE3 of the third thin film transistor T3. In one embodiment, the semiconductor layer of the fourth thin film transistor T4 and the third semiconductor layer A3 of the third thin film transistor T3 may be connected as one.

[0134] The first thin film transistor T1 and the third thin film transistor T3 may be electrically connected through a node connection line 166. The node connection line 166 may be disposed on the third interlayer insulating layer 210. One side of the node connection line 166 may be connected to the first gate electrode GE1 of the first thin film transistor T1, and the other side of the node connection line 166 may be connected to the third semiconductor layer A3 of the third thin film transistor T3.

[0135] The node connection line 166 may include aluminum (Al), copper (Cu) and / or titanium (Ti), and may be formed as a single layer or multiple layers including the above substances. For example, the node connection line 166 may have a three-layer structure of titanium layer / aluminum layer / titanium layer.

[0136] The first organic insulating layer 211 may be disposed on the node connection line 166 .

[0137] The data line DL and the driving voltage line PL may be disposed on the first organic insulating layer 211 and may be covered by the second organic insulating layer 213. The data line DL and the driving voltage line PL may include aluminum (Al), copper (Cu) and / or titanium (Ti), and may be formed as a single layer or multiple layers including the above substances. For example, the data line DL and the driving voltage line PL may have a three-layer structure of titanium layer / aluminum layer / titanium layer.

[0138] Figure 7 The data line DL and the driving voltage line PL are arranged on the first organic insulating layer 211 , but the present invention is not limited thereto. As another embodiment, one of the data line DL and the driving voltage line PL may be arranged on the same layer as the node connection line 166 .

[0139] A light emitting diode (eg, an organic light emitting diode OLED) may be disposed on the second organic insulating layer 213 .

[0140] The sub-pixel electrode 221 of the organic light emitting diode OLED may include a reflective film containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound thereof. As another embodiment, the sub-pixel electrode 221 may further include a conductive oxide layer above and / or below the above-mentioned reflective film. The conductive oxide layer may include indium tin oxide (ITO: indium tin oxide), indium zinc oxide (IZO: indium zinc oxide), zinc oxide (ZnO: zinc oxide), indium oxide (In 2 O 3 : indium oxide), indium gallium oxide (IGO: indiumgallium oxide) and / or aluminum zinc oxide (AZO: aluminum zinc oxide). As an embodiment, the sub-pixel electrode 221 may have a three-layer structure of ITO layer / Ag layer / ITO layer.

[0141] The bank layer 215 may be disposed on the sub-pixel electrode 221. The bank layer 215 may include an opening overlapping the sub-pixel electrode 221, and may cover an edge of the sub-pixel electrode 221. The bank layer 215 may include an organic insulator.

[0142] The intermediate layer 222 includes a light emitting layer 222b. The intermediate layer 222 may include a first functional layer 222a disposed below the light emitting layer 222b and / or a second functional layer 222c disposed above the light emitting layer 222b. The light emitting layer 222b may include a high molecular weight or low molecular weight organic substance that emits light of a predetermined color. The second functional layer 222c may include an electron transport layer (ETL: Electron Transport Layer) and / or an electron injection layer (EIL: Electron Injection Layer). The first functional layer 222a and the second functional layer 222c may include organic substances.

[0143] The counter electrode 223 may be formed of a conductive material having a low work function. For example, the counter electrode 223 may include a (semi) transparent layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Alternatively, the counter electrode 223 may also include a (semi) transparent layer containing the above-mentioned substances such as ITO, IZO, ZnO, or In 2 O 3 Such layers.

[0144] The light emitting layer 222b may be formed on the display area DA to overlap the subpixel electrode 221 through the opening of the bank layer 215. In contrast, the first and second functional layers 222a and 222c and the opposing electrode 223 may extend to be located in the middle area MA as well as the display area DA.

[0145] A spacer 217 may be formed on the bank layer 215. The spacer 217 may be formed together with the bank layer 215 in the same process, or may be formed separately in a separate process. As an embodiment, the spacer 217 may include an organic insulator such as polyimide.

[0146] The organic light emitting diode OLED may be covered by an encapsulation layer 300. The encapsulation layer 300 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. Figure 7 The encapsulation layer 300 is shown to include a first inorganic encapsulation layer 310 and a second inorganic encapsulation layer 330 and an organic encapsulation layer 320 interposed therebetween.

[0147] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include one or more inorganic substances selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be a single layer or multiple layers including the above substances. The organic encapsulation layer 320 may include a polymer-based substance. The polymer-based material may include acrylic resin, epoxy resin, polyimide resin, polyethylene resin, etc. As an embodiment, the organic encapsulation layer 320 may include acrylate.

[0148] The thicknesses of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be different from each other. The thickness of the first inorganic encapsulation layer 310 may be greater than the thickness of the second inorganic encapsulation layer 330. Alternatively, the thickness of the second inorganic encapsulation layer 330 may be greater than the thickness of the first inorganic encapsulation layer 310, or the thicknesses of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be the same as each other.

[0149] The display device 10 may include an image generating layer 20 including a substrate 100 , a circuit-diode layer 200 and an encapsulation layer 300 , and an input sensing layer 40 on the image generating layer 20 , wherein the circuit-diode layer 200 includes a sub-pixel circuit PC and a light-emitting diode arranged on the substrate 100 .

[0150] The input sensing layer 40 may include a first touch insulating layer 401 arranged on the second inorganic encapsulation layer 330 , a first conductive layer 402 on the first touch insulating layer 401 , a second touch insulating layer 403 on the first conductive layer 402 , a second conductive layer 404 on the second touch insulating layer 403 , and a third touch insulating layer 405 on the second conductive layer 404 .

[0151] The first touch insulating layer 401, the second touch insulating layer 403, and the third touch insulating layer 405 may include an inorganic insulator and / or an organic insulator, respectively. As an embodiment, the first touch insulating layer 401 and the second touch insulating layer 403 may include an inorganic insulator such as silicon oxide, silicon nitride, and / or silicon oxynitride, and the third touch insulating layer 405 may include an organic insulator.

[0152] The touch electrode TE of the input sensing layer 40 may include a structure in which a first conductive layer 402 and a second conductive layer 404 are connected. Alternatively, the touch electrode TE may be formed in one of the first conductive layer 402 and the second conductive layer 404, and may include a metal wire provided in the corresponding conductive layer. The first conductive layer 402 and the second conductive layer 404 may include aluminum (Al), copper (Cu) and / or titanium (Ti), respectively, and may be formed as a single layer or multiple layers including the above substances. For example, the first conductive layer 402 and the second conductive layer 404 may have a three-layer structure of titanium layer / aluminum layer / titanium layer, respectively.

[0153] Reference Figure 7 The middle area MA may include a reference Figure 6 The first sub-middle area SMA1 through which the meandering portions DL-C1 and DL-C2 of the data lines DL are passed is illustrated.

[0154] As an embodiment, the meandering portions DL-C1 and DL-C2 of the data line DL may be arranged on different layers. One of the meandering portions DL-C1 and DL-C2 of the adjacent data lines DL may be arranged on the third interlayer insulating layer 210, and the other may be arranged on the first organic insulating layer 211.

[0155] When the winding portions DL-C1 and DL-C2 of the data lines DL are alternately arranged with an insulating layer (e.g., the first organic insulating layer 211) placed therebetween, the spacing Δd between the winding portions DL-C1 and DL-C2 of the data lines DL can be reduced, so that the area in the middle area MA can be effectively utilized.

[0156] Figure 8 is a cross-sectional view of a display device 10 according to an embodiment of the present invention and is shown along Figure 6 The cross-sectional view taken along line III-III' of Fig. 9 This is a diagram for explaining the structure of the groove G and the tip PT, and is an enlarged view. Figure 8 Figure VI of the region.

[0157] Reference Figure 8 , the middle area MA may include an area adjacent to the display area DA ( Figure 7 ) and a first sub-middle area SMA1 adjacent to the opening area OA.

[0158] exist Figure 8 The first middle sub-area SMA1 may be provided with a reference Figure 7 The illustrated meandering portions DL-C1 and DL-C2 of the data lines DL may be disposed with the grooves G and the partition walls PW in the second sub-middle area SMA2, and the encapsulation layer 300 may extend to the middle area MA to cover the grooves G and the partition walls PW.

[0159] Reference Figure 8 In the second sub-middle area SMA2, the grooves G may be arranged to be spaced apart from each other. Figure 8 The first groove 1G, the second groove 2G, the third groove 3G and the fourth groove 4G are arranged from the first sub-middle area SMA1 toward the opening area OA. The first groove 1G, the second groove 2G, the third groove 3G and the fourth groove 4G may have a closed loop shape surrounding the opening area OA on a plane.

[0160] Reference Figure 8 and Fig. 9 , the groove G may be formed in the multilayer film ML including a plurality of layers, and the groove G formed concavely along the depth direction of the multilayer film ML may have an undercut structure. The multilayer film ML defining the groove G may include a first layer LL and a second layer UL on the first layer LL. The first layer LL may include a first organic insulating layer 211, and may further include an insulating layer below the first organic insulating layer 211. For example, the first layer LL may include a second gate insulating layer 209, a third interlayer insulating layer 210, and a first organic insulating layer 211. The second layer UL may include a metal pattern layer 212 and a second organic insulating layer 213. The groove G may be formed by removing a portion of the multilayer film ML. For example, as Figure 8 As shown, the first groove 1G, the second groove 2G, the third groove 3G and the fourth groove 4G may be formed by removing a portion of the second gate insulating layer 209, the third interlayer insulating layer 210, the first organic insulating layer 211 and the second organic insulating layer 213 included in the multilayer film ML.

[0161] The lower layer 120 is located directly below the groove G. The lower layer 120 may have a function as an etching stopper when an etching process for forming the groove G is performed. Therefore, the bottom surface of the groove G may be the upper surface of the lower layer 120. In this regard, Figure 8 The case is shown where the lower layer 120 is located below each of the first groove 1G, the second groove 2G, the third groove 3G and the fourth groove 4G and the bottom surface of each of the first groove 1G, the second groove 2G, the third groove 3G and the fourth groove 4G is the same plane as the upper surface of the lower layer 120.

[0162] The lower layer 120 may be located on the second interlayer insulating layer 207 and may be located at the same level as the reference Figure 7 The lower layer 120 may be formed in the same process as the third semiconductor layer A3 described above. The lower layer 120 may include the same material as the third semiconductor layer A3 (eg, an oxide-based semiconductor material). Similar to the groove G, the lower layer 120 may have a closed loop shape surrounding the opening area OA in a plane.

[0163] In the case where the groove G is formed on at least one inorganic insulating layer but not on the substrate 100, it can have an effect that moisture that may flow in through the substrate 100 is blocked by the at least one inorganic insulating layer. Figure 8 The following structure is shown: the groove G is formed on the buffer layer 201 , the first gate insulating layer 203 and the first interlayer insulating layer 205 , so the buffer layer 201 , the first gate insulating layer 203 and the first interlayer insulating layer 205 can block moisture that may flow in through the substrate 100 .

[0164] At least one of the grooves G may include a tip PT. As an example, Figure 8 As shown, the first groove 1G, the second groove 2G and the fourth groove 4G may include at least one tip PT. For example, the first groove 1G may have tips PT located on both sides relative to a virtual vertical line VXL passing through the center of the first groove 1G. Similar to the first groove 1G, the second groove 2G may also include a pair of tips PT. On the contrary, the fourth groove 4G may include one tip PT.

[0165] Reference Figure 8 and Fig. 9 , the groove G may be provided by overlapping the opening 211OP and the tip PT of the first organic insulating layer 211. The tip PT is an eaves portion, which may be provided on the metal pattern layer 212 disposed immediately above the first organic insulating layer 211 and the second organic insulating layer 213 disposed on the upper portion of the metal pattern layer 212. The second organic insulating layer 213 may cover the side surface 212s and the upper surface 212t of the metal pattern layer 212. Since the side surface 212s of the metal pattern layer 212 is covered by the second organic insulating layer 213, the side surface 212s of the metal pattern layer 212 may be prevented from being damaged during the formation of the groove G.

[0166] In other words, the metal pattern layer 212 and the second organic insulating layer 213 (ie, the second layer UL) may be provided with a tip PT that protrudes toward the center of the groove G from where a side surface 211s defining the opening 211OP of the first organic insulating layer 211 intersects with a bottom surface 212b of the metal pattern layer 212 .

[0167] The groove G may expose the side surface 213 s of the second organic insulating layer 213 without exposing the side surface 212 s of the metal pattern layer 212 . Also, the groove G may expose the bottom surface 212 b of the metal pattern layer 212 .

[0168] The second organic insulating layer 213 may include a material having a different etching selectivity from that of the first organic insulating layer 211. Fig.11e and Fig.11fAs shown, the first organic insulating layer 211 is over-etched than the second organic insulating layer 213 by the etchant used in the etching process, so that the groove G and the tip PT may be formed.

[0169] The first organic insulating layer 211 may include an organic insulator. In one embodiment, for example, the first organic insulating layer 211 may include photosensitive polyimide (PSPI).

[0170] The second organic insulating layer 213 may include an organic insulating material. In one embodiment, the second organic insulating layer 213 may include a siloxane material. In one embodiment, the second organic insulating layer 213 may include a siloxane organic material having a cyclic and / or cage bonding structure.

[0171] The dielectric constant of the second organic insulating layer 213 may be less than the dielectric constant of the first organic insulating layer 211. In one embodiment, the dielectric constant of the second organic insulating layer 213 may be less than about 3. In one embodiment, the dielectric constant of the first organic insulating layer 211 may exceed about 3. In one embodiment, the dielectric constant of the first organic insulating layer 211 may exceed about 3.2.

[0172] In one embodiment, the first organic insulating layer 211 may include photosensitive polyimide, and the second organic insulating layer 213 may include a siloxane-based organic material having a ring-shaped and / or cage-shaped bonding structure. In this case, the dielectric constant of the second organic insulating layer 213 may be less than the dielectric constant of the first organic insulating layer 211. The dielectric constant of the second organic insulating layer 213 may be less than about 3. Therefore, since the second organic insulating layer 213 has a low moisture absorption rate, moisture permeability and pixel shrinkage phenomena can be improved. In addition, the etching selectivity of the second organic insulating layer 213 may be different from the etching selectivity of the first organic insulating layer 211. In an etching process using oxygen (e.g., an ashing process), the etching rate of the first organic insulating layer 211 may be greater than the etching rate of the second organic insulating layer 213. Therefore, as described later Fig.11e and Fig.11f As shown, an etching process is performed to remove a portion of the first organic insulating layer 211 using the second organic insulating layer 213 as a mask, so that the groove G and the tip PT structure can be formed without an additional process using an additional mask.

[0173] The metal pattern layer 212 may be disposed between the first organic insulating layer 211 and the second organic insulating layer 213. The metal pattern layer 212 may include Figure 7The data lines DL and / or the driving voltage lines PL are made of the same metal. As an embodiment, the metal pattern layer 212 may have a three-layer structure of titanium layer / aluminum layer / titanium layer (Ti / Al / Ti).

[0174] The metal pattern layer 212 and the second organic insulating layer 213 may be arranged on at least one side with the groove G as the center. For example, the tip PT may be located on both sides with a virtual vertical line VXL passing through the center of the first groove 1G as the center. The ends of the metal pattern layer 212 and the second organic insulating layer 213 may form a tip PT protruding toward the center of the first groove 1G. The tip PT may pass through the first organic insulating layer 211 forming the inner surface of the first groove 1G and protrude toward the center of the first groove 1G.

[0175] Likewise, the tip PT may be located at both sides of the second groove 2G as the center. The ends of the metal pattern layer 212 and the second organic insulating layer 213 may protrude toward the center of the second groove 2G to form the tip PT.

[0176] The fourth groove 4G may include a tip PT. The tip PT may be located at one side of the fourth groove 4G, for example, at a side adjacent to the second partition wall PW2. The ends of the metal pattern layer 212 and the second organic insulating layer 213 may protrude toward the center of the fourth groove 4G through the first organic insulating layer 211 constituting the inner surface of the fourth groove 4G to form a tip PT.

[0177] A portion of the layers included in the organic light emitting diode OLED (eg, the first functional layer 222a and the second functional layer 222c as organic matter) may be disconnected by the groove G including the tip PT. The counter electrode 223 may also be disconnected or separated by the groove G including the tip PT.

[0178] Relatedly, Figure 8 1G, the second groove 2G, and the fourth groove 4G. In one embodiment, the third groove 3G may not include the tip PT. In this case, the first functional layer 222a, the second functional layer 222c, and the counter electrode 223 may not be disconnected by the third groove 3G and may be continuously formed. Moisture may flow toward the display area DA ( Figure 7 ) and the organic layers (eg, the first functional layer 222a and the second functional layer 222c) formed continuously can form the above-mentioned moisture permeation path. Figure 8 As shown, since the first functional layer 222 a and the second functional layer 222 c may be disconnected by the groove G including the tip PT, moisture may be prevented from moving toward the display area DA.

[0179] Reference Figure 8 and Fig. 9 , a metal dummy stack 110 may be arranged around the groove G. The metal dummy stack 110 may be arranged on both sides of a virtual vertical line passing through the groove G. The metal dummy stack 110 is a ridge-shaped object including overlapping metal layers and an insulating layer sandwiched between adjacent metal layers. The depth d of the groove G may be increased by arranging the metal dummy stack 110. The metal dummy stack 110 may include a first metal layer 111, a second metal layer 112, and a third metal layer 113.

[0180] The metal pattern layer 212 may be in direct contact with the uppermost layer (e.g., the first metal layer 111) of the metal dummy stack 110. The metal pattern layer 212 may be in direct contact with the upper surface of the first metal layer 111 through the hole 211H of the first organic insulating layer 211. The metal contact region MCL formed by the metal pattern layer 212 in direct contact with the metal dummy stack 110 may be arranged adjacent to each of the grooves G. The metal pattern layer 212 is arranged in the hole 211H of the first organic insulating layer 211, so that the movement of moisture that may move through the first organic insulating layer 211 can be blocked. The metal pattern layer 212 and the first metal layer 111 are both equipped with metal, so that the contact force can be strong.

[0181] The first metal layer 111, the second metal layer 112 and the third metal layer 113 may be located at the same position as the above Figure 5 The electrodes of the thin film transistor and the capacitor are on the same layer and may include the same material. For example, the first metal layer 111 may be connected to the node connection line 166 ( Figure 7 ) are located on the same layer and may include the same substance. The second metal layer 112 may be located on the same layer as the upper gate electrode G3B of the third gate electrode GE3 and may include the same substance. The third metal layer 113 is located on the same layer as the second capacitor electrode CE2 of the capacitor and / or the lower gate electrode G3A of the third gate electrode GE3 and may include the same substance. Figure 8 and Fig. 9 The metal dummy stack 110 is shown to include three overlapping metal layers with an insulating layer interposed between adjacent metal layers, but the present invention is not limited thereto. As another embodiment, the number of metal layers of the metal dummy stack 110 may be less than three or more than three.

[0182] Figure 8 and Fig. 9 Although the first groove 1G is mainly described, this structure can of course be applied to the second groove 2G and the fourth groove 4G which are grooves G having a tip PT.

[0183] A portion of the groove G (eg, the third groove 3G) may not include the tip PT. The third groove 3G may be used to monitor the organic encapsulation layer 320 of the encapsulation layer 300 .

[0184] The organic encapsulation layer 320 can be formed by curing the monomer after coating it. Since the monomer has fluidity, controlling the position of the monomer is one of the important factors when manufacturing the display device 10. The position of the organic encapsulation layer 320 can be measured by the amount of light reflected after the light is irradiated to the display device 10. Since the tip PT including the metal affects the reflectivity of the light used when monitoring the organic encapsulation layer 320, it may be difficult to track the position of the organic encapsulation layer 320 when all the grooves G include the tip PT. However, the display device 10 according to an embodiment of the present invention includes a third groove 3G without a tip PT and a fourth groove 4G in which the tip PT is formed only on one side, so that the position of the organic encapsulation layer 320 can be easily tracked.

[0185] In the middle area MA, a partition wall PW may be arranged. Figure 8 The first partition wall PW1 and the second partition wall PW2 are shown. The grooves G may be arranged to be spaced apart from each other in the second sub-middle area SMA2. The first groove 1G may be arranged between the first partition wall PW1 and the first sub-middle area SMA1. In other words, the first groove 1G may be arranged between the first partition wall PW1 and the display area DA ( Figure 6 The second trench 2G and the third trench 3G may be arranged between the first partition wall PW1 and the second partition wall PW2, and the fourth trench 4G may be arranged between the second partition wall PW2 and the opening area OA.

[0186] The groove G between the first partition wall PW1 and the second partition wall PW2 may be covered by the organic encapsulation layer 320. Figure 8The second groove 2G and the third groove 3G are shown in a case where the region between the first partition wall PW1 and the second partition wall PW2 is covered by the organic encapsulation layer 320. As a comparative example, in a case where the groove G (for example, the second groove 2G and the third groove 3G) between the first partition wall PW1 and the second partition wall PW2 is not covered by the organic encapsulation layer 320, contact of inorganic insulating layers such as the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may occur on the second groove 2G and the third groove 3G. In a case where the area of ​​the contact region between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 on the second groove 2G and the third groove 3G is relatively increased, cracks may be easily generated in the contact portion between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 by the concavo-convex structure of the second groove 2G and the third groove 3G themselves. The cracks may reduce the quality of the display device 10. However, in the embodiment of the present invention, when the organic encapsulating layer 320 covers the groove G (eg, the second groove 2G and the third groove 3G) between the first partition wall PW1 and the second partition wall PW2 , the contact area between the first inorganic encapsulating layer 310 and the second inorganic encapsulating layer 330 can be reduced.

[0187] The first inorganic encapsulation layer 310 of the encapsulation layer 300 may continuously cover the inner surface of the groove G, and the organic encapsulation layer 320 may cover the first sub-middle area SMA1 and a portion of the second sub-middle area SMA2. The organic encapsulation layer 320 may cover a portion of the groove G, for example, the first groove 1G and the second groove 2G and the third groove 3G between the first partition wall PW1 and the second partition wall PW2. The second inorganic encapsulation layer 330 may cover the middle area MA on the organic encapsulation layer 320 as a whole.

[0188] The first partition wall PW1 may include a plurality of protrusions to control the flow of the monomer when forming the organic encapsulation layer 320. As an embodiment, Figure 8 The first partition wall PW1 includes a first protrusion 1141 , a second protrusion 1142 , and a third protrusion 1143 that are spaced apart from each other.

[0189] In the middle area MA, the organic encapsulation layer 320 may be discontinuous due to the structure of the first partition wall PW1, etc. For example, a portion of the organic encapsulation layer 320 may be as follows: Figure 7 and Figure 8 As shown, the first inorganic encapsulating layer 330 covers the display area DA and the first sub-middle area SMA1, and another portion may cover the area between the first partition wall PW1 and the second partition wall PW2. On the third protrusion 1143 of the first partition wall PW1 as a discontinuity of the organic encapsulating layer 320, a portion of the second inorganic encapsulating layer 330 may directly contact a portion of the first inorganic encapsulating layer 310.

[0190] The end of the organic encapsulation layer 320 is located on one side of the second partition wall PW2 and extends toward the opening area OA without passing through the second partition wall PW2. Therefore, a portion of the second inorganic encapsulation layer 330 may be in direct contact with a portion of the first inorganic encapsulation layer 310 on the upper surface of the second partition wall PW2. In addition, the second inorganic encapsulation layer 330 may be in direct contact with the first inorganic encapsulation layer 310 between the second partition wall PW2 and the opening area OA.

[0191] Reference Figure 7 The touch insulating layer described can extend to the middle area MA. In this regard, Figure 8 The structure in which the first touch insulation layer 401 , the second touch insulation layer 403 , and the third touch insulation layer 405 extend toward the middle area MA is shown.

[0192] The planarization layer 450 may be located in the middle area MA. The planarization layer 450 may planarize the middle area MA. The planarization layer 450 may be located in the middle area MA, and may cover a structure provided under the planarization layer 450.

[0193] Reference Figure 7 and Figure 8 , the planarization layer 450 may be located only in the middle area MA and may not exist in the display area DA ( Figure 7 ). In this regard, Figure 7 The case where the outer edge 450e of the planarization layer 450 is not located in the display area DA is shown. The process of forming the planarization layer 450 may be performed between the process of forming the first touch insulation layer 401 and the process of forming the second touch insulation layer 403. Therefore, in the display area DA adjacent to the outer edge 450e of the planarization layer 450, the first touch insulation layer 401 and the second touch insulation layer 403 may be in direct contact.

[0194] Reference Figure 8 The display device 10 includes an opening 10OP. The opening 10OP of the display device 10 may include an opening of a component constituting the display device 10. For example, the opening 10OP of the display device 10 may include an opening 100OP of the substrate 100, openings 310OP and 330OP of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 in the encapsulation layer 300, and an opening 450OP of the planarization layer 450.

[0195] The openings of the components constituting the display device 10 may be formed simultaneously. Therefore, the inner surface 100IS of the substrate 100 defining the opening 100OP of the substrate 100 and the inner surface 450IS of the planarization layer 450 defining the opening 450OP of the planarization layer 450 may be located on the same vertical line.

[0196] Fig.10 is a cross-sectional view showing a portion of a display device according to an embodiment of the present invention and showing Fig. 9 In the following, Fig. 9 The differences between the embodiments are mainly described, and repeated contents are omitted.

[0197] Reference Fig.10 ,and Fig. 9 Different from the embodiment of the present invention, the metal dummy stack 110 may not be arranged around the groove G. For example, Fig.10 The case where the metal dummy stack 110 is not arranged around the first groove 1G is shown. The metal pattern layer 212 can be arranged on the flat upper surface of the first organic insulating layer 211, and the second organic insulating layer 213 can be arranged on the upper part of the metal pattern layer 212. The metal pattern layer 212 and the second organic insulating layer 213 can be arranged on at least one side with the groove G as the center.

[0198] The ends of the metal pattern layer 212 and the second organic insulating layer 213 may include a tip PT protruding toward the center of the first groove 1G. The second organic insulating layer 213 may cover the side surface 212s and the upper surface 212t of the metal pattern layer 212. The first groove 1G may expose the side surface 213s of the second organic insulating layer 213 without exposing the side surface 212s of the metal pattern layer 212. Furthermore, the first groove 1G may expose the bottom surface 212b of the metal pattern layer 212.

[0199] Although Fig.10 The first groove 1G is shown as an example, but this structure can also be applied to Figure 8 The second groove 2G and the fourth groove 4G shown.

[0200] As described above, the second organic insulating layer 213 may include a material having a different etching selectivity from that of the first organic insulating layer 211. Fig. 9 The structure is formed in the same way, Fig.11e and Fig.11f The etching process can be applied to Fig.10 The formation of the structure. Fig.11f By using an etchant in the embodiment, the first organic insulating layer 211 is overetched compared to the second organic insulating layer 213 , so that the groove G and the tip PT can be formed.

[0201] Figures 11a to 11f 1 is a cross-sectional view sequentially showing some steps of a method for manufacturing a display device according to an embodiment of the present invention. Specifically, Figures 11a to 11f Shown to form Fig. 9 The groove G and the tip PT approach.

[0202] Reference Fig.11aThe pre-metal pattern layer 212' may be formed on the upper surface of the first organic insulating layer 211 having the hole 211H. The pre-metal pattern layer 212' may be inserted into the hole 211H of the first organic insulating layer 211 to directly contact the upper surface of the first metal layer 111 of the metal dummy stack 110.

[0203] Reference Fig.11b , a photoresist pattern PR may be formed on the pre-metal pattern layer 212'. The photoresist pattern PR may be formed through an exposure and development process of a mask.

[0204] Reference Fig.11c The metal pattern layer 212 may be formed by patterning the pre-metal pattern layer 212'. The etching process of patterning the pre-metal pattern layer 212' may be performed by, for example, dry etching, wet etching, or a combination thereof. The metal pattern layer 212 may expose a portion of the lower layer 120 corresponding to the first organic insulating layer 211.

[0205] Reference Fig.11d and Fig.11e , a pre-second organic insulating layer 213' may be formed on the upper surface of the first organic insulating layer 211 in a manner covering the metal pattern layer 212. In one embodiment, the pre-second organic insulating layer 213' may include a siloxane-based organic substance having a ring-shaped and / or cage-shaped bonding structure. And, for example, the pre-second organic insulating layer 213' may include a positive photoresist. Fig.11d and Fig.11e In the embodiment, the case where the second organic insulating layer 213 ′ includes a positive photoresist is taken as an example, but the second organic insulating layer 213 ′ may also include a negative photoresist.

[0206] The mask M may be located on the pre-second organic insulating layer 213'. The mask M may include a first portion P1 and a second portion P2. The first portion P1 may be a light-transmitting portion, and the second portion P2 may be a light-shielding portion. Through the mask M, the pre-second organic insulating layer 213' may be exposed according to different exposure amounts, and through a development process, the pre-second organic insulating layer 213' may be patterned.

[0207] The second organic insulating layer 213 may include an opening 213OP corresponding to the portion exposed by the first portion P1. The opening 213OP of the second organic insulating layer 213 may expose a portion of the first organic insulating layer 211 corresponding to the lower layer 120. The second organic insulating layer 213 may cover the metal pattern layer 212. The second organic insulating layer 213 may cover the upper surface 212t and the side surface 212s of the metal pattern layer 212.

[0208] Reference Fig.11f , the second organic insulating layer 213 may be used as a mask to remove a portion of the first organic insulating layer 211, thereby forming an opening 211OP of the first organic insulating layer 211. A groove G (e.g., a first groove 1G) may be formed by removing a portion of the first layer LL including the second gate insulating layer 209, the third interlayer insulating layer 210, and the first organic insulating layer 211. At this time, the lower layer 120 may serve as an etching stopper. In one embodiment, the lower surface of the groove G may be equivalent to the upper surface of the lower layer 120.

[0209] The etching process of forming the opening 211OP of the first organic insulating layer 211 may be performed, for example, by a dry etching process (eg, an ashing process). In the etching process of forming the opening 211OP of the first organic insulating layer 211, a tip PT provided on the second layer UL including the metal pattern layer 212 and the second organic insulating layer 213 may be formed.

[0210] The second organic insulating layer 213 may have a lower dielectric constant than the first organic insulating layer 211. In one embodiment, the first organic insulating layer 211 may include photosensitive polyimide (PSPI). In one embodiment, the second organic insulating layer 213 may include a siloxane-based organic having a cyclic and / or cage-shaped bonding structure. The dielectric constant of the second organic insulating layer 213 may be less than the dielectric constant of the first organic insulating layer 211. In one embodiment, the dielectric constant of the second organic insulating layer 213 may be less than about 3. The etching selectivity of the second organic insulating layer 213 may be different from the etching selectivity of the first organic insulating layer 211. By the etchant used in the etching process, the first organic insulating layer 211 may be over-etched than the second organic insulating layer 213. Therefore, a groove G having an undercut structure and a tip PT may be formed. At this time, since the second organic insulating layer 213 covers the upper surface 212t and the side surface 212s of the metal pattern layer 212, the metal pattern layer 212 is not damaged in the etching process. The tip PT, which is one end portion of the metal pattern layer 212 and the second organic insulating layer 213 disposed immediately above the first organic insulating layer 211 , may protrude toward the center of the groove G.

[0211] According to an embodiment of the present invention, the second organic insulating layer 213 includes a siloxane-based organic material having a ring-shaped and / or cage-shaped bonding structure as a material having a different etching selectivity from the first organic insulating layer 211. Therefore, without the need for an additional mask additional process, the second organic insulating layer 213 is used as a mask to remove a portion of the first organic insulating layer 211, and a groove G and a tip PT having an undercut structure can be formed. Therefore, according to an embodiment of the present invention, the number of masks applied to the manufacturing process of the display device 10 can be reduced and productivity can be improved, and at the same time, external impurities such as moisture can be prevented from flowing in around the opening to damage the display element.

[0212] The present invention as described above is described with reference to an embodiment shown in the accompanying drawings, but this is only exemplary, and anyone with ordinary knowledge in the art can understand that various modifications and variations of the embodiments can be realized. Therefore, the true technical protection scope of the present invention should be determined based on the technical ideas of the attached claims.

Claims

1. A display device, comprising: A substrate comprising an opening area and a display area surrounding the opening area; A plurality of light emitting diodes are arranged in the display area; as well as A plurality of grooves are located in a middle area between the opening area and the display area, The plurality of grooves are defined in a multilayer film, the multilayer film comprising a first organic insulating layer, a metal pattern layer on the first organic insulating layer, and a second organic insulating layer on the metal pattern layer. The second organic insulating layer covers an upper surface and side surfaces of the metal pattern layer, and includes a substance having an etching selectivity different from that of the first organic insulating layer.

2. The display device according to claim 1, wherein: The metal pattern layer and the second organic insulating layer are provided with: A tip protrudes from a point where a side surface of the first organic insulating layer intersects a bottom surface of the metal pattern layer toward a center of the groove.

3. The display device according to claim 2, wherein: The groove is formed by overlapping the opening of the first organic insulating layer with the second organic insulating layer and the tip of the metal pattern layer.

4. The display device according to claim 1, wherein: The second organic insulating layer has a dielectric constant that is smaller than a dielectric constant of the first organic insulating layer.

5. The display device according to claim 1, wherein: The second organic insulating layer includes a siloxane-based organic substance having a ring-shaped or cage-shaped bonding structure.

6. The display device according to claim 1, wherein: The bottom surface of the groove is the upper surface of the lower layer made of the oxide-based semiconductor material.

7. The display device according to claim 1, wherein: A metal dummy stack is arranged around the groove, The metal pattern layer contacts the metal dummy stack through a hole provided in the first organic insulating layer.

8. The display device according to claim 7, wherein: The metal dummy stack includes a plurality of stacked metal layers, and an insulating layer is sandwiched between adjacent metal layers.

9. The display device according to claim 1, wherein: Each of the plurality of light emitting diodes: The sub-pixel circuits are arranged on the substrate and are respectively connected to the sub-pixel circuits, wherein the sub-pixel circuits include a thin film transistor including a silicon-based semiconductor layer and a thin film transistor including an oxide-based semiconductor layer.

10. The display device according to claim 1, wherein: The plurality of light emitting diodes include: a first electrode and a second electrode; A light emitting layer between the first electrode and the second electrode; and A functional layer between the first electrode and the second electrode, The functional layer and the second electrode are interrupted or separated by the groove in the middle region.

11. A method for manufacturing a display device, comprising the following steps: preparing a substrate including an opening area and a display area surrounding the opening area; forming a first organic insulating layer in a middle area between the opening area and the display area; forming a metal pattern layer on the first organic insulating layer in the middle region; forming a second organic insulating layer on the metal pattern layer in the middle region; forming a plurality of grooves by removing a portion of a multilayer film including the first organic insulating layer, the metal pattern layer, and the second organic insulating layer; as well as A plurality of light emitting diodes are formed in the display area, The second organic insulating layer covers the side surface and the upper surface of the metal pattern layer, and includes a material having an etching selectivity different from that of the first organic insulating layer.

12. The method for manufacturing a display device according to claim 11, wherein: The step of forming the second organic insulating layer comprises the following steps: forming a preliminary second organic insulating layer on the first organic insulating layer and the metal pattern layer; Positioning a mask on the preliminary second organic insulating layer; and The preliminary second organic insulating layer is exposed and developed using the mask.

13. The method for manufacturing a display device according to claim 11, wherein: The step of forming the plurality of grooves comprises the following steps: A portion of the first organic insulating layer is removed using the second organic insulating layer as a mask to form an opening in the first organic insulating layer.

14. The method for manufacturing a display device according to claim 13, wherein: Step of forming an opening of the first organic insulating layer: The etching process is performed by using a lower layer disposed under the first organic insulating layer as an etching stopper.

15. The method for manufacturing a display device according to claim 14, wherein: The lower layer includes an oxide-based semiconductor material.

16. The method for manufacturing a display device according to claim 13, wherein: The metal pattern layer and the second organic insulating layer include: A tip protrudes from where a side surface of the first organic insulating layer defining the opening intersects with a bottom surface of the metal pattern layer toward a center of the groove.

17. The method for manufacturing a display device according to claim 11, wherein: The second organic insulating layer has a dielectric constant that is smaller than a dielectric constant of the first organic insulating layer.

18. The method for manufacturing a display device according to claim 11, wherein: The second organic insulating layer includes a siloxane-based organic substance having a ring-shaped or cage-shaped bonding structure.

19. The method for manufacturing a display device according to claim 11, further comprising the following steps: forming a metal dummy stack arranged at a periphery of the slot, in, The metal pattern layer contacts the metal dummy stack through a hole provided in the first organic insulating layer.

20. The method for manufacturing a display device according to claim 11, wherein: The plurality of light emitting diodes include: A first electrode and a second electrode; A light emitting layer between the first electrode and the second electrode; and A functional layer between the first electrode and the second electrode, The functional layer and the second electrode are interrupted or separated by the groove in the middle region.

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