Voltage source circuit and micro-led driving circuit

Abstract

The application discloses a voltage source circuit and a Micro-LED driving circuit. The voltage source circuit comprises: a source end of a power tube is an input end of the voltage source circuit and is connected with a power supply; a drain end of the power tube is an output end of the voltage source circuit and outputs an output voltage; a gate end of the power tube is connected with an output end of an amplifier; a resistance feedback network is connected between the drain end of the power tube and an input end of the amplifier; the amplifier, the power tube and the resistance feedback network form a negative feedback loop; the amplifier is also connected with the power supply and is powered by the power supply; and a full-block feedforward frequency compensation module is connected between the drain end of the power tube and the amplifier. The voltage source circuit has the effects of traditional Miller compensation and can realize a full-block feedforward path and has better stability. When applied to the Micro-LED driving circuit, the anti-interference capability of the Micro-LED driving circuit is improved, the Micro-LED driving circuit works more stably, and color uniformity is better.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a voltage source circuit and a Micro-LED driving circuit. Background Technology

[0002] LDO (Low-dropout regulator) is a crucial component of a System-on-Chip (SoC), primarily serving as a voltage source for digital-to-analog converters, voltage-controlled oscillators, and other components, providing an ideal power supply. Because the load on an LDO is dynamically changing, its output current also varies dynamically. LDOs utilize operational amplifiers, power transistors, and feedback circuits to create negative feedback, making frequency compensation extremely important. Currently, Miller compensation is the most common compensation method, but its stability remains relatively poor. Summary of the Invention

[0003] The purpose of this application is to provide a voltage source circuit and a Micro-LED driver circuit with good stability.

[0004] To achieve the above objectives, this application provides a voltage source circuit, comprising: an amplifier, a power transistor, a resistive feedback network, and a fully blocking feedforward frequency compensation module; the source terminal of the power transistor is the input terminal of the voltage source circuit and is connected to a power supply; the drain terminal of the power transistor is the output terminal of the voltage source circuit, outputting an output voltage; the gate terminal of the power transistor is connected to the output terminal of the amplifier; the resistive feedback network is connected between the drain terminal of the power transistor and the input terminal of the amplifier; the amplifier, the power transistor, and the resistive feedback network are connected to form a negative feedback loop; the amplifier is also connected to the power supply and is powered by the power supply; and the fully blocking feedforward frequency compensation module is connected between the drain terminal of the power transistor and the amplifier.

[0005] In one embodiment, the fully blocking feedforward frequency compensation module includes a ninth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a resistor unit, and a second hundredth capacitor. The source terminal of the ninth PMOS transistor is connected to the power supply, the gate terminal of the ninth PMOS transistor is connected to a second hundredth P-type bias voltage, the drain terminal of the ninth PMOS transistor is connected to the drain terminal of the sixth NMOS transistor, the gate terminal of the sixth NMOS transistor is connected to the drain terminal of the power transistor, the source terminal of the sixth NMOS transistor is connected to the drain terminal of the seventh NMOS transistor, the gate terminal of the seventh NMOS transistor is connected to a second hundredth N-type bias voltage, the source terminal of the seventh NMOS transistor is connected to ground, the source terminal of the sixth NMOS transistor is also connected to one end of the resistor unit, the other end of the resistor unit is connected to one end of the second hundredth capacitor, and the other end of the second hundredth capacitor is connected to the amplifier.

[0006] In one embodiment, the resistor unit includes a 200th resistor and a 15th PMOS transistor. One end of the 200th resistor is one end of the resistor unit, and the other end of the 200th resistor is connected to the source terminal of the 15th PMOS transistor. The drain terminal of the 15th PMOS transistor is the other end of the resistor unit. The gate terminal of the 15th PMOS transistor is connected to ground, and the 15th PMOS transistor is biased in the deep linear region.

[0007] In one embodiment, the fully blocking feedforward frequency compensation module further includes an eighth resistor, wherein the gate terminal of the ninth PMOS transistor is not connected to the second P-type bias voltage, but is connected to the drain terminal of the ninth PMOS transistor via the eighth resistor.

[0008] In one embodiment, the amplifier includes a two-stage amplification structure. The first-stage amplification structure includes a third PMOS transistor, a fourth PMOS transistor, a second NMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a second resistor, and a third resistor. The source terminals of the third and fourth PMOS transistors together constitute the bias current input terminal of the amplifier, receiving a bias current. The gate terminal of the third PMOS transistor is the first input terminal of the amplifier and is connected to the resistor feedback network. The gate terminal of the fourth PMOS transistor is the second input terminal of the amplifier, receiving a reference voltage. The drain terminal of the fourth PMOS transistor, the drain terminal of the second NMOS transistor, and the second NMOS transistor... The gate terminals of the S-channel transistor, the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are all connected and receive the same bias voltage. The source terminal of the second NMOS transistor is connected to the drain terminal of the second NMOS transistor. The source terminal of the second NMOS transistor is connected to ground via the second resistor. The source terminal of the third NMOS transistor is connected to ground via the third resistor. The drain terminal of the third NMOS transistor is connected to the source terminal of the first NMOS transistor. The drain terminal of the first NMOS transistor is connected to the drain terminal of the fourth PMOS transistor. The drain terminal of the fourth PMOS transistor is the first stage output node of the amplifier. The source terminal of the first NMOS transistor is connected to the other end of the second capacitor.

[0009] In one embodiment, the second-stage amplification structure includes a fifth PMOS transistor, a sixth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a fourth resistor, and a fifth resistor. The source terminals of the fifth and sixth PMOS transistors are both connected to a power supply. The gate terminal of the fifth PMOS transistor is connected to the gate terminal of the sixth PMOS transistor and the drain terminal of the fifth PMOS transistor. The drain terminal of the fifth PMOS transistor is connected to the drain terminal of the fourth NMOS transistor. The gate terminal of the fourth NMOS transistor is connected to the drain terminal of the fourth PMOS transistor. The source terminal of the fourth NMOS transistor is connected to ground via the fourth resistor. The source terminal of the fifth NMOS transistor is connected to ground via the fifth resistor. The gate terminal of the fifth NMOS transistor also receives the bias voltage. The drain terminal of the fifth NMOS transistor is connected to the drain terminal of the sixth PMOS transistor. The drain terminal of the sixth PMOS transistor is the second-stage output node of the amplifier and also serves as the output terminal of the amplifier, connected to the gate terminal of the power transistor.

[0010] In one embodiment, the amplifier further includes a filter capacitor and a filter resistor, the gate terminal of the fourth PMOS transistor is connected to ground via the filter capacitor, and the gate terminal of the fourth PMOS transistor receives the reference voltage via the filter resistor.

[0011] In one embodiment, the voltage source circuit further includes a dynamic feedback current and zero-point compensation module, which is connected between the bias current input terminal of the amplifier and the output terminal of the amplifier.

[0012] In one embodiment, the dynamic feedback current and zero-point compensation module includes a second PMOS transistor, a twentieth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a first resistor, and a first capacitor. The source terminal of the twentieth PMOS transistor is connected to the power supply, the drain terminal of the twentieth PMOS transistor is connected to the source terminal of the second PMOS transistor, the drain terminal of the twentieth PMOS transistor is connected to the bias current input terminal of the amplifier, the gate terminals of the second PMOS transistor and the twentieth PMOS transistor are both connected to the output terminal of the amplifier, the source terminal of the seventh PMOS transistor is connected to the power supply via the first resistor, the gate terminal of the seventh PMOS transistor is connected to the gate terminal of the eighth PMOS transistor and the drain terminal of the seventh PMOS transistor, the drain terminal of the seventh PMOS transistor is connected to the output terminal of the amplifier, the source terminal of the eighth PMOS transistor is connected to the power supply, and the drain terminal of the eighth PMOS transistor is connected to the output terminal of the amplifier via the first capacitor.

[0013] In one embodiment, the dynamic feedback current and zero-point compensation module further includes a seventh resistor, and the source terminal of the eighth PMOS transistor is connected to the power supply via the seventh resistor.

[0014] In one embodiment, the voltage source circuit further includes a capacitor discharge module, which is connected between the amplifier and the output terminal of the voltage source circuit.

[0015] In one embodiment, the capacitor discharge module includes a tenth PMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor. The source terminal of the tenth PMOS transistor is connected to a power supply, the gate terminal of the tenth PMOS transistor receives a second P-type bias voltage, the drain terminal of the tenth PMOS transistor is connected to the drain terminal of the eighth NMOS transistor, the gate terminal of the eighth NMOS transistor is connected to the drain terminal of the fifth PMOS transistor, the source terminal of the eighth NMOS transistor is connected to ground, the source terminal of the ninth NMOS transistor is connected to ground, the gate terminal of the ninth NMOS transistor is connected to the drain terminal of the tenth PMOS transistor, and the drain terminal of the ninth NMOS transistor is connected to the drain terminal of the power transistor.

[0016] In one embodiment, the capacitor discharge module further includes a 100th PMOS transistor, an 81st NMOS transistor, and an 82nd NMOS transistor. The drain of the 10th PMOS transistor is connected to the drain of the 8th NMOS transistor via the 100th PMOS transistor. The source of the 100th PMOS transistor is connected to the drain of the 10th PMOS transistor. The drain of the 100th PMOS transistor is connected to the drain of the 8th NMOS transistor. The gate of the 100th PMOS transistor receives a first P-type bias voltage. The source of the 8th NMOS transistor is connected to ground via the 81st NMOS transistor and the 82nd NMOS transistor. The drain of the 81st NMOS transistor is connected to the source of the 8th NMOS transistor. The source of the 82nd NMOS transistor is connected to ground. The gates of the 81st NMOS transistor and the 82nd NMOS transistor are both connected to the gate of the 8th NMOS transistor.

[0017] In one embodiment, the resistive feedback network includes a first feedback resistor and a second feedback resistor connected in series. One end of the first feedback resistor is connected to the drain of the power transistor, and one end of the second feedback resistor is connected to ground. The connection point of the first feedback resistor and the second feedback resistor is connected to the gate of the third PMOS transistor.

[0018] In one embodiment, the resistive feedback network further includes a second capacitor connected between the drain terminal of the power transistor and the connection point of the first feedback resistor and the second feedback resistor.

[0019] In one embodiment, the voltage source circuit further includes a current-voltage bias module, which includes a 200th PMOS transistor, a first PMOS transistor, a 12th PMOS transistor, a 13th PMOS transistor, a 14th PMOS transistor, a 10th NMOS transistor, an 11th NMOS transistor, a 12th NMOS transistor, a 13th NMOS transistor, a current source, and a sixth resistor. The source terminals of the 200th PMOS transistor and the 12th PMOS transistor are both connected to a power supply. The gate terminal of the 200th PMOS transistor is connected to the gate terminal of the 12th PMOS transistor, the drain terminal of the 13th PMOS transistor, and one end of the sixth resistor, and all receive the same 200th P-type bias voltage. The drain terminal of the 200th PMOS transistor is connected to the source terminal of the first PMOS transistor. The drain terminal of the first PMOS transistor serves as the bias current output terminal of the current-voltage bias module, outputting a bias current. The gate terminal of the first PMOS transistor is connected to the gate terminal of the 13th PMOS transistor, the other end of the sixth resistor, and the first PMOS transistor. The drains of all thirteen NMOS transistors are connected and receive the same first P-type bias voltage. The source of the thirteenth PMOS transistor is connected to the drain of the twelfth PMOS transistor. The gate of the thirteenth NMOS transistor is connected to the gate of the twelfth NMOS transistor, the drain of the twelfth NMOS transistor, and the drain of the fourteenth PMOS transistor, and serves as the bias voltage output terminal of the current-voltage bias module, outputting a bias voltage. The source of the thirteenth NMOS transistor is connected to the drain of the eleventh NMOS transistor. The gate of the eleventh NMOS transistor is connected to the gate of the tenth NMOS transistor, the drain of the tenth NMOS transistor, and the source of the twelfth NMOS transistor, and receives the same second N-type bias voltage. The sources of the eleventh NMOS transistor and the tenth NMOS transistor are both connected to ground. The gate of the fourteenth PMOS transistor receives an enable signal. The source of the fourteenth PMOS transistor is connected to the output terminal of the current source. The input terminal of the current source is connected to the power supply.

[0020] This application also provides a system-on-a-chip Micro-LED driving circuit, the Micro-LED driving circuit including a voltage source module, the voltage source module being the voltage source circuit as described above, providing power supply voltage to other modules in the Micro-LED driving circuit.

[0021] In summary, the beneficial effects of this application are as follows: The voltage source circuit of this application, by setting a fully blocking feedforward frequency compensation module between the circuit output and the amplifier, not only achieves the effect of traditional Miller compensation, but also realizes a fully blocking feedforward path, completely blocking the noise path from the power supply to the circuit output, avoiding interference from power supply noise, and thus possessing better stability. When applied to a Micro-LED driver circuit to provide power voltage to other modules in the Micro-LED driver circuit, it can improve the anti-interference capability of the Micro-LED driver circuit, making its operation more stable and its color uniformity better. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This application provides a functional structure diagram of a voltage source circuit;

[0024] Figure 2 A schematic diagram of the specific circuit structure of a voltage source circuit provided in the first embodiment of this application;

[0025] Figure 3 This is a schematic diagram of the specific circuit structure of a voltage source circuit provided in the second embodiment of this application. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application.

[0027] Please see Figure 1As shown, this application provides a voltage source circuit, which includes: an amplifier 10, a power transistor 20, a resistor feedback network 30, and a fully blocking feedforward frequency compensation module 40; the source terminal of the power transistor 20 is the input terminal of the voltage source circuit and is connected to a power supply Vdd; the drain terminal of the power transistor 20 is the output terminal of the voltage source circuit, outputting an output voltage Vout; the gate terminal of the power transistor is connected to the output terminal of the amplifier 10; the resistor feedback network 30 is connected between the drain terminal of the power transistor 20 and the input terminal of the amplifier 10; the amplifier 10, the power transistor 20, and the resistor feedback network 30 are connected to form a negative feedback loop; the amplifier 10 is also connected to the power supply Vdd and is powered by the power supply Vdd; the fully blocking feedforward frequency compensation module 40 is connected between the drain terminal of the power transistor 20 and the amplifier 10.

[0028] The voltage source circuit of this application, through the fully blocking feedforward frequency compensation module 40, not only achieves the effect of traditional Miller compensation, but also realizes a fully blocking feedforward path, completely blocking the noise path from the power supply to the output of the circuit, avoiding interference from power supply noise, and thus has better stability.

[0029] For details, please refer to Figure 2 As shown, in the first embodiment, the fully blocking feedforward frequency compensation module 40 (the dashed box C in the figure) includes a ninth PMOS transistor P9, a sixth NMOS transistor N6, a seventh NMOS transistor N7, a resistor unit, and a second capacitor C200. The source terminal of the ninth PMOS transistor P9 is connected to the power supply Vdd, and the gate terminal of the ninth PMOS transistor P9 is connected to the second P-type bias voltage vbp200 (Note: This is referred to as the P-type bias voltage, not necessarily meaning that the bias voltage is P-type, but for ease of distinction, this bias voltage is used for P-type MOS transistors, while the N-type bias voltage mentioned later is used for N-type MOS transistors). The drain of OS transistor P9 is connected to the drain of the sixth NMOS transistor N6. The gate of the sixth NMOS transistor N6 is connected to the drain of the power transistor 20. The source of the sixth NMOS transistor N6 is connected to the drain of the seventh NMOS transistor N7. The gate of the seventh NMOS transistor N7 is connected to the second N-type bias voltage vbn200. The source of the seventh NMOS transistor N7 is connected to ground Gnd. The source of the sixth NMOS transistor N6 is also connected to one end of the resistor unit. The other end of the resistor unit is connected to one end of the second capacitor C200. The other end of the second capacitor C200 is connected to the amplifier 10.

[0030] The amplifier 10 (excluding all dashed boxes and power transistor 20 in the figure) includes a two-stage amplification structure. The first-stage amplification structure includes a third PMOS transistor P3, a fourth PMOS transistor P4, a second NMOS transistor N200, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a second resistor R2, and a third resistor R3. The source terminals of the third PMOS transistor P3 and the fourth PMOS transistor P4 together form the bias current input terminal of the amplifier 10, receiving a bias current (this bias current is connected to the power supply Vdd, provided by the current-voltage bias module described later). The gate terminal of the third PMOS transistor P3 is the first input terminal of the amplifier 10, connected to the resistor feedback network 30. The gate terminal of the fourth PMOS transistor P4 is the second input terminal of the amplifier 10, receiving a reference voltage Vref. The drain terminal of the fourth PMOS transistor P4 is connected to the drain terminal of the second NMOS transistor N200. The gate terminals of the 200th NMOS transistor N200, the first NMOS transistor N1, the second NMOS transistor N2, and the third NMOS transistor N3 are all connected and receive the same bias voltage (this bias voltage is connected to the power supply Vdd, provided by the current-voltage bias module described later). The source terminal of the 200th NMOS transistor N200 is connected to the drain terminal of the second NMOS transistor N2. The source terminal of the second NMOS transistor N2 is connected to ground Gnd via the second resistor R2. The source terminal of the third NMOS transistor N3 is connected to ground Gnd via the third resistor R3. The drain terminal of the third NMOS transistor N3 is connected to the source terminal of the first NMOS transistor N1. The drain terminal of the first NMOS transistor N1 is connected to the drain terminal of the fourth PMOS transistor P4. The drain terminal of the fourth PMOS transistor P4 is the first stage output node of amplifier 10. The source terminal of the first NMOS transistor N1 is connected to the other end of the 200th capacitor C200.

[0031] This application's fully blocking feedforward frequency compensation module 40 constructs a zero in the left half-plane, which is used to compensate the first-stage output node of amplifier 10. Furthermore, there is no feedforward path between the circuit's output and amplifier 10. This is because when high-frequency noise exists in the power supply Vdd, the noise is transmitted to the first-stage output node of amplifier 10, specifically the drain of the fourth PMOS transistor P4, which is also the drain of the first NMOS transistor N1, and then to the source of the first NMOS transistor N1. Since the second capacitor C200 is approximately short-circuited, the noise is attenuated by the resistor unit. Even if some high-frequency noise reaches the source of the sixth NMOS transistor N6, it cannot further propagate to the gate of the sixth NMOS transistor N6. Thus, the noise path from the power supply Vdd to the circuit's output is completely blocked. Therefore, the zero in the right half-plane is eliminated, avoiding the reduction of the circuit's phase margin and resulting in a better power supply rejection ratio.

[0032] Please compare and refer to the following: Figure 2 and Figure 3 ,exist Figure 2 In the first embodiment shown, the resistor unit only includes the second hundredth resistor R200; while... Figure 3 In the second embodiment shown, the resistor unit includes a second 100th resistor R200 and a fifteenth PMOS transistor P15. One end of the second 100th resistor R200 is one end of the resistor unit, and the other end of the second 100th resistor R200 is connected to the source terminal of the fifteenth PMOS transistor P15. The drain terminal of the fifteenth PMOS transistor P15 is the other end of the resistor unit, and the gate terminal of the fifteenth PMOS transistor P15 is connected to ground Gnd. The fifteenth PMOS transistor P15 is biased in the deep linear region. Because the resistor unit in this application requires a high resistance value, if only one resistor is selected, that resistor will occupy a large chip area. However, the MOS transistor biased in the deep linear region can itself be regarded as a high-resistance resistor. By combining it with a smaller-resistance resistor to serve as the resistor unit, the chip area can be reduced, and the chip cost can be lowered.

[0033] Please compare and refer to the following: Figure 2 and Figure 3 ,exist Figure 3 In the second embodiment shown, the fully blocking feedforward frequency compensation module 40 further includes an eighth resistor R8. The gate terminal of the ninth PMOS transistor P9 is not connected to the second P-type bias voltage vbp200, but is connected to the drain terminal of the ninth PMOS transistor P9 via the eighth resistor R8.

[0034] Next, please refer to Figure 2As shown, the remaining structures of amplifier 10 will be described further. The second-stage amplification structure includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a fourth resistor R4, and a fifth resistor R5. The source terminals of the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are both connected to the power supply Vdd. The gate terminal of the fifth PMOS transistor P5 is connected to the gate terminal of the sixth PMOS transistor P6 and the drain terminal of the fifth PMOS transistor P5. The drain terminal of the fifth PMOS transistor P5 is connected to the drain terminal of the fourth NMOS transistor N4. The drain of the fourth PMOS transistor P4 is connected to the source of the fourth NMOS transistor N4, which is connected to ground Gnd via the fourth resistor R4. The source of the fifth NMOS transistor N5 is connected to ground Gnd via the fifth resistor R5. The gate of the fifth NMOS transistor N5 also receives the bias voltage. The drain of the fifth NMOS transistor N5 is connected to the drain of the sixth PMOS transistor P6. The drain of the sixth PMOS transistor P6 is the second-stage output node of amplifier 10 and also serves as the output terminal of amplifier 10, connected to the gate of power transistor 20. The amplifier 10 used in the voltage source circuit of this application is a push-pull amplifier 10 with a two-stage amplification structure.

[0035] In one embodiment, the amplifier 10 further includes a filter capacitor Clpf and a filter resistor Rlpf. The gate terminal of the fourth PMOS transistor P4 is connected to ground Gnd via the filter capacitor Clpf, and the gate terminal of the fourth PMOS transistor P4 receives the reference voltage Vref via the filter resistor Rlpf. The filter capacitor Clpf and the filter resistor Rlpf constitute a low-pass filter to filter the reference voltage Vref received at the second input terminal of the amplifier 10, thereby ensuring the purity of the reference voltage Vref and improving the accuracy of the comparison amplification of the amplifier 10.

[0036] Please refer to the following: Figure 1 As shown, in one embodiment, the voltage source circuit further includes a dynamic feedback current and zero-point compensation module 50, which is connected between the bias current input terminal and the output terminal of the amplifier 10. The dynamic feedback current and zero-point compensation module 50 of this application not only constructs a zero point that tracks changes in the load current, but also possesses a dynamic zero-point and feedback mechanism. It can dynamically track changes in the primary and secondary poles in the loop, providing better applicability for frequency compensation and further improving the stability of the voltage source circuit.

[0037] Please see Figure 2As shown, in the first embodiment, the dynamic feedback current and zero-point compensation module 50 includes a second PMOS transistor P2, a twentieth PMOS transistor P20, an eighth PMOS transistor P8, a first resistor R1, a seventh resistor R7, and a first capacitor C1. The source terminal of the twentieth PMOS transistor P20 is connected to the power supply Vdd, the drain terminal of the twentieth PMOS transistor P20 is connected to the source terminal of the second PMOS transistor P2, and the drain terminal of the twentieth PMOS transistor P20 is connected to the bias current input terminal of the amplifier 10. The gate terminal of the second PMOS transistor P2, the twentieth PMOS transistor P8, the eighth PMOS transistor P8, the first resistor R1, the seventh resistor R7, and the first capacitor C1. The gate terminals of PMOS transistors P20 are all connected to the output terminal of amplifier 10. The source terminal of the seventh PMOS transistor P7 is connected to the power supply Vdd via the first resistor R1. The gate terminal of the seventh PMOS transistor P7 is connected to the gate terminal of the eighth PMOS transistor P8 and the drain terminal of the seventh PMOS transistor P7. The drain terminal of the seventh PMOS transistor P7 is connected to the output terminal of amplifier 10. The source terminal of the eighth PMOS transistor P8 is connected to the power supply Vdd. The drain terminal of the eighth PMOS transistor P8 is connected to the output terminal of amplifier 10 via the first capacitor C1.

[0038] The eighth PMOS transistor P8 is biased in the linear region, and its resistance changes with the output node of the second stage of amplifier 10. When the load current increases, the pole at this point shifts to a higher frequency, and the resistance of the eighth PMOS transistor P8 decreases, thus the constructed zero also shifts to a higher frequency. Furthermore, as the load current increases, the second PMOS transistor P2, the twentieth PMOS transistor P20, the seventh PMOS transistor P7, and the first resistor R1 detect the increased load current and feed it back to the bias current input of amplifier 10, which in turn feeds back to the first and second stage output nodes of amplifier 10, pushing these two poles outwards towards the unity-gain bandwidth product. This helps the LDO loop become increasingly stable as the load current increases. Therefore, compared to the fixed zero-pole voltage source circuit of traditional Miller compensation, the dynamic feedback current and zero-point compensation module 50 of this application has a dynamic zero-point and feedback mechanism, which can dynamically track the changes in the primary and secondary poles in the loop, providing better applicability for frequency compensation.

[0039] Please compare and refer to the following: Figure 2 and Figure 3 ,exist Figure 3 In the second embodiment shown, the dynamic feedback current and zero-point compensation module 50 further includes a seventh resistor R7. The source terminal of the eighth PMOS transistor P8 is not directly connected to the power supply Vdd, but is connected to the power supply Vdd via the seventh resistor R7. This avoids the situation where the equivalent resistance generated by the eighth PMOS transistor P8 is too small, leading to failure of the dynamic compensation zero point.

[0040] Please refer to the following: Figure 1As shown, in one embodiment, the voltage source circuit further includes a capacitor discharge module connected between the amplifier 10 and the output terminal of the voltage source circuit. The capacitor discharge module detects excessive overshoot voltage spikes in the voltage source circuit and opens the discharge path of the output capacitor (also known as an off-chip capacitor) to reduce the overshoot peak voltage and overshoot recovery time.

[0041] Please see Figure 2 As shown, in the first embodiment, the capacitor discharge module includes a tenth PMOS transistor P10, an eighth NMOS transistor N8, and a ninth NMOS transistor N9. The source terminal of the tenth PMOS transistor P10 is connected to the power supply Vdd, the gate terminal of the tenth PMOS transistor P10 receives a second P-type bias voltage vbp200, the drain terminal of the tenth PMOS transistor P10 is connected to the drain terminal of the eighth NMOS transistor N8, the gate terminal of the eighth NMOS transistor N8 is connected to the drain terminal of the fifth PMOS transistor P5, the source terminal of the eighth NMOS transistor N8 is connected to ground Gnd, the source terminal of the ninth NMOS transistor N9 is connected to ground Gnd, the gate terminal of the ninth NMOS transistor N9 is connected to the drain terminal of the tenth PMOS transistor P10, and the drain terminal of the ninth NMOS transistor N9 is connected to the drain terminal of the power transistor 20.

[0042] The capacitor discharge module works by triggering when a large overshoot voltage occurs at the output voltage. It provides an additional charge discharge path to the output terminal (external capacitor), thereby reducing the overshoot voltage. Specifically, when a large overshoot occurs at the output voltage Vout, the gate voltage of the eighth NMOS transistor N8 decreases. Therefore, the current generated by the eighth NMOS transistor N8 is less than the current generated by the tenth PMOS transistor P10. Consequently, the gate voltage of the ninth NMOS transistor N9 increases, ultimately causing N9 to conduct and generate a current path to ground (Gnd), discharging to the output terminal (external capacitor) of the LDO, thus reducing the overshoot voltage. Please refer to the comparison below. Figure 2 and Figure 3 ,exist Figure 3In the second embodiment shown, the capacitor discharge module further includes a 100th PMOS transistor P100, an 81st NMOS transistor N81, and an 82nd NMOS transistor N82. The drain of the 10th PMOS transistor P10 is connected to the drain of the 8th NMOS transistor N81 via the 100th PMOS transistor P100. The source of the 100th PMOS transistor P100 is connected to the drain of the 10th PMOS transistor P10. The drain of the 100th PMOS transistor P100 is connected to the drain of the 8th NMOS transistor N82. The gate of the 100th PMOS transistor P100 receives a first P-type bias voltage v. bp1, the source terminal of the eighth NMOS transistor N8 is connected to ground Gnd via the eighty-first NMOS transistor N81 and the eighty-second NMOS transistor N82. The drain terminal of the eighty-first NMOS transistor N81 is connected to the source terminal of the eighth NMOS transistor N8. The source terminal of the eighty-first NMOS transistor N81 is connected to the drain terminal of the eighty-second NMOS transistor N82. The source terminal of the eighty-second NMOS transistor N82 is connected to ground Gnd. The gate terminals of the eighty-first NMOS transistor N81 and the eighty-second NMOS transistor N82 are both connected to the gate terminal of the eighth NMOS transistor N8.

[0043] The 100th PMOS transistor P100 and the 10th PMOS transistor P10 form a common-source, common-gate current mirror, resulting in more accurate current readings. The 81st NMOS transistor N81, the 82nd NMOS transistor N82, and the 8th NMOS transistor N8 together increase the gate length, reducing the current in this branch. This ensures that when there is a large overshoot in the output voltage Vout, the current in this branch is less than the current in the branch containing the 10th PMOS transistor P10, allowing the 9th NMOS transistor N9 to turn on normally.

[0044] Please see Figure 2 and Figure 3 ,exist Figure 2 The first embodiment shown and Figure 3 In the second embodiment shown, each resistor feedback network 30 includes a first feedback resistor Rfb1 and a second feedback resistor Rfb2, which are connected in series. One end of the first feedback resistor Rfb1 is connected to the drain of the power transistor 20, and one end of the second feedback resistor Rfb2 is connected to ground Gnd. The connection point of the first feedback resistor Rfb1 and the second feedback resistor Rfb2 is connected to the gate of the third PMOS transistor P3. The resistor feedback network 30 feeds the load current back to the amplifier 10, enabling the amplifier 10 to dynamically adjust the gate voltage of the power transistor 20, thereby dynamically adjusting the input (equivalent on-resistance) of the voltage source circuit to stabilize the output voltage Vout.

[0045] Please see Figure 2 and Figure 3,exist Figure 2 The first embodiment shown and Figure 3 In the second embodiment shown, the resistive feedback network 30 further includes a second capacitor C2, which is connected between the drain terminal of the power transistor 20 and the connection point of the first feedback resistor Rfb1 and the second feedback resistor Rfb2. Thus, a pole-zero pair can be constructed here, with the pole frequency higher than the zero. Setting the zero near the unity-gain bandwidth product can further help improve the phase margin.

[0046] Finally, as mentioned above, please refer to Figure 2 and Figure 3 ,exist Figure 2 The first embodiment shown and Figure 3In the second embodiment shown, each voltage source circuit further includes a current-voltage bias module to provide bias current and bias voltage for each module in the circuit. The current-voltage bias module includes a 200th PMOS transistor P200, a first PMOS transistor P1, a 12th PMOS transistor P12, a 13th PMOS transistor P13, a 14th PMOS transistor P14, a 10th NMOS transistor N10, an 11th NMOS transistor N11, a 12th NMOS transistor N12, a 13th NMOS transistor N13, a current source idc, and a sixth resistor R6. The source terminals of the 200th PMOS transistor P200 and the 12th PMOS transistor P12 are both connected to the power supply Vdd. The gate terminal of the 200th PMOS transistor P200 is connected to the 12th PMOS transistor P12. The gate of the MOS transistor P12, the drain of the thirteenth PMOS transistor P13, and one end of the sixth resistor R6 are all connected and receive the same second-hundredth P-type bias voltage vbp200. The drain of the second-hundredth PMOS transistor P200 is connected to the source of the first PMOS transistor P1. The drain of the first PMOS transistor P1 serves as the bias current output terminal of the current-voltage bias module, outputting the bias current. The gate of the first PMOS transistor P1 is connected to the gate of the thirteenth PMOS transistor P13, the other end of the sixth resistor R6, and the drain of the thirteenth NMOS transistor N13. All are connected and receive the same first P-type bias voltage vbp1. The source terminal of the thirteenth PMOS transistor P13 is connected to the drain terminal of the twelfth PMOS transistor P12. The gate terminal of the thirteenth NMOS transistor N13 is connected to the gate terminal of the twelfth NMOS transistor N12, the drain terminal of the twelfth NMOS transistor N12, and the drain terminal of the fourteenth PMOS transistor P14, and serves as the bias voltage output terminal of the current-voltage bias module, outputting the bias voltage. The source terminal of the thirteenth NMOS transistor N13 is connected to the drain terminal of the eleventh NMOS transistor N11. The gate of the 11th NMOS transistor N11 is connected to the gate of the 10th NMOS transistor N10, the drain of the 10th NMOS transistor N10, and the source of the 12th NMOS transistor N12, and all receive the same 200th type N bias voltage vbn200. The source of the 11th NMOS transistor N11 and the source of the 10th NMOS transistor N10 are both connected to ground Gnd. The gate of the 14th PMOS transistor P14 receives the enable signal en. The source of the 14th PMOS transistor P14 is connected to the output of the current source idc. The input of the current source idc is connected to the power supply Vdd.

[0047] This application also provides a system-on-a-chip Micro-LED driving circuit, the Micro-LED driving circuit including a voltage source module, the voltage source module being the voltage source circuit as described above, providing power supply voltage to other modules (e.g., digital-to-analog converters or voltage-controlled oscillators) in the Micro-LED driving circuit.

[0048] In summary, the beneficial effects of this application are:

[0049] This voltage source circuit, by incorporating a fully blocking feedforward frequency compensation module between the circuit's output and the amplifier, not only achieves the effect of traditional Miller compensation but also realizes a fully blocking feedforward path, completely isolating the noise path from the power supply to the circuit's output, thus avoiding power supply noise interference and resulting in better stability. When applied to Micro-LED driver circuits to provide power to other modules within the Micro-LED driver circuit, this enhances the Micro-LED driver circuit's anti-interference capability, making its operation more stable and improving color uniformity.

[0050] This application's fully blocking feedforward frequency compensation module constructs a zero in the left half-plane, which is used to compensate the first-stage output node of the amplifier. Furthermore, there is no feedforward path between the LDO output and the amplifier output. This is because when high-frequency noise exists in the power supply, the noise propagates to the first-stage output node of the amplifier, specifically the drain of the fourth PMOS transistor, which is also the drain of the first NMOS transistor, and then to the source of the first NMOS transistor. Since the second capacitor is approximately short-circuited, the noise propagation to the resistor unit is attenuated by the resistor unit. Even if some high-frequency noise reaches the source of the sixth NMOS transistor, it cannot further propagate to the gate of the sixth NMOS transistor. Thus, the noise path from the power supply to the LDO output is completely blocked. Therefore, the zero in the right half-plane is eliminated, avoiding the reduction of the LDO's phase margin caused by the right half-plane zero, resulting in a better power supply rejection ratio.

[0051] The voltage source circuit of this application, through dynamic feedback current and zero-point compensation module, not only constructs a zero point that tracks changes in load current, but also has a dynamic zero-point and feedback mechanism, which can dynamically track changes in the primary and secondary poles in the loop, has better applicability for frequency compensation, and further improves the stability of the voltage source circuit.

[0052] In the dynamic feedback current and zero-point compensation module of this application, the eighth PMOS transistor is biased in the linear region, and its resistance changes with the output node of the second stage of the amplifier. When the load current increases, the pole at this point shifts to a higher frequency, and the resistance of the eighth PMOS transistor decreases, thus the constructed zero also shifts to a higher frequency. Furthermore, as the load current increases, the second, twentieth, and seventh PMOS transistors, along with the first resistor, detect this increase and feed it back to the amplifier's bias current input, which in turn feeds back to the first and second stage output nodes of the amplifier, pushing these two poles outwards towards the unity-gain bandwidth product. This helps the LDO loop become increasingly stable as the load current increases. Therefore, compared to the fixed zero-pole voltage source circuit of traditional Miller compensation, the dynamic feedback current and zero-point compensation module of this application possesses a dynamic zero-point and feedback mechanism, which can dynamically track the changes in the primary and secondary poles in the loop, providing better applicability for frequency compensation.

[0053] The voltage source circuit of this application detects excessive overshoot voltage spikes in the voltage source circuit through a capacitor discharge module, and opens the discharge path of the output capacitor (also known as the off-chip capacitor) to reduce the recovery time of the overshoot.

[0054] The resistive feedback network of this application also includes a second capacitor, which is connected between the drain of the power transistor and the connection point of the first and second feedback resistors. This allows for the construction of a pole-zero pair, with the pole's frequency higher than the zero. Setting the zero near the unity-gain bandwidth product can further enhance the phase margin.

[0055] The technical solutions provided by the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A voltage source circuit, characterized by, The voltage source circuit comprises an amplifier, a power tube, a resistance feedback network and a full-break feedforward frequency compensation module; a source end of the power tube is an input end of the voltage source circuit and is connected to a power supply; a drain end of the power tube is an output end of the voltage source circuit and outputs an output voltage; a gate end of the power tube is connected to an output end of the amplifier; the resistance feedback network is connected between the drain end of the power tube and an input end of the amplifier; the amplifier, the power tube and the resistance feedback network form a negative feedback loop; the amplifier is also connected to the power supply and is powered by the power supply; and the full-break feedforward frequency compensation module is connected between the drain end of the power tube and the amplifier. The full-break feedforward frequency compensation module comprises a ninth PMOS tube, a sixth NMOS tube, a seventh NMOS tube, a resistance unit and a second capacitor; a source end of the ninth PMOS tube is connected to a power supply; a gate end of the ninth PMOS tube is connected to a second P-type bias voltage; a drain end of the ninth PMOS tube is connected to a drain end of the sixth NMOS tube; a gate end of the sixth NMOS tube is connected to a drain end of the power tube; a source end of the sixth NMOS tube is connected to a drain end of the seventh NMOS tube; a gate end of the seventh NMOS tube is connected to a second N-type bias voltage; a source end of the seventh NMOS tube is connected to the ground; the source end of the sixth NMOS tube is also connected to one end of the resistance unit; the other end of the resistance unit is connected to one end of the second capacitor; and the other end of the second capacitor is connected to the amplifier. The amplifier comprises a two-stage amplification structure, wherein a first-stage amplification structure comprises a third PMOS tube, a fourth PMOS tube, a second NMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a second resistance and a third resistance; a source end of the third PMOS tube and a source end of the fourth PMOS tube jointly form a bias current input end of the amplifier and receive a bias current; a gate end of the third PMOS tube is a first input end of the amplifier and is connected to the resistance feedback network; a gate end of the fourth PMOS tube is a second input end of the amplifier and receives a reference voltage; a drain end of the fourth PMOS tube is connected to a drain end of the second NMOS tube, a gate end of the second NMOS tube, a gate end of the first NMOS tube, a gate end of the second NMOS tube and a gate end of the third NMOS tube, and receives a same bias voltage; a source end of the second NMOS tube is connected to a drain end of the second NMOS tube; a source end of the second NMOS tube is connected to the ground via the second resistance; a source end of the third NMOS tube is connected to the ground via the third resistance; a drain end of the third NMOS tube is connected to a source end of the first NMOS tube; a drain end of the first NMOS tube is connected to a drain end of the fourth PMOS tube; the drain end of the fourth PMOS tube is a first-stage output junction of the amplifier; and a source end of the first NMOS tube is connected to the other end of the second capacitor.

2. The voltage source circuit of claim 1, wherein, The resistance unit comprises a second hundredth resistance and a fifteenth PMOS tube, one end of the second hundredth resistance is one end of the resistance unit, the other end of the second hundredth resistance is connected with the source end of the fifteenth PMOS tube, the drain end of the fifteenth PMOS tube is the other end of the resistance unit, the gate end of the fifteenth PMOS tube is connected with the ground, and the fifteenth PMOS tube is biased in a deep linear region.

3. The voltage source circuit of claim 1, wherein, The full-blocking feedforward frequency compensation module further comprises an eighth resistance, and the gate end of the ninth PMOS tube is not connected with the second hundredth P-type bias voltage, but is connected with the drain end of the ninth PMOS tube through the eighth resistance.

4. The voltage source circuit of claim 1, wherein, The second-stage amplification structure comprises a fifth PMOS tube, a sixth PMOS tube, a fourth NMOS tube, a fifth NMOS tube, a fourth resistance and a fifth resistance, the source end of the fifth PMOS tube and the source end of the sixth PMOS tube are connected with a power supply, the gate end of the fifth PMOS tube is connected with the gate end of the sixth PMOS tube and the drain end of the fifth PMOS tube, the drain end of the fifth PMOS tube is connected with the drain end of the fourth NMOS tube, the gate end of the fourth NMOS tube is connected with the drain end of the fourth PMOS tube, the source end of the fourth NMOS tube is connected with the ground through the fourth resistance, the source end of the fifth NMOS tube is connected with the ground through the fifth resistance, the gate end of the fifth NMOS tube also receives the bias voltage, the drain end of the fifth NMOS tube is connected with the drain end of the sixth PMOS tube, the drain end of the sixth PMOS tube is a second-stage output node of the amplifier and also serves as an output end of the amplifier and is connected with the gate end of the power tube.

5. The voltage source circuit of claim 1, wherein, The amplifier further comprises a filter capacitor and a filter resistance, the gate end of the fourth PMOS tube is connected with the ground through the filter capacitor, and the gate end of the fourth PMOS tube receives the reference voltage through the filter resistance.

6. The voltage source circuit of claim 4, wherein, The voltage source circuit further comprises a dynamic feedback current and zero point compensation module, which is connected between the bias current input end of the amplifier and the output end of the amplifier.

7. The voltage source circuit of claim 6, wherein, The dynamic feedback current and zero point compensation module comprises a second PMOS tube, a twentieth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a first resistance and a first capacitor, the source end of the twentieth PMOS tube is connected with a power supply, the drain end of the twentieth PMOS tube is connected with the source end of the second PMOS tube, the drain end of the twentieth PMOS tube is connected with the bias current input end of the amplifier, the gate end of the second PMOS tube and the gate end of the twentieth PMOS tube are both connected with the output end of the amplifier, the source end of the seventh PMOS tube is connected with the power supply through the first resistance, the gate end of the seventh PMOS tube is connected with the gate end of the eighth PMOS tube and the drain end of the seventh PMOS tube, the drain end of the seventh PMOS tube is connected with the output end of the amplifier, the source end of the eighth PMOS tube is connected with the power supply, and the drain end of the eighth PMOS tube is connected with the output end of the amplifier through the first capacitor.

8. The voltage source circuit of claim 7, wherein, The dynamic feedback current and zero point compensation module further comprises a seventh resistor, and a source end of the eighth PMOS is connected to a power supply via the seventh resistor.

9. The voltage source circuit of claim 4, wherein, The voltage source circuit further comprises a capacitor discharge module connected between the amplifier and an output end of the voltage source circuit.

10. The voltage source circuit of claim 9, wherein, The capacitor discharge module comprises a tenth PMOS, an eighth NMOS and a ninth NMOS, a source end of the tenth PMOS is connected to a power supply, a gate end of the tenth PMOS receives a second P-type bias voltage, a drain end of the tenth PMOS is connected to a drain end of the eighth NMOS, a gate end of the eighth NMOS is connected to a drain end of the fifth PMOS, a source end of the eighth NMOS is connected to ground, a source end of the ninth NMOS is connected to ground, a gate end of the ninth NMOS is connected to a drain end of the tenth PMOS, and a drain end of the ninth NMOS is connected to a drain end of the power tube.

11. The voltage source circuit of claim 10, wherein, The capacitor discharge module further comprises a one-hundredth PMOS, an eighty-first NMOS and an eighty-second NMOS, the drain end of the tenth PMOS is connected to the drain end of the eighth NMOS via the one-hundredth PMOS, a source end of the one-hundredth PMOS is connected to the drain end of the tenth PMOS, a drain end of the one-hundredth PMOS is connected to the drain end of the eighth NMOS, a gate end of the one-hundredth PMOS receives a first P-type bias voltage, a source end of the eighth NMOS is connected to ground via the eighty-first NMOS and the eighty-second NMOS, a drain end of the eighty-first NMOS is connected to a source end of the eighth NMOS, a source end of the eighty-first NMOS is connected to a drain end of the eighty-second NMOS, a source end of the eighty-second NMOS is connected to ground, and a gate end of the eighty-first NMOS and a gate end of the eighty-second NMOS are both connected to the gate end of the eighth NMOS.

12. The voltage source circuit of claim 1, wherein, The resistance feedback network comprises a first feedback resistor and a second feedback resistor, the first feedback resistor and the second feedback resistor are connected in series, one end of the first feedback resistor is connected to the drain end of the power tube, one end of the second feedback resistor is connected to ground, and a connection point of the first feedback resistor and the second feedback resistor is connected to the gate end of the third PMOS.

13. The voltage source circuit of claim 12, wherein, The resistance feedback network further comprises a second capacitor connected between the drain end of the power tube and the connection point of the first feedback resistor and the second feedback resistor.

14. The voltage source circuit of claim 1, wherein, The voltage source circuit further comprises a current voltage biasing module, the current voltage biasing module comprises a second hundred PMOS, a first PMOS, a twelfth PMOS, a thirteenth PMOS, a fourteenth PMOS, a tenth NMOS, an eleventh NMOS, a twelfth NMOS, a thirteenth NMOS, a current source and a sixth resistance, the source end of the second hundred PMOS and the source end of the twelfth PMOS are connected with a power supply, the gate end of the second hundred PMOS is connected with the gate end of the twelfth PMOS, the drain end of the thirteenth PMOS and one end of the sixth resistance, and receives the same second hundred P-type biasing voltage, the drain end of the second hundred PMOS is connected with the source end of the first PMOS, the drain end of the first PMOS is used as the biasing current output end of the current voltage biasing module, outputs the biasing current, the gate end of the first PMOS is connected with the gate end of the thirteenth PMOS, the other end of the sixth resistance and the drain end of the thirteenth NMOS, and receives the same first P-type biasing voltage, the source end of the thirteenth PMOS is connected with the drain end of the twelfth PMOS, the gate end of the thirteenth NMOS is connected with the gate end of the twelfth NMOS, the drain end of the twelfth NMOS and the drain end of the fourteenth PMOS, and is used as the biasing voltage output end of the current voltage biasing module, outputs the biasing voltage, the source end of the thirteenth NMOS is connected with the drain end of the eleventh NMOS, the gate end of the eleventh NMOS is connected with the gate end of the tenth NMOS, the drain end of the tenth NMOS and the source end of the twelfth NMOS, and receives the same second hundred N-type biasing voltage, the source end of the eleventh NMOS and the source end of the tenth NMOS are connected with the ground, the gate end of the fourteenth PMOS receives an enable signal, the source end of the fourteenth PMOS is connected with the output end of the current source, and the input end of the current source is connected with the power supply.

15. A Micro-LED driving circuit, characterized in that, The Micro-LED driving circuit comprises a voltage source module, the voltage source module is the voltage source circuit according to any one of claims 1-14, and provides a power supply voltage for other modules in the Micro-LED driving circuit.

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