Control methods, control devices, and network port devices

Abstract

This application discloses a control method, control device, and network port device, relating to the field of communication technology. The network port device includes a CPU and a switch chip. The interface between the switch and the CPU includes a data port and a management port. The control method for the network port device includes: running the switch chip initialization firmware; configuring the working mode of the data port through the management port; and transmitting initialization data to the register of the switch chip via the data port to initialize the switch chip. This application initializes the switch chip by running the switch chip initialization firmware when the network port device is powered on, configuring the working mode of the data port through the management port, and transmitting initialization data to the register of the switch chip via the data port. This achieves the initialization of the switch chip before the network port device enters the system, thus eliminating the need for driver installation.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a control method, control device, and network port device for a network port. Background Technology

[0002] In the existing multi-port network device architecture, with the continuous evolution of chip technology, PC processors have gradually integrated the functions of MAC controllers. This change allows motherboard manufacturers to achieve comprehensive network functionality with just a single PHY chip. Furthermore, by installing a matching PHY driver in the operating system, the network function can operate smoothly. However, given the replaceability of PC systems, users have the right to change their operating system according to their needs. This characteristic brings a challenge: after changing their system, users must reinstall the PHY (or switch) driver to ensure the normal operation of the network function, significantly increasing the maintenance costs and workload for motherboard manufacturers. Summary of the Invention

[0003] The main objective of this invention is to provide a control method for a network port device, which aims to complete the initialization of the SWITCH chip in the firmware, thereby eliminating the need for driver installation in solutions using the SWITCH chip.

[0004] To achieve the above objectives, the present invention provides a control method for a network port device, the network port device including a CPU and a SWITCH chip, the interface between the SWITCH and the CPU including a data port and a management port, and the control method including:

[0005] Run the SWITCH chip initialization firmware and configure the data port working mode through the management port;

[0006] Initialization data is transmitted to the register of the SWITCH chip via the data port to initialize the SWITCH chip.

[0007] Optionally, the firmware for running the switch chip initialization includes:

[0008] Set the corresponding clock signal and set the corresponding data signal;

[0009] When the clock signal is at the rising edge, the data signal is set to read, and the model and version information corresponding to the SWITCH chip is identified;

[0010] Based on the model and version information, run the initialization firmware corresponding to the SWITCH chip.

[0011] Optionally, identifying the model version information corresponding to the SWITCH chip includes:

[0012] After the data signal is set, obtain the remaining length of the data to be transmitted;

[0013] If the length of the data to be transmitted is empty, set the clock signal to low;

[0014] If the length of the data to be transmitted is not empty, the clock signal is set to low, and after a first preset time delay, the clock signal is toggled. Data is sampled when the clock signal is at its rising edge, and after a second preset time delay, the clock signal is set to low.

[0015] Optionally, the step of transmitting initialization data to the register of the SWITCH chip via the data port specifically involves:

[0016] Obtain the corresponding clock signal and data signal;

[0017] When the clock signal is at its rising edge, the data signal is set to write, and then the initialization data is transmitted to the register of the SWITCH chip via the data port.

[0018] Optionally, setting the data signal to be written and then transmitting initialization data to the register of the SWITCH chip via the data port includes:

[0019] Set the clock signal as output and set the data signal as output;

[0020] After setting up, obtain the remaining length of the data to be transmitted;

[0021] If the length of the data to be transmitted is empty, set the clock signal to low;

[0022] If the length of the data to be transmitted is not empty, the clock signal is set to low, and after a first preset time delay, the clock signal is toggled. Data sampling is performed when the clock signal is in the rising edge stage, and the clock signal is toggled after a second preset time delay.

[0023] Optionally, the clock signal corresponding to the setting is specifically:

[0024] The clock signal is determined based on the high and low level signals corresponding to the timing output of the GPIO.

[0025] Optionally, determining the clock signal based on the high and low level signals corresponding to the timing of the GPIO output includes:

[0026] The clock signal is achieved by periodically switching between high and low levels using the corresponding GPIO, and the frequency of the clock signal is determined by setting the delay time of the high-low level transition of the GPIO output.

[0027] Optionally, the data signal corresponding to the setting is specifically:

[0028] At the rising edge of the clock signal, the corresponding level status signal is output based on GPIO to determine the data signal;

[0029] Data signals include data transmission and data acquisition.

[0030] In addition, to achieve the above objectives, the present invention also provides a control device, the control device comprising: a memory, a processor, and a control program for a network port device stored in the memory and executable on the processor, the control program for the network port device being configured to implement the control method for the network port device as described above.

[0031] In addition, to achieve the above objectives, the present invention also provides a network port device, including the control device described above.

[0032] This invention initializes the SWITCH chip by running the SWITCH chip initialization firmware when the network port device is powered on and configuring the data port's working mode through the management port. This allows the initialization data to be transmitted to the SWITCH chip's registers via the data port, thus initializing the SWITCH chip. In this solution, the SWITCH chip initialization can be completed before the network port device enters the operating system, eliminating the need for subsequent driver installation under the operating system. Attached Figure Description

[0033] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0034] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0035] Figure 1 This is a schematic flowchart of a control method for a network port device according to an embodiment of the present invention;

[0036] Figure 2 This is a schematic flowchart of a control method for a network port device according to another embodiment of the present invention;

[0037] Figure 3 This is a schematic flowchart of a control method for a network port device according to another embodiment of the present invention;

[0038] Figure 4This is a schematic flowchart of a control method for a network port device according to another embodiment of the present invention;

[0039] Figure 5 This is a schematic flowchart of a control method for a network port device according to another embodiment of the present invention;

[0040] Figure 6 This is a schematic flowchart of a control method for a network port device according to another embodiment of the present invention;

[0041] Figure 7 This is a schematic flowchart of a control method for a network port device according to another embodiment of the present invention;

[0042] Figure 8 This is a schematic flowchart of a control method for a network port device according to another embodiment of the present invention;

[0043] Figure 9 This is a schematic diagram of the seven-layer OSI model;

[0044] Figure 10 This is a schematic diagram of the PHY chip in operation.

[0045] Figure 11 This is a schematic diagram of how the switch chip works.

[0046] Figure 12 This is a block diagram of the internal structure of the network port device in this application;

[0047] Figure 13 This is a timing diagram of the CL22 protocol when reading and writing registers.

[0048] Figure 14 A schematic diagram illustrating the data frame implementation of the CL22 protocol;

[0049] Figure 15 A schematic diagram of instruction data for implementing read / write access operations using four CL22 protocol protocols.

[0050] Figure 16 for Figure 15 A schematic diagram of the data frame containing the instruction data.

[0051] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0052] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Well-known modules, units, and their connections, links, communications, or operations are not shown or described in detail. Furthermore, the described features, architectures, or functions can be combined in any way in one or more embodiments. Those skilled in the art should understand that the various embodiments described below are only for illustrative purposes and not for limiting the scope of protection of the present invention. It is also readily understood that the modules, units, or processing methods in the various embodiments described herein and shown in the accompanying drawings can be combined and designed in various different configurations. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0053] The definitions of various terms or methods used in the following embodiments are, except where logically impossible, generally defined as broad concepts that can be implemented under the premise of the content disclosed in the embodiments. Under this understanding, all specific subordinate limitations of the terms or methods should be considered as part of the invention and should not be narrowly interpreted or biased simply because the specification does not disclose such a specific limitation. Similarly, provided that it is logically feasible, the order of the steps in the method is flexible and varied, and all specific subordinate limitations in the broad concepts of various terms or methods fall within the scope of protection of this invention.

[0054] It should be understood that the firmware mentioned in this application is used to load the operating system image or the embedded application into memory and then jump to the space where the operating system is located to start the operating system.

[0055] In addition, network port devices are generally referred to as PHY (Physical), which is a common abbreviation for the physical layer of the OSI model.

[0056] In the connection between the CPU and the network port, a Serial Management Interface (SMI) or MII Management Interface is typically used. The SMI interface includes two signal lines: MDC and MDIO. MDIO is a PHY management interface used to read / write PHY registers to control PHY behavior or obtain PHY status. MDC, generated by the MAC, provides a clock to MDIO.

[0057] Due to existing technologies, such as Figure 9As shown, the OSI (Open System Interconnect) seven-layer model is a standardized framework that divides computer network communication protocols into seven different layers. Each layer is responsible for different functions, ranging from physical connection to application processing. This model helps different systems better understand and manage the network communication process. The seven-layer model defines a seven-layer framework for network interconnection (physical layer, data link layer, network layer, transport layer, session layer, presentation layer, and application layer), which is the OSI Open System Interconnection Reference Model. The physical layer and data link layer typically have corresponding hardware devices in a computer.

[0058] In the OSI model, the data link layer corresponds to the MAC layer. The MAC layer handles data frame assembly, addressing, error detection (but not correction, which is handled by upper-layer protocols), frame transmission and reception, etc. The OSI physical layer corresponds to the PHY layer. The PHY layer is responsible for transmitting raw bit streams through physical media. Its functions include data encoding and decoding, voltage conversion, driver and receiver management, data transmission rate adaptation, and physical connection maintenance.

[0059] The drivers for the MAC controller and PHY controller are collectively referred to as network card drivers in the system, or simply MAC drivers and PHY drivers. Furthermore, commonly used computer network cards have interfaces such as USB and PCIe. These types of network cards typically integrate the MAC and PHY components, so they can be considered as a single unit. Therefore, in computers, the drivers for the MAC and PHY components can also be directly called network card drivers.

[0060] On embedded devices, such as Figure 10 As shown, a MAC controller is usually integrated on the SOC, and a PHY chip is externally connected to the SOC. In this case, the MAC driver is provided by the SOC manufacturer, and the PHY driver is provided by the PHY chip manufacturer. The PHY and MAC work together in an agreed manner to realize the network function of the system.

[0061] In a multi-port device system, that is, a switch device, such as Figure 11 As shown, it internally combines a MAC and a PHY, and its main function is to forward data between different ports. It also includes a data interface for interfacing with devices such as a System-on-a-Chip (SoC).

[0062] With the continuous evolution of chip technology, PC processors have gradually integrated the functions of the MAC controller. This transformation allows motherboard manufacturers to achieve full network functionality with just a single PHY chip. Furthermore, by installing a matching PHY driver in the operating system, the network function operates smoothly. However, given the replaceability of PC systems, users have the right to change their operating system according to their needs. This characteristic brings a challenge: after changing systems, users must reinstall the PHY (or switch) driver to ensure the normal operation of network functions, significantly increasing the maintenance costs and workload for motherboard manufacturers.

[0063] Among them, such as Figure 10 and Figure 11 As shown, for the CPU, there is little difference between PHY and SWITCH; both are connected to the PHY chip or SWITCH chip respectively through the MAC controller.

[0064] The PHY and SWITCH driver solutions under the Linux platform mainly rely on the MAC controller driver. The MAC controller includes a data interface (RGMII) and a management interface (MDIO). The data interface is used for network data transmission, and the management interface is used to configure the PHY controller, such as configuring the working mode of the PHY chip and controlling the LEDs of the network port.

[0065] like Figure 10 and Figure 11 As shown, after the MAC controller driver is successfully initialized in the Linux system, an MDIO bus is registered. During registration, the PHY driver provides the system with a PHY ID and some interfaces for operating the PHY. The Linux kernel uses all the MDIO buses in the system to send commands to downstream devices and read fixed registers. IEEE 802.3 defines the functions of 16 registers with addresses 0-15. Therefore, the functions of the first 16 registers are the same for each PHY chip, including the PHY ID. Each chip has a different PHY ID. When the kernel reads the PHY ID, it compares it with the ID provided in the PHY driver. If they match, it means that the driver for this PHY chip has been matched. Subsequent PHY initialization, LED configuration, and other operations will be performed using the reporting method of this PHY driver, thus completing the binding between the MAC driver and the PHY driver.

[0066] Based on the above-mentioned technologies, in the existing technologies, given the replaceability of PC systems, users have the right to change the operating system according to their own needs. After the user changes the system, the PHY (or SWITCH) driver must be reinstalled to ensure the normal operation of the network function, which greatly increases the maintenance cost and workload of motherboard manufacturers. In addition, when the Linux system is updated, the PHY (or SWITCH) driver may also become unusable.

[0067] It is important to understand that in this application, the CPU reads or writes data to registers through the management interface using the CL22 protocol. The CL22 protocol, during both read and write operations, is simulated using two GPIO pins of the CPU. Figure 13 As shown, Figure 13 The upper part of the timing diagram shows the timing of the CL22 protocol when reading and accessing the SWITCH register. Figure 13 The lower part of the timing diagram shows the timing of the CL22 protocol when writing to the SWITCH register. The CL22 protocol has two signal lines: a clock signal line and a data signal line. This protocol is simulated using two GPIO pins. The clock signal is generated by periodically pulling the GPIO pin high and low; the delay between high and low signals determines the clock frequency. The data signal line has input and output modes. Data is sent and acquired on the rising edge of the clock signal (i.e., after the GPIO output level changes from low to high). For example, setting the data signal high after the clock signal changes from low to high transmits a 1 to the slave device, and setting it low transmits a 0. The acquisition method is the same; by reading the level of the data signal after the clock signal changes from low to high, the level of the data transmitted from the slave device can be used to determine whether the data is 0 or 1, thus simulating the CL22 protocol.

[0068] The implementation of the CL22 protocol is shown in the table below:

[0069]

[0070] Among them, as shown in the table above and Figure 14As shown, PRE is the frame preamble, consisting of 32 consecutive "1" bits; ST is the start of frame marker, where the start marker in the CL22 protocol is bit "01"; OP is the opcode, where bit "10" in the CL22 protocol indicates a read operation frame, and bit "01" indicates a write operation frame; PHYAD is the physical address of the MMD, consisting of 5 bits. Each MMD compares its address with these 5 bits; if they match, the subsequent operation is initiated; otherwise, the subsequent operation is ignored; REGAD is used to select the 3rd generation MMD. The address of one of the two registers; TA is the state transition field. If it is a read operation, MDIO is in a high-impedance state during the first bit, and MDIO is set to "0" by MMD during the second bit. If it is a write operation, MDIO is still controlled by STA and outputs two consecutive "10" bits; DATA is the data field of the frame register, which has 16 bits. If it is a read operation, it is the data sent from MMD to STA. If it is a write operation, it is the data sent from STA to MMD; IDLE is the idle state after the frame ends. At this time, MDIO is passively driven and is in a high-impedance state. Figure 14 In this context, phyAddr, regAddr, and regVal are variable data, while the others are fixed data. Figure 14 The upper part shows the data frame arrangement style when writing using the CL22 protocol. Figure 14 The lower part shows the data frame arrangement style when reading data using the CL22 protocol.

[0071] It is necessary to understand that, such as Figure 15 As shown, in the register read / write implementation, both the address and value of the SWITCH register are 32-bit data. The address of the register to be written is passed to the device by calling the CL22 protocol write interface twice, and the data to be written is passed to the device by calling the CL22 write interface twice more. This completes one SWITCH register write operation. Therefore, four CL22 protocol instructions are needed to form a complete register read / write interface. In fact, four CL22 instructions can be combined into one register read / write instruction. Each call passes a portion of the value to the slave device. For example, in the register write process: four calls pass the register to be written and the value to be written to that register. The read process is similar; first, the value of the register to be read is passed through the first two CL22 instructions, and then the contents of the register are read through the last two CL22 instructions. And as... Figure 16 The register operation results shown indicate that read and write operations were performed on the switch's registers. This means that these four cl22 instructions have been combined to form a read and write interface. Subsequent access to the switch chip's registers will rely on this read and write interface. Figure 16 In the image, the selected areas in the left image correspond sequentially to the selected areas in the right image.

[0072] It's important to understand that the PHY driver is primarily used to configure the clock frequency, such as gigabit or 100Mbps mode; configure the operating mode, such as RGMII, SGMII, etc.; perform chip initialization; implement soft reset; control the network port LEDs; and control entering and exiting sleep mode. Except for the LEDs and sleep mode, the others are executed only once initially and do not need to be executed again. However, the SWITCH, because it is connected to the MAC address internally on the motherboard, does not have LEDs and is always in a connected state.

[0073] Therefore, in solving the above problems, since the sleep function of the SWITCH chip and the control of the LED lights do not need to be controlled by the CPU, in scenarios where the sleep function and LED lights are not required, the initialization of the SWITCH chip can be completed in the firmware. By running the SWITCH chip initialization firmware when the network port device is powered on, other PHY configurations are executed in the firmware, and the working mode of the data port is configured through the management port. Thus, the initialization data is transmitted to the register of the SWITCH chip through the data port, thereby initializing the SWITCH chip. It is equivalent to the PHY being initialized before entering the operating system, thus achieving the effect of driverless operation under the system.

[0074] In this embodiment, for ease of description, the following description will focus on the control device as the executing entity.

[0075] This application provides a solution that enables the SWITCH chip to be initialized before the network port device enters the system in a solution using the SWITCH chip, thereby eliminating the need for driver installation.

[0076] Therefore, this invention proposes a control method for a network port device. It is understood that the network port device is equipped with a control device for storing and executing the following method. The control device can be implemented using a main controller, such as an MCU (Microcontroller Unit), a DSP (Digital Signal Processor), an FPGA (Field Programmable Gate Array), or a SOC (System On Chip).

[0077] It is necessary to understand that, such as Figure 12 As shown, the network port device in this embodiment includes a CPU and a SWITCH chip. The CPU and SWITCH chip are on the same motherboard and are always connected. The interface between the SWITCH and the CPU includes a data port and a management port.

[0078] In this system, the CPU configures the data port's operating mode through the management port. Subsequent data transmission and reception are then handled by the system's MAC driver. However, in this application, the SWITCH chip needs to be initialized in the firmware via its management port. The SWITCH chip's management port typically uses an MDIO bus, which has two signal lines: clock and data input / output. The data communication protocol is usually SMI, and reading and writing to the SWITCH registers follows the CL22 protocol.

[0079] Reference Figure 1 In one embodiment of the present invention, the control method for the network port device includes steps S100-S200, wherein:

[0080] S100: Run the SWITCH chip initialization firmware and configure the data port working mode through the management port;

[0081] S200: Initialization data is transmitted to the register of the SWITCH chip via the data port to initialize the SWITCH chip.

[0082] In this embodiment, the SWITCH chip initialization firmware is pre-stored in the CPU's non-volatile memory, such as EEPROM (Electrically Erasable Programmable Read-Only Memory). When the network device powers on, the CPU automatically executes the initialization code in the firmware, thereby activating the SWITCH chip's initialization process. The SWITCH chip initialization firmware configures the clock frequency (Gigabit / Megabit mode), operating mode (RGMII, SGMII, etc.), performs a soft reset, configures the management port to enable communication with the SWITCH chip, and sets the data port's operating mode to ensure the correctness and stability of data transmission.

[0083] The SWITCH chip initialization firmware can be set independently of other firmware in other CPUs and stored in one of the CPU's multiple partitions. Alternatively, it can be an adjustment and modification of the original boot firmware so that the original boot firmware contains the corresponding SWITCH chip initialization data.

[0084] During initialization, the firmware sends a series of control commands to the switch chip through the management port. These commands include, but are not limited to, setting the switching table, configuring port speeds, and enabling or disabling specific ports. Simultaneously, the firmware writes necessary initialization data, such as the default MAC address, VLAN configuration, and QoS parameters, to the switch chip's registers to ensure proper operation when connected to the network.

[0085] This embodiment initializes the SWITCH chip by running the SWITCH chip initialization firmware when the network port device is powered on and configuring the working mode of the data port through the management port. The initialization data is then transmitted to the register of the SWITCH chip through the data port, thereby initializing the SWITCH chip. This allows the SWITCH chip to be initialized before the network port device enters the operating system, thus eliminating the need for subsequent driver installation under the operating system.

[0086] Optionally, refer to Figure 2 Another embodiment of the present invention provides a control method for a network port device, based on the above. Figure 1 The illustrated embodiment runs the SWITCH chip initialization firmware, including steps S110-S130, wherein:

[0087] S110, Set the corresponding clock signal and set the corresponding data signal;

[0088] S120. When the clock signal is at the rising edge, set the data signal to read and identify the model and version information of the SWITCH chip.

[0089] S130. Based on the model and version information, run the initialization firmware corresponding to the SWITCH chip.

[0090] In this embodiment, the clock signal can be set by providing it to MDIO through the MDC of the Serial Management Interface, or by setting the management port to GPIO (General Purpose Input / Output) mode and setting the clock signal through the high and low level state transitions of GPIO. The data signal can be set through the MDIO of the Serial Management Interface, or by setting the data signal through the high and low level state transitions of GPIO.

[0091] First, the multiplexing function of the CPU's corresponding pin is changed from MDIO to GPIO, defined as two pins, DATA and SCK, respectively, and the corresponding delay function is set. In the implementation process, the clock signal is realized by controlling the output of the SCK pin to be high or low, and inserting a fixed delay before each level change. The rising edge of the SCK signal is the sampling point, so DATA is set immediately after the CLK level is set high, thereby realizing the transmission of DATA data.

[0092] The data signal can be set to read or write. When the network port device is powered on, the firmware initialization process of the SWITCH chip needs to identify the model and version information of the corresponding SWITCH chip and call the initialization program in the firmware that matches the model and version information, so as to ensure the accuracy and efficiency of the initialization process.

[0093] The clock signal frequency is set to match the specifications of the switch chip to ensure that the data signals can be read correctly. Setting the data signals involves configuring the data signal lines to a high or low level to indicate a read or write operation.

[0094] When the clock signal is at its rising edge, the data signal is set to read mode. At this time, the CPU monitors the data signal lines to identify the model and version information of the switch chip. This model and version information is typically contained in the switch chip's internal registers and can be retrieved using specific read commands. Once the model and version information is identified, the CPU selects and runs the initialization firmware that matches the switch chip model, or retrieves the initialization data corresponding to the model and version information from the switch chip's initialization firmware, thereby completing the initialization of the switch chip within the firmware.

[0095] Through the above method, this embodiment can ensure that when the network port device is powered on, the correct initialization firmware can be automatically identified and loaded, thereby achieving fast and accurate initialization of the SWITCH chip.

[0096] Optionally, refer to Figure 3 Another embodiment of the present invention provides a control method for a network port device, based on the above. Figure 2 The embodiment shown identifies the model version information corresponding to the SWITCH chip, including steps S121-S123, wherein:

[0097] S121. After the data signal is set, obtain the remaining length of the data to be transmitted;

[0098] S122. If the length of the data to be transmitted is empty, set the clock signal to low;

[0099] S123. If the length of the data to be transmitted is not empty, set the clock signal to low, and after a first preset time delay, toggle the clock signal. When the clock signal is at the rising edge, perform data sampling, and after a second preset time delay, set the clock signal to low.

[0100] In this embodiment, identifying the model version information of the SWITCH chip mainly involves reading the model version information stored in the registers of the SWITCH chip. During the reading process, it is necessary to ensure the stability and accuracy of the data signal. First, after the data signal is set, the remaining length of the data to be transmitted is obtained. If the length of the data to be transmitted is empty, the clock signal will be set to a low level to wait for the next data transmission or reading. If the length of the data to be transmitted is not empty, the clock signal needs to be set to a low level first, and after a first preset time delay, the clock signal is toggled to produce a rising edge, allowing the model version information to be read at the rising edge of the clock signal, ensuring correct data sampling. Subsequently, after a second preset time delay, the clock signal is set to a low level again to prepare for the next data transmission or reading. The first and second preset times can be equal or unequal in length, depending on the stability and timing requirements of the data transmission.

[0101] Optionally, refer to Figure 4 Another embodiment of the present invention provides a control method for a network port device, based on the above. Figure 1 In the embodiment shown, transmitting initialization data to the register of the SWITCH chip via the data port specifically involves steps S210-S220, wherein:

[0102] S210, Obtain the corresponding clock signal and data signal;

[0103] S220: When the clock signal is at the rising edge, the data signal is set to write, and the initialization data is transmitted to the register of the SWITCH chip via the data port.

[0104] In this embodiment, the clock signal and data signal settings have already been completed during firmware operation. When the clock signal is needed, the stored setting value is retrieved. Specifically, when initialization data needs to be transmitted to the SWITCH chip's registers, the control device obtains the clock signal and data signal configured during firmware operation to ensure the accuracy of data transmission.

[0105] In this embodiment, during the transmission of initialization data, the control device first acquires the corresponding clock signal and data signal, and sets the data signal to write mode when the clock signal is at its rising edge. Then, the control device transmits the initialization data to the register of the SWITCH chip via the data port. To ensure the reliability of data transmission, the control device performs multiple sampling and verification processes during data transmission to ensure the integrity and correctness of the data.

[0106] Optionally, refer to Figure 5 The present invention also provides a control method for a network port device based on the above. Figure 4 The embodiment shown describes a process where, after the data signal is set to be written, initialization data is transmitted to the register of the SWITCH chip via the data port, including steps S221-S224, wherein:

[0107] S221. Set the clock signal as output and the data signal as output;

[0108] S222. After setting, obtain the remaining length of the data to be transmitted;

[0109] S223. If the length of the data to be transmitted is empty, set the clock signal to low;

[0110] S224. If the length of the data to be transmitted is not empty, set the clock signal to low, and after a first preset time delay, toggle the clock signal. When the clock signal is at the rising edge stage, perform data sampling, and after a second preset time delay, toggle the clock signal.

[0111] In this embodiment, during the transmission of initialization data to the SWITCH chip register, the control device ensures the synchronization of the clock signal and data signal to avoid any errors or delays during data transmission. First, the control device sets the clock signal to output mode and also sets the data signal to output mode. This setting ensures that the data signal and clock signal can be accurately sent to the SWITCH chip according to a predetermined timing sequence.

[0112] After setup, the control device will obtain the remaining length of the data to be transmitted. If the data length is empty, meaning no more data needs to be sent, the control device will set the clock signal to a low level to avoid unnecessary clock pulse transmission. This allows it to wait for the next data transmission, improving the overall efficiency of the network port device.

[0113] If the length of the data to be transmitted is not empty, the control device sets the clock signal to a low level and, after a first preset time delay, toggles the clock signal, generating a rising edge. While the clock signal is at its rising edge, the control device samples the data to ensure it can be correctly read by the switch chip. After a second preset time delay, the clock signal toggles again to prepare for the next data transmission. By adjusting the clock signal using a time delay and sampling the data at appropriate times, the accuracy and stability of data transmission are ensured, guaranteeing that the initialization data is accurately transmitted to the switch chip's registers, thus completing the initialization process.

[0114] Optionally, refer to Figure 6 Another embodiment of the present invention provides a control method for a network port device, based on the above. Figure 2 In the embodiment shown, setting the corresponding clock signal specifically involves step S111, wherein:

[0115] S111. Determine the clock signal based on the high and low level signals corresponding to the GPIO output timing.

[0116] In this embodiment, GPIO is obtained by modifying the management port between the SWITCH chip and the CPU and reusing it, that is, reusing the MDIO interface to realize general data input and output. By outputting high and low level signals through GPIO, the timing of the clock signal can be precisely controlled, thereby ensuring the synchronization and accuracy of data transmission. In the process of setting the clock signal, the control device first determines the required clock frequency and timing requirements, and then outputs the corresponding high and low level signal sequence through the programmed GPIO port to simulate the waveform of the clock signal.

[0117] It's important to understand that the firmware data in the MDIO ports of CPUs currently on the market has already been processed by manufacturers using preset encryption methods. When it's necessary to add firmware or modify the program in the firmware, it cannot be directly modified. Furthermore, some manufacturers do not provide and keep the firmware confidential, making it impossible to achieve the required driverless switching chip. Therefore, to solve the above problems, the MDIO port can be multiplexed and adjusted to be used as a GPIO port. By multiplexing the GPIO port, the problems of firmware data encryption and lack of modification capability in the market can be effectively solved.

[0118] The required clock frequency and timing parameters can be calculated by consulting the specifications and datasheet of the switch chip. Then, the GPIO ports can be programmed to output high and low levels corresponding to the timing, thereby simulating the clock and data signals. For example, if a 1MHz clock signal is needed, the GPIO ports can be controlled to alternately output high and low level signals at 1-microsecond intervals, thus meeting the timing control requirements in the network port driver process.

[0119] Optionally, refer to Figure 7 Another embodiment of the present invention provides a control method for a network port device, based on the above. Figure 6 The embodiment shown determines the clock signal based on the high and low level signals corresponding to the GPIO output timing, including step S1111, wherein:

[0120] S1111: The clock signal is implemented by the periodic high-low transition of the corresponding GPIO, and the frequency of the clock signal is determined by setting the delay time of the high-low transition of the GPIO output.

[0121] In this embodiment, the clock signal exhibits a clear periodicity. It outputs high and low levels via GPIO, and each high-low level transition constitutes a complete cycle.

[0122] By controlling the delay time of the GPIO output level transitions, the frequency of the clock signal can be precisely controlled. For example, to generate a 1MHz clock signal, the control device will set the GPIO port to alternately output high and low level signals at 1-microsecond intervals. To generate a 10MHz clock signal, the control device will set the GPIO port to alternately output high and low level signals at 100-nanosecond intervals to simulate the waveform of the clock signal. This periodic high-low level transition ensures the stability and accuracy of the clock signal, thereby meeting the timing requirements of the network interface device during data transmission.

[0123] Furthermore, the control device can dynamically adjust the delay time of the GPIO output to change the frequency of the clock signal according to different application scenarios and performance requirements. This flexibility enables the network port device to adapt to various network environments and data transmission rates, improving the device's applicability and reliability, and effectively completing the initialization process while ensuring that data is accurately transmitted to the registers of the SWITCH chip.

[0124] Optionally, refer to Figure 8 Another embodiment of the present invention provides a control method for a network port device, based on the above. Figure 6 In the embodiment shown, setting the corresponding data signal specifically involves step S112, wherein:

[0125] S112. At the rising edge of the clock signal, output the corresponding level status signal based on GPIO to determine the data signal;

[0126] Data signals include data transmission and data acquisition.

[0127] In this embodiment, sampling at the rising edge of the clock signal ensures that all operations are performed at the same reference point, thereby guaranteeing the synchronization of the initialization firmware during operation and maintaining data consistency and integrity. Furthermore, sampling data at the rising edge of the clock utilizes the rapid changes in the clock edge to trigger the sampling action, reducing erroneous sampling caused by noise or signal jitter. By setting appropriate setup and hold times, the state of the data signal can be accurately captured at the rising edge of the clock. This helps avoid misreading problems caused by data instability and improves the reliability of data transmission.

[0128] In this embodiment, the setting of the data signal is simulated by using high and low level data output from GPIO. This GPIO and the GPIO port for setting the clock signal are not on the same CPU pin; that is, the clock signal and data signal each have their own GPIO port. This improves the stability and accuracy of data transmission. During the data signal setting process, the control device first determines the data transmission rate and format, and then outputs the corresponding high and low level signal sequences through programming the GPIO port to simulate the waveform of the data signal. For example, if an 8-bit data signal needs to be transmitted, the GPIO port can be configured to output high and low level signals in a specific sequence to ensure the correctness and integrity of the data signal.

[0129] The data signal can have both input and output modes. Data is sent and acquired on the rising edge of the clock signal (that is, after it changes from low to high). For example, after the clock signal changes from low to high, setting the data signal to a high level transmits a 1 to the SWITCH chip, while setting it to a low level transmits a 0. The acquisition method is the same. After the clock signal changes from low to high, the level of the data signal can be read to determine whether the data transmitted by the SWITCH chip is 0 or 1, thus completing the transmission or acquisition of data.

[0130] The present invention also proposes a control device, the control device comprising: a memory, a processor, and a control program for a network port device stored in the memory and executable on the processor, the control program for the network port device being configured to implement the control method for the network port device as described above.

[0131] It is worth noting that since the control device of the present invention is based on the control method of the network port device described above, the embodiments of the control device of the present invention include all the technical solutions of all embodiments of the control method of the network port device described above, and the technical effects achieved are exactly the same, so they will not be repeated here.

[0132] The present invention also proposes a network port device, which includes the control device as described in the above embodiments.

[0133] It is worth noting that since the network port device of the present invention is based on the above-mentioned control device, the embodiments of the network port device of the present invention include all the technical solutions of all the embodiments of the above-mentioned control device, and the technical effects achieved are exactly the same, which will not be repeated here.

[0134] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0135] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0136] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0137] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A control method for a network port device, the network port device comprising a CPU and a SWITCH chip, wherein the interface between the SWITCH and the CPU includes a data port and a management port, characterized in that, The control method includes: Run the SWITCH chip initialization firmware and configure the working mode of the data port through the management port; Initialization data is transmitted to the register of the SWITCH chip via the data port to initialize the SWITCH chip; The specific steps of transmitting initialization data to the register of the SWITCH chip via the data port are as follows: Obtain the corresponding clock signal and data signal; When the clock signal is at the rising edge, the data signal is set to write, and the initialization data is transmitted to the register of the SWITCH chip via the data port. After setting the data signal to write, the initialization data is transmitted to the register of the SWITCH chip via the data port, including: Set the clock signal as output and set the data signal as output; After setting up, obtain the remaining length of the data to be transmitted; If the remaining length of the data to be transmitted is empty, set the clock signal to low; If the remaining length of the data to be transmitted is not empty, the clock signal is set to low, and after a first preset time delay, the clock signal is toggled. Data sampling is performed when the clock signal is in the rising edge stage, and the clock signal is toggled after a second preset time delay.

2. The control method for the network port device as described in claim 1, characterized in that, The firmware for initializing the SWITCH chip includes: Set the corresponding clock signal and set the corresponding data signal; When the clock signal is at the rising edge, the data signal is set to read, and the model and version information corresponding to the SWITCH chip is identified; Based on the model and version information, run the initialization firmware corresponding to the SWITCH chip.

3. The control method for the network port device as described in claim 2, characterized in that, The identification of the model version information corresponding to the SWITCH chip includes: After the data signal is set, obtain the remaining length of the data to be transmitted; If the remaining length of the data to be transmitted is empty, set the clock signal to low; If the remaining length of the data to be transmitted is not empty, the clock signal is set to low, and after a first preset time delay, the clock signal is toggled. Data is sampled when the clock signal is at its rising edge, and after a second preset time delay, the clock signal is set to low.

4. The control method for the network port device as described in claim 2, characterized in that, The specific clock signal corresponding to the setting is: The clock signal is determined based on the high and low level signals corresponding to the timing output of the GPIO.

5. The control method for the network port device as described in claim 4, characterized in that, The determination of the clock signal based on the high and low level signals corresponding to the timing of the GPIO output includes: The clock signal is achieved by periodically switching between high and low levels using the corresponding GPIO, and the frequency of the clock signal is determined by setting the delay time of the high-low level transition of the GPIO output.

6. The control method for the network port device as described in claim 4, characterized in that, The specific data signal corresponding to the setting is: At the rising edge of the clock signal, the data signal is determined based on the corresponding level status signal output by the GPIO. Data signals include data transmission and data acquisition.

7. A control device, characterized in that, The control device includes: a memory, a processor, and a control program for the network port device stored in the memory and executable on the processor, wherein the control program for the network port device is configured to implement the control method for the network port device as described in any one of claims 1 to 6.

8. A network port device, characterized in that, Includes the control device as described in claim 7.

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