Verification method and system of RTL test item of RISC-V DSP chip and medium
Through the RTL testing framework, real-time verification and dynamic adjustment of configuration information of the RISC-V DSP chip test items are solved, which solves the problem that the accuracy of the test data cannot be effectively verified in the prior art and improves the test accuracy.
Patent Information
- Application Number
- CN202411925051.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2025-04-18
AI Technical Summary
Existing verification methods cannot verify the accuracy of test data for different test items, making it difficult to dynamically adjust the configuration parameters of the test framework, affecting the test effect.
The test data of the test items is verified in real time through the RTL testing framework, and the configuration information is dynamically adjusted according to the verification results to improve the test accuracy of the test items.
Real-time verification of test data of test items and dynamic adjustment of configuration information is realized, and the testing accuracy of test items is improved.
Smart Images
Figure CN119847841A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of chip test data verification, and in particular to a verification method, system and medium for RTL test items of a RISC-VDSP chip. Background Art
[0002] The RTL batch automatic testing framework is used to perform batch automatic testing in the scenario of multiple projects / multiple test case sets at the RTL (Register-Transfer Level) level during VERILOG design.
[0003] The RTL batch automatic testing framework includes general configuration and independent configuration information for each project, a set of input stimuli (test cases) for each project, and the RTL design code for each project. It conforms to the test stimulus-test environment-test output architecture design and can be used to test the RTL code of each project itself, as well as the key data used by the RTL code. It can also test various input stimuli that may have specific functions in subsequent applications.
[0004] The test framework has the characteristics of batch and parallel testing, which can quickly verify the above test purposes and perform rapid migration and regression testing in test projects with inheritance.
[0005] The existing verification methods cannot verify the accuracy of test data for different test items, making it difficult to dynamically adjust the configuration parameters of the test framework, affecting the test results. Summary of the invention
[0006] The purpose of the embodiments of the present application is to provide a verification method, system and medium for RTL test items of a RISC-V DSP chip, to verify the test data of the test items in real time through an RTL test framework, and to dynamically adjust the configuration information according to the verification results to improve the test accuracy of the test items.
[0007] The embodiment of the present application also provides a method for verifying RTL test items of a RISC-V DSP chip, including:
[0008] Select test items, test them based on the RTL test framework, and obtain test data;
[0009] Obtain configuration information of the RTL test framework, verify the test data based on the configuration information, and obtain verification information;
[0010] Compare the verification information with the set condition information to obtain the test deviation rate;
[0011] Determining whether the test deviation rate is greater than or equal to a set test deviation rate threshold;
[0012] If the value is greater than or equal to the set test deviation rate threshold, correction information is generated, and the configuration information of the RTL test framework is adjusted based on the correction information;
[0013] If it is less than the set test deviation rate threshold, the test data will be used to generate a test report in real time, and the test report will be sent to the terminal according to the set transmission method.
[0014] Optionally, in the RTL test item verification method of the RISC-V DSP chip described in the embodiment of the present application, selecting a test item, testing the test item based on the RTL test framework, and obtaining test data specifically includes:
[0015] Obtain test input data, test criteria code or script input into the tested environment;
[0016] Obtain independent configuration of test items, and generate test logic based on the independent configuration of test items;
[0017] Based on the test logic, test input data, test criteria code or script in the tested environment are independently tested to obtain test data;
[0018] The test data includes initialized RAM data, Flash data, ROM data, OTP data and timing-related external stimulus data.
[0019] Optionally, in the verification method of the RTL test items of the RISC-V DSP chip described in the embodiment of the present application, obtaining the configuration information of the RTL test framework, verifying the test data based on the configuration information, and obtaining the verification information specifically includes:
[0020] Get the configuration information of the RTL test framework, which includes the general configuration information of the framework and the independent configuration information of the test items;
[0021] Verifying the test data in a first manner based on the general configuration information of the framework to generate first verification information;
[0022] Performing a second mode verification on the test data based on the independent configuration information of the test item to generate second verification information;
[0023] The first verification information and the second verification information are merged to obtain final verification information.
[0024] Optionally, in the verification method of the RTL test items of the RISC-V DSP chip described in the embodiment of the present application, the configuration information of the RTL test framework is adjusted based on the correction information, specifically including:
[0025] Comparing the test deviation rate with a set test deviation rate threshold, wherein the set test deviation rate includes a first test deviation rate threshold and a second test deviation rate threshold, and the first test deviation rate threshold is less than the second test deviation rate threshold;
[0026] If the test deviation rate is greater than a first test deviation rate threshold and less than a second test deviation rate threshold, generating first correction information;
[0027] Adjusting the configuration information of the RTL test framework in a first manner based on the first correction information;
[0028] If the test deviation rate is greater than or equal to a second test deviation rate threshold, generating second correction information;
[0029] The configuration information of the RTL test framework is adjusted in a second manner based on the second correction information.
[0030] Optionally, in the verification method of the RTL test items of the RISC-V DSP chip described in the embodiment of the present application, a test report is generated in real time from the test data, and the test report is sent to the terminal according to a set transmission mode, specifically including:
[0031] Match the corresponding test data based on the independent configuration of the test items;
[0032] Generate a sub-report for the test data of different independently configured test items;
[0033] Arrange all the sub-reports of test items into a complete test report;
[0034] The memory usage of the test report is analyzed and stored in a storage area in the terminal that is larger than the memory usage based on the memory usage.
[0035] Optionally, in the verification method of the RTL test items of the RISC-V DSP chip described in the embodiment of the present application, obtaining the configuration information of the RTL test framework, verifying the test data based on the configuration information, and obtaining the verification information further includes:
[0036] Get the configuration information of the RTL test framework, which includes the general configuration information of the framework and the independent configuration information of the test items;
[0037] Generate processing information of the test data based on the independent configuration information of the test item to obtain processing data;
[0038] The verification interaction logic of the test framework is generated based on the common configuration information of the framework, and the processed data is interactively verified based on the verification interaction logic of the verification framework to generate verification information.
[0039] In a second aspect, an embodiment of the present application provides a verification system for RTL test items of a RISC-V DSP chip, the system comprising: a memory and a processor, the memory comprising a program of a verification method for RTL test items of a RISC-V DSP chip, and the program of the verification method for RTL test items of the RISC-V DSP chip is executed by the processor to implement the following steps:
[0040] Select test items, test them based on the RTL test framework, and obtain test data;
[0041] Obtain configuration information of the RTL test framework, verify the test data based on the configuration information, and obtain verification information;
[0042] Compare the verification information with the set condition information to obtain the test deviation rate;
[0043] Determining whether the test deviation rate is greater than or equal to a set test deviation rate threshold;
[0044] If the value is greater than or equal to the set test deviation rate threshold, correction information is generated, and the configuration information of the RTL test framework is adjusted based on the correction information;
[0045] If it is less than the set test deviation rate threshold, the test data will be used to generate a test report in real time, and the test report will be sent to the terminal according to the set transmission method.
[0046] Optionally, in the RTL test item verification system of the RISC-V DSP chip described in the embodiment of the present application, selecting a test item, testing the test item based on the RTL test framework, and obtaining test data specifically includes:
[0047] Obtain test input data, test criteria code or script input into the tested environment;
[0048] Obtain independent configuration of test items, and generate test logic based on the independent configuration of test items;
[0049] Based on the test logic, test input data, test criteria code or script in the tested environment are independently tested to obtain test data;
[0050] The test data includes initialized RAM data, Flash data, ROM data, OTP data and timing-related external stimulus data.
[0051] Optionally, in the verification system of the RTL test items of the RISC-V DSP chip described in the embodiment of the present application, the configuration information of the RTL test framework is obtained, and the test data is verified based on the configuration information to obtain the verification information, which specifically includes:
[0052] Get the configuration information of the RTL test framework, which includes the general configuration information of the framework and the independent configuration information of the test items;
[0053] Verifying the test data in a first manner based on the general configuration information of the framework to generate first verification information;
[0054] Performing a second mode verification on the test data based on the independent configuration information of the test item to generate second verification information;
[0055] The first verification information and the second verification information are merged to obtain final verification information.
[0056] In a third aspect, an embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium includes a verification method program for RTL test items of a RISC-V DSP chip. When the verification method program for the RTL test items of the RISC-V DSP chip is executed by a processor, the steps of the verification method for the RTL test items of the RISC-V DSP chip as described in any one of the above items are implemented.
[0057] As can be seen from the above, an embodiment of the present application provides a verification method, system and medium for RTL test items of a RISC-V DSP chip, which selects a test item, tests the test item based on an RTL test framework, and obtains test data; obtains configuration information of the RTL test framework, verifies the test data based on the configuration information, and obtains verification information; compares the verification information with the set condition information to obtain a test deviation rate; determines whether the test deviation rate is greater than or equal to a set test deviation rate threshold; if it is greater than or equal to the set test deviation rate threshold, generates correction information, and adjusts the configuration information of the RTL test framework based on the correction information; if it is less than the set test deviation rate threshold, generates a test report in real time for the test data, and sends the test report to the terminal according to the set transmission method; verifies the test data of the test item in real time through the RTL test framework, and dynamically adjusts the configuration information according to the verification result to improve the test accuracy of the test item. BRIEF DESCRIPTION OF THE DRAWINGS
[0058] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0059] Figure 1 A flowchart of a method for verifying RTL test items of a RISC-V DSP chip provided in an embodiment of the present application;
[0060] Figure 2 A flow chart of a test data acquisition method for a verification method of an RTL test item of a RISC-V DSP chip provided in an embodiment of the present application;
[0061] Figure 3 A flow chart of a verification information acquisition method for a verification method for RTL test items of a RISC-V DSP chip provided in an embodiment of the present application. DETAILED DESCRIPTION
[0062] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.
[0063] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.
[0064] Please refer to Figure 1 , Figure 1 The present invention is a flowchart of a method for verifying an RTL test item of a RISC-V DSP chip in some embodiments of the present invention. The method for verifying an RTL test item of a RISC-V DSP chip is used in a terminal device, and the method for verifying an RTL test item of a RISC-V DSP chip comprises the following steps:
[0065] S101, selecting a test item, testing the test item based on an RTL test framework, and obtaining test data;
[0066] S102, obtaining configuration information of the RTL test framework, and verifying the test data based on the configuration information to obtain verification information;
[0067] S103, comparing the verification information with the set condition information to obtain a test deviation rate;
[0068] S104, determining whether the test deviation rate is greater than or equal to a set test deviation rate threshold;
[0069] S105: If the value is greater than or equal to the set test deviation rate threshold, correction information is generated, and the configuration information of the RTL test framework is adjusted based on the correction information; if the value is less than the set test deviation rate threshold, a test report is generated in real time based on the test data, and the test report is sent to the terminal according to the set transmission method.
[0070] It should be noted that the test data is verified in real time through the RTL test framework, and the verification information is dynamically analyzed, so that the configuration information of the RTL test framework is dynamically adjusted according to the analysis results to improve the test accuracy of the test items.
[0071] Please refer to Figure 2 , Figure 2 This is a flow chart of a test data acquisition method of a verification method for an RTL test item of a RISC-V DSP chip in some embodiments of the present application. According to an embodiment of the present invention, a test item is selected, and the test item is tested based on an RTL test framework to obtain test data, specifically including:
[0072] S201, obtaining test input data, test criteria code or script and inputting it into the tested environment;
[0073] S202, obtaining independent configuration of the test item, and generating test logic based on the independent configuration of the test item;
[0074] S203, independently testing the test input data, test criterion code or script in the tested environment based on the test logic to obtain test data;
[0075] S204, the test data includes initialized RAM data, Flash data, ROM data, OTP data and timing-related external stimulus data.
[0076] It should be noted that by independently configuring the test items, corresponding test logic is generated, and different test logics test the test input data to accurately obtain the test data.
[0077] Please refer to Figure 3 , Figure 3 The present invention is a flowchart of a verification information acquisition method of a verification method for an RTL test item of a RISC-V DSP chip in some embodiments of the present application. According to an embodiment of the present invention, the configuration information of the RTL test framework is obtained, and the test data is verified based on the configuration information to obtain the verification information, which specifically includes:
[0078] S301, obtaining configuration information of an RTL test framework, where the configuration information includes general configuration information of the framework and independent configuration information of test items;
[0079] S302, verifying the test data in a first manner based on the general configuration information of the framework to generate first verification information;
[0080] S303, verifying the test data in a second manner based on the independent configuration information of the test item to generate second verification information;
[0081] S304: merge the first verification information and the second verification information to obtain final verification information.
[0082] It should be noted that the common configuration of the framework and the independent configuration information of the test items are verified separately to generate different verification information, which are then integrated to obtain accurate verification information and improve the verification effect.
[0083] According to an embodiment of the present invention, adjusting the configuration information of the RTL test framework based on the correction information specifically includes:
[0084] Comparing the test deviation rate with a set test deviation rate threshold, the set test deviation rate includes a first test deviation rate threshold and a second test deviation rate threshold, and the first test deviation rate threshold is less than the second test deviation rate threshold;
[0085] If the test deviation rate is greater than a first test deviation rate threshold and less than a second test deviation rate threshold, generating first correction information;
[0086] Adjusting the configuration information of the RTL test framework in a first manner based on the first correction information;
[0087] If the test deviation rate is greater than or equal to a second test deviation rate threshold, generating second correction information;
[0088] The configuration information of the RTL test framework is adjusted in a second manner based on the second correction information.
[0089] It should be noted that by analyzing the test deviation rate, different test deviation rates generate different correction information, so that the configuration information of the test framework is accurately adjusted in different ways to improve the adjustment accuracy.
[0090] According to an embodiment of the present invention, generating a test report from test data in real time, and sending the test report to a terminal according to a set transmission mode, specifically includes:
[0091] Match the corresponding test data based on the independent configuration of the test items;
[0092] Generate a sub-report for the test data of different independently configured test items;
[0093] Arrange all the sub-reports of test items into a complete test report;
[0094] The memory usage of the test report is analyzed and stored in a storage area in the terminal that is larger than the memory usage based on the memory usage.
[0095] It should be noted that by analyzing the test data of the test items corresponding to different independent configurations, the test data of different independent configurations are analyzed separately, thereby improving the calling efficiency when calling the data, and ensuring that the storage area can meet the memory usage of the test report when saving.
[0096] According to an embodiment of the present invention, obtaining configuration information of an RTL test framework, verifying test data based on the configuration information, and obtaining verification information further includes:
[0097] Get the configuration information of the RTL test framework, which includes the general configuration information of the framework and the independent configuration information of the test items;
[0098] Generate processing information of the test data based on the independent configuration information of the test item to obtain processing data;
[0099] The verification interaction logic of the test framework is generated based on the common configuration information of the framework, and the processed data is interactively verified based on the verification interaction logic of the verification framework to generate verification information.
[0100] It should be noted that by cross-validating the test data, the accuracy of the verification is guaranteed and verification errors that occur during single-method verification are prevented.
[0101] In a second aspect, an embodiment of the present application provides a verification system for RTL test items of a RISC-V DSP chip, the system comprising: a memory and a processor, the memory comprising a program of a verification method for RTL test items of a RISC-V DSP chip, and when the program of the verification method for RTL test items of a RISC-V DSP chip is executed by the processor, the following steps are implemented:
[0102] Select test items, test them based on the RTL test framework, and obtain test data;
[0103] Obtain configuration information of the RTL test framework, verify the test data based on the configuration information, and obtain verification information;
[0104] Compare the verification information with the set condition information to obtain the test deviation rate;
[0105] Determine whether the test deviation rate is greater than or equal to a set test deviation rate threshold;
[0106] If the value is greater than or equal to the set test deviation rate threshold, correction information is generated, and the configuration information of the RTL test framework is adjusted based on the correction information;
[0107] If it is less than the set test deviation rate threshold, the test data will be used to generate a test report in real time, and the test report will be sent to the terminal according to the set transmission method.
[0108] It should be noted that the test data is verified in real time through the RTL test framework, and the verification information is dynamically analyzed, so that the configuration information of the RTL test framework is dynamically adjusted according to the analysis results to improve the test accuracy of the test items.
[0109] According to an embodiment of the present invention, a test item is selected, and the test item is tested based on an RTL test framework to obtain test data, which specifically includes:
[0110] Obtain test input data, test criteria code or script input into the tested environment;
[0111] Obtain independent configuration of test items, and generate test logic based on the independent configuration of test items;
[0112] Based on the test logic, test input data, test criteria code or script in the tested environment are independently tested to obtain test data;
[0113] The test data includes initialized RAM data, Flash data, ROM data, OTP data, and timing-related external stimulus data.
[0114] It should be noted that by independently configuring the test items, corresponding test logic is generated, and different test logics test the test input data to accurately obtain the test data.
[0115] According to an embodiment of the present invention, obtaining configuration information of an RTL test framework, verifying test data based on the configuration information, and obtaining verification information specifically includes:
[0116] Get the configuration information of the RTL test framework, which includes the general configuration information of the framework and the independent configuration information of the test items;
[0117] Verifying the test data in a first manner based on the general configuration information of the framework to generate first verification information;
[0118] Performing a second mode verification on the test data based on the independent configuration information of the test item to generate second verification information;
[0119] The first verification information and the second verification information are merged to obtain final verification information.
[0120] It should be noted that the common configuration of the framework and the independent configuration information of the test items are verified separately to generate different verification information, which are then integrated to obtain accurate verification information and improve the verification effect.
[0121] According to an embodiment of the present invention, adjusting the configuration information of the RTL test framework based on the correction information specifically includes:
[0122] Comparing the test deviation rate with a set test deviation rate threshold, the set test deviation rate includes a first test deviation rate threshold and a second test deviation rate threshold, and the first test deviation rate threshold is less than the second test deviation rate threshold;
[0123] If the test deviation rate is greater than a first test deviation rate threshold and less than a second test deviation rate threshold, generating first correction information;
[0124] Adjusting the configuration information of the RTL test framework in a first manner based on the first correction information;
[0125] If the test deviation rate is greater than or equal to a second test deviation rate threshold, generating second correction information;
[0126] The configuration information of the RTL test framework is adjusted in a second manner based on the second correction information.
[0127] It should be noted that by analyzing the test deviation rate, different test deviation rates generate different correction information, so that the configuration information of the test framework is accurately adjusted in different ways to improve the adjustment accuracy.
[0128] According to an embodiment of the present invention, generating a test report from test data in real time, and sending the test report to a terminal according to a set transmission mode, specifically includes:
[0129] Match the corresponding test data based on the independent configuration of the test items;
[0130] Generate a sub-report for the test data of different independently configured test items;
[0131] Arrange all the sub-reports of test items into a complete test report;
[0132] The memory usage of the test report is analyzed and stored in a storage area in the terminal that is larger than the memory usage based on the memory usage.
[0133] It should be noted that by analyzing the test data of the test items corresponding to different independent configurations, the test data of different independent configurations are analyzed separately, thereby improving the calling efficiency when calling the data, and ensuring that the storage area can meet the memory usage of the test report when saving.
[0134] According to an embodiment of the present invention, obtaining configuration information of an RTL test framework, verifying test data based on the configuration information, and obtaining verification information further includes:
[0135] Get the configuration information of the RTL test framework, which includes the general configuration information of the framework and the independent configuration information of the test items;
[0136] Generate processing information of the test data based on the independent configuration information of the test item to obtain processing data;
[0137] The verification interaction logic of the test framework is generated based on the common configuration information of the framework, and the processed data is interactively verified based on the verification interaction logic of the verification framework to generate verification information.
[0138] It should be noted that by cross-validating the test data, the accuracy of the verification is guaranteed and verification errors that occur during single-method verification are prevented.
[0139] A third aspect of the present invention provides a computer-readable storage medium, which includes a verification method program for the RTL test items of a RISC-V DSP chip. When the verification method program for the RTL test items of a RISC-V DSP chip is executed by a processor, the steps of the verification method for the RTL test items of a RISC-V DSP chip as described in any of the above items are implemented.
[0140] The present invention discloses a verification method, system and medium for RTL test items of a RISC-V DSP chip. The method comprises the following steps: selecting a test item, testing the test item based on an RTL test framework, and obtaining test data; obtaining configuration information of the RTL test framework, and verifying the test data based on the configuration information, and obtaining verification information; comparing the verification information with set condition information, and obtaining a test deviation rate; judging whether the test deviation rate is greater than or equal to a set test deviation rate threshold; if the test deviation rate is greater than or equal to the set test deviation rate threshold, generating correction information, and adjusting the configuration information of the RTL test framework based on the correction information; if the test deviation rate is less than the set test deviation rate threshold, generating a test report from the test data in real time, and sending the test report to a terminal according to a set transmission mode; verifying the test data of the test item in real time through the RTL test framework, and dynamically adjusting the configuration information according to the verification result, so as to improve the test accuracy of the test item.
[0141] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.
[0142] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.
[0143] In addition, all functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.
[0144] Those skilled in the art can understand that: all or part of the steps of implementing the above method embodiments can be completed by hardware related to program instructions, the aforementioned program can be stored in a readable storage medium, and when the program is executed, it executes the steps of the above method embodiments; and the aforementioned storage medium includes: mobile storage devices, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), disks or optical disks, and other media that can store program codes.
[0145] Or, if the above-mentioned integrated unit of the present invention is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present invention can be essentially or partly reflected in the form of a software product that contributes to the prior art. The software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROM, RAM, magnetic disks or optical disks.
Claims
1. A verification method for RTL test items of a RISC-V DSP chip, characterized in that: include: Select test items, test them based on the RTL test framework, and obtain test data; Obtain configuration information of the RTL test framework, verify the test data based on the configuration information, and obtain verification information; Compare the verification information with the set condition information to obtain the test deviation rate; Determining whether the test deviation rate is greater than or equal to a set test deviation rate threshold; If the value is greater than or equal to the set test deviation rate threshold, correction information is generated, and the configuration information of the RTL test framework is adjusted based on the correction information; If it is less than the set test deviation rate threshold, the test data will be used to generate a test report in real time, and the test report will be sent to the terminal according to the set transmission method.
2. The verification method for RTL test items of a RISC-V DSP chip according to claim 1, characterized in that: Select test items, test them based on the RTL test framework, and obtain test data, including: Obtain test input data, test criteria code or script input into the tested environment; Obtain independent configuration of test items, and generate test logic based on the independent configuration of test items; Based on the test logic, test input data, test criteria code or script in the tested environment are independently tested to obtain test data; The test data includes initialized RAM data, Flash data, ROM data, OTP data and timing-related external stimulus data.
3. The verification method of the RTL test items of the RISC-V DSP chip according to claim 2, characterized in that: Get the configuration information of the RTL test framework, verify the test data based on the configuration information, and obtain verification information, including: Get the configuration information of the RTL test framework, which includes the general configuration information of the framework and the independent configuration information of the test items; Verifying the test data in a first manner based on the general configuration information of the framework to generate first verification information; Performing a second mode verification on the test data based on the independent configuration information of the test item to generate second verification information; The first verification information and the second verification information are merged to obtain final verification information.
4. The verification method for RTL test items of a RISC-V DSP chip according to claim 3, characterized in that: Adjust the configuration information of the RTL test framework based on the correction information, including: Comparing the test deviation rate with a set test deviation rate threshold, wherein the set test deviation rate includes a first test deviation rate threshold and a second test deviation rate threshold, and the first test deviation rate threshold is less than the second test deviation rate threshold; If the test deviation rate is greater than a first test deviation rate threshold and less than a second test deviation rate threshold, generating first correction information; Adjusting the configuration information of the RTL test framework in a first manner based on the first correction information; If the test deviation rate is greater than or equal to a second test deviation rate threshold, generating second correction information; The configuration information of the RTL test framework is adjusted in a second manner based on the second correction information.
5. The verification method for RTL test items of a RISC-V DSP chip according to claim 4, characterized in that: Generate a test report from the test data in real time, and send the test report to the terminal according to the set transmission method, including: Match the corresponding test data based on the independent configuration of the test items; Generate a sub-report for the test data of different independently configured test items; Arrange all the sub-reports of test items into a complete test report; The memory usage of the test report is analyzed and stored in a storage area in the terminal that is larger than the memory usage based on the memory usage.
6. The verification method for RTL test items of a RISC-V DSP chip according to claim 1, characterized in that: Obtain the configuration information of the RTL test framework, verify the test data based on the configuration information, and obtain verification information, which also includes: Get the configuration information of the RTL test framework, which includes the general configuration information of the framework and the independent configuration information of the test items; Generate processing information of the test data based on the independent configuration information of the test item to obtain processing data; The verification interaction logic of the test framework is generated based on the common configuration information of the framework, and the processed data is interactively verified based on the verification interaction logic of the verification framework to generate verification information.
7. A verification system for RTL test items of a RISC-V DSP chip, characterized in that: The system includes: a memory and a processor, wherein the memory includes a program of a verification method for an RTL test item of a RISC-V DSP chip, and when the program of the verification method for an RTL test item of a RISC-V DSP chip is executed by the processor, the following steps are implemented: Select test items, test them based on the RTL test framework, and obtain test data; Obtain configuration information of the RTL test framework, verify the test data based on the configuration information, and obtain verification information; Compare the verification information with the set condition information to obtain the test deviation rate; Determining whether the test deviation rate is greater than or equal to a set test deviation rate threshold; If the value is greater than or equal to the set test deviation rate threshold, correction information is generated, and the configuration information of the RTL test framework is adjusted based on the correction information; If it is less than the set test deviation rate threshold, the test data will be used to generate a test report in real time, and the test report will be sent to the terminal according to the set transmission method.
8. The verification system for RTL test items of a RISC-V DSP chip according to claim 7, characterized in that: Select test items, test them based on the RTL test framework, and obtain test data, including: Obtain test input data, test criteria code or script input into the tested environment; Obtain independent configuration of test items, and generate test logic based on the independent configuration of test items; Based on the test logic, test input data, test criteria code or script in the tested environment are independently tested to obtain test data; The test data includes initialized RAM data, Flash data, ROM data, OTP data and timing-related external stimulus data.
9. The verification system for RTL test items of a RISC-V DSP chip according to claim 8, characterized in that: Get the configuration information of the RTL test framework, verify the test data based on the configuration information, and obtain verification information, including: Get the configuration information of the RTL test framework, which includes the general configuration information of the framework and the independent configuration information of the test items; Verifying the test data in a first manner based on the general configuration information of the framework to generate first verification information; Performing a second mode verification on the test data based on the independent configuration information of the test item to generate second verification information; The first verification information and the second verification information are merged to obtain final verification information.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a verification method program for the RTL test items of the RISC-V DSP chip. When the verification method program for the RTL test items of the RISC-V DSP chip is executed by the processor, the steps of the verification method for the RTL test items of the RISC-V DSP chip as described in any one of claims 1 to 6 are implemented.