Control methods, control devices, and computer program products for single-wire communication

Abstract

This application provides a control method, control device, and computer program product for single-wire communication, including: an initiation step, in which a first controller initiates communication; an output step, in which the first controller sequentially outputs a first voltage signal of a first set duration and a second voltage signal of a second set duration; a reading step, in which the first pin of the first controller is set as an input port and a timer is started, and the pin level of the first pin is read at fixed intervals until the timer reaches a third set duration; and a storage step, in which, if the pin levels read within the third set duration are the same, the current bit data is received, and the current bit data is stored sequentially in a communication data array, and the initiation step, output step, reading step, and storage step are repeated at least once until the communication data of the set length is read. This application solves the problem of wasted chip resources caused by the need for multiple line resources in communication chips when using multiple lines for communication in the prior art.

Description

Technical Field

[0001] This invention relates to the field of line communication technology, and more specifically, to a control method, control device, computer-readable storage medium, and computer program product for single-line communication. Background Technology

[0002] In the field of microcontrollers, standard serial communication protocols such as I2C and SPI are typically used for communication between two microcontrollers. However, due to various limitations, these two protocols have certain limitations in practical applications: First, I2C is a half-duplex communication protocol, transmitting data only on two lines: a data line (SDA) and a clock line (SCL). This half-duplex approach limits the data transmission speed and cannot meet the requirements of high-speed transmission. Furthermore, the complex timing of I2C requires strict timing control, placing high demands on the hardware resources of the microcontroller and making it difficult to implement. Second, while SPI is a full-duplex communication protocol with four lines (SCLK, MISO, MOSI, and SS), hardware resource limitations in practical applications mean that communication between multiple SPI devices can only be achieved by multiplexing the SPI interface across multiple devices or using a master-slave mode. This increases the complexity of hardware design and reduces communication flexibility. Currently, common communication methods on circuit boards include IIC, SPI, and UART. When multiple communication channels exist, the chip must have multiple communication resources, resulting in wasted development and selection time and increased procurement costs. Summary of the Invention

[0003] The main objective of this application is to provide a control method, control device, computer-readable storage medium, and computer program product for single-line communication, so as to at least solve the problem of wasted chip resources caused by the use of multiple lines for communication in the prior art, which requires multiple line resources for communication chips.

[0004] To achieve the above objectives, according to one aspect of this application, a control method for single-wire communication is provided, comprising: an initiation step, wherein a first controller initiates communication, the first controller including a first pin, the first pin being an I / O port; and an output step, wherein the first controller sequentially outputs a first voltage signal of a first set duration and a second voltage signal of a second set duration, such that a second controller triggers rising edge detection or falling edge detection, wherein the first voltage signal and the second voltage signal are opposite level signals, the rising edge detection is a low-level-to-high-level detection, and the falling edge detection is a high-level-to-low-level detection. The system communicates with the second controller. In the reading step, the first pin of the first controller is set as an input port and a timer is started. The pin level of the first pin is read at fixed intervals until the timer reaches a third set duration, which is a multiple of the fixed time. In the storage step, if the pin levels read within the third set duration are the same, the system receives the current bit data sent by the second controller and stores the current bit data sequentially into the communication data array. The system repeats the initiation step, the output step, the reading step, and the storage step at least once until the communication data of the set length is read.

[0005] Optionally, before the first controller initiates communication, the method further includes: initializing the first pin of the first controller as an output port and outputting the second voltage signal, and initializing the timer of the first controller.

[0006] Optionally, the first controller sequentially outputs a first voltage signal of a first set duration and a second voltage signal of a second set duration, including: the first controller outputs the first voltage signal, and at the same time, the first controller controls a timer to count to obtain a first timing duration; when the first timing duration reaches the first set duration, the timer of the first controller is initialized, the first controller adjusts the output to the second voltage signal, and at the same time, the first controller controls the timer to count until the second set duration is reached.

[0007] Optionally, the first controller sequentially outputs a first voltage signal of a first set duration and a second voltage signal of a second set duration, so that the second controller triggers rising edge detection or falling edge detection, including: triggering the second controller to perform rising edge detection when the first voltage signal is low and the second voltage signal is high, wherein the low level is 0 and the high level is 1; and triggering the second controller to perform falling edge detection when the first voltage signal is high and the second voltage signal is low.

[0008] Optionally, the first pin of the first controller and the second pin of the second controller are connected via a single-line communication connection, with a first resistor connected between the single lines. A second resistor is connected between the third pin of the second controller and the target-side line of the single line. The target-side line is the line between the second pin and the first resistor. The second controller includes a second pin and a third pin, where the second pin is an I / O port and the third pin is an external interrupt port. Receiving current bit data sent by the second controller includes: initializing the second pin and the third pin; determining whether the third pin of the second controller identifies a rising edge or a falling edge of a target node, where the target node is the connection node between the second resistor and the target-side line; and, if the third pin identifies the rising edge or the falling edge, switching the second pin of the second controller to an output port so that the first controller receives the current bit data sent by the output port.

[0009] Optionally, before determining whether the third pin of the second controller has identified a rising edge or a falling edge, the method includes: determining a target duration condition, wherein the target duration condition is a duration condition in which the target duration is less than the sum of the second set duration and the third set duration, and the target duration is the time interval from when the third pin identifies the rising edge or the falling edge to when the second pin outputs the current bit data.

[0010] Optionally, the second controller includes a second pin and a third pin, the second pin being an I / O port and the third pin being an external input port, receiving current bit data sent by the second controller. The controller further includes: initializing the second pin and the third pin; determining whether the third pin of the second controller recognizes a level change in the target node; and, if the level change is a transition from low to high or from high to low, switching the second pin of the second controller to an output port so that the first controller receives current bit data sent by the output port.

[0011] According to another aspect of this application, a control device for single-wire communication is provided. The device includes: an initiating unit for executing an initiation step, wherein a first controller initiates communication, the first controller including a first pin, the first pin being an I / O port; and an output unit for executing an output step, wherein the first controller sequentially outputs a first voltage signal of a first set duration and a second voltage signal of a second set duration, such that a second controller triggers rising edge detection or falling edge detection. The first voltage signal and the second voltage signal are opposite level signals, the rising edge detection is a low-to-high level detection, and the falling edge detection is a high-to-low level detection. The first controller and the... The second controller is connected for communication; a reading unit is used to perform a reading step, which adjusts the first pin of the first controller to an input port and starts timing, reads the pin level of the first pin at fixed intervals until the timing duration reaches a third set duration, the third set duration being a multiple of the fixed duration; a storage unit is used to perform a storage step, which, if the pin levels read within the third set duration are the same, receives the current bit data sent by the second controller, stores the current bit data in sequence into the communication data array, and repeats the initiation step, the output step, the reading step, and the storage step at least once until the communication data of the set length is read.

[0012] According to another aspect of this application, a computer-readable storage medium is provided, the computer-readable storage medium including a stored program, wherein, when the program is executed, it controls the device on which the computer-readable storage medium is located to perform any of the methods described.

[0013] According to another aspect of this application, a computer program product is provided, including computer instructions that, when executed by a processor, implement any of the methods described.

[0014] Applying the technical solution of this application, in the control method for single-wire communication, firstly, in the initiation step, a first controller initiates communication. The first controller includes a first pin, which is an I / O port. Then, in the output step, the first controller sequentially outputs a first voltage signal of a first set duration and a second voltage signal of a second set duration, so that the second controller triggers rising edge detection or falling edge detection. The first voltage signal and the second voltage signal are opposite level signals. The rising edge detection is a low-level to high-level detection, and the falling edge detection is a high-level to low-level detection. The first controller and the second controller... The communication connection is established; then, in the reading step, the first pin of the first controller is set as an input port and a timer is started. The pin level of the first pin is read at fixed intervals until the timer reaches a third set duration, which is a multiple of the fixed time. Finally, in the storage step, if the pin levels read within the third set duration are the same, the current bit data sent by the second controller is received, and the current bit data is stored sequentially in the communication data array. The initiation step, the output step, the reading step, and the storage step are repeated at least once until the communication data of the set length is read. To achieve communication on a single line, this application sets up two controller MCUs (i.e., the first controller and the second controller mentioned above) on that line. Communication is initiated by the first controller. The first pin of the first controller first outputs a first voltage signal for a first set time, and then outputs a second voltage signal for a second set time. The main purpose of this is to provide an interrupt to the second controller. Therefore, the duration of the first and second set times only needs to meet the interrupt detection of the second controller. After the second set time, the first pin of the first controller becomes an input port. A timer generates a time T1. If the same level is detected multiple times consecutively, it is considered that the correct bit data has been read, and the current bit data is stored in the communication data array. The above steps are repeated until the data reading is completed. Through the above steps, single-line communication is achieved, thereby reducing chip resource waste. This application solves the problem of chip resource waste caused by the use of multiple lines for communication in the prior art, which requires multiple line resources for the communication chip. Attached Figure Description

[0015] Figure 1 A hardware structure block diagram of a mobile terminal for performing a control method for single-wire communication according to an embodiment of this application is shown.

[0016] Figure 2 A flowchart illustrating a control method for single-wire communication according to an embodiment of this application is shown.

[0017] Figure 3 A circuit diagram of a single-wire communication according to an embodiment of this application is shown;

[0018] Figure 4 A schematic diagram of a single-wire communication protocol according to an embodiment of this application is shown;

[0019] Figure 5 A schematic diagram of the communication flow of a first controller according to an embodiment of this application is shown;

[0020] Figure 6 A schematic diagram of the communication flow of a second controller according to an embodiment of this application is shown;

[0021] Figure 7 A structural block diagram of a single-wire communication control device provided according to an embodiment of this application is shown.

[0022] The above figures include the following reference numerals:

[0023] 102. Processor; 104. Memory; 106. Transmission device; 108. Input / output device. Detailed Implementation

[0024] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0025] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0027] As described in the background section, the communication methods commonly used on circuit boards in the present technology are IIC, SPI, UART, etc. When there is multiple communication, the chip is required to have multiple communication resources, which wastes development and selection time and increases procurement costs. In order to solve the problem of chip resource waste caused by the use of multiple lines for communication in the present technology, the embodiments of this application provide a control method, control device, computer-readable storage medium and computer program product for single-line communication.

[0028] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0029] The methods and embodiments provided in this application can be executed on a mobile terminal, computer terminal, or similar computing device. Taking running on a mobile terminal as an example, Figure 1 This is a hardware structure block diagram of a mobile terminal implementing a control method for single-line communication according to an embodiment of the present invention. Figure 1 As shown, a mobile terminal may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. The mobile terminal may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the mobile terminal described above. For example, the mobile terminal may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0030] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the single-wire communication control method in this embodiment of the invention. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thereby implementing the above-described method. The memory 104 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to the mobile terminal via a network. Examples of the aforementioned networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof. The transmission device 106 is used to receive or send data via a network. Specific examples of the aforementioned networks may include wireless networks provided by the mobile terminal's communication provider. In one example, the transmission device 106 includes a network interface controller (NIC), which can be connected to other network devices via a base station to communicate with the Internet. In one example, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0031] This embodiment provides a control method for single-line communication that runs on a mobile terminal, computer terminal, or similar computing device. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Also, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0032] Figure 2 This is a flowchart illustrating a single-line communication control method according to an embodiment of this application. Figure 2 As shown, the method includes the following steps:

[0033] Step S201, Initiation step, the first controller initiates communication, the first controller includes a first pin, the first pin is an I / O port.

[0034] Specifically, Figure 3 To illustrate a circuit diagram provided in an embodiment of this application, a single line includes a first controller ( Figure 3 MCU1) and the second controller ( Figure 3In the MCU2), the first pin of the first controller MCU1 is represented by P3. The first controller and the second controller are located at the two ends of the single line, respectively. Single-line communication is performed through the first controller and the second controller. The communication is initiated by MCU1 and a fixed time is set, such as reading a packet of data at 500ms interval. Assuming that there are 40 bits in a packet of data, the time to read 40 bits of data is less than the interval of 500ms.

[0035] Step S202, output step, the first controller sequentially outputs a first voltage signal of a first set duration and a second voltage signal of a second set duration, so that the second controller triggers rising edge detection or falling edge detection. The first voltage signal and the second voltage signal are opposite level signals. The rising edge detection is a low-level to high-level detection, and the falling edge detection is a high-level to low-level detection. The first controller and the second controller are communicatively connected.

[0036] Specifically, the P3 port of the first controller MCU1 first outputs 0 for the TL time (first set duration), and then outputs 1 for the TH time (second set duration). The main purpose of this is to provide MCU2 with a rising edge, so the durations of TL and TH only need to meet the rising edge detection requirements of MCU2; there is no strict duration requirement. Alternatively, the P3 port of the first controller MCU1 first outputs 1 for the TL time (first set duration), and then outputs 0 for the TH time (second set duration). The main purpose of this is to provide MCU2 with a falling edge; similarly, the durations of TL and TH only need to meet the falling edge detection requirements of MCU2. Figure 4 As shown in the protocol diagram, solid lines represent the output of 0 or 1 from pin P3 of the first controller MCU1, TL represents the duration of outputting 0, and TH represents the duration of outputting 1. Dashed lines represent the P3 port of the MCU as an input port, and TZ represents the duration of the input port setting. Tbit represents the duration of data output from the P2 port (second pin) of the second controller MCU2.

[0037] Step S203, reading step, adjust the first pin of the first controller to the input port and start timing, read the pin level of the first pin at fixed time until the timing duration reaches the third set duration, the third set duration is a multiple of the fixed time.

[0038] Specifically, after the TH time (the second set duration mentioned above), the P3 port of the first controller MCU1 is converted into an input port, and a time T1 time (i.e., the fixed time mentioned above) is generated through a timer. The pin level of the first pin is read according to the fixed time within the third set duration.

[0039] Step S204, storage step: if the pin voltages read within the third set time period are the same, receive the current bit data sent by the second controller, store the current bit data in sequence into the communication data array, and repeat the above initiation step, the above output step, the above reading step and the above storage step at least once until the communication data reading of the set length is completed.

[0040] Specifically, detecting the same level 3 or 5 times consecutively indicates that the correct bit data has been read, and the read bit data is then stored in the array. Therefore, the TZ time (i.e., the third set duration mentioned above) must be greater than 3*T1 or 5*T1, and 7*T1 is recommended to ensure that the data can be read completely 3 or 5 times. Repeat the above initiation step, output step, reading step, and storage step 39 times (because it was previously assumed that a data packet is 40 bits, the specific number of times is determined according to the number of bits in each data packet) to complete the transmission and reading of 40 bits of data. The correctness and integrity of the data can be guaranteed by the second controller MCU2 sending out the 40 data in sequence.

[0041] In this embodiment, firstly, in the initiation step, the first controller initiates communication. The first controller includes a first pin, which is an I / O port. Then, in the output step, the first controller sequentially outputs a first voltage signal of a first set duration and a second voltage signal of a second set duration, so that the second controller triggers rising edge detection or falling edge detection. The first voltage signal and the second voltage signal are opposite level signals. The rising edge detection is a low-level to high-level detection, and the falling edge detection is a high-level to low-level detection. The first controller and the second controller are communicatively connected. Afterwards... The reading step involves adjusting the first pin of the first controller to an input port and starting a timer. The pin level of the first pin is read at fixed intervals until the timer reaches a third set duration, which is a multiple of the fixed time. Finally, the storage step involves receiving the current bit data sent by the second controller if the pin levels read within the third set duration are the same, and storing the current bit data in sequence into the communication data array. The initiation step, the output step, the reading step, and the storage step are repeated at least once until the communication data of the set length is read. To achieve communication on a single line, this application sets up two controller MCUs (i.e., the first controller and the second controller mentioned above) on that line. Communication is initiated by the first controller. The first pin of the first controller first outputs a first voltage signal for a first set time, and then outputs a second voltage signal for a second set time. The main purpose of this is to provide an interrupt to the second controller. Therefore, the duration of the first and second set times only needs to meet the interrupt detection of the second controller. After the second set time, the first pin of the first controller becomes an input port. A timer generates a time T1. If the same level is detected multiple times consecutively, it is considered that the correct bit data has been read, and the current bit data is stored in the communication data array. The above steps are repeated until the data reading is completed. Through the above steps, single-line communication is achieved, thereby reducing chip resource waste. This application solves the problem of chip resource waste caused by the use of multiple lines for communication in the prior art, which requires multiple line resources for the communication chip.

[0042] To enable those skilled in the art to better understand the technical solution of this application, the implementation process of the single-line communication control method of this application will be described in detail below with reference to specific embodiments.

[0043] To establish a stable communication environment and improve the reliability of data reading, in an optional implementation, before step S201 above, the method further includes:

[0044] Step S301: Initialize the first pin of the first controller as an output port and output the second voltage signal, and initialize the timer of the first controller.

[0045] In the above embodiments, such as Figure 5 As shown, the first pin of the first controller MCU1 is initialized. P3 is the output port, and it can output either 0 or 1. This invention uses output 1 as an example for explanation. The timer of MCU1 is initialized, and the timing of time T is set (the first, second, and third set durations in this invention are all timed in T as the smallest unit). In the configuration code of the first controller MCU1, the P3 pin is set to output mode. This usually involves writing to the port configuration register of the MCU to ensure that the bit related to the P3 pin in the register is set to the output state. A suitable second voltage signal is selected and implemented by outputting a high level (1) or a low level (0) to the P3 pin, ensuring that the P3 pin is in the correct state before communication begins so that the level can be switched accurately in subsequent steps. A timer is configured to interrupt periodically, with the interrupt interval set to T1 time (e.g., 200 microseconds). Once the above initialization is completed, the second controller is ready to send data, and the first controller enters the receiving mode. Through initialization, the system can establish a stable communication environment, ensuring the accurate transmission and reception of subsequent data. It also provides the necessary hardware preparation for communication timing control, thereby improving communication efficiency and data transmission reliability.

[0046] To ensure that the second controller successfully completes the interrupt detection, in one optional implementation, step S202 includes:

[0047] In step S2021, the first controller outputs the first voltage signal, and at the same time, the first controller controls the timer to keep time and obtain the first timing duration;

[0048] Step S2022: When the first timing duration reaches the first set duration, the timer of the first controller is initialized, the first controller adjusts the output to the second voltage signal, and the first controller controls the timer to keep timing until the second set duration is reached.

[0049] In the above embodiments, such as Figure 5As shown, taking the first voltage signal as 0 and the second voltage signal as 1 as an example, MCU1's P3 pin outputs 0; a timer is used to perform a first set time for a long duration; it is checked whether the first set duration has been reached. If it has, MCU1's P3 pin outputs 1; otherwise, the timing continues. A timer is used to perform a second set time for a long duration; it is checked whether the second set duration has been reached. If it has been reached, MCU1's P3 pin becomes an input port; otherwise, the timing continues. MCU1's P3 port first outputs 0 for the TL time and then outputs 1 for the TH time. The main purpose of this is to provide MCU2 with a rising edge. Therefore, the durations of TL and TH only need to meet the rising edge detection requirements of MCU2; there is no strict duration requirement.

[0050] To ensure that the transmitted data bits can be correctly identified by the receiving end, in an optional implementation, step S202 includes:

[0051] Step S2023: When the first voltage signal is low and the second voltage signal is high, the second controller is triggered to perform the rising edge detection, where the low level is 0 and the high level is 1.

[0052] Step S2024: When the first voltage signal is at the high level and the second voltage signal is at the low level, the second controller is triggered to perform the falling edge detection.

[0053] In the above embodiment, the interrupt on the third pin P1 of the second controller can be set to be triggered by a falling edge. Therefore, the first pin P3 of the first controller needs to be changed to output 1 first and then 0. By quickly switching the level of the P3 pin of MCU1 in single-wire communication, the external interrupt of the P1 pin of MCU2 can be triggered, thereby starting the interrupt service routine. A transition from 1 to 0 and then back to 1 on the P3 pin can be recognized as a rising edge by the P1 pin of MCU2, triggering an interrupt; a transition from 1 to 0 and then back to 1 on the P3 pin can be recognized as a falling edge, also triggering an interrupt. By controlling the rising and falling edges of the control signals, it is ensured that the transmission of data bits can be correctly recognized by the receiving end. A rising edge is usually used to indicate the start of a data bit, while a falling edge may be used to indicate the end of a data bit or the start of the next data bit, depending on the specific communication protocol. By utilizing the interrupt mechanism, real-time signal detection and response can be achieved, thereby improving communication efficiency. When a signal changes, MCU2 can immediately enter interrupt handling without polling the signal status in the main program. This reduces communication latency and improves data transmission rate.

[0054] It should be noted that, as Figure 3 As shown, the interruption is to determine Figure 3Point A in the code will trigger an interrupt only if a rising edge occurs. The rising edge of point A is determined by the output level change of MCU1's P3 port, so this ensures that point A can accurately detect the rising edge. The concern is whether an abnormal rising edge will occur at point A when P3 is an input port. When P3 is an input port, the level of point A is determined by the output level of MCU2's P2 port. P2 outputs a stable level at this time, so we only need to consider whether the level change at the moment P3 switches from output to input will produce an abnormal rising edge. If P2 outputs 1, when P3 switches from output to input, the level of point A changes from 1 to 1 without a rising edge; if P2 outputs 0, when P3 switches from output to input, the level of point A changes from 1 to 0 without a rising edge. From the above analysis, it can be seen that the program processing will not cause the interrupt to be triggered incorrectly.

[0055] To improve data transmission efficiency, in one optional implementation, step S204 includes:

[0056] Step S2041: Initialize the second pin and the third pin.

[0057] Step S2042: Determine whether the third pin of the second controller has identified the rising edge or falling edge of the target node. The target node is the connection node between the second resistor and the target side line.

[0058] Step S2043: When the third pin detects the rising edge or the falling edge, the second pin of the second controller is switched to an output port so that the first controller can receive the current bit data sent by the output port.

[0059] In the above embodiments, such as Figure 3 As shown, the first pin P3 of the first controller MCU1 and the second pin P2 of the second controller MCU2 are connected via a single-line communication connection. A first resistor R1 is connected between the single line and the third pin P1 of the second controller MCU2 is connected to the target side line of the single line via a second resistor R2. The target side line is the line between the second pin and the first resistor. The second controller includes the second pin P2 and the third pin P1. Figure 6 As shown, initialize the pins of MCU2. P1 is the interrupt port, detecting rising edges (0→1). P2 is not critical; it can be either an input or output port. Figure 5Taking the input port as an example. It checks if the P1 pin of MCU2 has detected a rising edge (0→1). If so, the second pin (P2) of the second controller MCU2 is switched to an output port; otherwise, the check continues. The current bit data is output through the second pin (P2) of MCU2, enabling the first controller to receive the current bit data sent from the output port. Real-time detection of signal changes is achieved through an external interrupt mechanism. When a level change at point A (the target node) is detected by the P1 pin, the interrupt service routine is immediately entered to determine if it is a valid data bit start signal. This improves the real-time performance and efficiency of communication, enabling rapid response to signal changes and avoiding data bit loss. Once a valid signal change is detected, the P2 pin of MCU2 is set to output mode and outputs the corresponding level according to the current bit data state. This allows MCU1 to receive data from MCU2 and complete the data bit transmission process. By precisely controlling signal changes and utilizing external interrupts for rapid response, data transmission efficiency is improved, maintaining stable communication performance even under high network load.

[0060] It should also be noted that the T-bit duration of the data output by MCU2 includes the TL and TH times of MCU1. Therefore, it is required that regardless of whether the P2 port of MCU2 outputs 0 or 1, it should not affect the influence of the output 0 or 1 of MCU1 on the level at point A. For example, if R1 = 10K and R2 = 1K are selected, this invention uses the MCU's low-level identification range of 0 to Vcc*0.2 and high-level identification range of Vcc*0.8 to Vcc. As shown in Table 1, the usage requirements are met regardless of the Vcc (Volt Current Condenser, supply voltage) level.

[0061] Table 1

[0062]

[0063]

[0064] To ensure the accuracy of the data read by the first controller, in an optional implementation, before step S2042 above, the method further includes:

[0065] Step S401: Determine the target duration condition. The target duration condition is a duration condition where the target duration is less than the sum of the second set duration and the third set duration. The target duration is the time interval from when the third pin identifies the rising edge or the falling edge to when the second pin outputs the current bit data.

[0066] In the above embodiments, such as Figure 3As shown, the P1 port of the second controller MCU2 is an external interrupt port. Upon detecting a rising edge, it enters an interrupt, and then the P2 port outputs the current bit's data (0 or 1). The time from P1 detecting the interrupt to P2 outputting data depends on the MCU2's program processing and clock frequency. The processing of the P2 output is placed within the interrupt handler in the program, allowing the entire process to be completed within the microsecond (µs) level. It is important to note that the time t from MCU1's P1 pin recognizing the rising edge to the P2 output level (i.e., the target duration) must satisfy the condition that the target duration t < the second set duration + the third set duration. This ensures that P3 does not read the level while P2 is still outputting the previous bit value or in an input state, leading to data errors.

[0067] To conserve I / O port resources of the second controller MCU2, in an optional implementation, step S204 includes:

[0068] Step S2044: Initialize the second pin and the third pin mentioned above;

[0069] Step S2045: Determine whether the third pin of the second controller has detected the level change of the target node;

[0070] Step S2046: When the level change is from low to high or from high to low, the second pin of the second controller is switched to an output port so that the first controller receives the current bit data sent by the output port.

[0071] In the above embodiment, the second controller includes a first pin P2 and a second pin P1. The first pin P1 is an I / O port. The second pin P1 does not need to be an interrupt I / O port. The level change can be identified by reading the level through the input port. Then, the second pin P2 port is processed. At this time, the second controller MCU2 uses an external input port instead of the rising edge to identify the external level change, which is more friendly to the I / O port resources of the second controller MCU2. Because the external interrupt port of the MCU is limited, but an additional timer is still needed to generate time to read the external level. In order to ensure the stability of the level reading, there needs to be filtering processing of reading the same level n times in a row. The time t will be relatively long (the target duration t in step S401 is < the second set duration + the third set duration t).

[0072] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0073] This application also provides a control device for single-line communication. It should be noted that the control device for single-line communication in this application can be used to execute the control method for single-line communication provided in this application. This device is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0074] The control device for single-line communication provided in the embodiments of this application will be described below.

[0075] Figure 7 This is a structural block diagram of a single-wire communication control device according to an embodiment of this application. Figure 7 As shown, the device includes:

[0076] Initiating unit 10 is used to execute the initiation step, wherein the first controller initiates communication, and the first controller includes a first pin, which is an I / O port.

[0077] Specifically, Figure 3 To illustrate a circuit diagram provided in an embodiment of this application, a single line includes a first controller ( Figure 3 MCU1) and the second controller ( Figure 3 In the MCU2), the first pin of the first controller MCU1 is represented by P3. The first controller and the second controller are located at the two ends of the single line, respectively. Single-line communication is performed through the first controller and the second controller. The communication is initiated by MCU1 and a fixed time is set, such as reading a packet of data at 500ms interval. Assuming that there are 40 bits in a packet of data, the time to read 40 bits of data is less than the interval of 500ms.

[0078] The output unit 20 is used to perform the output step. The first controller sequentially outputs a first voltage signal of a first set duration and a second voltage signal of a second set duration, so that the second controller triggers rising edge detection or falling edge detection. The first voltage signal and the second voltage signal are opposite level signals. The rising edge detection is a low-level to high-level detection, and the falling edge detection is a high-level to low-level detection. The first controller and the second controller are communicatively connected.

[0079] Specifically, the P3 port of the first controller MCU1 first outputs 0 for the TL time (first set duration), and then outputs 1 for the TH time (second set duration). The main purpose of this is to provide MCU2 with a rising edge, so the durations of TL and TH only need to meet the rising edge detection requirements of MCU2; there is no strict duration requirement. Alternatively, the P3 port of the first controller MCU1 first outputs 1 for the TL time (first set duration), and then outputs 0 for the TH time (second set duration). The main purpose of this is to provide MCU2 with a falling edge; similarly, the durations of TL and TH only need to meet the falling edge detection requirements of MCU2. Figure 4 As shown in the protocol diagram, solid lines represent the output of 0 or 1 from pin P3 of the first controller MCU1, TL represents the duration of outputting 0, and TH represents the duration of outputting 1. Dashed lines represent the P3 port of the MCU as an input port, and TZ represents the duration of the input port setting. Tbit represents the duration of data output from the P2 port (second pin) of the second controller MCU2.

[0080] The reading unit 30 is used to perform the reading step, adjust the first pin of the first controller to the input port and start timing, and read the pin level of the first pin at fixed intervals until the timing duration reaches a third set duration, wherein the third set duration is a multiple of the fixed duration.

[0081] Specifically, after the TH time (the second set duration mentioned above), the P3 port of the first controller MCU1 is converted into an input port, and a time T1 time (i.e., the fixed time mentioned above) is generated through a timer. The pin level of the first pin is read according to the fixed time within the third set duration.

[0082] Storage unit 40 is used to perform the storage step. If the pin voltages read within the third set time period are the same, it receives the current bit data sent by the second controller, stores the current bit data in sequence into the communication data array, and repeats the initiation step, the output step, the reading step and the storage step at least once until the communication data reading of the set length is completed.

[0083] Specifically, detecting the same level 3 or 5 times consecutively indicates that the correct bit data has been read, and the read bit data is then stored in the array. Therefore, the TZ time (i.e., the third set duration mentioned above) must be greater than 3*T1 or 5*T1, and 7*T1 is recommended to ensure that the data can be read completely 3 or 5 times. Repeat the above initiation step, output step, reading step, and storage step 39 times (because it was previously assumed that a data packet is 40 bits, the specific number of times is determined according to the number of bits in each data packet) to complete the transmission and reading of 40 bits of data. The correctness and integrity of the data can be guaranteed by the second controller MCU2 sending out the 40 data in sequence.

[0084] In this embodiment, the initiating unit is used to execute the initiation step, in which the first controller initiates communication. The first controller includes a first pin, which is an I / O port. The output unit is used to execute the output step, in which the first controller sequentially outputs a first voltage signal of a first set duration and a second voltage signal of a second set duration, so that the second controller triggers rising edge detection or falling edge detection. The first voltage signal and the second voltage signal are opposite level signals. The rising edge detection is a low-level to high-level detection, and the falling edge detection is a high-level to low-level detection. The first controller and the second controller are communicatively connected. The unit is used to perform the reading step, adjust the first pin of the first controller to the input port and start timing, read the pin level of the first pin at fixed intervals until the timing duration reaches a third set duration, the third set duration being a multiple of the fixed time; the storage unit is used to perform the storage step, if the pin levels read within the third set duration are the same, receive the current bit data sent by the second controller, store the current bit data in sequence into the communication data array, and repeat the initiation step, the output step, the reading step and the storage step at least once until the communication data reading of the set length is completed. This application aims to achieve communication over a single line by setting up two controller MCUs (i.e., the first controller and the second controller mentioned above). Communication is initiated by the first controller. The first pin of the first controller first outputs a first voltage signal for a first set time, and then outputs a second voltage signal for a second set time. The main purpose of this is to provide an interrupt to the second controller. Therefore, the duration of the first and second set times only needs to meet the interrupt detection of the second controller. After the second set time, the first pin of the first controller becomes an input port. A timer generates a time T1. If the same level is detected multiple times consecutively, it is considered that the correct bit data has been read, and the current bit data is stored in the communication data array. The above steps are repeated until the data reading and transmission are completed. Through the above steps, single-line communication is achieved, thereby reducing chip resource waste. This application solves the problem of chip resource waste caused by the use of multiple lines for communication in the prior art, which requires multiple line resources for the communication chip.

[0085] To establish a stable communication environment and improve the reliability of data reading, in one optional embodiment, the device further includes:

[0086] An initialization unit is used to initialize the first pin of the first controller as an output port and output the second voltage signal before the first controller initiates communication, and to initialize the timer of the first controller.

[0087] In the above embodiments, such as Figure 5As shown, the first pin of the first controller MCU1 is initialized. P3 is the output port, and it can output either 0 or 1. This invention uses output 1 as an example for explanation. The timer of MCU1 is initialized, and the timing of time T is set (the first, second, and third set durations in this invention are all timed in T as the smallest unit). In the configuration code of the first controller MCU1, the P3 pin is set to output mode. This usually involves writing to the port configuration register of the MCU to ensure that the bit related to the P3 pin in the register is set to the output state. A suitable second voltage signal is selected and implemented by outputting a high level (1) or a low level (0) to the P3 pin, ensuring that the P3 pin is in the correct state before communication begins so that the level can be switched accurately in subsequent steps. A timer is configured to interrupt periodically, with the interrupt interval set to T1 time (e.g., 200 microseconds). Once the above initialization is completed, the second controller is ready to send data, and the first controller enters the receiving mode. Through initialization, the system can establish a stable communication environment, ensuring the accurate transmission and reception of subsequent data. It also provides the necessary hardware preparation for communication timing control, thereby improving communication efficiency and data transmission reliability.

[0088] To ensure the second controller successfully completes the interrupt detection, in one optional implementation, the above-mentioned step output unit includes:

[0089] The first output module is used for the first controller to output the first voltage signal, and at the same time, the first controller controls the timer to perform timing to obtain the first timing duration.

[0090] The second output module is used to initialize the timer of the first controller when the first timing duration reaches the first set duration. The first controller adjusts the output to the second voltage signal and controls the timer to keep timing until the second set duration is reached.

[0091] In the above embodiments, such as Figure 5 As shown, taking the first voltage signal as 0 and the second voltage signal as 1 as an example, MCU1's P3 pin outputs 0; a timer is used to perform a first set time for a long duration; it is checked whether the first set duration has been reached. If it has, MCU1's P3 pin outputs 1; otherwise, the timing continues. A timer is used to perform a second set time for a long duration; it is checked whether the second set duration has been reached. If it has been reached, MCU1's P3 pin becomes an input port; otherwise, the timing continues. MCU1's P3 port first outputs 0 for the TL time and then outputs 1 for the TH time. The main purpose of this is to provide MCU2 with a rising edge. Therefore, the durations of TL and TH only need to meet the rising edge detection requirements of MCU2; there is no strict duration requirement.

[0092] To ensure that the transmitted data bits can be correctly identified by the receiving end, in one optional embodiment, the output unit further includes:

[0093] The first trigger module is used to trigger the second controller to perform the rising edge detection when the first voltage signal is low and the second voltage signal is high, wherein the low level is 0 and the high level is 1.

[0094] The second trigger module is used to trigger the second controller to perform the falling edge detection when the first voltage signal is at the high level and the second voltage signal is at the low level.

[0095] In the above embodiment, the interrupt on the third pin P1 of the second controller can be set to be triggered by a falling edge. Therefore, the first pin P3 of the first controller needs to be changed to output 1 first and then 0. By quickly switching the level of the P3 pin of MCU1 in single-wire communication, the external interrupt of the P1 pin of MCU2 can be triggered, thereby starting the interrupt service routine. A transition from 1 to 0 and then back to 1 on the P3 pin can be recognized as a rising edge by the P1 pin of MCU2, triggering an interrupt; a transition from 1 to 0 and then back to 1 on the P3 pin can be recognized as a falling edge, also triggering an interrupt. By controlling the rising and falling edges of the control signals, it is ensured that the transmission of data bits can be correctly recognized by the receiving end. A rising edge is usually used to indicate the start of a data bit, while a falling edge may be used to indicate the end of a data bit or the start of the next data bit, depending on the specific communication protocol. By utilizing the interrupt mechanism, real-time signal detection and response can be achieved, thereby improving communication efficiency. When a signal changes, MCU2 can immediately enter interrupt handling without polling the signal status in the main program. This reduces communication latency and improves data transmission rate.

[0096] It should be noted that, as Figure 3 As shown, the interruption is to determine Figure 3 Point A in the code will trigger an interrupt only if a rising edge occurs. The rising edge of point A is determined by the output level change of MCU1's P3 port, so this ensures that point A can accurately detect the rising edge. The concern is whether an abnormal rising edge will occur at point A when P3 is an input port. When P3 is an input port, the level of point A is determined by the output level of MCU2's P2 port. P2 outputs a stable level at this time, so we only need to consider whether the level change at the moment P3 switches from output to input will produce an abnormal rising edge. If P2 outputs 1, when P3 switches from output to input, the level of point A changes from 1 to 1 without a rising edge; if P2 outputs 0, when P3 switches from output to input, the level of point A changes from 1 to 0 without a rising edge. From the above analysis, it can be seen that the program processing will not cause the interrupt to be triggered incorrectly.

[0097] To improve data transmission efficiency, in one optional embodiment, the storage unit includes:

[0098] The first initialization module is used to initialize the second pin and the third pin mentioned above.

[0099] The first judgment module is used to determine whether the third pin of the second controller has identified the rising edge or falling edge of the target node, wherein the target node is the connection node between the second resistor and the target side line.

[0100] The first switching module is used to switch the second pin of the second controller to an output port when the third pin detects the rising edge or the falling edge, so that the first controller can receive the current bit data sent by the output port.

[0101] In the above embodiments, such as Figure 3 As shown, the first pin P3 of the first controller MCU1 and the second pin P2 of the second controller MCU2 are connected via a single-line communication connection. A first resistor R1 is connected between the single line and the third pin P1 of the second controller MCU2 is connected to the target side line of the single line via a second resistor R2. The target side line is the line between the second pin and the first resistor. The second controller includes the second pin P2 and the third pin P1. Figure 6 As shown, initialize the pins of MCU2. P1 is the interrupt port, detecting rising edges (0→1). P2 is not critical; it can be either an input or output port. Figure 5 Taking the input port as an example. It checks if the P1 pin of MCU2 has detected a rising edge (0→1). If so, the second pin (P2) of the second controller MCU2 is switched to an output port; otherwise, the check continues. The current bit data is output through the second pin (P2) of MCU2, enabling the first controller to receive the current bit data sent from the output port. Real-time detection of signal changes is achieved through an external interrupt mechanism. When a level change at point A (the target node) is detected by the P1 pin, the interrupt service routine is immediately entered to determine if it is a valid data bit start signal. This improves the real-time performance and efficiency of communication, enabling rapid response to signal changes and avoiding data bit loss. Once a valid signal change is detected, the P2 pin of MCU2 is set to output mode and outputs the corresponding level according to the current bit data state. This allows MCU1 to receive data from MCU2 and complete the data bit transmission process. By precisely controlling signal changes and utilizing external interrupts for rapid response, data transmission efficiency is improved, maintaining stable communication performance even under high network load.

[0102] It should also be noted that the T-bit duration of the data output by MCU2 includes the TL and TH times of MCU1. Therefore, it is required that regardless of whether the P2 port of MCU2 outputs 0 or 1, it should not affect the influence of the output 0 or 1 of MCU1 on the level at point A. For example, if R1 = 10K and R2 = 1K are selected, this invention uses the MCU's low-level identification range of 0 to Vcc*0.2 and high-level identification range of Vcc*0.8 to Vcc. As shown in Table 1, the usage requirements are met regardless of the Vcc (Volt Current Condenser, supply voltage) level.

[0103] Table 1

[0104]

[0105]

[0106] To ensure the accuracy of data read by the first controller, in one optional embodiment, the device further includes:

[0107] The determining unit is used to determine a target duration condition before determining whether the third pin of the second controller has identified a rising edge or a falling edge. The target duration condition is a duration condition in which the target duration is less than the sum of the second set duration and the third set duration. The target duration is the time interval from when the third pin identifies the rising edge or the falling edge to when the second pin outputs the current bit data.

[0108] In the above embodiments, such as Figure 3 As shown, the P1 port of the second controller MCU2 is an external interrupt port. Upon detecting a rising edge, it enters an interrupt, and then the P2 port outputs the current bit's data (0 or 1). The time from P1 detecting the interrupt to P2 outputting data depends on the MCU2's program processing and clock frequency. The processing of the P2 output is placed within the interrupt handler in the program, allowing the entire process to be completed within the microsecond (µs) level. It is important to note that the time t from MCU1's P1 pin recognizing the rising edge to the P2 output level (i.e., the target duration) must satisfy the condition that the target duration t < the second set duration + the third set duration. This ensures that P3 does not read the level while P2 is still outputting the previous bit value or in an input state, leading to data errors.

[0109] To conserve I / O port resources of the second controller MCU2, in one optional embodiment, the aforementioned storage unit includes:

[0110] The second initialization module is used to initialize the second pin and the third pin mentioned above.

[0111] The second judgment module is used to determine whether the third pin of the second controller has detected the level change of the target node.

[0112] The second switching module is used to switch the second pin of the second controller to an output port when the level change is from low to high or from high to low, so that the first controller can receive the current bit data sent by the output port.

[0113] In the above embodiment, the second controller includes a first pin P2 and a second pin P1. The first pin P1 is an I / O port. The second pin P1 does not need to be an interrupt I / O port. The level change can be identified by reading the level through the input port. Then, the second pin P2 port is processed. At this time, the second controller MCU2 uses an external input port instead of the rising edge to identify the external level change. This is more friendly to the I / O port resources of the second controller MCU2 because the external interrupt port of the MCU is limited. However, an additional timer is still needed to generate time to read the external level. In order to ensure the stability of the level reading, filtering processing is required for reading the same level n times in a row. The time t will be relatively long.

[0114] The aforementioned single-wire communication control device includes a processor and a memory. The initiating unit, output unit, and reading unit are all stored as program units in the memory, and the processor executes these program units to achieve the corresponding functions. All of the above modules reside in the same processor; alternatively, the modules may be located in different processors in any combination.

[0115] The processor contains a kernel, which retrieves the corresponding program units from memory. One or more kernels can be configured, and adjusting kernel parameters can address the resource waste caused by the need for multiple communication lines in existing technologies.

[0116] The memory may include non-permanent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0117] This invention provides a computer-readable storage medium including a stored program, wherein the program, when running, controls the device containing the computer-readable storage medium to execute the single-wire communication control method.

[0118] Specifically, the control methods for single-wire communication include:

[0119] Step S201, Initiation step, the first controller initiates communication, the first controller includes a first pin, the first pin is an I / O port;

[0120] Step S202, output step, the first controller sequentially outputs a first voltage signal of a first set duration and a second voltage signal of a second set duration, so that the second controller triggers rising edge detection or falling edge detection. The first voltage signal and the second voltage signal are opposite level signals. The rising edge detection is a low-level to high-level detection, and the falling edge detection is a high-level to low-level detection. The first controller and the second controller are communicatively connected.

[0121] Step S203, reading step, adjust the first pin of the first controller to the input port and start timing, read the pin level of the first pin at fixed time until the timing duration reaches the third set duration, the third set duration is a multiple of the fixed time;

[0122] Step S204, storage step: if the pin voltages read within the third set time period are the same, receive the current bit data sent by the second controller, store the current bit data in sequence into the communication data array, and repeat the above initiation step, the above output step, the above reading step and the above storage step at least once until the communication data reading of the set length is completed.

[0123] This invention provides a processor for running a program, wherein the program executes the single-wire communication control method during runtime.

[0124] Specifically, the control methods for single-wire communication include:

[0125] Step S201, Initiation step, the first controller initiates communication, the first controller includes a first pin, the first pin is an I / O port;

[0126] Step S202, output step, the first controller sequentially outputs a first voltage signal of a first set duration and a second voltage signal of a second set duration, so that the second controller triggers rising edge detection or falling edge detection. The first voltage signal and the second voltage signal are opposite level signals. The rising edge detection is a low-level to high-level detection, and the falling edge detection is a high-level to low-level detection. The first controller and the second controller are communicatively connected.

[0127] Step S203, reading step, adjust the first pin of the first controller to the input port and start timing, read the pin level of the first pin at fixed time until the timing duration reaches the third set duration, the third set duration is a multiple of the fixed time;

[0128] Step S204, storage step: if the pin voltages read within the third set time period are the same, receive the current bit data sent by the second controller, store the current bit data in sequence into the communication data array, and repeat the above initiation step, the above output step, the above reading step and the above storage step at least once until the communication data reading of the set length is completed.

[0129] This invention provides a single-wire communication control system, which includes a processor, a memory, and a program stored in the memory and executable on the processor. When the processor executes the program, it performs at least the following steps:

[0130] Step S201, Initiation step, the first controller initiates communication, the first controller includes a first pin, the first pin is an I / O port;

[0131] Step S202, output step, the first controller sequentially outputs a first voltage signal of a first set duration and a second voltage signal of a second set duration, so that the second controller triggers rising edge detection or falling edge detection. The first voltage signal and the second voltage signal are opposite level signals. The rising edge detection is a low-level to high-level detection, and the falling edge detection is a high-level to low-level detection. The first controller and the second controller are communicatively connected.

[0132] Step S203, reading step, adjust the first pin of the first controller to the input port and start timing, read the pin level of the first pin at fixed time until the timing duration reaches the third set duration, the third set duration is a multiple of the fixed time;

[0133] Step S204, storage step: if the pin voltages read within the third set time period are the same, receive the current bit data sent by the second controller, store the current bit data in sequence into the communication data array, and repeat the above initiation step, the above output step, the above reading step and the above storage step at least once until the communication data reading of the set length is completed.

[0134] This application also provides a computer program product, which, when executed on a data processing device, is suitable for executing an initialization program having at least the following method steps:

[0135] Step S201, Initiation step, the first controller initiates communication, the first controller includes a first pin, the first pin is an I / O port;

[0136] Step S202, output step, the first controller sequentially outputs a first voltage signal of a first set duration and a second voltage signal of a second set duration, so that the second controller triggers rising edge detection or falling edge detection. The first voltage signal and the second voltage signal are opposite level signals. The rising edge detection is a low-level to high-level detection, and the falling edge detection is a high-level to low-level detection. The first controller and the second controller are communicatively connected.

[0137] Step S203, reading step, adjust the first pin of the first controller to the input port and start timing, read the pin level of the first pin at fixed time until the timing duration reaches the third set duration, the third set duration is a multiple of the fixed time;

[0138] Step S204, storage step: if the pin voltages read within the third set time period are the same, receive the current bit data sent by the second controller, store the current bit data in sequence into the communication data array, and repeat the above initiation step, the above output step, the above reading step and the above storage step at least once until the communication data reading of the set length is completed.

[0139] It is obvious to those skilled in the art that the modules or steps of the present invention described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those described herein, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the present invention is not limited to any particular combination of hardware and software.

[0140] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0141] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0142] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0143] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0144] In a typical configuration, a computing device includes one or more processors (CPUs), input / output pins, network pins, and memory.

[0145] Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, like read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0146] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0147] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0148] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0149] 1) The single-wire communication control method of this application includes an initiation step whereby a first controller initiates communication. The first controller includes a first pin, which is an I / O port. An output step whereby the first controller sequentially outputs a first voltage signal of a first set duration and a second voltage signal of a second set duration, thereby triggering rising edge detection or falling edge detection by the second controller. The first voltage signal and the second voltage signal are opposite level signals. The rising edge detection is a low-to-high level transition detection, and the falling edge detection is a high-to-low level transition detection. The first controller communicates with the second controller. The connection and reading steps involve adjusting the first pin of the first controller to an input port and starting a timer. The pin level of the first pin is read at fixed intervals until the timer reaches a third set duration, which is a multiple of the fixed time. The storage step involves receiving the current bit data sent by the second controller when the pin levels read within the third set duration are the same, storing the current bit data in sequence into the communication data array, and repeating the initiation step, output step, reading step, and storage step at least once until the communication data of the set length is read. This application aims to achieve communication over a single line by setting up two controller MCUs (i.e., the first controller and the second controller mentioned above). Communication is initiated by the first controller. The first pin of the first controller first outputs a first voltage signal for a first set time, and then outputs a second voltage signal for a second set time. The main purpose of this is to provide an interrupt to the second controller. Therefore, the duration of the first and second set times only needs to meet the interrupt detection of the second controller. After the second set time, the first pin of the first controller becomes an input port. A timer generates a time T1. If the same level is detected multiple times consecutively, it is considered that the correct bit data has been read, and the current bit data is stored in the communication data array. The above steps are repeated until the data reading and transmission are completed. Through the above steps, single-line communication is achieved, thereby reducing chip resource waste. This application solves the problem of chip resource waste caused by the use of multiple lines for communication in the prior art, which requires multiple line resources for the communication chip.

[0150] 2) The single-wire communication control device of this application includes an initiation unit for executing an initiation step, wherein a first controller initiates communication, the first controller including a first pin, the first pin being an I / O port; and an output unit for executing an output step, wherein the first controller sequentially outputs a first voltage signal of a first set duration and a second voltage signal of a second set duration, thereby triggering a rising edge detection or a falling edge detection by the second controller. The first voltage signal and the second voltage signal are opposite level signals, the rising edge detection is a low-level-to-high-level detection, and the falling edge detection is a high-level-to-low-level detection. The first controller communicates with the second controller. The system includes a connection and a reading unit, which performs a reading step by adjusting the first pin of the first controller to an input port and starting a timer, reading the pin level of the first pin at fixed intervals until the timer reaches a third set duration, where the third set duration is a multiple of the fixed time. A storage unit performs a storage step by receiving current bit data sent by the second controller when the pin levels read within the third set duration are equal, storing the current bit data sequentially into a communication data array, and repeating the initiation step, the output step, the reading step, and the storage step at least once until a set length of communication data is read. This application aims to achieve communication over a single line by setting up two controller MCUs (i.e., the first controller and the second controller mentioned above). Communication is initiated by the first controller. The first pin of the first controller first outputs a first voltage signal for a first set time, and then outputs a second voltage signal for a second set time. The main purpose of this is to provide an interrupt to the second controller. Therefore, the duration of the first and second set times only needs to meet the interrupt detection of the second controller. After the second set time, the first pin of the first controller becomes an input port. A timer generates a time T1. If the same level is detected multiple times consecutively, it is considered that the correct bit data has been read, and the current bit data is stored in the communication data array. The above steps are repeated until the data reading and transmission are completed. Through the above steps, single-line communication is achieved, thereby reducing chip resource waste. This application solves the problem of chip resource waste caused by the use of multiple lines for communication in the prior art, which requires multiple line resources for the communication chip.

[0151] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A control method of single-wire communication, characterized by, The method comprises: a step of initiating communication by a first controller, the first controller comprising a first pin, the first pin being an I / O port; a step of outputting, by the first controller, a first voltage signal of a first set time length and a second voltage signal of a second set time length in sequence, so that a second controller triggers rising edge detection or falling edge detection, the first voltage signal and the second voltage signal being mutually opposite level signals, the rising edge detection being detection of a low level to a high level, the falling edge detection being detection of a high level to a low level, the first controller being in communication connection with the second controller, and the second controller triggering the rising edge detection or the falling edge detection serving to enable the second controller to complete interrupt detection and ensure that data bit transmission can be correctly identified by a receiving end; a step of reading, by adjusting the first pin of the first controller to an input port and starting timing, reading a pin level of the first pin at a fixed time until a timing length reaches a third set time length, the third set time length being a multiple of the fixed time; a step of storing, in the case of the pin level read within the third set time length being the same, current bit data sent by the second controller, storing the current bit data in a communication data array in sequence, and repeatedly performing the step of initiating communication, the step of outputting, the step of reading, and the step of storing at least once until communication data of a set length is read.

2. The method of claim 1, wherein, Before the first controller initiates communication, the method further comprises: initializing the first pin of the first controller to an output port and outputting the second voltage signal, and initializing a timer of the first controller.

3. The method of claim 1, wherein, The first controller outputs a first voltage signal of a first set time length and a second voltage signal of a second set time length in sequence, comprising: the first controller outputs the first voltage signal, and the first controller controls the timer to time to obtain a first timing length; in the case where the first timing length reaches the first set time length, the timer of the first controller is initialized, and the first controller adjusts output to the second voltage signal, and the first controller controls the timer to time until the second set time length is reached.

4. The method of claim 1, wherein, The first controller outputs a first voltage signal of a first set time length and a second voltage signal of a second set time length in sequence, so that a second controller triggers rising edge detection or falling edge detection, comprising: in the case where the first voltage signal is a low level and the second voltage signal is a high level, the second controller is triggered to perform the rising edge detection, the low level being 0 and the high level being 1; in the case where the first voltage signal is the high level and the second voltage signal is the low level, the second controller is triggered to perform the falling edge detection.

5. The method of claim 1, wherein, The first pin of the first controller is connected with a second pin of the second controller through a single line, a first resistor is connected between the single line, a third pin of the second controller is connected with a target side line of the single line, the target side line is a line between the second pin and the first resistor, the second controller comprises the second pin and the third pin, the second pin is an I / O port, and the third pin is an external interrupt port, Receiving current bit data sent by the second controller, comprising: Initializing the second pin and the third pin; Judging whether the third pin of the second controller identifies a rising edge or a falling edge of a target node, the target node being a connection node of the second resistor and the target side line; In the case that the third pin identifies the rising edge or the falling edge, switching the second pin of the second controller to an output port, so that the first controller receives current bit data sent by the output port.

6. The method of claim 5, wherein, Before judging whether the third pin of the second controller identifies a rising edge or a falling edge, the method comprises: Determining a target time length condition, the target time length condition being a time length condition that a target time length is less than a sum of the second set time length and the third set time length, the target time length being a time interval from the third pin identifying the rising edge or the falling edge to the second pin outputting the current bit data.

7. The method of claim 5, wherein, The second controller comprises a second pin and a third pin, the second pin being an I / O port, and the third pin being an external input port, receiving current bit data sent by the second controller, and further comprising: Initializing the second pin and the third pin; Judging whether the third pin of the second controller identifies a level change of the target node; In the case that the level change is from low level to high level or the level change is from the high level to the low level, switching the second pin of the second controller to an output port, so that the first controller receives current bit data sent by the output port.

8. A control device for single-wire communication, characterized by The device comprises: An initiating unit is configured to perform an initiating step, a first controller initiates communication, the first controller comprising a first pin, and the first pin being an I / O port; An output unit is configured to perform an output step, the first controller sequentially outputs a first voltage signal of a first set time length and a second voltage signal of a second set time length, so that a second controller triggers rising edge detection or falling edge detection, the first voltage signal and the second voltage signal being mutually opposite level signals, the rising edge detection being detection of low level to high level, and the falling edge detection being detection of high level to low level, the first controller being in communication connection with the second controller, and the second controller triggering the rising edge detection or the falling edge detection serving to make the second controller complete interrupt detection and ensure that data bit transmission can be correctly identified by a receiving end. The reading unit is configured to perform a reading step, adjust the first pin of the first controller as an input port and start timing, read the pin level of the first pin at a fixed time until the timing duration reaches a third set duration, and the third set duration is a multiple of the fixed time. The storage unit is configured to perform a storage step, in the case that the pin level read in the third set duration is the same, receive the current bit data sent by the second controller, store the current bit data in the communication data array in sequence, and repeat the initiation step, the output step, the reading step and the storage step at least once in sequence until the communication data of the set length is read.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium comprises a stored program, wherein the program controls the device where the computer readable storage medium is located to perform the method of any one of claims 1 to 7 when the program is running.

10. A computer program product comprising computer instructions, characterized in that, The computer instructions are executed by the processor to implement the method of any one of claims 1 to 7.

Images