Data transmission method, signal transmitting circuit, signal receiving circuit, equipment, system, medium and product

Abstract

The invention provides a data transmission method, a signal sending circuit, a signal receiving circuit, equipment, a system, a medium and a product. The data transmission method is applied to a first device. The method comprises the following steps: sending a clock signal and a first data signal to at least one second device; respectively and correspondingly sending a level single-ended or level differential chip selection signal to the at least one second device, wherein the chip selection signal is used for representing whether the second device is selected or not; wherein when the second device is selected by the chip selection signal sent by the first device, the second device receives the first data signal. According to the method provided by the invention, the form of the chip selection signal is flexibly configured, so that the second equipment can accurately determine whether the chip selection signal is selected according to the chip selection signal, the communication quality can be effectively ensured, and various communication requirements are met.

Description

Technical Field

[0001] The present application relates to communication technology, and in particular to a data transmission method, a signal sending circuit, a signal receiving circuit, a device, a system, a medium and a product. Background Art

[0002] In the prior art, the host and the slave communicate through single-ended signals, which are easily interfered by noise and have poor communication quality, and cannot meet the communication requirements in many scenarios such as long-distance vehicle communication. Summary of the invention

[0003] Embodiments of the present application provide a data transmission method, a signal sending circuit, a signal receiving circuit, a device, a system, a medium and a product to improve communication quality.

[0004] In a first aspect, an embodiment of the present application provides a data transmission method, which is applied to a first device, and the method includes:

[0005] sending a clock signal and a first data signal to at least one second device;

[0006] A single-ended or differential chip select signal is sent to the at least one second device respectively, and the chip select signal is used to indicate whether the second device is selected; wherein, when the second device is selected by the chip select signal sent by the first device, the second device receives the first data signal.

[0007] In a second aspect, an embodiment of the present application provides a data transmission method, which is applied to a second device, and the method includes:

[0008] Receiving a clock signal and a first data signal sent by a first device;

[0009] receiving a single-ended or differential chip select signal sent by the first device, wherein the chip select signal is used to indicate whether the second device is selected;

[0010] When the second device is selected by the chip selection signal sent by the first device, the first data signal is received.

[0011] In a third aspect, an embodiment of the present application provides a data transmission method, which is applied to a data transmission system, wherein the data transmission system includes a first device and at least one second device; the method includes:

[0012] The first device sends a clock signal and a first data signal to the at least one second device;

[0013] The first device sends a single-ended or differential chip select signal to the at least one second device respectively, wherein the chip select signal is used to indicate whether the second device is selected;

[0014] When the second device is selected by the chip selection signal sent by the first device, it receives the first data signal.

[0015] In a fourth aspect, an embodiment of the present application provides a signal sending circuit, including:

[0016] A sending module, configured to receive an enable signal and a level single-ended signal to be sent; and, according to the enable signal being in different states, output the level single-ended signal to be sent to an output end, or generate a level differential signal to be sent based on the received level single-ended signal to be sent;

[0017] The output end is connected to the sending module and is used to send the single-ended or differential level signal to be sent output by the sending module to other devices.

[0018] In a fifth aspect, an embodiment of the present application provides a signal receiving circuit, including:

[0019] A receiving end is used to receive a single-ended or differential level signal to be sent from other devices;

[0020] The processing module is used to integrate the level single-ended or level differential signals to be sent into a level single-ended signal.

[0021] In a sixth aspect, an embodiment of the present application provides a device, comprising: a signal sending circuit as described above and / or a signal receiving circuit as described above.

[0022] In a seventh aspect, an embodiment of the present application provides a data transmission system, comprising a host and at least one slave; the host and the slave comprise: the signal sending circuit as described above and / or the signal receiving circuit as described above.

[0023] In an eighth aspect, an embodiment of the present application provides a first device, including:

[0024] A first sending module, used for sending a clock signal and a first data signal to a second device;

[0025] The second sending module is used to send a single-ended or differential chip select signal to the second device, and the chip select signal is used to indicate whether the second device is selected; wherein, when the second device is selected by the chip select signal sent by the first device, the second device receives the first data signal.

[0026] In a ninth aspect, an embodiment of the present application provides a second device, including:

[0027] A first receiving module, used to receive a clock signal and a first data signal sent by a first device;

[0028] A second receiving module, used for receiving a single-ended or differential chip select signal sent by the first device, wherein the chip select signal is used for indicating whether the second device is selected;

[0029] The third receiving module is used to receive the first data signal when the second device is selected by the chip selection signal sent by the first device.

[0030] In a tenth aspect, an embodiment of the present application provides a data transmission system, including a first device and a second device; wherein:

[0031] The first device sends a clock signal and a first data signal to the second device;

[0032] The first device sends a single-ended or differential chip select signal to the second device, where the chip select signal is used to indicate whether the second device is selected;

[0033] When the second device is selected by the chip selection signal sent by the first device, the first data signal is received.

[0034] In an eleventh aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to implement the method as described above when executed by a processor.

[0035] In a twelfth aspect, an embodiment of the present application provides a computer program product, including a computer program, which implements the method as described above when the computer program is executed by a processor.

[0036] In the data transmission method, signal sending circuit, signal receiving circuit, device, system, medium and product provided in the embodiments of the present application, a first device sends a clock signal and a first data signal to at least one second device. According to the communication requirements of different scenarios, it can be flexibly selected to send a single-ended or differential chip select signal to at least one second device respectively. For example, when the communication quality requirement is low, a single-ended chip select signal is sent to at least one second device respectively; when the communication quality requirement is high, a differential chip select signal is sent to at least one second device respectively. Thus, each second device can accurately determine whether it is selected according to the chip select signal, and receive the first data signal when selected. By flexibly configuring the form of the chip select signal, the communication quality can be effectively guaranteed to meet various communication requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0038] Figure 1A schematic diagram of a data transmission method provided by an embodiment of the present application is exemplarily shown in FIG.

[0039] Figure 2 exemplarily shows a schematic diagram of downlink frame sampling based on a level single-ended chip select signal provided in an embodiment of the present application;

[0040] Figure 3 A schematic diagram of downlink frame sampling based on a level differential chip select signal provided in an embodiment of the present application is exemplarily shown in FIG.

[0041] Figure 4 A schematic diagram of a flow chart of another data transmission method provided in an embodiment of the present application is exemplarily shown in FIG.

[0042] Figure 5 A flowchart of another data transmission method provided by an embodiment of the present application is exemplarily shown in FIG.

[0043] Figure 6 The structure diagram of the signal transmission circuit provided by the embodiment of the present application is exemplarily shown in FIG.

[0044] Figure 7 The structure diagram of the signal receiving circuit provided by the embodiment of the present application is exemplarily shown in FIG.

[0045] Figure 8 A schematic diagram of the structure of a device provided by an embodiment of the present application is exemplarily shown in FIG.

[0046] Fig. 9 A schematic diagram of the structure of a data transmission system provided in an embodiment of the present application is exemplarily shown in FIG.

[0047] Fig.10 A structural diagram of another data transmission system provided in an embodiment of the present application is exemplarily shown in FIG.

[0048] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0049] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0050] The module in this application refers to a functional module or a logical module. It can be in software form, and its functions are realized by executing program code by a processor; it can also be in hardware form. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the related objects before and after are in an "or" relationship.

[0051] First, the terms involved in this application are explained:

[0052] Micro Second Channel (MSC) communication: is a high-speed synchronous serial communication mode, which is usually used for one-to-one and one-to-many communication between the host (including but not limited to the microcontroller unit (MCU), field programmable gate array (FPGA) and the slave (including but not limited to the external power device STL9788, TLE8888), and is often used in long-distance vehicle communication scenarios. The host sends a downlink frame to the slave through the high-speed synchronous serial downlink channel. The slave responds after identifying the valid downlink frame during the effective period of the chip select signal; wherein, the MSC downlink frame includes a clock signal, a data signal and a chip select signal. The existing MSC downlink frame signal line usually consists of a pair of differential clock lines, a pair of differential data lines and one or more single-ended chip select lines. The slave detects the received chip select signal, and when the chip select signal is valid, samples the host data signal according to the clock signal.

[0053] Chip select signal: refers to the control signal that indicates whether the slave is selected by the host. The chip select signal can be a low-level effective signal or a high-level effective signal.

[0054] Single-ended signal: refers to the way of transmitting signals with only one signal pin. In single-ended signal transmission, the change of voltage or current of the signal source relative to the ground (or reference voltage) represents the information of the signal. Single-ended signal transmission is simple and common, suitable for short-distance data transmission. The advantage is that it is simple and convenient, and can meet the needs of data acquisition in most fields. The disadvantage is that the anti-interference ability is relatively weak.

[0055] Differential signal: refers to the method of transmitting signals through two signal pins in opposite directions. One pin transmits a positive signal and the other pin transmits a negative signal. Differential signal transmission uses the voltage difference or current difference between the two pins to represent the signal information, which can provide better anti-interference ability for long-distance transmission.

[0056] In the prior art, the host and the slave communicate with each other through single-ended signals, which are easily interfered by noise and have poor communication quality, and cannot meet the communication requirements in many scenarios such as long-distance vehicle communication.

[0057] In view of this, the embodiments of the present application provide a data transmission method, a signal sending circuit, a signal receiving circuit, a device, a system, a medium and a product. The signal sending circuit can convert the single-ended signal to be output into a differential signal and then output it, so that communication can be carried out by differential signal, effectively improving the quality of signal transmission; at the same time, in order to improve the flexibility of the signal sending circuit, two output modes can be set, in one mode the signal is directly output, and in another mode the single-ended signal is differentially processed and then output, so that various types of signals can be flexibly output, which can better adapt to the signal requirements of the signal receiver.

[0058] The technical solution of the present application is illustrated below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0059] An embodiment of the present application provides a data transmission method. Figure 1 The flowchart of a data transmission method provided in the embodiment of the present application is shown in FIG. The execution subject of the method is a first device. Figure 1 As shown, the method includes:

[0060] S101, sending a clock signal and a first data signal to at least one second device;

[0061] S102. Send a single-ended or differential chip select signal to at least one second device respectively, where the chip select signal is used to indicate whether the second device is selected; when the second device is selected by the chip select signal sent by the first device, the second device receives the first data signal.

[0062] In a specific implementation, the first device may be a host, and the second device may be a slave. The first device sends a downlink frame signal to at least one second device, and the downlink frame signal includes a clock signal, a first data signal, and a chip select signal. The first device sends the same clock signal and the first data signal to at least one second device, and sends a chip select signal to each second device respectively. When the second device is selected by the chip select signal, it receives the first data signal, and when the second device is not selected by the chip select signal, it does not receive the first data signal. When the first device expects to send the first data signal to a second device, the chip select signal corresponding to the second device is configured to select the second device.

[0063] In actual communication scenarios, it is possible to flexibly select to send a single-ended or differential-level chip select signal to at least one second device respectively according to the communication quality requirements. For example, when the communication quality requirements are low, a single-ended chip select signal is sent to at least one second device respectively, and when the communication quality requirements are high, a differential-level chip select signal is sent to at least one second device respectively. Thus, the chip select signal can accurately indicate whether each second device is selected, avoiding the second device from erroneously receiving or not receiving the first data signal due to noise interference and the like.

[0064] In this embodiment, by flexibly configuring the form of the chip select signal, the second device can accurately determine whether it is selected according to the chip select signal, which can effectively ensure the communication quality and meet various communication requirements.

[0065] It should be noted that the chip select signal may be in different forms for different second devices. The first device may send a single-ended chip select signal to some of the second devices, and a differential chip select signal to the rest of the second devices; or, the first device may send a high-level valid chip select signal to some of the second devices, and a low-level valid chip select signal to the rest of the second devices. The first device may configure the chip select signal corresponding to the second device according to the communication environment and the configuration information of the second device.

[0066] In a possible implementation, the level-differential chip select signal includes: a first chip select component signal and a second chip select component signal, wherein when the difference between the first chip select component signal and the second chip select component signal is within a preset range, it indicates whether the second device is selected.

[0067] In a specific implementation, the level-differential chip select signal includes a first chip select component signal and a second chip select component signal, and the difference between the first chip select component signal and the second chip select component signal indicates whether the second device is selected. For example, when the difference between the first chip select component signal and the second chip select component signal is higher than a first threshold, it indicates that the second device is selected; when the difference between the first chip select component signal and the second chip select component signal is lower than a second threshold, it indicates that the second device is not selected.

[0068] Exemplarily, the first chip selection component signal and the second chip selection component signal are equal in magnitude and opposite in polarity.

[0069] In this embodiment, the difference between the first chip select component signal and the second chip select component signal is used to characterize whether the second device is selected. When the chip select signal jitters due to common mode interference, the difference between the first chip select component signal and the second chip select component signal can offset the jitter, thereby accurately characterizing whether the second device is selected, which is beneficial to improving communication quality.

[0070] In a possible implementation, the method further includes:

[0071] When the second device is selected, a second data signal with a single-ended level or a differential level returned by the second device is received.

[0072] In a specific implementation, when the second device is selected, a corresponding response action can be performed according to the received first data signal. Exemplarily, the first data signal can be used to indicate control of the second device, indicate reading the status of the second device, or indicate the second device to control a downstream device. When the first data signal indicates reading the status of the second device, the first device receives the second data signal returned by the second device. Among them, the second device can also flexibly configure the second data signal as a single-ended level or a differential level form according to the requirements of the communication quality, so that the first device can accurately obtain the data sent by the second device.

[0073] In this embodiment, by flexibly configuring the second data signal as a single-ended level or a differential level form, the first device can accurately obtain the data sent by the second device, which is conducive to ensuring communication quality and meeting various communication requirements.

[0074] In a possible implementation manner, the second data signal with a level difference includes: a first data component signal and a second data component signal, and the first device is further configured to:

[0075] A data signal represented by a difference between the first data component signal and the second data component signal is received.

[0076] In a specific implementation, the level-differential second data signal includes a first data component signal and a second data component signal, and data is transmitted to the first device through the difference between the first data component signal and the second data component signal. For example, when the difference between the first chip select component signal and the second chip select component signal is higher than the third threshold, data "1" is transmitted; when the difference between the first chip select component signal and the second chip select component signal is lower than the fourth threshold, data "0" is transmitted.

[0077] Exemplarily, the first data component signal and the second data component signal are equal in magnitude and opposite in polarity.

[0078] In this embodiment, data is sent via the difference between the first data component signal and the second data component signal. When the second data signal is jittered due to common-mode interference, the difference between the first data component signal and the second data component signal can offset the jitter, so that the first device can accurately obtain the data sent by the second device, which is beneficial to improving communication quality.

[0079] In a possible implementation manner, the clock signal and / or the first data signal is in a level differential form.

[0080] In a specific implementation, in order to ensure the communication quality, the clock signal and the first data signal can also be flexibly configured as single-ended or differential-level forms according to the communication quality requirements. For example, when the communication quality requirements are low, a single-ended clock signal and a first data signal are sent to at least one second device, and when the communication quality requirements are high, a differential-level clock signal and a first data signal are sent to at least one second device.

[0081] In this embodiment, when the communication quality requirement is high, the clock signal and / or the first data signal may be configured in a level differential form, which can effectively ensure the communication quality.

[0082] In a possible implementation, the first device transmits the clock signal and the first data signal in the form of a data frame, and the data frame includes a data transmission phase;

[0083] The data transmission phase is used to transmit valid data, and the duration of the data transmission phase is less than or equal to the duration of the data frame.

[0084] In a specific implementation, the first device transmits a clock signal, a chip select signal and a first data signal in the form of a data frame. For example, the data frame may adopt the MSC communication protocol. The data frame includes a data transmission phase, the data transmission phase is used to transmit valid data to the second device, and the duration of the data transmission phase is less than or equal to the duration of the data frame.

[0085] Correspondingly, in the data transmission phase, at least one second device is selected. The first device transmits valid data to the selected second device in the data transmission phase.

[0086] In a possible implementation, the data frame further includes an idle phase;

[0087] In the idle phase, the first data signal is a continuous high level signal or a low level signal.

[0088] In a specific implementation, the data frame can be divided into a data transmission phase and an idle phase. In the idle phase, the first data signal does not transmit valid data and is a continuous high level or low level signal.

[0089] Correspondingly, in the idle phase, no second device is selected, and each second device does not receive the first data signal.

[0090] Combine the following Figure 2 , explaining how single-ended signals are susceptible to noise interference.

[0091] Figure 2A schematic diagram of downlink frame sampling based on a level single-ended chip select signal provided in an embodiment of the present application. Take the case where a first device communicates with a second device, the clock signal and the first data signal are in level differential form, the chip select signal is in level single-ended form, the clock signal is valid during the entire downlink frame transmission period, the chip select signal is valid at a low level, and the first device and the second device both jump at the rising edge of the clock and sample at the falling edge of the clock as an example. Figure 2 As shown, the second device receives two frames of MSC downlink frame signals sent by the first device, and the downlink frames include a clock signal pair SCK_P and SCK_N in the form of a differential signal, a first data signal pair SDO_P and SDO_N in the form of a differential signal, and a chip select signal CSreal in the form of a single-ended signal. CSideal is the chip select signal sent by the first device to the second device in an ideal state. Assuming that the current communication environment is poor, due to the interference of common-mode noise, the CSreal actually sent by the first device jitters, and CSreal and CSideal appear different. The second device detects CSreal based on the preset high-level threshold Vthr and low-level threshold Vthf, and identifies and obtains the chip select signal CSreal_slave1.

[0092] Among them, CSreal will jitter due to common mode noise interference in the level switching process (including the falling process and the rising process) and the level holding process (including the low and high level holding process). If CSreal has negative jitter in the falling process, and the voltage swing value of the jitter reaches Vthf, the second device samples the first data signal pair SDO_P and SDO_N at sampling point ⑥, which is different from the expected sampling point ②, causing the second device to mistakenly identify the last bit of data in the idle phase of the first frame downlink frame as the first bit of data in the data transmission phase of the second frame; if CSreal has negative jitter in the rising process, and the voltage swing value of the jitter reaches Vthf, the second device samples the first data signal pair SDO_P and SDO_N at sampling point ④. Sampling is performed, which is different from the expected sampling point ③; if CSreal has positive jitter during the low-level holding process, and the voltage swing value of the jitter reaches Vthr, and the jitter is aligned in time domain with the effective sampling edge (sampling point ⑤) of the second device, the second device mistakenly recognizes that the current downlink frame has ended at sampling point ⑤; if CSreal has negative jitter during the high-level holding process, and the voltage swing value reaches Vthf, and the jitter is aligned in time domain with the effective sampling edge (sampling point ①) of the second device, the second device mistakenly recognizes that the next downlink frame has started at sampling point ①.

[0093] In the embodiment of the present application, when the communication quality requirement is high or the communication environment is poor, the first device can configure the chip select signal to be in a level differential form to effectively improve the anti-interference ability of the signal. Figure 3 Provide explanation.

[0094] Figure 3 A schematic diagram of downlink frame sampling based on level differential chip select signals provided in an embodiment of the present application. For example, a first device communicates with a second device, a clock signal, a first data signal, and a chip select signal are all level differential, the clock signal is valid in the entire downlink frame sending device, the chip select signal is valid at a low level, and the first device and the second device both jump on the rising edge of the clock and sample on the falling edge of the clock. Figure 3 As shown, the second device receives two frames of MSC downlink frame signals sent by the first device. The downlink frames include a clock signal pair SCK_P and SCK_N in the form of differential signals, a first data signal pair SDO_P and SDO_N in the form of differential signals, and a chip select signal pair CSreal_P and CSreal_N in the form of differential signals. CSideal is the chip select signal sent by the first device to the second device in an ideal state. Due to the interference of common mode noise, the CSreal_P and CSreal_N actually sent by the first device jitter, and CSreal_P and CSideal appear different. The second device makes a difference between CSreal_P and CSreal_N based on the preset high level threshold Vthr and low level threshold Vthf, and obtains the chip select signal CSreal_slave2 according to the difference. When there is noise interference from the outside, it will be coupled to CSreal_P and CSreal_N almost at the same time, and jitters of the same amplitude and phase will appear on CSreal_P and CSreal_N, so the common mode noise can be offset on the second device side.

[0095] Among them, CSreal_slave2 is the same as CSideal, so the second device can accurately sample in the effective phase expected by the first device. The first actual sampling point of the second downlink frame received by the second device matches the theoretical sampling point ⑥, which will not cause the second device to mistakenly identify the last bit of data in the idle phase of the first downlink frame as the first bit of the data transmission phase of the second frame. Similarly, if CSreal_P and CSreal_N both have negative jitter during the rising process, the second device side can also offset the jitter based on the difference between CSreal_P and CSreal_N. The last actual sampling point of the idle phase of the second downlink frame data received by the second device will match the theoretical sampling point ③, which will not cause the second device to mistakenly identify that the downlink frame data transmission phase has not ended. If CSreal_P and CSreal_N both have positive jitter with a voltage swing value reaching Vthr during the low-level holding process, and the jitter is aligned with the time domain of the effective sampling edge (sampling point ⑤) of the second device, the second device side can also offset the jitter and will not mistakenly identify that the current downlink frame has ended. Similarly, if CSreal_P and CSreal_N both experience negative jitter with a voltage swing value reaching Vthf during the high-level maintenance process, and the jitter is aligned with the effective sampling edge (sampling point ①) of the second device in the time domain, the second device side can also offset the jitter and will not mistakenly recognize that the next downlink frame has started. Figure 2 The downlink frame sampling process based on the level single-ended chip select signal shown uses a level differential chip select signal when there is noise interference. The second device can extract a valid chip select signal that is consistent with the ideal chip select signal, thereby increasing the system's anti-interference ability.

[0096] In a possible implementation, sending a single-ended level or a differential level chip select signal to at least one second device respectively includes:

[0097] respectively acquiring first configuration information of at least one second device, where the first configuration information indicates a form of a chip select signal received by the second device;

[0098] According to the first configuration information of at least one second device, a single-ended level or a differential level chip select signal is correspondingly sent to at least one second device.

[0099] In a specific implementation, the first device may obtain the first configuration information of each second device, and send a single-ended or differential chip select signal to each second device respectively according to the form of the chip select signal received by each second device.

[0100] In this embodiment, the first device can send a single-ended or differential chip select signal to at least one second device respectively according to the form of the chip select signal received by the second device, which is conducive to improving the flexibility and reliability of communication.

[0101] In a possible implementation, sending a chip select signal with a level difference to at least one second device respectively includes:

[0102] A first enable signal is obtained, and according to the first enable signal, a single-ended chip select signal is converted into a differential chip select signal, and the differential chip select signal is sent to at least one second device respectively.

[0103] In a specific implementation, the first device may support converting a single-ended chip select signal into a differential chip select signal. The first device acquires a first enable signal, and the first enable signal is used to indicate whether the first device converts the single-ended chip select signal into a differential chip select signal. When the first enable signal is enabled, the first device converts the single-ended chip select signal into a differential chip select signal and sends it to the second device; when the first enable signal is not enabled, the single-ended chip select signal is sent to the second device.

[0104] It should be noted that for multiple second devices, there can be multiple first enable signals. The first device can convert the single-ended chip select signal corresponding to each second device into a differential chip select signal or not convert it according to the first enable signal corresponding to each second device.

[0105] In this embodiment, the first device can convert the single-ended chip select signal into a differential chip select signal and send it to the second device, thereby effectively improving the anti-interference capability of the chip select signal.

[0106] In a possible implementation, the method further includes:

[0107] A first amplitude signal is obtained, and the amplitude of the chip selection signal of the level difference is controlled according to the first amplitude signal.

[0108] In a specific implementation, when the first device converts a level single-ended chip select signal into a level differential chip select signal, the amplitude of the level differential chip select signal can be controlled according to the first amplitude signal.

[0109] It should be noted that, for multiple second devices, there can be multiple first amplitude signals.

[0110] In this embodiment, based on the first amplitude signal, the first device can control the amplitude of the chip select signal of the level difference, which can better adapt to the communication requirements of the second device and improve the flexibility of communication.

[0111] The embodiment of the present application also provides a first device, including:

[0112] A first sending module, used for sending a clock signal and a first data signal to a second device;

[0113] The second sending module is used to send a single-ended or differential chip select signal to the second device, where the chip select signal is used to indicate whether the second device is selected; when the second device is selected by the chip select signal sent by the first device, the second device receives the first data signal.

[0114] It should be noted that the first device provided in the embodiment of the present application can be used to execute the data transmission method with the execution subject being the first device as described above. Its basic principles and specific implementation methods are as described above and will not be repeated here.

[0115] The embodiment of the present application also provides a data transmission method. Figure 4 1 is a flow chart of another data transmission method provided in an embodiment of the present application. The execution subject of the method is the second device. Figure 4 As shown, the method includes:

[0116] S401, receiving a clock signal and a first data signal sent by a first device;

[0117] S402, receiving a single-ended or differential chip select signal sent by the first device, where the chip select signal is used to indicate whether the second device is selected;

[0118] S403: When the second device is selected by the chip selection signal sent by the first device, the second device receives the first data signal.

[0119] In a specific implementation, the first device may be a host, and the second device may be a slave. The first device sends a downlink frame signal to at least one second device, and the downlink frame signal includes a clock signal, a first data signal, and a chip select signal. The first device sends the same clock signal and the first data signal to at least one second device, and sends a chip select signal to each second device respectively. When the second device is selected by the chip select signal, it receives the first data signal, and when the second device is not selected by the chip select signal, it does not receive the first data signal. When the first device expects to send the first data signal to a second device, the chip select signal corresponding to the second device is configured to select the second device.

[0120] According to different communication requirements, the chip select signal can be configured as a single-ended or differential-level signal. For example, when the communication quality requirement is low, the second device receives a single-ended chip select signal, and when the communication quality requirement is high, the second device receives a differential-level chip select signal. Thus, the chip select signal can accurately indicate whether the second device is selected, avoiding the second device from erroneously receiving or not receiving the first data signal due to noise interference and the like.

[0121] In this embodiment, by flexibly configuring the form of the chip select signal, the second device can accurately determine whether it is selected according to the chip select signal, which can effectively ensure the communication quality and meet various communication requirements.

[0122] It should be noted that the chip select signal may be in different forms for different second devices. Some second devices may receive single-ended chip select signals, and the rest of the second devices may receive differential chip select signals; or, some second devices receive high-level valid chip select signals, and the rest of the second devices receive low-level valid chip select signals. The first device may configure the chip select signal corresponding to the second device according to the communication environment and the configuration information of the second device.

[0123] In a possible implementation, the level-differential chip select signal includes: a first chip select component signal and a second chip select component signal, wherein when the difference between the first chip select component signal and the second chip select component signal is within a preset range, it indicates whether the second device is selected.

[0124] In a specific implementation, the level-differential chip select signal includes a first chip select component signal and a second chip select component signal, and the difference between the first chip select component signal and the second chip select component signal indicates whether the second device is selected. For example, when the difference between the first chip select component signal and the second chip select component signal is higher than a first threshold, it indicates that the second device is selected; when the difference between the first chip select component signal and the second chip select component signal is lower than a second threshold, it indicates that the second device is not selected.

[0125] Exemplarily, the first chip selection component signal and the second chip selection component signal are equal in magnitude and opposite in polarity.

[0126] In this embodiment, the difference between the first chip select component signal and the second chip select component signal is used to characterize whether the second device is selected. When the chip select signal jitters due to common mode interference, the difference between the first chip select component signal and the second chip select component signal can offset the jitter, thereby accurately characterizing whether the second device is selected, which is beneficial to improving communication quality.

[0127] In a possible implementation, the method further includes:

[0128] According to the first data signal, a second data signal with a single-ended level or a differential level is returned to the first device.

[0129] In a specific implementation, when the second device is selected, a corresponding response action can be performed according to the received first data signal. Exemplarily, the first data signal can be used to indicate control of the second device, indicate reading the status of the second device, or indicate the second device to control a downstream device. When the first data signal indicates reading the status of the second device, the second device returns a second data signal to the first device. Among them, the second device can also flexibly configure the second data signal as a single-ended level or a differential level form according to the requirements of the communication quality, so that the first device can accurately obtain the data sent by the second device.

[0130] In this embodiment, by flexibly configuring the second data signal as a level single-ended or level differential form, data can be accurately sent to the first device, which is conducive to ensuring communication quality and meeting various communication requirements.

[0131] In a possible implementation manner, the second data signal with a level difference includes: a first data component signal and a second data component signal, and the first device is further configured to:

[0132] A data signal represented by a difference between the first data component signal and the second data component signal is received.

[0133] In a specific implementation, the level-differential second data signal includes a first data component signal and a second data component signal, and data is transmitted to the first device through the difference between the first data component signal and the second data component signal. For example, when the difference between the first chip select component signal and the second chip select component signal is higher than the third threshold, data "1" is transmitted; when the difference between the first chip select component signal and the second chip select component signal is lower than the fourth threshold, data "0" is transmitted.

[0134] Exemplarily, the first data component signal and the second data component signal are equal in magnitude and opposite in polarity.

[0135] In this embodiment, data is received based on the difference between the first data component signal and the second data component signal. When the second data signal is jittered due to common-mode interference, the difference between the first data component signal and the second data component signal can offset the jitter, so that the first device can accurately obtain the data sent by the second device, which is conducive to improving communication quality.

[0136] In a possible implementation manner, the clock signal and / or the first data signal is in a level differential form.

[0137] In a specific implementation, in order to ensure the communication quality, the clock signal and the first data signal can also be configured as a single-ended level or a differential level. For example, when the communication quality requirement is low, the second device receives a single-ended clock signal and a first data signal, and when the communication quality requirement is high, the second device receives a differential level clock signal and a first data signal.

[0138] In this embodiment, when the communication quality requirement is high, the clock signal and / or the first data signal may be configured in a level differential form, which can effectively ensure the communication quality.

[0139] In a possible implementation, the first device transmits the clock signal and the first data signal in the form of a data frame, and the data frame includes a data transmission phase;

[0140] The data transmission phase is used to transmit valid data, and the duration of the data transmission phase is less than or equal to the duration of the data frame.

[0141] In a specific implementation, the first device transmits a clock signal, a chip select signal and a first data signal in the form of a data frame. For example, the data frame may adopt the MSC communication protocol. The data frame includes a data transmission phase, the data transmission phase is used to transmit valid data to the second device, and the duration of the data transmission phase is less than or equal to the duration of the data frame.

[0142] Correspondingly, in the data transmission phase, at least one second device is selected. The first device transmits valid data to the selected second device in the data transmission phase.

[0143] In a possible implementation, the data frame further includes an idle phase;

[0144] In the idle phase, the first data signal is a continuous high level signal or a low level signal.

[0145] In a specific implementation, the data frame can be divided into a data transmission phase and an idle phase. In the idle phase, the first data signal does not transmit valid data and is a continuous high level or low level signal.

[0146] Correspondingly, in the idle phase, no second device is selected, and each second device does not receive the first data signal.

[0147] In a possible implementation, returning a second data signal with a single-ended level or a differential level to the first device includes:

[0148] Acquire second configuration information of the first device, where the second configuration information indicates a format of a second data signal received by the first device;

[0149] According to the second configuration information of the first device, a second data signal with a single-ended level or a differential level is returned to the first device.

[0150] In a specific implementation, the second device may obtain the second configuration information of the first device, and send a second data signal of single-ended level or differential level to the first device according to the form of the second data signal received by the first device.

[0151] In this embodiment, the second device may send a second data signal of single-ended level or differential level to the first device according to the form of the second data signal received by the first device, which is beneficial to improving the flexibility and reliability of communication.

[0152] In a possible implementation, returning a second data signal with a level difference to the first device includes:

[0153] A second enable signal is obtained, and according to the second enable signal, a second single-ended data signal is converted into a second differential data signal, and the second differential data signal is returned to the first device.

[0154] In a specific implementation, the second device may support converting a second data signal of a single-ended level into a second data signal of a differential level. The second device obtains a second enable signal, and the second enable signal is used to indicate whether the second device converts the second data signal of a single-ended level into a second data signal of a differential level. When the second enable signal is enabled, the second device converts the second data signal of a single-ended level into a second data signal of a differential level and sends it to the first device; when the second enable signal is not enabled, the second data signal of a single-ended level is sent to the first device.

[0155] In this embodiment, the second device may convert the single-ended second data signal into a differential second data signal and send the signal to the first device, thereby effectively improving the anti-interference capability of the chip select signal.

[0156] In a possible implementation, the method further includes:

[0157] A second amplitude signal is obtained, and the amplitude of the second data signal with a level difference is controlled according to the second amplitude signal.

[0158] In a specific implementation, when the second device converts the single-ended second data signal into a differential second data signal, the amplitude of the differential second data signal can be controlled according to the second amplitude signal.

[0159] In this embodiment, based on the second amplitude signal, the second device can control the amplitude of the second data signal with a level difference, which can better meet the communication requirements of the first device and improve the flexibility of communication.

[0160] The embodiment of the present application also provides a second device, including:

[0161] A first receiving module, used to receive a clock signal and a first data signal sent by a first device;

[0162] A second receiving module is used to receive a single-ended or differential chip select signal sent by the first device, where the chip select signal is used to indicate whether the second device is currently selected;

[0163] The third receiving module is used to receive the first data signal when the second device is selected by the chip selection signal sent by the first device.

[0164] It should be noted that the second device provided in the embodiment of the present application can be used to execute the data transmission method with the execution subject being the second device as described above. Its basic principles and specific implementation methods are as described above and will not be repeated here.

[0165] The embodiment of the present application also provides a data transmission method. Figure 5 Another data transmission method provided in an embodiment of the present application. The execution subject of the method is a data transmission system, and the data transmission system includes a first device and at least one second device. Figure 5 As shown, the method includes:

[0166] S501. A first device sends a clock signal and a first data signal to at least one second device;

[0167] S502, the first device sends a single-ended or differential chip select signal to at least one second device respectively, where the chip select signal is used to indicate whether the second device is selected;

[0168] S503: When the second device is selected by the chip selection signal sent by the first device, the second device receives the first data signal.

[0169] In a possible implementation, the method further includes:

[0170] The second device returns a second data signal of single-ended level or differential level to the first device according to the first data signal;

[0171] The method also includes:

[0172] When the second device is selected, the first device receives a second data signal with a single-ended level or a differential level returned by the second device.

[0173] In a possible implementation, the level-differential chip select signal includes: a first chip select component signal and a second chip select component signal, wherein when the difference between the first chip select component signal and the second chip select component signal is within a preset range, it indicates whether the second device is selected.

[0174] In a possible implementation manner, the first chip selection component signal and the second chip selection component signal are equal in magnitude and opposite in polarity.

[0175] In a possible implementation manner, the second data signal with a level difference includes: a first data component signal and a second data component signal, and the first device is further configured to:

[0176] A data signal represented by a difference between the first data component signal and the second data component signal is received.

[0177] In a possible implementation manner, the first data component signal and the second data component signal are equal in magnitude and opposite in polarity.

[0178] In a possible implementation manner, the clock signal and / or the first data signal is in a level differential form.

[0179] In a possible implementation, the method further includes:

[0180] The first device respectively obtains first configuration information of at least one second device, where the first configuration information indicates a form of a chip select signal received by the second device;

[0181] The first device sends a single-ended or differential chip select signal to at least one second device respectively, including:

[0182] The first device sends a single-ended level or a differential level chip select signal to the at least one second device respectively according to the first configuration information of the at least one second device.

[0183] In a possible implementation, the first device sends a level-differential chip select signal to at least one second device respectively, including:

[0184] The first device obtains a first enable signal, converts a single-ended chip select signal into a differential chip select signal according to the first enable signal, and sends the differential chip select signal to at least one second device respectively.

[0185] In a possible implementation, the method further includes:

[0186] The first device obtains a first amplitude signal, and controls the amplitude of a chip select signal of a level difference according to the first amplitude signal.

[0187] In a possible implementation manner, the second device returns a second data signal with a single-ended level or a differential level to the first device, including:

[0188] The second device acquires second configuration information of the first device, where the second configuration information indicates a format of a second data signal received by the first device;

[0189] According to the second configuration information of the first device, a second data signal with a single-ended level or a differential level is returned to the first device.

[0190] In a possible implementation manner, the second device returns a second data signal with a level difference to the first device, including:

[0191] A second enable signal is obtained, and according to the second enable signal, a second single-ended data signal is converted into a second differential data signal, and the second differential data signal is returned to the first device.

[0192] In a possible implementation, the method further includes:

[0193] A second amplitude signal is obtained, and the amplitude of the second data signal with a level difference is controlled according to the second amplitude signal.

[0194] In a possible implementation, the first device transmits the clock signal and the first data signal in the form of a data frame, and the data frame includes a data transmission phase;

[0195] The data transmission phase is used to transmit valid data, and the duration of the data transmission phase is less than or equal to the duration of the data frame.

[0196] In a possible implementation manner, at least one second device is selected during the data transmission phase.

[0197] In a possible implementation, the data frame further includes an idle phase;

[0198] In the idle phase, the first data signal is a continuous high level signal or a low level signal.

[0199] In a possible implementation, in the idle phase, no second device is selected.

[0200] It should be noted that the basic principle and specific implementation of the data transmission method can be referred to the data transmission method applied to the first device and the data transmission method applied to the second device as described above, and will not be repeated here.

[0201] The embodiment of the present application also provides a data transmission system, including a first device and a second device; wherein:

[0202] The first device sends a clock signal and a first data signal to the second device;

[0203] The first device sends a single-ended or differential chip select signal to the second device, where the chip select signal is used to indicate whether the second device is currently selected;

[0204] When the second device is selected by the chip selection signal sent by the first device, the second device receives the first data signal.

[0205] Since the data transmission system is the system corresponding to the first device and the second device in the embodiment of the present application, and the principle of solving the problem by the data transmission system is similar to that of the first device and the second device, the implementation of the data transmission system can refer to the implementation of the first device and the second device as described above, and the repeated parts will not be repeated.

[0206] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, they are used to implement the various data transmission methods described above.

[0207] An embodiment of the present application also provides a computer program product, including a computer program, which implements the various data transmission methods described above when executed by a processor.

[0208] The present application also provides a signal transmission circuit. Figure 6 , the signal sending circuit provided in the embodiment of the present application is described.

[0209] Figure 6 This is a schematic diagram of the structure of a signal transmission circuit provided in an embodiment of the present application. Figure 6 As shown, the signal sending circuit 60 may include: a sending module 610 and an output terminal 620; wherein,

[0210] The sending module 610 is used to receive an enable signal and a level single-ended signal to be sent; and output the level single-ended signal to be sent to the output terminal 620 according to different states of the enable signal, or generate a level differential signal to be sent based on the received level single-ended signal to be sent;

[0211] The output terminal 620 is connected to the sending module 610 and is used to send the single-ended or differential signal to be sent output by the sending module 610 to other devices.

[0212] In a specific implementation, the sending module may include a first mode and a second mode, and the enable signal may represent different modes by high and low levels. For example, when the enable signal is at a low level, the sending module 610 switches to the first mode, and directly outputs the single-ended signal to be sent to the output terminal 320; when the enable signal is at a high level, the sending module 610 switches to the second mode, and generates a differential signal to be sent based on the received single-ended signal to be sent.

[0213] The output terminal 620 is used to output the single-ended or differential level signal to be sent output by the sending module 610 to other devices, circuits or modules. The sending module 610 can be connected to the analog ground IOVSS and / or the digital ground VSS to receive the power supply voltage IOVCC and / or the digital logic voltage VD.

[0214] Exemplarily, the sending module 610 may be a sending module LVDS_IP_TX supporting an LVDS output function. When the sending module 610 supports the LVDS function, it may generate a low voltage differential signal to be sent based on a received single-ended signal to be sent.

[0215] Exemplarily, the signal transmission circuit may be used to output an MSC frame. In a possible implementation, the signal to be transmitted includes a chip selection signal, a clock signal or a data signal.

[0216] In this embodiment, the signal sending circuit can directly output the single-ended signal to be sent, or convert the single-ended signal to be sent into a differential signal to be sent, thereby effectively improving the anti-interference ability of the output signal and improving the communication quality. Based on different signal sending modes, the signal sending circuit can meet the needs of various communication scenarios, thereby improving the flexibility and reliability of the system.

[0217] In order to output a differential signal, the output terminal 620 includes at least two sub-output terminals. In a possible implementation, the output terminal 620 includes a first output terminal IO0 and a second output terminal IO1;

[0218] The first output terminal IO0 is used to send the first component signal of the single-ended signal to be sent or the differential signal to be sent output by the sending module 610 to other devices;

[0219] The second output terminal IO1 is used to send the second component signal of the single-ended signal to be sent or the differential signal to be sent output by the sending module 610 to other devices.

[0220] In a specific implementation, in the first mode, the number of level single-ended signals to be sent received by the sending module 610 is at least one. In a possible implementation, the sending module 610 is further configured to receive one or more level single-ended signals to be sent, and output one or more level single-ended signals to be sent to the output terminal 620.

[0221] Specifically, in the first mode, if the sending module 610 receives a level single-ended signal to be sent, it outputs the level single-ended signal to be sent to the first output terminal IO0 or the second output terminal IO1; accordingly, the first output terminal IO0 or the second output terminal IO1 sends the level single-ended signal to be sent to other devices. Exemplarily, the signal to be sent can be a chip select signal, and the signal sending circuit 60 can directly output a level single-ended chip select signal to other devices.

[0222] In the first mode, if the sending module 610 receives two level single-ended signals to be sent, it outputs the two level single-ended signals to be sent to the first output terminal IO0 and the second output terminal IO1 respectively; accordingly, the first output terminal IO0 and the second output terminal IO1 respectively send the level single-ended signals to be sent to other devices. Exemplarily, one of the two level single-ended signals to be sent can be a level single-ended chip select signal, and the signal sending circuit 60 can directly output a level single-ended chip select signal to other devices, and directly output another level single-ended signal to be sent to the device or another other device.

[0223] In this embodiment, the sending module supports direct output of multiple level single-ended signals to be sent, which can effectively improve the flexibility of the sending module.

[0224] In the second mode, the sending module 610 generates a level-differential signal to be sent based on the received level-single-ended signal to be sent, outputs the first component signal of the level-differential signal to be sent to the first output terminal IO0, and outputs the second component signal to the second output terminal IO1; accordingly, the first output terminal IO0 is used to send the first component signal of the level-differential signal to be sent to other devices; the second output terminal IO1 is used to send the second component signal of the level-differential signal to be sent to other devices. Exemplarily, the signal to be sent can be a chip select signal, and the signal sending circuit 60 can convert the level-single-ended chip select signal into a level-differential chip select signal and output it to other devices. In order to accurately output the signal, the first output terminal IO0 and the second output terminal IO1 can be set to output a component of a certain polarity of the level-differential signal to be sent.

[0225] In this embodiment, based on the first output end and the second output end, a single-ended signal or a differential signal can be output, so it can support the output of various types of signals. Different output methods can be selected based on different modes, effectively improving the reliability and flexibility of signal transmission.

[0226] In a possible implementation, the sending module 610 is further configured to receive a level-differential signal to be sent, and output the level-differential signal to be sent to an output end.

[0227] In a specific implementation, the signal to be sent received by the sending module 610 can also be in a level differential form. The sending module 610 is also used to directly output the first component signal of the level differential signal to be sent and the second component signal of the level differential signal to be sent to the first output terminal IO0 in the first mode.

[0228] In this embodiment, the sending module also supports direct output of level differential signals to be sent, and the signal sending circuit can flexibly select a variety of output signal modes, which can effectively improve the flexibility of communication.

[0229] Based on the above example, in a possible implementation, the sending module 610 has a first port 611 and a second port 612;

[0230] The sending module 610 is used to output the signal received by the first port 611 in the first mode; and to output the signal received by the second port 612 in the second mode.

[0231] Specifically, in the first mode, the sending module 610 is responsible for processing the signal received by the first port 611 based on the first mode, such as direct output. As an example, in the first mode, the sending module 610 directly outputs the signal received by the first port 611 through the first output terminal IO0 and / or the second output terminal IO1. In combination with the above, the direct output mentioned here also supports multiple types of signals. In the second mode, the sending module 610 is responsible for processing the signal received by the second port 612 based on the second mode, specifically generating a corresponding differential signal and outputting a differential signal according to the signal received by the second port 612. That is, in the first mode, the sending module 610 directly outputs the level single-ended or level differential signal to be sent received by the first port 611; in the second mode, the level single-ended signal to be sent received by the second port 612 is converted into a level differential signal to be sent and output. Through this example scheme, it is possible to flexibly select the mode in which the signal is transmitted, such as the single-ended signal mode or the differential signal mode, according to the signal transmission needs, to improve the reliability and flexibility of signal transmission. Furthermore, in this example, corresponding ports are set for different modes to facilitate signal differentiation and functional expansion of the sending module.

[0232] Taking the example that the sending module 610 supports the LVDS differential function, the signal received by the second port 612 is called LVDS_DATA_IN. In the second mode, the sending module 610 generates a low-voltage differential signal to be sent based on the signal LVDS_DATA_IN received by the second port 612. The first output terminal IO0 can be set to output the P-pole component LVDS_P of the low-voltage differential signal to be sent, and the second output terminal IO1 can be set to output the N-pole component LVDS_N of the low-voltage differential signal to be sent. Among them, the P-pole component LVDS_P and the N-pole component LVDS_N of the low-voltage differential signal to be sent are explained by taking the example of the sending module 610 performing low-voltage differential processing on the first signal, and do not constitute a limitation on the solution provided in the embodiment of the present application. In actual applications, the sending module 610 can also adopt other differential processing methods, which are not limited here.

[0233] In this embodiment, according to different mode selections, the sending module outputs the signal received by the corresponding port, effectively isolating the signal inputs of multiple modes, and improving the reliability and flexibility of signal transmission.

[0234] Considering supporting the processing of multiple types of signals, the signal received by the first port 611 may include a single-ended signal or a differential signal, so the first port 611 may include at least two input ports. In a possible implementation, the first port 611 includes a first input port 6111 and a second input port 6112;

[0235] The sending module 610 is used for, in the first mode, if one of the first input port 6111 and the second input port 6112 receives a signal, outputting the received signal to the first output port IO0 or the second output port IO1;

[0236] The sending module 610 is further configured to output the received signals to the output terminal 221 and the second output terminal IO1 respectively in the second mode if both the first input port 6111 and the second input port 6112 receive signals.

[0237] Specifically, the signal received by the first input port 6111 is referred to as IO_DATA_OUT0, and the signal received by the second input port 6112 is referred to as IO_DATA_OUT1. In the first mode, when the signal received by the first port 611 is a single-ended signal to be sent, one of the first input port 6111 and the second input port 6112 receives a signal, and the first input port 6111 receives the signal IO_DATA_OUT0 or the second input port 6112 receives the signal IO_DATA_OUT1. In this case, the sending module 610 outputs the signal IO_DATA_OUT0 received by the first input port 6111 or the signal IO_DATA_OUT1 received by the second input port 6112 to the first output terminal IO0 or the second output terminal IO1; when the signal received by the first port 611 is a differential-level signal to be sent or two single-ended signals to be sent, the first input port 6111 and the second input port 6112 both receive signals, and the first input port 2131 receives the signal IO_DATA_OUT0 and the second input port 2132 receives the signal IO_DATA_OUT1. In this case, the sending module 610 outputs the signals received by the first input port 6111 and the second input port 6112 to the first output terminal IO0 and the second output terminal IO1, respectively.

[0238] In this embodiment, through the first input port and the second input port, a single-ended signal to be sent or a differential signal to be sent can be received in the first mode, supporting the reception of multiple types of signals and adopting different signal output methods based on different signal formats, thereby effectively improving the reliability and flexibility of signal transmission.

[0239] In a possible implementation, the first output terminal IO0 corresponds to the first input port 6111, and the second output terminal IO1 corresponds to the second input port 6112;

[0240] The sending module 610 is used to output the signal received by the first input port 6111 to the first output port IO0 and output the signal received by the second input port 6112 to the second output port IO1 in the first mode.

[0241] Specifically, in the first mode, when the signal received by the first port 611 is a level single-ended signal to be sent, one of the first input port 6111 and the second input port 6112 receives a signal. In this case, when the first input port 6111 receives the signal IO_DATA_OUT0, the sending module 610 outputs the signal IO_DATA_OUT0 received by the first input port 6111 to the first output terminal IO0, and when the second input port 6112 receives the signal IO_DATA_OUT1, the sending module 610 outputs the signal IO_DATA_OUT2 received by the first input port 6111 to the first output terminal IO0. OUT1 is output to the second output terminal IO1; when the signal received by the first port 611 is a level differential signal to be sent or a two-level single-ended signal to be sent, the first input port 6111 and the second input port 6112 both receive signals, the first input port 6111 receives the signal IO_DATA_OUT0, and the second input port 6112 receives the signal IO_DATA_OUT1. In this case, the sending module 610 outputs the signals received by the first input port 6111 and the second input port 6112 to the first output terminal IO0 and the second output terminal IO1 respectively. In the first mode, the signal received by the input port is output to the corresponding output terminal, and the signals received by different input terminals are isolated, so that the signal can be accurately transmitted and the reliability of signal transmission is improved.

[0242] In a possible implementation, the signal sending circuit 60 further includes: a polarity adjustment module 630;

[0243] The polarity adjustment module 630 is connected to the sending module 610, and is used to adjust the polarity of the signal to be sent according to the polarity selection signal to obtain a single-ended signal to be sent, and transmit the single-ended signal to be sent to the sending module; the polarity selection signal in different states represents different polarities.

[0244] Taking the example that the transmitting module 610 supports the LVDS differential function, the polarity selection signal received by the polarity selection circuit 630 is called LVDS_INV_MUX_SEL. In this embodiment, the polarity selection circuit 630 adjusts the signal to be transmitted according to the polarity selection signal LVDS_INV_MUX_SEL, and transmits the obtained single-ended signal to be transmitted to the second port 612 of the transmitting module 610. In practical applications, the first selection signal LVDS_INV_MUX_SEL can be configured accordingly based on the receivable signal format currently configured by the signal receiving party, so as to ensure that the signal receiving party can receive a signal that can be correctly received and identified, and accurately transmit the signal.

[0245] Exemplarily, the polarity selection circuit 630 may include: an inverter 631 and a first multiplexer (MUX) 632;

[0246] The input end of the inverter 631 is used to receive a single-ended signal to be transmitted;

[0247] The first input end of the first multiplexer 632 is connected to the output end of the inverter 631, the second input end of the first multiplexer 632 is used to receive a single-ended signal to be sent, the output end of the first multiplexer 632 is connected to the sending module, and the control end of the first multiplexer 632 receives a polarity selection signal.

[0248] Specifically, the inverter 631 performs inversion processing on the level single-ended signal to be sent to obtain the same amplitude inverted (also known as the same amplitude, opposite polarity) signal corresponding to the level single-ended signal to be sent; the first multiplexer 632 receives the level single-ended signal to be sent and the same amplitude inverted signal corresponding to the level single-ended signal to be sent. According to the first selection signal, the level single-ended signal to be sent or the same amplitude inverted signal corresponding to the level single-ended signal to be sent is selected to be output to the second port 612, thereby realizing the polarity control of the signal to be sent.

[0249] The first selection signal can instruct the first multiplexer 632 to output the corresponding signal through high and low levels. For example, when the first selection signal is at a low level, the first multiplexer 632 outputs a single-ended signal to be sent; when the first selection signal is at a low level, the first multiplexer 632 outputs a same-amplitude inverted signal corresponding to the single-ended signal to be sent.

[0250] In this embodiment, through the first multiplexer and the inverter, the single-ended signal to be sent or the inverted signal of the single-ended signal to be sent can be input into the sending module according to the format requirements of the signal receiver, so as to control the polarity of the generated differential signal to be sent, thereby ensuring that the signal receiver can receive a signal that can be correctly received and identified, and accurately transmit the signal.

[0251] In a possible implementation, the signal sending circuit 60 may further include:

[0252] The second multiplexer 640 receives multiple signals and a selection signal and is connected to the sending module 610 , and is used to select a signal to be sent from the multiple signals according to the selection signal.

[0253] Specifically, the second multiplexer 640 may select a signal to be transmitted from the received multiple signals according to the selection signal, and output the signal to the transmitting module 610 .

[0254] The selection signal can be used to instruct the second multiplexer 640 to output a signal of a corresponding format as a signal to be sent based on the receivable signal format currently configured by the signal receiving party, so that the signal sending circuit sends a signal that the signal receiving party can recognize and process. For example, if the signal receiving party is configured to receive a single-ended signal, the selection signal can be used to instruct the second multiplexer 640 to output a single-ended signal to be sent; if the signal receiving party is configured to receive a differential signal, the second selection signal can be used to instruct the second multiplexer 640 to output a differential signal to be sent.

[0255] Exemplarily, the signal transmission circuit 60 may include a plurality of second multiplexers 640. The transmission module 610 may include a first port 611 and a second port 612, and accordingly, the signal transmission circuit 60 may include two second multiplexers 640, which respectively receive different selection signals, wherein an output end of one second multiplexer 640 is connected to the first port 611, and an output end of another second multiplexer 640 is connected to the second port 612; the transmission module 610 may include a first input port 6111, a second input port 6112, and a second port 612, and accordingly, the signal transmission circuit 60 may include three second multiplexers 640, which respectively receive different selection signals IO0_MUX_SEL, IO0_MUX_SEL, and LVDS_MUX_SEL, and are respectively connected to the first input port 6111, the second input port 6112, and the second port 612.

[0256] Among them, in the pass-through mode, if the signal to be transmitted is a differential signal, the selection signals IO0_MUX_SEL and IO1_MUX_SEL need to be correctly configured to ensure that the signals IO_DATA_OUT0 and IO_DATA_OUT1 selected by the two second multiplexers 640 corresponding to the first input port 6111 and the second input port 6112 are two components of the signal to be transmitted with a level difference. Further, if the first output terminal IO0 and the second output terminal IO1 fixedly output a differential signal component of a certain polarity, the selection signals IO0_MUX_SEL and IO1_MUX_SEL need to be correctly configured so that the signals IO_DATA_OUT0 and IO_DATA_OUT1 selected are two corresponding components of the signal to be transmitted with a differential signal level difference. For example, assuming that the first output terminal IO0 outputs the P-pole component of the differential signal and the second output terminal IO1 outputs the N-pole component of the differential signal, the signals IO_DATA_OUT0 and IO_DATA_OUT1 selected by the second multiplexer 640 based on the selection signals IO0_MUX_SEL and IO1_MUX_SEL are respectively the P-pole component and the N-pole component of the signal to be transmitted with a level difference.

[0257] In this embodiment, the second multiplexer accurately selects the signal to be transmitted from the plurality of signals according to the selection signal, so as to improve the accuracy and reliability of signal transmission.

[0258] In a possible implementation, the signal sending circuit 60 further includes: an input and output module 650;

[0259] The input-output module 650 is connected to the sending module 610 and the output terminal 620 and is used for buffering the signal.

[0260] In this embodiment, an input-output module is provided between the sending module and the signal terminal to be sent, so as to buffer the signal and protect the circuit, thereby effectively improving the reliability of signal transmission.

[0261] In a possible implementation, the sending module 610 is further configured to receive an amplitude control signal;

[0262] The sending module 610 is used to generate a level differential signal to be sent at a corresponding amplitude based on the received level single-ended signal to be sent and the amplitude control signal.

[0263] When the transmitting module 610 adopts the LVDS differential processing mode, the amplitude control signal is called LVDS_VSWG. The amplitude control signal LVDS_VSWG can be used to indicate the amplitude of the level differential signal to be transmitted generated by the transmitting module 610 based on the receivable signal format currently configured by the signal receiving party, so that the signal transmitting circuit 610 can send a signal that the signal receiving party can recognize and process.

[0264] In this embodiment, the amplitude of the differential signal is adjusted based on the amplitude control signal so that the receiver of the output signal can identify the processed signal, thereby improving the reliability of signal transmission.

[0265] It should be noted that the signal to be sent includes a chip selection signal, a clock signal or a data signal.

[0266] The present application also provides a signal receiving circuit. Figure 7 , the signal receiving circuit provided in the embodiment of the present application is described.

[0267] Figure 7 A schematic diagram of a signal receiving circuit provided in an embodiment of the present application. The signal receiving circuit 70 may include:

[0268] The receiving end 710 is used to receive a single-ended or differential level signal to be sent from other devices;

[0269] The processing module 720 is used to integrate the single-ended or differential-level signals to be sent into a single-ended level signal.

[0270] Exemplarily, the signal sending circuit may be Figure 6 The signal sending circuit 60 is shown.

[0271] Specifically, the signal to be sent received by the receiving end 710 can be in the form of a single-ended level or a differential level. When the sending module 610 adopts the LVDS differential processing method, the signal to be sent can be the single-ended level signal IO_DATA_OUT0 and / or IO_DATA_OUT1 to be sent sent by the signal sending circuit 60, or it can be the differential level signal IO_DATA_OUT0, IO_DATA_OUT1 or LVDS_P, LVDS_N to be sent sent by the signal sending circuit 60. The processing module 720 is used to integrate the single-ended level or differential level signal to be sent into a single-ended level signal. The module or device where the signal receiving circuit 70 is located can be further parsed and processed based on the single-ended level signal. In practical applications, the sending module 610 can also adopt other differential processing methods, which are not limited here.

[0272] The level differential signal to be sent may be a level differential signal to be sent received by a signal sending circuit, or a level differential signal to be sent generated by a signal sending circuit based on a level single-ended signal to be sent.

[0273] It should be noted that the signal to be sent refers to the signal sent by the signal sending circuit 60 to the signal receiving circuit 70, which may be a level single-ended or level differential signal to be sent output by the signal sending circuit, and may also include a part of the signal sent by the signal sending circuit. For example, when the signal to be sent is two level single-ended signals to be sent IO_DATA_OUT0 and IO_DATA_OUT1, the signal sending circuit 60 can output one of the level single-ended signals to be sent IO_DATA_OUT0 or IO_DATA_OUT1 to the signal receiving circuit 70, and send the other level single-ended signal to be sent to other signal receivers, so as to realize the multiplexing of the signal sending circuit 60.

[0274] Exemplarily, the signal to be sent includes a chip select signal, a clock signal or a data signal.

[0275] In a possible implementation, the receiving end 710 includes a first receiving end 711 and a second receiving end 712;

[0276] The first receiving end 711 is used to receive a first component signal of a single-ended signal to be sent or a differential signal to be sent sent by other devices;

[0277] The second receiving end 712 is used to receive a reference voltage or a second component signal of a signal to be transmitted with a level difference sent by other equipment.

[0278] In a specific implementation, when the signal receiving circuit 70 receives a single-ended signal to be sent sent by other devices, the first receiving end 711 receives the single-ended signal to be sent, and the second receiving end 712 receives a reference voltage; when the signal receiving circuit 70 receives a differential signal to be sent sent by other devices, the first receiving end 711 receives a first component signal of the differential signal to be sent sent by other devices, and the second receiving end 712 receives a second component signal of the differential signal to be sent sent by other devices.

[0279] Correspondingly, when the signal transmitting circuit 60 transmits a level single-ended signal to be transmitted to the signal receiving circuit 70, one of the first output terminal IO0 and the second output terminal IO1 of the signal transmitting circuit 60 and the first receiving terminal 711 of the signal receiving circuit 70, and the second receiving terminal 712 of the signal receiving circuit 70 receive the reference voltage; when the signal transmitting circuit 60 transmits a level differential signal to be transmitted to the signal receiving circuit 70, the first output terminal IO0 and the second output terminal IO1 of the signal transmitting circuit 60 are respectively connected to the first receiving terminal 711 and the second receiving terminal 712 of the signal receiving circuit 70. In practical applications, the output terminal 620 of the signal transmitting circuit 60 and the receiving terminal 710 of the signal receiving circuit 70 can be implemented in various forms, such as chip pins, device interfaces, etc. Therefore, during the initial configuration, the signal transmitting circuit 60 and the signal receiving circuit 70 to be received by the signal transmitting circuit 60 will be connected first, such as through a cable. The different connection methods of the signal transmitting circuit 60 and the signal receiving circuit 70 in the above examples can be implemented based on different interface cables.

[0280] In this embodiment, based on the first receiving end and the second receiving end, it can support receiving the signal to be sent with single-ended or differential level, and select different receiving modes based on different configurations, thereby effectively improving the reliability and flexibility of signal transmission.

[0281] In a possible implementation, the processing module 720 is specifically configured to:

[0282] The difference between the signals received by the first receiving end 721 and the signals received by the second receiving end 721 is calculated to obtain a level single-ended signal.

[0283] In combination with the foregoing, the signal sending circuit can support multiplexing, that is, it can transmit signals to multiple signal receiving circuits. Therefore, according to the current configuration of the signal receiving circuit, such as whether it supports receiving single-ended signals or differential signals, the signal sending circuit pre-connected to the signal receiving point circuit can be configured. As an example, assuming that the configuration representation of the signal receiving circuit A supports the reception of single-ended signal 1, and the signal receiving circuit A is connected to the signal sending circuit B, then the multiple output ends of the signal sending circuit B are configured. Specifically, the output end for outputting the single-ended signal 1 is set, then the other output ends will be set to transmit signals other than the single-ended signal 1. For example, assuming that multiplexing is supported and it is also connected to the signal receiving circuit C, the signal receiving circuit C is configured to receive the single-ended signal 2, then the other output ends of the signal sending circuit B can be set to output the single-ended signal 2. These settings can be achieved by controlling the selection signal of the second multiplexer.

[0284] Still taking the signal receiving circuit A and the signal transmitting circuit B as an example, assuming that the signal receiving circuit A is currently configured to support receiving the differential signal provided by the signal receiving circuit A, then in actual application, the signal terminals of the signal receiving circuit A and the signal transmitting circuit B can be connected correspondingly, and the two signal terminals of the signal transmitting circuit B can be set to output the two components of the differential signal respectively. Similarly, this setting can be achieved by controlling the selection signal of the second multiplexer.

[0285] The present application also provides a device, as shown below: Figure 8 , the device provided in the embodiment of the present application is described.

[0286] Figure 8 This is a schematic diagram of the structure of a device provided in an embodiment of the present application. Figure 8 As shown, the device may include: the signal sending circuit as described above and / or the signal receiving circuit as described above.

[0287] The device can send signals through the signal sending circuit, and can also receive signals through the signal receiving circuit.

[0288] In a possible implementation, multiple devices may communicate with each other, wherein the device may be a host or a slave. The host may send a signal to the slave to obtain data from the slave or control the operation of the slave, thereby controlling and managing the slave.

[0289] For ease of understanding, the following Fig. 9 , the data transmission system involved in the embodiment of the present application is described.

[0290] Fig. 9 This is a schematic diagram of the structure of the data transmission system provided in the embodiment of the present application. Fig. 9 As shown, the data transmission system includes a host and at least one slave; wherein the host and the slave are both the devices as described above, and the host and the slave include the signal sending circuit as described above and / or the signal receiving circuit as described above.

[0291] Among them, the host can be the main controller of the vehicle, including but not limited to a microcontroller unit (MCU), a field programmable gate array (FPGA), etc., and the slave can be a slave controller of the vehicle, for example, power components such as control chips of different models.

[0292] In a possible implementation, the host sends a single-ended or differential chip select signal to at least one slave through a signal sending circuit corresponding to each slave.

[0293] Specifically, the signal sending circuit that outputs the chip select signal in the host is called a chip select output module. The host is provided with at least one chip select output module for at least one slave. Each chip select output module outputs a corresponding single-ended or differential chip select signal to a slave.

[0294] In a possible implementation, the host sends a clock signal to at least one slave through the same signal sending circuit;

[0295] The host sends a first data signal to at least one slave through the same signal sending circuit.

[0296] Specifically, the signal sending circuit that outputs the clock signal in the host is called a clock output module, and the signal sending circuit that outputs the first data signal in the host is called a host data output module. The host can only set up one clock output module and one host data output module. The host outputs the same clock signal to at least one slave through the clock output module, and outputs the same first data signal to at least one slave through the host data output module.

[0297] like Fig. 9 As shown, when the host communicates with n slaves, the host is provided with n chip select output modules, each of which corresponds to a different slave. The host can send clock signals to the clock input modules of the n slaves through the clock output module; and send host data signals to the host data input modules of the n slaves through the host data output module; and send corresponding chip select signals to the chip select input modules of the n slaves through the n chip select output modules; and receive slave data signals sent by the slave data output modules of the n slaves through the n slave data input modules.

[0298] In this embodiment, the host can output the corresponding chip select signal to at least one slave through the chip select output modules corresponding to each slave, so as to accurately communicate with the slave; through the clock output module and the host data output module, the clock signal and the host data signal are output to at least one slave respectively, which can effectively reduce the system cost.

[0299] In one possible implementation, when the slave is selected by the chip select signal sent by the host, the slave sends a second data signal (also called a slave data signal) with a single-ended or differential level to a corresponding signal receiving circuit in the host through a signal sending circuit.

[0300] Specifically, the signal receiving circuit that receives the chip select signal in the slave is called a chip select input module, the signal receiving circuit that receives the clock signal in the slave is called a clock input module, the signal receiving circuit that receives the first data signal (also called the host data signal) in the slave is called a host data input module, the signal sending circuit that sends the second data signal in the slave is called a slave data output module, and the signal receiving circuit that receives the second data signal in the host is called a host data output module.

[0301] The slave receives the chip select signal sent by the host through the chip select input module, receives the clock signal sent by the host through the clock input module, and receives the first data signal sent by the host through the host data input module. When the chip select signal is valid, the slave makes corresponding response actions according to the clock signal and the host data signal. Among them, the response actions include but are not limited to:

[0302] If the host data signal indicates that the host requests to control the slave, the slave makes a corresponding response action, including but not limited to switching of the slave relay driver, modification of the uplink channel clock division coefficient, etc.;

[0303] If the host data signal indicates that the host requests to read the slave status, the slave returns the corresponding slave data signal (including but not limited to slave data or status, etc.) to the host through the uplink channel;

[0304] If the host data signal indicates that the host requests the slave to control the downstream device, the slave makes a corresponding response action to control the downstream device. For example, the slave may include a driver module of the downstream device, and the slave may drive the corresponding driver module in response to the host's request to drive the downstream device.

[0305] In this embodiment, based on the chip select input module, the clock input module, the host data input module and the slave data input module, the slave can receive the single-ended or differential-level chip select signal, clock signal and host data signal sent by the host, and send the single-ended or differential-level slave data signal to the host to realize communication between the host and the slave.

[0306] Fig.10 This is a schematic diagram of another data transmission system provided in an embodiment of the present application. Fig.10 As shown, the slave may further include a shift module;

[0307] The shift module is connected to the clock input module and the data output module, and is used to shift the data to be sent from the slave according to the clock signal to obtain the slave data signal.

[0308] Exemplarily, the shift module may include a frequency division unit and a shift unit; the frequency division unit is connected to the clock input module and is used to perform frequency division processing on the clock signal; the shift unit is connected to the frequency division unit and the data output module and is used to shift the data to be sent by the slave according to the clock signal after the frequency division processing to obtain the slave data signal.

[0309] It should be noted that Fig.10 Only an example of a data transmission system including one slave is used for description. In actual applications, the number of slaves can be freely selected and is not limited here.

[0310] In this embodiment, the slave data signal can be shifted by the shift module, so as to accurately output the slave data signal to the host.

[0311] In a possible implementation, the communication system further includes: a downstream device;

[0312] At least one slave is connected to a downstream device and is used to drive the downstream device according to a host data signal.

[0313] Specifically, when the received host data signal indicates that the host requests the slave to control the downstream device, the slave can make a corresponding response action to control the downstream device.

[0314] The downstream device can be a controllable device on the vehicle, such as a fuel injector, a solenoid valve, etc. The slave can control the downstream device according to the instructions of the host. For example, if the downstream device is a fuel injector, the fuel injector can spray fuel from a small nozzle at high speed to form a mist of fuel and air to achieve a more uniform and sufficient mixing, thereby improving combustion efficiency, reducing emissions and improving the power performance of the engine. The host can send a control signal to the slave according to the operating status and environmental conditions of the vehicle engine. The slave controls the injection amount of the injector according to the control signal, thereby accurately controlling the operation of the injector and achieving the best combustion effect.

[0315] Exemplarily, the downstream device may be an injector load, the slave makes a corresponding response action, and controlling the downstream device may include driving the slave injector driver to drive the injector load. Exemplarily, the downstream device may be an electromagnetic valve load, the slave makes a corresponding response action, and controlling the downstream device may include driving the slave electromagnetic valve driver to drive the electromagnetic valve load.

[0316] It is understandable that each slave may be connected to one or more downstream devices, or may not be connected to any downstream device, which is not limited herein.

[0317] In this embodiment, the slave drives the downstream device in response to the host data signal to achieve automatic control of the system.

[0318] It is understood that the step numbers in the various embodiments of the present application do not constitute a limitation on the execution order, and the execution order of the steps in each embodiment should be determined according to its internal logic. The various embodiments described in this application can be implemented separately or independently, and this application does not make specific limitations on this.

[0319] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0320] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A data transmission method, characterized in that: Applied to a first device, the method includes: sending a clock signal and a first data signal to at least one second device; A single-ended or differential chip select signal is sent to the at least one second device respectively, and the chip select signal is used to indicate whether the second device is selected; wherein, when the second device is selected by the chip select signal sent by the first device, the second device receives the first data signal.

2. The method according to claim 1, characterized in that The method further comprises: When the second device is selected, a second data signal with a single-ended level or a differential level returned by the second device is received.

3. The method according to claim 1, characterized in that The level-differential chip select signal includes: a first chip select component signal and a second chip select component signal, wherein when the difference between the first chip select component signal and the second chip select component signal is within a preset range, it indicates whether the second device is selected.

4. The method according to claim 3, characterized in that The first chip selection component signal and the second chip selection component signal are equal in magnitude and opposite in polarity.

5. The method according to claim 2, characterized in that: The second data signal with a level difference includes: a first data component signal and a second data component signal, and the first device is further used for: A data signal represented by a difference between the first data component signal and the second data component signal is received.

6. The method according to claim 5, characterized in that The first data component signal and the second data component signal are equal in magnitude and opposite in polarity.

7. The method according to any one of claims 1 to 6, characterized in that: The clock signal and / or the first data signal are in level differential form.

8. The method according to claim 1, characterized in that The sending a single-ended or differential chip select signal to the at least one second device respectively includes: respectively acquiring first configuration information of the at least one second device, where the first configuration information indicates a form of a chip select signal received by the second device; According to the first configuration information of the at least one second device, a single-ended level or a differential level chip select signal is correspondingly sent to the at least one second device.

9. The method according to claim 1, characterized in that: The sending the chip select signal with level difference to the at least one second device respectively includes: A first enable signal is obtained, and according to the first enable signal, a single-ended chip select signal is converted into a differential chip select signal, and the differential chip select signal is sent to the at least one second device respectively.

10. The method according to claim 9, characterized in that The method further comprises: A first amplitude signal is acquired, and the amplitude of the chip select signal of the level difference is controlled according to the first amplitude signal.

11. The method according to any one of claims 1 to 6, characterized in that: The first device transmits a clock signal and a first data signal in the form of a data frame, and the data frame includes a data transmission phase; The data transmission phase is used to transmit valid data, and the duration of the data transmission phase is less than or equal to the duration of the data frame.

12. The method according to claim 11, characterized in that During the data transmission phase, at least one of the second devices is selected.

13. The method according to claim 11, characterized in that The data frame also includes an idle phase; In the idle phase, the first data signal is a continuous high level signal or a low level signal.

14. The method according to claim 13, characterized in that In the idle phase, the second device is not selected.

15. A data transmission method, characterized in that: Applied to the second device, the method includes: Receiving a clock signal and a first data signal sent by a first device; receiving a single-ended or differential chip select signal sent by the first device, wherein the chip select signal is used to indicate whether the second device is selected; When the second device is selected by the chip selection signal sent by the first device, the first data signal is received.

16. The method according to claim 15, characterized in that The method further comprises: According to the first data signal, a second data signal with a single-ended level or a differential level is returned to the first device.

17. The method according to claim 15, characterized in that The level-differential chip select signal includes: a first chip select component signal and a second chip select component signal, wherein when the difference between the first chip select component signal and the second chip select component signal is within a preset range, it indicates whether the second device is selected.

18. The method according to claim 17, characterized in that The first chip selection component signal and the second chip selection component signal are equal in magnitude and opposite in polarity.

19. The method according to claim 16, characterized in that The second data signal with a level difference includes: a first data component signal and a second data component signal, and the first device is further used for: A data signal represented by a difference between the first data component signal and the second data component signal is received.

20. The method according to claim 19, characterized in that The first data component signal and the second data component signal are equal in magnitude and opposite in polarity.

21. The method according to any one of claims 15 to 20, characterized in that: The clock signal and / or the first data signal are in level differential form.

22. The method according to claim 16, characterized in that The step of returning a second data signal with a single-ended level or a differential level to the first device includes: Acquire second configuration information of the first device, where the second configuration information indicates a format of a second data signal received by the first device; According to the second configuration information of the first device, a second data signal with a single-ended level or a differential level is returned to the first device.

23. The method according to claim 16, characterized in that The step of returning a second data signal with a level difference to the first device comprises: A second enable signal is obtained, and according to the second enable signal, a second single-ended data signal is converted into a second differential data signal, and the second differential data signal is returned to the first device.

24. The method according to claim 23, characterized in that The method further comprises: A second amplitude signal is acquired, and the amplitude of the second data signal with the level difference is controlled according to the second amplitude signal.

25. The method according to any one of claims 15 to 20, characterized in that: The first device transmits a clock signal and a first data signal in the form of a data frame, and the data frame includes a data transmission phase; The data transmission phase is used to transmit valid data, and the duration of the data transmission phase is less than or equal to the duration of the data frame.

26. The method according to claim 25, characterized in that During the data transmission phase, at least one second device is selected.

27. The method according to claim 25, characterized in that The data frame also includes an idle phase; In the idle phase, the first data signal is a continuous high level signal or a low level signal.

28. The method according to claim 27, characterized in that In the idle phase, the second device is not selected.

29. A data transmission method, characterized in that: Applied to a data transmission system, the data transmission system includes a first device and at least one second device; the method includes: The first device sends a clock signal and a first data signal to the at least one second device; The first device sends a single-ended or differential chip select signal to the at least one second device respectively, wherein the chip select signal is used to indicate whether the second device is selected; When the second device is selected by the chip selection signal sent by the first device, it receives the first data signal.

30. The method according to claim 29, characterized in that The method further comprises: Returning a second data signal of single-ended level or differential level to the first device according to the first data signal; The method further comprises: When the second device is selected, the first device receives a second data signal with a single-ended level or a differential level returned by the second device.

31. The method according to claim 29, characterized in that The level-differential chip select signal includes: a first chip select component signal and a second chip select component signal, wherein when the difference between the first chip select component signal and the second chip select component signal is within a preset range, it indicates whether the second device is selected.

32. The method according to claim 31, characterized in that The first chip selection component signal and the second chip selection component signal are equal in magnitude and opposite in polarity.

33. The method according to claim 30, characterized in that The second data signal with a level difference includes: a first data component signal and a second data component signal, and the first device is further used for: A data signal represented by a difference between the first data component signal and the second data component signal is received.

34. The method according to claim 33, characterized in that The first data component signal and the second data component signal are equal in magnitude and opposite in polarity.

35. The method according to any one of claims 29 to 34, characterized in that: The clock signal and / or the first data signal are in level differential form.

36. The method according to claim 29, characterized in that The method further comprises: The first device respectively acquires first configuration information of the at least one second device, where the first configuration information indicates a form of a chip select signal received by the second device; The first device sends a single-ended level or a differential level chip select signal to the at least one second device respectively, including: The first device sends a single-ended level or a differential level chip select signal to the at least one second device respectively according to the first configuration information of the at least one second device.

37. The method according to claim 29, characterized in that The first device sends a chip select signal with a level difference to the at least one second device respectively, including: The first device obtains a first enable signal, converts a single-ended chip select signal into a differential chip select signal according to the first enable signal, and sends the differential chip select signal to the at least one second device respectively.

38. The method according to claim 36, characterized in that The method further comprises: The first device obtains a first amplitude signal, and controls the amplitude of the level-differential chip select signal according to the first amplitude signal.

39. The method according to claim 32, characterized in that The second device returns a second data signal of a single-ended level or a differential level to the first device, including: The second device acquires second configuration information of the first device, where the second configuration information indicates a format of a second data signal received by the first device; According to the second configuration information of the first device, a second data signal with a single-ended level or a differential level is returned to the first device.

40. The method according to claim 30, characterized in that The second device returns a second data signal with a level difference to the first device, including: A second enable signal is obtained, and according to the second enable signal, a second single-ended data signal is converted into a second differential data signal, and the second differential data signal is returned to the first device.

41. The method according to claim 40, characterized in that The method further comprises: A second amplitude signal is acquired, and the amplitude of the second data signal with the level difference is controlled according to the second amplitude signal.

42. The method according to any one of claims 29 to 34, characterized in that: The first device transmits a clock signal and a first data signal in the form of a data frame, and the data frame includes a data transmission phase; The data transmission phase is used to transmit valid data, and the duration of the data transmission phase is less than or equal to the duration of the data frame.

43. The method according to claim 42, characterized in that During the data transmission phase, at least one of the second devices is selected.

44. The method according to claim 42, characterized in that The data frame also includes an idle phase; In the idle phase, the first data signal is a continuous high level signal or a low level signal.

45. The method according to claim 44, characterized in that In the idle phase, the second device is not selected.

46. ​​A signal sending circuit, characterized in that: include: A sending module, used for receiving an enable signal and a single-ended signal to be sent; And, according to the enable signal being in different states, outputting the level single-ended signal to be sent to the output end, or generating a level differential signal to be sent based on the received level single-ended signal to be sent; The output end is connected to the sending module and is used to send the single-ended or differential level signal to be sent output by the sending module to other devices.

47. The signal transmission circuit according to claim 46, characterized in that: The output end includes a first output end and a second output end; The first output terminal is used to send the first component signal of the single-ended signal to be sent or the differential signal to be sent output by the sending module to other devices; The second output terminal is used to send the single-ended signal to be sent or the second component signal of the differential signal to be sent output by the sending module to other devices.

48. The signal transmission circuit according to claim 46, characterized in that: The sending module is further used to receive the level-differential signal to be sent, and output the level-differential signal to be sent to the output end.

49. The signal transmission circuit according to claim 46, characterized in that: The sending module is further used to receive a plurality of level single-ended signals to be sent, and output the plurality of level single-ended signals to be sent to the output end.

50. The signal transmission circuit according to claim 48, characterized in that: The device also includes: a polarity adjustment module; The polarity adjustment module is connected to the sending module, and is used to adjust the polarity of the signal to be sent according to the polarity selection signal to obtain a level single-ended signal to be sent, and transmit the level single-ended signal to be sent to the sending module; the polarity selection signal in different states represents different polarities.

51. The signal transmission circuit according to claim 50, characterized in that: The polarity selection circuit comprises: an inverter and a first multiplexer; The input end of the inverter is used to receive the single-ended signal to be sent; The first input end of the first multiplexer is connected to the output end of the inverter, the second input end of the first multiplexer is used to receive the single-ended signal to be sent, the output end of the first multiplexer is connected to the sending module, and the control end of the first multiplexer receives the polarity selection signal.

52. The signal transmission circuit according to claim 46, characterized in that: The signal sending circuit also includes: The second multiplexer receives a plurality of signals and a selection signal and is connected to the sending module, and is used for selecting a signal to be sent from the plurality of signals according to the selection signal.

53. The signal transmission circuit according to claim 46, characterized in that: The sending module is also used to receive the amplitude control signal; The sending module is used to generate a level differential signal to be sent at a corresponding amplitude based on the received level single-ended signal to be sent and the amplitude control signal.

54. The signal transmission circuit according to any one of claims 46 to 53, characterized in that: The signal to be sent is a chip selection signal, a clock signal or a data signal.

55. A signal receiving circuit, characterized in that: include: A receiving end is used to receive a single-ended or differential level signal to be sent from other devices; The processing module is used to integrate the level single-ended or level differential signals to be sent into a level single-ended signal.

56. The signal receiving circuit according to claim 55, characterized in that: The receiving end includes a first receiving end and a second receiving end; The first receiving end is used to receive the first component signal of the single-ended level signal to be sent or the differential level signal to be sent sent by other devices; The second receiving end is used to receive a reference voltage or a second component signal of the level-differential signal to be transmitted sent by other equipment.

57. The signal receiving circuit according to claim 56, characterized in that: The processing module is specifically used for: The signal received by the first receiving end and the signal received by the second receiving end are subtracted to obtain the level single-ended signal.

58. The signal receiving circuit according to any one of claims 55 to 57, characterized in that: The signal to be sent is a chip selection signal, a clock signal or a data signal.

59. A device, characterized in that include: A signal sending circuit as described in any one of claims 46-54 and / or a signal receiving circuit as described in any one of claims 55-58.

60. A data transmission system, characterized in that: It comprises a host and at least one slave; the host and the slave comprise: a signal sending circuit as described in any one of claims 46-54 and / or a signal receiving circuit as described in any one of claims 55-58.

61. The system according to claim 60, characterized in that The host sends a single-ended or differential chip select signal to the at least one slave through a signal sending circuit corresponding to each slave.

62. The system according to claim 60, characterized in that When the slave is selected by the chip selection signal sent by the host, the slave sends a second data signal with a single-ended level or a differential level to a corresponding signal receiving circuit in the host through a signal sending circuit.

63. The system according to any one of claims 60-62, characterized in that: The host sends a clock signal to the at least one slave through the same signal sending circuit; The host sends a first data signal to the at least one slave through the same signal sending circuit.

64. A first device, characterized in that: include: A first sending module, used for sending a clock signal and a first data signal to a second device; The second sending module is used to send a single-ended or differential chip select signal to the second device, and the chip select signal is used to indicate whether the second device is selected; wherein, when the second device is selected by the chip select signal sent by the first device, the second device receives the first data signal.

65. A second device, characterized in that: include: A first receiving module, used to receive a clock signal and a first data signal sent by a first device; A second receiving module, used for receiving a single-ended or differential chip select signal sent by the first device, wherein the chip select signal is used for indicating whether the second device is selected; The third receiving module is used to receive the first data signal when the second device is selected by the chip selection signal sent by the first device.

66. A data transmission system, characterized in that: It includes a first device and a second device; wherein, The first device sends a clock signal and a first data signal to the second device; The first device sends a single-ended or differential chip select signal to the second device, where the chip select signal is used to indicate whether the second device is selected; When the second device is selected by the chip selection signal sent by the first device, the first data signal is received.

67. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 45 when executed by a processor.

68. A computer program product, characterized in that The method comprises a computer program, which implements the method according to any one of claims 1 to 45 when executed by a processor.

Images