Image recognition system and method

Abstract

The invention provides an image recognition system and method, and relates to the technical field of image recognition, and the system comprises an image preprocessing module, a dynamic defogging enhancement module, a neural network acceleration module, an intelligent data scheduling module and an energy consumption management module. The image preprocessing module is used for preprocessing the to-be-recognized image; the dynamic defogging enhancement module is used for carrying out defogging enhancement processing on the preprocessed image; the neural network acceleration module is used for selecting a target neural network model suitable for the current image from the plurality of neural network models, and identifying the current image through the target neural network model; the target neural network model identifies the current image based on a parallel block convolution acceleration algorithm; the intelligent data scheduling module is used for dynamically managing data streams of other modules; and the energy consumption management module is used for performing energy consumption management on other modules. According to the invention, the recognition efficiency and adaptability of image recognition can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of image recognition, and in particular to an image recognition system and method. Background Art

[0002] Image recognition is an important branch of computer vision, which aims to automatically identify and classify objects, scenes, and features in images through computer algorithms. However, current image recognition technology has problems such as low recognition efficiency and low adaptability.

[0003] Based on this, how to improve the recognition efficiency and adaptability of image recognition has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] In view of this, in order to solve the above technical problems, the present invention provides an image recognition system and method.

[0005] The present invention adopts the following technical solution: In a first aspect, the present invention provides an image recognition system, comprising: an image preprocessing module, a dynamic defogging enhancement module, a neural network acceleration module, an intelligent data scheduling module and an energy consumption management module; The image preprocessing module is used to preprocess the image to be recognized and send the preprocessed image to the dynamic defogging enhancement module; The dynamic defogging enhancement module is used to determine whether the preprocessed image needs to be defogged and enhanced. When the preprocessed image needs to be defogged and enhanced, the defogged and enhanced image is processed and sent to the neural network acceleration module. When the preprocessed image does not need to be defogged and enhanced, the preprocessed image is sent to the neural network acceleration module. The neural network acceleration module is used to select a target neural network model suitable for the current image from multiple neural network models, and recognize the current image through the target neural network model; the target neural network model recognizes the current image based on a parallel block convolution acceleration algorithm; The intelligent data scheduling module is used to dynamically manage the data flows of other modules; The energy consumption management module is used to manage the energy consumption of other modules.

[0006] Optionally, the image preprocessing module is specifically used to perform at least one of the following preprocessing operations on the image to be recognized: Color space conversion, edge detection and enhancement, bilateral filtering, erosion and dilation, corner detection, image registration and infinite scaling.

[0007] Optionally, the dynamic defogging enhancement module performs defogging enhancement processing on the preprocessed image based on dark channel defogging technology and adaptive illumination adjustment strategy.

[0008] Optionally, the neural network acceleration module is also used to allocate computing resources to each layer according to the load of each layer of the target neural network model after selecting the target neural network model, so that the heavier the load, the more computing resources it obtains.

[0009] Optionally, the intelligent data scheduling module is specifically used for: For each first module in the image preprocessing module, the dynamic defogging enhancement module, the neural network acceleration module and the energy consumption management module, calculate the load weight of the first module according to the current data demand, computing power and average response time of the first module; Calculating a buffer size of the first module according to the load weight; Allocate a buffer for the first module according to the buffer size.

[0010] Optionally, the intelligent data scheduling module is further used to: After calculating the load weight of each of the first modules, calculating the resource allocation ratio of each of the first modules according to the load weight; Computing and storage resources are allocated to each of the first modules according to the resource allocation ratio.

[0011] Optionally, the intelligent data scheduling module is further used to: For any second module among the image preprocessing module, the dynamic defogging enhancement module, the neural network acceleration module and the energy consumption management module, predict the data demand of the second module at the next moment according to the historical data correlation coefficient of the second module and the input data stream at the previous moment; Based on the data demand at the next moment, the target data required by the second module at the next moment is loaded in advance, so as to complete the loading of the target data before the data demand for the target data is generated.

[0012] Optionally, the energy consumption management module is specifically used to: For any third module among the image preprocessing module, the dynamic defogging enhancement module, the neural network acceleration module and the intelligent data scheduling module, the energy consumption weight of the third module is calculated according to the instantaneous power consumption, load degree and execution time of the current task of the third module; According to the energy consumption weight and the current power state of the third module, determining whether it is necessary to switch the power state of the third module; the power state includes a high power state, a medium power state and a low power state; When the power state of the third module needs to be switched, the power state of the third module is switched.

[0013] Optionally, the energy consumption management module is further used to: Calculating the electric energy allocation ratio of the third module according to the priority of the current task of the third module and the energy consumption weight; According to the electric energy distribution ratio, electric energy is distributed to the third module.

[0014] In a second aspect, the present invention provides an image recognition method, which is applied to the image recognition system as described above, and the image recognition method comprises: After receiving the image to be identified, the image preprocessing module preprocesses the image to be identified and sends the preprocessed image to the dynamic defogging enhancement module; The dynamic defogging enhancement module determines whether the pre-processed image needs to be defogged and enhanced; When the preprocessed image needs to be defogged and enhanced, the dynamic defogging enhancement module performs defogging and enhancement processing on the preprocessed image, and sends the defogged and enhanced image to the neural network acceleration module; when the preprocessed image does not need to be defogged and enhanced, the dynamic defogging enhancement module sends the preprocessed image to the neural network acceleration module; The neural network acceleration module selects a target neural network model suitable for the current image from multiple neural network models, and recognizes the current image through the target neural network model; the target neural network model recognizes the current image based on a parallel block convolution acceleration algorithm.

[0015] The present invention adopts the above technical scheme, an image recognition system includes: an image preprocessing module, a dynamic defogging enhancement module, a neural network acceleration module, an intelligent data scheduling module and an energy consumption management module; the image preprocessing module is used to preprocess the image to be recognized, and send the preprocessed image to the dynamic defogging enhancement module; the dynamic defogging enhancement module is used to determine whether the preprocessed image needs to be defogged and enhanced. When the preprocessed image needs to be defogged and enhanced, the preprocessed image is defogged and enhanced, and the defogged and enhanced image is sent to the neural network acceleration module; when the preprocessed image does not need to be defogged and enhanced, the preprocessed image is sent to the neural network acceleration module; the neural network acceleration module is used to select a target neural network model suitable for the current image from multiple neural network models, and recognize the current image through the target neural network model; the target neural network model recognizes the current image based on a parallel block convolution acceleration algorithm; the intelligent data scheduling module is used to dynamically manage the data streams of other modules; the energy consumption management module is used to manage the energy consumption of other modules.

[0016] Based on this, the present invention sets multiple neural network models in advance, and then the neural network acceleration module can select a target neural network model suitable for the current image from the multiple neural network models, so that the present invention can quickly switch between different models according to task requirements. This flexible adaptability makes it more versatile and adaptable in multi-task processing and different application scenarios. In addition, the present invention recognizes the current image based on the parallel block convolution acceleration algorithm through the target neural network model, that is, the parallel computing unit in the system circuit processes multiple sub-block convolution operations at the same time, so that the present invention improves the efficiency of image recognition. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 is a structural schematic diagram of an image recognition system provided by an embodiment of the present invention; Figure 2 It is a flowchart of an image recognition method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0019] To make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be described in detail below. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other implementation methods obtained by ordinary technicians in this field without creative work belong to the scope of protection of the present invention.

[0020] Image recognition is an important branch of computer vision, which aims to automatically identify and classify objects, scenes and features in images through computer algorithms. Current image recognition technology usually uses a single neural network model. When it is needed for different tasks, the model parameters need to be manually adjusted to adapt to different task requirements, resulting in low recognition efficiency and low adaptability of existing image recognition technology.

[0021] Based on this, in order to improve the recognition efficiency and adaptability of image recognition, the present invention provides an image recognition system and method.

[0022] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings.

[0023] Figure 1 It is a structural diagram of an image recognition system provided by an embodiment of the present invention. It should be noted that the image recognition system can be applied to existing integrated circuits such as FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), GPU (Graphics Processing Unit) and ARM (Advanced RISC Machines). The embodiment of the present invention is described by taking the application to FPGA as an example, and those skilled in the art can easily think of the specific implementation method applied to other integrated circuits.

[0024] like Figure 1 As shown, the image recognition system includes: an image preprocessing module 11, a dynamic defogging enhancement module 12, a neural network acceleration module 13, an intelligent data scheduling module 14 and an energy consumption management module 15.

[0025] The image preprocessing module 11 is used to preprocess the image to be recognized and send the preprocessed image to the dynamic defogging enhancement module 12. The image preprocessing module 11 is described in detail below.

[0026] The image preprocessing module 11 integrates image preprocessing operations such as color space conversion, edge detection and enhancement, bilateral filtering and erosion and dilation, and further adds advanced preprocessing functions such as corner detection, image registration and infinite scaling, thereby significantly improving the usability of images in complex environments and providing enhanced image input for recognition.

[0027] In practical applications, the image preprocessing module 11 is specifically used to perform at least one preprocessing operation of color space conversion, edge detection and enhancement, bilateral filtering, erosion and expansion, corner detection, image registration and infinite scaling on the image to be identified according to actual conditions.

[0028] The image preprocessing module 11 can specifically preprocess the image to be recognized by parallel computing to improve its preprocessing efficiency. For example, when the image preprocessing module 11 performs color space conversion on its input image, by converting the image from RGB color space to YC b C r The color space realizes the separation of brightness information and chromaticity information, which makes it easier to focus on the structural details of the image in subsequent processing. Specifically, let the pixel matrix of the input image be ,in represents the spatial coordinates of the image, , , The pixel values ​​of the red, green, and blue channels are converted. This conversion process is completed by the parallel multiplication and addition circuit in the FPGA. The component calculation of each pixel is performed in an independent data stream, ensuring efficient conversion without increasing system latency.

[0029] After color space conversion, the image brightness channel It can be input into the multi-scale edge enhancement algorithm. Through multi-scale edge detection and enhancement, the image details at different scales are captured to ensure clear edge information in a complex background. Specifically, the system first calculates the horizontal and vertical gradient values ​​of the brightness channel through the Sobel operator. Assume that the image gradient is , whose horizontal and vertical components are and , obtained through the Sobel convolution kernel: ...... (1) ...... (2) in and is the Sobel kernel matrix. The gradient amplitude is calculated as follows: ...... (3) On this basis, the gradient image can be further smoothed by multi-scale Gaussian filtering to extract detail information of different scales. Assume that the Gaussian filtering parameters of different scales are , the gradient image of the corresponding scale is expressed as The final edge image is obtained by the weighted sum of the gradient images at each scale: ...... (4) in, are weight coefficients at different scales. This multi-scale mechanism allows the system to enhance edge information at different levels of detail to ensure that the outlines of key objects are clearly discernible even against complex backgrounds. This multi-scale edge enhancement process is accomplished through parallel convolution and addition circuits in the FPGA, enabling multi-scale edge enhancement to be completed efficiently, significantly improving the system's real-time processing capabilities.

[0030] After edge enhancement, the image preprocessing module can use the adaptive bilateral denoising algorithm to denoise the image. This algorithm combines the weights of spatial distance and color similarity to remove noise while retaining edge information. Specifically, let the output of bilateral filtering be , then the calculation formula is: ...... (5) in, is the spatial distance weight function, is the color similarity weight function, Pixel The neighborhood range of is the normalization coefficient, which is used to ensure that the sum of weights is 1. The algorithm is implemented in FPGA through parallel accumulation circuits, so that the denoising process effectively suppresses noise without losing image details, ensuring the clarity of the final image output.

[0031] The dynamic defogging enhancement module 12 is used to determine whether the preprocessed image needs to be defogged and enhanced. When the preprocessed image needs to be defogged and enhanced, the defogging and enhanced processing is performed on the preprocessed image, and the defogged and enhanced image is sent to the neural network acceleration module 13. When the preprocessed image does not need to be defogged and enhanced, the preprocessed image is sent to the neural network acceleration module 13. The dynamic defogging and enhancement module 12 is described in detail below.

[0032] The core algorithm of the dynamic defogging enhancement module 12 is the adaptive dark channel defogging enhancement algorithm, which combines the dark channel defogging technology and the adaptive illumination adjustment strategy to effectively improve the image clarity in low light and high haze environments. In addition, the dynamic defogging enhancement module 12 can also use parallel computing to perform defogging enhancement processing to improve the defogging enhancement processing efficiency and realize real-time dynamic defogging processing.

[0033] Specifically, the algorithm preliminarily estimates the impact of haze by calculating the dark channel image of the image. Suppose the pixel value of the input image is ,in Represents the spatial coordinates of the image, and the values ​​of the three RGB channels are . Dark channel image Defined as: ...... (6) in, Indicates The size of the neighborhood is adaptively adjusted according to the image resolution and haze thickness. On the FPGA, the minimum value search of the dark channel is implemented through parallel computing, and the minimum value calculation of each channel is completed quickly through the comparison of pixels in the neighborhood, ensuring the real-time defogging.

[0034] Next, the transmittance is estimated using the dark channel image , that is, the proportion of effective information retained in the dehazed image. The transmittance estimation formula is: ...... (7) in, It is an adjustment coefficient used to control the intensity of transmittance to make the defogging effect more natural. This coefficient is adaptively adjusted according to the ambient lighting conditions to adapt to changes in different lighting and haze concentrations.

[0035] Based on the above transmittance, the system estimates the global atmospheric light component A to simulate the light scattering effect in the natural environment. Atmospheric light A is one of the brightest pixel values ​​in the input image. The value is estimated by selecting some pixels with the highest dark channel value in the image and taking their color mean. This process is also completed in parallel on the FPGA to ensure efficient calculation.

[0036] Then, the dehazed image is restored by the following formula: ...... (8) in, is a small constant to prevent division by zero. The restoration process is implemented on FPGA through multiplication and division circuits, which realizes the output of real-time dehazed images and ensures the natural transition and visual effect of images.

[0037] In order to enhance the adaptability of the system in dynamic environments, the algorithm further adds a light adaptive adjustment module. Specifically, this module dynamically adjusts the average brightness of the input image by real-time monitoring. and The size of the system increases the defogging effect to maintain high clarity under different lighting conditions. and the size of the neighborhood window to obtain a stronger defogging effect; in a high-brightness environment, these parameters are appropriately reduced to avoid loss of details caused by excessive defogging. This adaptive adjustment strategy is implemented in the FPGA through control logic, and the algorithm parameters are updated in real time to ensure the stability of the system in complex environments.

[0038] The neural network acceleration module 13 is used to select a target neural network model suitable for the current image from multiple neural network models, and recognize the current image through the target neural network model; the target neural network model recognizes the current image based on a parallel block convolution acceleration algorithm. The neural network acceleration module 13 is described in detail below.

[0039] The neural network acceleration module 13 can support a variety of neural network models such as convolutional neural networks and multi-layer perceptrons through deep integration of FPGA and neural network accelerator. The core of this module is the adaptive model selection and dynamic acceleration algorithm. By selecting the optimal neural network model and adjusting the allocation of computing resources in real time, it ensures that the system achieves a balance between recognition speed and accuracy in a complex environment and provides support for subsequent recognition. In addition, the neural network acceleration module 13 can also use parallel computing to improve its computing efficiency.

[0040] Specifically, the system loads multiple neural network models with different depths and structures, denoted as , each model In actual use, the neural network acceleration module 13 first selects the neural network model corresponding to the target scene from multiple neural network models according to the target scene selected by the user, and then calculates the selection weights of each neural network model corresponding to the target scene by analyzing the feature distribution of the current input image. : ...... (9) in, Representation Model The computational complexity of It is a tuning parameter to control the complexity of the model. It reflects the applicability of the model under the current task conditions, and automatically selects the optimal model (i.e., the target neural network model) from the neural network models corresponding to the target scenario according to the selection weights of the neural network models corresponding to the target scenario. In the FPGA architecture, this selection process is completed by parallel calculation of weights, and hardware resources are dynamically allocated to ensure the efficient operation of the optimal model.

[0041] Furthermore, an adaptive dynamic acceleration strategy is used to allocate an appropriate amount of computing resources to the selected model to optimize the processing speed and power consumption during the recognition process. Specifically, for the convolution calculation of each layer of the network, the present invention proposes a parallel block convolution acceleration algorithm. Assume that the input feature map of the current convolution layer is , the convolution kernel weight is ,in , and are the height, width and number of channels of the input feature map respectively, is the convolution kernel size, is the number of output channels. The algorithm takes the input feature map Divided into multiple sub-blocks , each sub-block performs convolution calculation independently, the formula is as follows: ...... (10) in, For sub-block The parallel computing unit in the FPGA processes multiple sub-block convolution operations simultaneously, which accelerates the convolution calculation of each layer. In addition, in order to further improve the computing efficiency, the on-chip memory can be used on the FPGA to store the convolution kernel weights to avoid frequent memory access, thereby reducing the delay of data transmission.

[0042] The neural network acceleration module 13 is also used to allocate computing resources to each layer according to the load of each layer of the target neural network model after selecting the target neural network model, so that the heavier the load, the more computing resources it obtains. Specifically, the neural network acceleration module 13 also adds an adaptive computing load distribution algorithm in the neural network reasoning process, which is used to dynamically schedule the hardware resources of the FPGA between different computing tasks to further optimize computing performance. The algorithm dynamically adjusts the resource allocation ratio of each computing task by monitoring the load of each layer of convolution and pooling operations. Assume that the load weight of the current task is , then the resource allocation ratio of each layer is: ...... (11) in, is the number of layers of the neural network, Represents the computational complexity of the lth layer. FPGA can allocate more resources to the layers with higher computational load and reduce resource allocation to the layers with lower load, thus balancing the overall computational speed and energy consumption. The algorithm is implemented in FPGA through a hardware scheduler, and the computational resource allocation of each layer can be adaptively optimized.

[0043] In summary, the neural network acceleration module 13 combines model selection, parallel acceleration and dynamic resource scheduling to achieve high efficiency and low power consumption of deep learning reasoning on FPGA. By selecting the adaptation model in real time and dynamically adjusting the computing resources, the neural network acceleration module can still maintain high-speed operation under the conditions of high system load and complex computing tasks, providing high-precision and low-latency recognition results for image recognition tasks in complex environments. The parallel structure of FPGA is organically combined with the algorithm design, so that the module not only has high computing performance, but also can be flexibly adjusted according to environmental requirements, greatly enhancing the adaptability and stability of the image recognition system.

[0044] The intelligent data scheduling module 14 is used to dynamically manage the data flow of other modules, and realizes efficient scheduling of data caching and transmission through a DDR (Double Data Rate SDRAM) multi-way arbitration controller to ensure that the data throughput of each module is optimized, and at the same time balance the data flow under high load conditions to prevent system bottlenecks.

[0045] The intelligent data scheduling module 14 can be specifically used for: (1) For each first module in the image preprocessing module 11, the dynamic defogging enhancement module 12, the neural network acceleration module 13 and the energy consumption management module 15, the load weight of the first module is calculated according to the current data demand, computing power and average response time of the first module.

[0046] (2) Calculate the buffer size of the first module according to the load weight; (3) Allocate a buffer for the first module according to the buffer size.

[0047] The intelligent data scheduling module 14 can also be used for: After the load weight of each first module is calculated, the resource allocation ratio of each first module is calculated according to the load weight; and computing and storage resources are allocated to each first module according to the resource allocation ratio.

[0048] The intelligent data scheduling module 14 can also be used for: (1) For any second module among the image preprocessing module 11, the dynamic defogging enhancement module 12, the neural network acceleration module 13 and the energy consumption management module 15, the data demand of the second module at the next moment is predicted according to the historical data correlation coefficient of the second module and the input data stream at the previous moment.

[0049] (2) Based on the data demand at the next moment, the target data required by the second module at the next moment is loaded in advance, so as to complete the loading of the target data before the data demand for the target data is generated.

[0050] The intelligent data scheduling module 14 is described in detail below.

[0051] First, the algorithm dynamically adjusts the priority of data distribution by calculating the load weight of each module. Suppose the load weight of each module is ,but Adaptively adjust based on the module's real-time data requirements, computing power, and response speed: ...... (12) in, For modules Current data needs, is the computing power of the module, is the average response time of the module. It reflects the priority of each module’s demand for data resources under the current task conditions. The scheduling control unit in the FPGA calculates the value to ensure that data resources are allocated preferentially among high-load modules.

[0052] In the data transmission process, the DDR multi-channel arbitration controller plays a key role. Its priority-based dynamic buffer management strategy can avoid data transmission bottlenecks. Specifically, the module allocates a buffer for each data channel, and the size of the buffer is adjusted according to the load weight of each module. Assume that the current buffer size is ,but: ...... (13) in, is the base buffer size, is the adjustment coefficient. This adaptive buffer strategy, combined with the scheduling function of the DDR multi-channel arbitration controller, ensures the stability of data flow under sudden high load conditions, effectively avoids transmission blockage, and ensures efficient data flow. At the same time, the FPGA manages the buffers of multiple data channels in parallel, and realizes fast data writing and reading through on-chip cache, ensuring that the system can still maintain stable transmission efficiency under high data flow.

[0053] In addition, the algorithm introduces a real-time data prefetching algorithm to further improve the efficiency of data scheduling. By analyzing the data flow characteristics of the previous moment, the next data demand of each module is predicted, and the required data is loaded from the memory in advance. Assume that the input data flow of the previous moment is , then the predicted data demand at the next moment is , the formula is: ...... (14) in, It is the historical data correlation coefficient, which is used to control the amount of data pre-fetched. Through the high-speed data channel of FPGA, the system can complete data loading before data demand occurs, so as to reduce access delay and improve processing speed. The prediction mechanism effectively reduces the data waiting time between modules, ensuring that the system can still respond quickly when the task volume changes.

[0054] In addition, the real-time data prefetching mechanism of the present invention can be replaced by a cache optimization-based strategy. Specifically, the key data is preloaded in the data stream through the cache controller to reduce the waiting time for data transmission. For example, a hierarchical cache strategy is adopted to load data into caches of different levels (each level corresponds to a layer of the target neural network model, and the cache of any level will be placed in the corresponding neural network model layer) to achieve a similar prefetching effect.

[0055] In addition, to further optimize data transmission, the intelligent data scheduling module adopts resource allocation and arbitration algorithm to adjust the resource allocation ratio inside the FPGA so that the high-load module can obtain more computing and storage resource support. Assume that the current resource allocation ratio is ,but By load weight The calculation results are: ...... (15) in, N is the total number of modules in the system. When the DDR multi-way arbitration controller is executed, it combines the priority arbitration mechanism to ensure that the high-load modules obtain the required resources, avoid resource waste, realize dynamic optimization and allocation of resources, and ensure the smooth operation of the system under high load conditions. This process is implemented in the FPGA resource scheduler, and the resource usage of each module is optimized and dynamically allocated, ensuring the smooth operation of the system under high load.

[0056] The energy consumption management module 15 is used to manage the energy consumption of other modules.

[0057] The energy consumption management module 15 can be specifically used for: (1) For any third module among the image preprocessing module 11, the dynamic defogging enhancement module 12, the neural network acceleration module 13 and the intelligent data scheduling module 14, the energy consumption weight of the third module is calculated according to the instantaneous power consumption, load level and execution time of the current task of the third module.

[0058] (2) According to the energy consumption weight and the current power state of the third module, determine whether it is necessary to switch the power state of the third module; the power state includes a high power state, a medium power state and a low power state.

[0059] (3) When the power state of the third module needs to be switched, the power state of the third module is switched.

[0060] The energy consumption management module 15 can also be used for: The electric energy allocation ratio of the third module is calculated according to the priority and energy consumption weight of the current task of the third module; and electric energy is allocated to the third module according to the electric energy allocation ratio.

[0061] The above scheme is described in detail below.

[0062] The energy consumption management module 15 adjusts the power state of each module by monitoring the power consumption requirements and task execution of each module. First, the energy consumption management module 15 monitors the real-time load status of each module and calculates its energy consumption weight according to the workload and current power consumption of each module. : ...... (16) in, Representation Module The instantaneous power consumption, For modules The load level, For modules About the execution time of the current task. Energy consumption weight It reflects the energy consumption priority of each module under the current task conditions, providing a basis for subsequent energy consumption allocation and power management. The monitoring unit in the FPGA calculates the energy consumption of each module in real time. , ensuring that energy resources are allocated to key modules first.

[0063] In terms of power consumption control, the energy consumption management module 15 adopts the power state adjustment mechanism proposed by the present invention to dynamically reduce the energy consumption of the system by quickly switching the power state. This mechanism divides the power state of the FPGA into three levels: high power state, medium power state and low power state. and the overall energy consumption requirements. Assume that the switching threshold of the power state is , then the power state of the system Switching occurs when the following conditions are met: ...... (17) in, and The FPGA power management unit calculates the power state of each module through this formula and triggers state switching when the conditions are met, thus reducing the overall power consumption of the system.

[0064] In addition, the energy management module 15 further reduces the total energy consumption of the system by recycling unused power. Based on the FPGA power distribution and reuse mechanism, the energy management module 15 monitors the power consumption fluctuations of each module when it is low-load or in standby mode, and recycles the unused power to support the high-load tasks of other modules. , then the energy recovery ratio for: ...... (18) in, is the total power consumption of the system. The power distributor in the FPGA uses this recovery ratio to redistribute the recovered power to the high-load modules, thereby achieving efficient use and dynamic balance of power, so that the system can maintain stable power consumption when the load fluctuates.

[0065] In addition, the energy consumption management module 15 also combines a power management mechanism based on task priority to ensure that high-priority tasks obtain stable power consumption support. Assume that the priority of the task is , then the power distribution ratio of each module According to the priority of its current task and energy consumption weight Dynamic adjustment. Power distribution ratio for: ...... (19) in, N The power management mechanism dynamically adjusts the power allocation ratio to ensure that high-priority tasks can be executed efficiently under limited power consumption, thereby meeting the power requirements of key tasks while ensuring the overall low power consumption of the system.

[0066] It can be seen that the energy management module improves the adaptability and energy efficiency of the system under different load conditions through refined power management and energy recovery strategies, providing reliable support for the application of image recognition systems in embedded and edge computing scenarios.

[0067] To summarize, the embodiment of the present invention adopts the above-mentioned technical solution, and the energy consumption management module automatically adjusts the power state of each module according to the energy consumption weight of each module, so as to reduce or even avoid energy waste while meeting the energy consumption requirements of the module; the energy consumption management module also reallocates unused electrical energy to other modules through an energy recovery mechanism, further avoiding energy waste; the energy consumption management module also allocates electrical energy to each module according to the priority of the current task and its energy consumption weight, thereby meeting the power requirements of key tasks while ensuring the overall low power consumption of the system.

[0068] In addition, the intelligent data scheduling module determines the buffer size and resource allocation ratio of each module according to the load weight of each module, so that in a high-load scenario, the system can dynamically allocate data transmission resources according to the load weight of each module, avoid data congestion, and improve the stability of image recognition speed; the intelligent data scheduling module also uses a real-time data prefetching mechanism to predict the data requirements of each module according to the task load and load data in advance, further reducing data waiting time, so that the system can still achieve fast response and data fluency even in a high-concurrency task environment. This advantage significantly improves the system's performance in real-time applications.

[0069] The multi-scale edge enhancement algorithm and adaptive bilateral denoising algorithm in the image preprocessing module enable the system to dynamically adjust the edge and denoising effects for different environments during image preprocessing. For example, in complex backgrounds, multi-scale edge detection can enhance the clarity of key details, while the adaptive bilateral denoising algorithm retains important image edge information while removing noise. This adaptability of image preprocessing ensures that the system can maintain high recognition accuracy in low light, uneven lighting or complex background environments, improving recognition reliability and environmental adaptability.

[0070] The neural network acceleration module can automatically select a target neural network model suitable for the current task from multiple neural network models, so that the system can quickly switch between different models according to task requirements, so that the system can show higher versatility and adaptability in multi-task processing and different application scenarios; the neural network acceleration module also adopts a parallel block convolution acceleration algorithm to improve the recognition speed of the target neural network model; the neural network acceleration module also allocates computing resources to each layer according to the load of each layer of the target neural network model, so that the heavier the load, the more computing resources it gets, thereby improving the balance of computing resource allocation.

[0071] Based on a general inventive concept, the present invention further provides an image recognition method, which is implemented by the above-mentioned image recognition system. Figure 2 FIG. 1 is a flow chart of an image recognition method provided by an embodiment of the present invention. Figure 2 As shown, this process includes: Step 201: After receiving the image to be recognized, the image preprocessing module preprocesses the image to be recognized and sends the preprocessed image to the dynamic defogging enhancement module.

[0072] Step 202: The dynamic defogging enhancement module determines whether the preprocessed image needs to be defogged and enhanced; when the preprocessed image needs to be defogged and enhanced, step 203 is executed, and when the preprocessed image does not need to be defogged and enhanced, step 204 is executed.

[0073] Step 203: The dynamic defogging enhancement module performs defogging enhancement processing on the pre-processed image, and sends the defogging enhancement processed image to the neural network acceleration module.

[0074] Step 204: The dynamic defogging enhancement module sends the preprocessed image to the neural network acceleration module. That is, when the preprocessed image does not need to be defogged, the dynamic defogging enhancement module directly sends the received image to the neural network acceleration module.

[0075] Step 205: The neural network acceleration module selects a target neural network model suitable for the current image from multiple neural network models, and recognizes the current image through the target neural network model; the target neural network model recognizes the current image based on a parallel block convolution acceleration algorithm.

[0076] Optionally, the image recognition method of the embodiment of the present invention further includes: Before the neural network acceleration module recognizes the current image through the target neural network model, the intelligent data scheduling module loads the required data of the target neural network model when recognizing the current image in advance through the real-time data pre-fetching algorithm, and sends the required data to the target neural network model, so that the target neural network model recognizes the current image according to the required data, thereby improving the image recognition efficiency.

[0077] It should be noted that the present image recognition method and the aforementioned image recognition system are based on a general inventive concept and have the same or corresponding implementation process. Therefore, the specific scheme of the present image recognition method can be found in the aforementioned embodiments and will not be repeated here.

[0078] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0079] It should be noted that, in the description of the present invention, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" refers to at least two.

[0080] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present invention belong.

[0081] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0082] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0083] In addition, each functional unit in each embodiment of the present invention may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0084] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0085] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0086] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. An image recognition system, characterized in that: include: Image preprocessing module, dynamic defogging enhancement module, neural network acceleration module, intelligent data scheduling module and energy consumption management module; The image preprocessing module is used to preprocess the image to be recognized and send the preprocessed image to the dynamic defogging enhancement module; The dynamic defogging enhancement module is used to determine whether the preprocessed image needs to be defogged and enhanced. When the preprocessed image needs to be defogged and enhanced, the defogged and enhanced image is processed and sent to the neural network acceleration module. When the preprocessed image does not need to be defogged and enhanced, the preprocessed image is sent to the neural network acceleration module. The neural network acceleration module is used to select a target neural network model suitable for the current image from multiple neural network models, and recognize the current image through the target neural network model; the target neural network model recognizes the current image based on a parallel block convolution acceleration algorithm; The intelligent data scheduling module is used to dynamically manage the data flows of other modules; The energy consumption management module is used to manage the energy consumption of other modules.

2. The image recognition system according to claim 1, characterized in that: The image preprocessing module is specifically used to perform at least one of the following preprocessing operations on the image to be recognized: Color space conversion, edge detection and enhancement, bilateral filtering, erosion and dilation, corner detection, image registration and infinite scaling.

3. The image recognition system according to claim 1, characterized in that: The dynamic defogging enhancement module performs defogging enhancement processing on the pre-processed image based on dark channel defogging technology and adaptive illumination adjustment strategy.

4. The image recognition system according to claim 1, characterized in that: The neural network acceleration module is also used to allocate computing resources to each layer according to the load of each layer of the target neural network model after selecting the target neural network model, so that the heavier the load, the more computing resources it obtains.

5. The image recognition system according to claim 1, characterized in that: The intelligent data scheduling module is specifically used for: For each first module in the image preprocessing module, the dynamic defogging enhancement module, the neural network acceleration module and the energy consumption management module, calculate the load weight of the first module according to the current data demand, computing power and average response time of the first module; Calculating a buffer size of the first module according to the load weight; Allocate a buffer for the first module according to the buffer size.

6. The image recognition system according to claim 5, characterized in that: The intelligent data scheduling module is also specifically used for: After calculating the load weight of each of the first modules, calculating the resource allocation ratio of each of the first modules according to the load weight; Computing and storage resources are allocated to each of the first modules according to the resource allocation ratio.

7. The image recognition system according to any one of claims 1 to 6, characterized in that: The intelligent data scheduling module is also specifically used for: For any second module among the image preprocessing module, the dynamic defogging enhancement module, the neural network acceleration module and the energy consumption management module, predict the data demand of the second module at the next moment according to the historical data correlation coefficient of the second module and the input data stream at the previous moment; Based on the data demand at the next moment, the target data required by the second module at the next moment is loaded in advance, so as to complete the loading of the target data before the data demand for the target data is generated.

8. The image recognition system according to claim 1, characterized in that: The energy consumption management module is specifically used for: For any third module among the image preprocessing module, the dynamic defogging enhancement module, the neural network acceleration module and the intelligent data scheduling module, the energy consumption weight of the third module is calculated according to the instantaneous power consumption, load degree and execution time of the current task of the third module; According to the energy consumption weight and the current power state of the third module, determining whether it is necessary to switch the power state of the third module; the power state includes a high power state, a medium power state and a low power state; When the power state of the third module needs to be switched, the power state of the third module is switched.

9. The image recognition system according to claim 8, characterized in that: The energy consumption management module is also specifically used for: Calculating the electric energy allocation ratio of the third module according to the priority of the current task of the third module and the energy consumption weight; According to the electric energy distribution ratio, electric energy is distributed to the third module.

10. An image recognition method, characterized in that: Applied to the image recognition system according to any one of claims 1 to 9, the image recognition method comprises: After receiving the image to be identified, the image preprocessing module preprocesses the image to be identified and sends the preprocessed image to the dynamic defogging enhancement module; The dynamic defogging enhancement module determines whether the pre-processed image needs to be defogged and enhanced; When the preprocessed image needs to be defogged and enhanced, the dynamic defogging enhancement module performs defogging and enhancement processing on the preprocessed image, and sends the defogged and enhanced image to the neural network acceleration module; when the preprocessed image does not need to be defogged and enhanced, the dynamic defogging enhancement module sends the preprocessed image to the neural network acceleration module; The neural network acceleration module selects a target neural network model suitable for the current image from multiple neural network models, and recognizes the current image through the target neural network model; the target neural network model recognizes the current image based on a parallel block convolution acceleration algorithm.

Images