Light emitting diode display device

Abstract

The invention discloses a light-emitting diode display device which comprises a light-emitting diode display panel and a first thin film flip-chip packaging structure. The first thin film flip packaging structure is bonded to the light emitting diode display panel and comprises a first chip, a second chip and a first circuit substrate. The first chip includes a plurality of first signal output bumps and a plurality of first dummy bumps. The second chip includes a plurality of second signal output bumps. The first signal output lines are electrically connected to the first signal output bumps, respectively. The second signal output lines are electrically connected to the second signal output bumps, respectively. At least parts of the second signal output lines are electrically connected to the first dummy bumps, respectively. One of the first chip and the second chip is a light-emitting signal control chip.

Description

Technical Field

[0001] The invention relates to a light emitting diode display device. Background Art

[0002] LED display devices, especially micro LED display devices, have the advantage of high resolution. Micro LEDs in the display device are arranged in pixels and are used to display fine display images. Generally speaking, a driver chip is used to control the current and signal used to operate the micro LEDs.

[0003] Chip on Film (COF) technology is a thin film packaging method that is mainly used to package the driver chip on a flexible substrate and set it at the edge area of ​​the display panel. The thin film flip package can be bent to the back of the display panel, thereby saving the frame size of the display device. The driver chip is connected to the micro LED components in the display panel through COF technology and is used to output signals to the micro LED to ensure the precise operation of the display device. Summary of the invention

[0004] The invention provides a light emitting diode display device which can reduce the cost required for a thin film flip chip packaging structure.

[0005] At least one embodiment of the present invention provides a light-emitting diode display device, which includes a light-emitting diode display panel and a first thin film flip-chip packaging structure. The first thin film flip-chip packaging structure is bonded to the light-emitting diode display panel and includes a first chip, a second chip and a first circuit substrate. The first chip includes a plurality of first signal output bumps and a plurality of first dummy bumps. The second chip includes a plurality of second signal output bumps. The first circuit substrate includes a plurality of first signal output lines and a plurality of second signal output lines. The first signal output lines are electrically connected to the first signal output bumps, respectively. The second signal output lines are electrically connected to the second signal output bumps, respectively. At least part of the second signal output lines are electrically connected to the first dummy bumps, respectively. One of the first chip and the second chip is a light-emitting signal control chip.

[0006] At least one embodiment of the present invention provides a light-emitting diode display device, which includes a light-emitting diode display panel and a thin film flip-chip packaging structure. The first thin film flip-chip packaging structure is bonded to the light-emitting diode display panel and includes an integrated chip and a circuit substrate. The integrated chip includes a first circuit and a second circuit. The first circuit is a light-emitting signal control circuit. The second circuit is a gate signal control circuit, a data signal control circuit or a reset signal control circuit. The circuit substrate includes a plurality of first signal output lines and a plurality of second signal output lines. The first signal output line is electrically connected to the first circuit. The first circuit outputs a light-emitting signal to the first signal output line. The second signal output line is electrically connected to the second circuit. The second circuit outputs a gate signal, a data signal or a reset signal to the second signal output lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a schematic top view of a light emitting diode display device according to an embodiment of the present invention;

[0008] Figure 1B yes Figure 1A A schematic top view of a first thin film flip chip packaging structure;

[0009] Figure 1C yes Figure 1B A schematic top view of a first chip and a second chip in a first thin film flip-chip packaging structure;

[0010] Figure 1D yes Figure 1A A schematic top view of a second thin film flip-chip packaging structure;

[0011] Figure 1E yes Figure 1D A schematic top view of a third chip and a fourth chip in a second thin film flip-chip packaging structure;

[0012] Figure 1F yes Figure 1A A schematic top view of a third thin film flip chip packaging structure;

[0013] Figure 1G yes Figure 1F A schematic top view of a fifth chip and a sixth chip in a third thin film flip-chip packaging structure;

[0014] Figure 2A is a schematic top view of a light emitting diode display device according to an embodiment of the present invention;

[0015] Figure 2B yes Figure 2A A schematic top view of a first thin film flip chip packaging structure;

[0016] Figure 2C yes Figure 2BA schematic top view of a first chip and a second chip in a first thin film flip-chip packaging structure;

[0017] Figure 2D yes Figure 2A A schematic top view of a second thin film flip-chip packaging structure;

[0018] Figure 2E yes Figure 2D A schematic top view of a third chip and a fourth chip in a second thin film flip-chip packaging structure;

[0019] Figure 2F yes Figure 2A A schematic top view of a third thin film flip chip packaging structure;

[0020] Figure 2G yes Figure 2F A schematic top view of a fifth chip and a sixth chip in a third thin film flip-chip packaging structure;

[0021] Figure 3A is a schematic top view of a light emitting diode display device according to an embodiment of the present invention;

[0022] Figure 3B yes Figure 3A A top view schematic diagram of a thin film flip chip packaging structure;

[0023] Figure 4 is a top view schematic diagram of a light emitting diode display panel and a thin film flip chip packaging structure according to an embodiment of the present invention;

[0024] Figure 5 It is a top view schematic diagram of a light emitting diode display panel and a thin film flip chip packaging structure according to an embodiment of the present invention;

[0025] Figure 6 is a partial top view schematic diagram of a thin film flip chip packaging structure according to an embodiment of the present invention;

[0026] Figure 7 is a partial top view schematic diagram of a thin film flip chip packaging structure according to an embodiment of the present invention;

[0027] Figure 8 is a partial top view schematic diagram of a thin film flip chip packaging structure according to an embodiment of the present invention;

[0028] Fig. 9A is a circuit diagram of a pixel structure according to an embodiment of the present invention;

[0029] Fig. 9B is a timing diagram of a signal for operating a pixel structure according to an embodiment of the present invention;

[0030] Fig.10is a top view schematic diagram of a first chip and a second chip in a first thin film flip-chip packaging structure according to another embodiment of the present invention;

[0031] Fig.11 It is a top view schematic diagram of a first chip and a second chip in a first thin film flip-chip packaging structure according to another embodiment of the present invention.

[0032] Explanation of symbols

[0033] 10A, 10B, 10C: Light emitting diode display device

[0034] 100A, 100D: First circuit substrate

[0035] 100B, 100E: Second circuit substrate

[0036] 100C, 100F: Third circuit board

[0037] 100G: Circuit board

[0038] 101A, 101B, 101C, 101D, 101E, 101F, 101G: Input pads

[0039] 102A, 102D, 102G: First signal output pad

[0040] 102B, 102E: Third signal output pad

[0041] 102C, 102F: Fifth signal output pad

[0042] 104A, 104D, 104G: Second signal output pads

[0043] 104B, 104E: Fourth signal output pad

[0044] 104C, 104F: Sixth signal output pad

[0045] 106A, 106B, 106C, 106D, 106E, 106F, 106G: Power delivery pads

[0046] 110A, 110D: First Chip

[0047] 110B, 110D: The third chip

[0048] 110C, 110F: The fifth chip

[0049] 110a, 120a, 110c, 120c, 110e, 120e, 110g, 120g, 110i, 120i, 110k,120k: Side 1

[0050] 110b, 120b, 110d, 120d, 110f, 120f, 110h, 120h, 110j, 120j, 110l,120l: Second side

[0051] 112A, 113A, 112D: First signal output bump

[0052] 112B, 113B, 112E: Third signal output bump

[0053] 112C, 113C, 112F: Fifth signal output bump

[0054] 114A, 114D: first dummy bump

[0055] 114B, 114E: third dummy bump

[0056] 114C, 114F: fifth dummy bump

[0057] 115A, 115D: First power input bump

[0058] 115B, 115E: Third power input bump

[0059] 115C, 115F: Fifth power input bump

[0060] 116A, 116D: first signal input bump

[0061] 116B, 116E: Third signal input bump

[0062] 116C, 116F: Fifth signal input bump

[0063] 120A, 120D: Second chip

[0064] 120B, 120E: The fourth chip

[0065] 120C, 120F: Sixth chip

[0066] 122A, 123A, 122D: Second signal output bump

[0067] 122B, 123B, 122E: Fourth signal output bump

[0068] 122C, 123C, 122F: Sixth signal output bump

[0069] 124A: second dummy bump

[0070] 124B: fourth dummy bump

[0071] 124C: Sixth dummy bump

[0072] 125A, 125D: Second power input bump

[0073] 125B, 125E: Fourth power input bump

[0074] 125C, 125F: Sixth power input bump

[0075] 126A, 126D: Second signal input bump

[0076] 126B, 126E: fourth signal input bump

[0077] 126C, 126F: Sixth signal input bump

[0078] 127D, 127E, 127F: Power output bump

[0079] 132A, 132B, 132C, 132D, 132E, 132F, 132G: Power transmission line

[0080] 134A, 134D: First signal input line

[0081] 134B: Third signal input line

[0082] 134C, 135D: Fifth signal input line

[0083] 135A: Second signal input line

[0084] 135B: Fourth signal input line

[0085] 135C: Sixth signal input line

[0086] 136A, 136D: First power supply line

[0087] 136B: Third power supply line

[0088] 136C: Fifth power supply line

[0089] 137A, 137D: Second power supply line

[0090] 137B: Fourth power supply line

[0091] 137C: Sixth power supply line

[0092] 142A: First connection line

[0093] 142B: Third connecting line

[0094] 142C: Fifth connection line

[0095] 144A: Second connection line

[0096] 144B: Fourth connection line

[0097] 144C: ​​Sixth connecting line

[0098] 144D:Connecting wire

[0099] 152A, 152D, 152G, 152A-1, 152A-2: First signal output line

[0100] 152B: Third signal output line

[0101] 152C: Fifth signal output line

[0102] 154A, 154D, 154G, 154A-1, 154A-2: Second signal output line

[0103] 154B: Fourth signal output line

[0104] 154C: Sixth signal output line

[0105] 160: Integrated Chip

[0106] 162: First Circuit

[0107] 164: Second Circuit

[0108] 200: First circuit board

[0109] 210: Power IC

[0110] 220:Memory integrated circuit

[0111] 300: Second circuit board

[0112] 320, 420: Flexible printed circuit board

[0113] 400: The third circuit board

[0114] 410: Timing Control Integrated Circuit

[0115] 500: LED display panel

[0116] 510: Pixel structure

[0117] CA:Capacitance

[0118] C1, C7: First Circuit

[0119] C2, C8: Second Circuit

[0120] C3, C9: Third Circuit

[0121] C4, C10: Fourth Circuit

[0122] C5, C11: Fifth Circuit

[0123] C6, C12: Sixth Circuit

[0124] CFA, CFD: The first thin film flip chip packaging structure

[0125] CFB, CFE: Second film flip chip packaging structure

[0126] CFC, CFF: Third Film Flip Chip Packaging Structure

[0127] CFG: Thin Film Flip Chip Packaging Structure

[0128] Data: Data signal line

[0129] DR1: First Direction

[0130] DR2: Second direction

[0131] EM: Luminous signal line

[0132] Gate: Gate signal line

[0133] L: Light Emitting Diode

[0134] R1: Zone 1

[0135] R2: Second Zone

[0136] R3: The third zone

[0137] Reset: Reset signal line

[0138] S1, S3, S5, S7, S9, S11, S13: First side

[0139] S2, S4, S6, S8, S10, S12, S14: Second side

[0140] T1: The first transistor

[0141] T2: Second transistor

[0142] T3: The third transistor

[0143] T4: The fourth transistor

[0144] T5: The fifth transistor

[0145] T6: The sixth transistor

[0146] T7: Seventh transistor

[0147] VDD: First power signal line

[0148] Vinit: Starting signal line

[0149] Vref: reference voltage signal line

[0150] VSS: Second power signal line DETAILED DESCRIPTION

[0151] Figure 1A FIG. 1 is a top view of a light emitting diode display device 10A according to an embodiment of the present invention. Figure 1A The LED display device 10A is a spliced ​​display device and includes a plurality of LED display panels 500 spliced ​​together. Each LED display panel 500 includes a plurality of pixel structures 510 arranged in an array, and each pixel structure 510 includes a pixel circuit and a corresponding LED.

[0152] In some embodiments, each LED display panel 500 is electrically connected to the first thin film flip package structure CFA, the second thin film flip package structure CFB, and the third thin film flip package structure CFC. For example, the first thin film flip package structure CFA, the second thin film flip package structure CFB, and the third thin film flip package structure CFC are bonded to the edge area of ​​the LED display panel 500. The first thin film flip package structure CFA, the second thin film flip package structure CFB, and the third thin film flip package structure CFC may have the same or different structures. Although in Figure 1A Each LED display panel 500 is electrically connected to three TFT packaging structures, but the present invention is not limited thereto. Each LED display panel 500 can be electrically connected to more or less TFT packaging structures.

[0153] Each light emitting diode display panel 500 is electrically connected to the first circuit board 200 through the first thin film flip chip packaging structure CFA, the second thin film flip chip packaging structure CFB and the third thin film flip chip packaging structure CFC. In some embodiments, the first circuit board 200 includes a power integrated circuit 210 and a memory integrated circuit 220. For example, the power integrated circuit 210 and the memory integrated circuit 220 are respectively arranged in different chips, and these chips are bonded to the first circuit board 200.

[0154] The plurality of first circuit boards 200 are electrically connected to the second circuit board 300 through the plurality of flexible circuit boards 320. The second circuit board 300 is electrically connected to the third circuit board 400 through the flexible circuit board 420. In some embodiments, the third circuit board 400 includes a timing control integrated circuit 410. In some embodiments, the timing control integrated circuit 410 is disposed in a chip, and the chip is bonded to the third circuit board 400.

[0155] Please refer to Figure 1A , Figure 1B as well as Figure 1C The first thin film flip chip packaging structure CFA includes a first circuit substrate 100A, a first chip 110A and a second chip 120A. The first circuit substrate 100A is, for example, a flexible printed circuit board, and includes a plurality of input pads 101A, a plurality of first signal output pads 102A, a plurality of second signal output pads 104A, a plurality of power transmission pads 106A, a plurality of power transmission lines 132A, a plurality of first power supply lines 136A, a plurality of second power supply lines 137A, a plurality of first signal input lines 134A, a plurality of second signal input lines 135A, a plurality of first connection lines 142A, a plurality of second connection lines 144A, a plurality of first signal output lines 152A and a plurality of second signal output lines 154A. In some embodiments, the first circuit substrate 100A includes a flexible substrate and multiple conductive layers and multiple insulating layers arranged on the flexible substrate, and the above-mentioned pads, power transmission lines, power supply lines, signal input lines, connecting lines and signal output lines can be distributed in the same or different conductive layers.

[0156] The first signal output pad 102A, the second signal output pad 104A, and the power transmission pad 106A are arranged along the first side S1 of the first flip-chip packaging structure CFA, and bonded to the LED display panel 500. For example, the first signal output pad 102A, the second signal output pad 104A, and the power transmission pad 106A are arranged along the first direction DR1 near the first side S1.

[0157] The input pads 101A are arranged along a second side S2 of the first flip chip package structure CFA opposite to the first side S1 and bonded to the first circuit board 200. For example, the input pads 101A are arranged along the first direction DR1 near the second side S2.

[0158] The power transmission line 132A connects the power transmission pad 106A to the corresponding input pad 101A. For example, the power signal is transmitted to the LED display panel 500 through the corresponding input pad 101A, the power transmission line 132A and the power transmission pad 106A, and further transmitted to the corresponding pixel structure 510.

[0159] The first chip 110A and the second chip 120A are bonded to the first circuit substrate 100A. In this embodiment, the arrangement direction of the first chip 110A and the second chip 120A is staggered on the virtual line between the first side S1 and the second side S2 (for example, the virtual line parallel to the second direction DR2). In some embodiments, the second direction DR2 is perpendicular to the first direction DR1. In some embodiments, the first chip 110A and the second chip 120A are arranged along the first direction DR1.

[0160] Please refer to Figure 1B and Figure 1C , the first chip 110A includes a plurality of first signal output bumps 112A, 113A, a plurality of first dummy bumps 114A, a plurality of first power input bumps 115A, and a plurality of first signal input bumps 116A. The second chip 120A includes a plurality of second signal output bumps 122A, 123A, a plurality of second dummy bumps 124A, a plurality of second power input bumps 125A, and a plurality of second signal input bumps 126A. In some embodiments, the first signal output bumps 112A, 113A and the first dummy bumps 114A are arranged in an interlaced manner, and the second signal output bumps 122A, 123A and the second dummy bumps 124A are arranged in an interlaced manner. The number of the first signal output bumps 112A, 113A and the first dummy bumps 114A can be adjusted according to demand. In some embodiments, the total number of the first signal output bumps 112A, 113A is greater than or equal to the total number of the first dummy bumps 114A. Similarly, the number of the second signal output bumps 122A, 123A and the second dummy bumps 124A can be adjusted as required. In some embodiments, the total number of the second signal output bumps 122A, 123A is greater than or equal to the total number of the second dummy bumps 124A.

[0161] In some embodiments, the first signal output bumps 112A, 113A and the first dummy bumps 114A are arranged along the first side 110a of the first chip 110A, and the first power input bumps 115A and the first signal input bumps 116A are arranged along the second side 110b of the first chip 110A opposite to the first side 110a. In some embodiments, the second signal output bumps 122A, 123A and the second dummy bumps 124A are arranged along the first side 120a of the second chip 120A, and the second power input bumps 125A and the second signal input bumps 126A are arranged along the second side 120b of the second chip 120B opposite to the first side 120a.

[0162] In this embodiment, the first signal output line 152A is electrically connected to the first signal output bumps 112A, 113A respectively. Specifically, the first chip 110A outputs signals via the first signal output bumps 112A, 113A, and transmits the signals to the first signal output pad 102A electrically connected thereto through the first signal output line 152A. In this embodiment, the first connection line 142A extends from the second dummy bump 124A to at least a portion of the first signal output bump (i.e., the first signal output bump 113A). The first signal output bump 113A is connected to the second dummy bump 124A through the first connection line 142A, and then electrically connected to the corresponding first signal output line 152A through the second dummy bump 124A. In this embodiment, part of the first signal output lines 152A are electrically connected to the first signal output bumps 112A and extend outward from the first signal output bumps 112A of the first chip 110A; another part of the first signal output lines 152A are electrically connected to the second dummy bumps 124A and extend outward from the second dummy bumps 124A of the second chip 120A.

[0163] The first power input bump 115A and the first signal input bump 116A are electrically connected to the first power supply line 136A and the first signal input line 134A, respectively.

[0164] In this embodiment, the second signal output line 154A is electrically connected to the second signal output bumps 122A, 123A. Specifically, the second chip 120A outputs signals via the second signal output bumps 122A, 123A, and transmits the signals to the second signal output pad 104A electrically connected thereto through the second signal output line 154A. In this embodiment, the second connection line 144A extends from the first dummy bump 114A to at least a portion of the second signal output bump (i.e., the second signal output bump 123A). The second signal output bump 123A is electrically connected to the first dummy bump 114A through the second connection line 144A, and then connected to the corresponding second signal output line 154A through the first dummy bump 114A. In this embodiment, part of the second signal output lines 154A are electrically connected to the second signal output bumps 122A and extend outward from the second signal output bumps 122A of the second chip 120A; another part of the second signal output lines 154A are electrically connected to the first dummy bumps 114A and extend outward from the first dummy bumps 114A of the first chip 110A.

[0165] The second power input bump 125A and the second signal input bump 126A are electrically connected to the second power supply line 137A and the second signal input line 135A, respectively.

[0166] In some embodiments, one of the first chip 110A and the second chip 120A is a light emitting signal control chip, and the other is a gate signal control chip, a data signal control chip, or a reset signal control chip. For example, the first chip 110A is a light emitting signal control chip. The first circuit C1 in the first chip 110A is a light emitting signal control circuit, and the second circuit C2 in the second chip 120A is a gate signal control circuit, a data signal control circuit, or a reset signal control circuit. In some embodiments, the first circuit C1 (e.g., a light emitting signal control circuit) is electrically connected to the first signal output bumps 112A, 113A, and the first dummy bump 114A is independent of the first circuit C1. In some embodiments, the second circuit C2 is electrically connected to the second signal output bumps 122A, 123A, and the second dummy bump 124A is independent of the second circuit C2.

[0167] In some embodiments, the timing control integrated circuit 410 (see Figure 1A ) is transmitted to the first chip 110A through the first signal input line 134A and the first signal input bump 116A.

[0168] exist Figure 1C In the embodiment, the first chip 110A includes the first dummy bump 114A, and the second chip 120A includes the second dummy bump 124A, but the present invention is not limited thereto. In other embodiments, part or all of the first dummy bump 114A and part or all of the second dummy bump 124A may be omitted, and part or all of the first connection wire 142A and part or all of the second connection wire 144A may also be omitted, such as Fig.10 Please refer to Fig.10 The first thin film flip chip packaging structure includes first signal output lines 152A-1, 152A-2 and second signal output lines 154A-1, 154A-2. The first signal output line 152A-1 is electrically connected to the first signal output bump 112A, and the first signal output line 152A-2 is electrically connected to the first signal output bump 113A.

[0169] exist Fig.10 In the embodiment, at least part of the first signal output line (e.g., the first signal output line 152A-1) extends outward from the first signal output bump 112A and does not overlap the second chip 120A. At least part of the first signal output line (e.g., the first signal output line 152A-2) extends from the first signal output bump 113A toward the second chip 120A and extends from one side of the second chip 120A (e.g., Fig.10 The left side of the second chip 120A in FIG. 1 extends from below the second chip 120A to below the second chip 120A, and extends from another side of the second chip 120A (eg, Fig.10The first signal output line 152A- 2 extends below the first side 120 a of the chip 120A and exceeds the second chip 120A. In this embodiment, a portion of the first signal output line 152A- 2 overlaps the second chip 120A.

[0170] On the other hand, Fig.10 In the embodiment, at least part of the second signal output line (such as the second signal output line 154A-1) extends outward from the second signal output bump 122A and does not overlap the first chip 110A. At least part of the second signal output line (such as the second signal output line 154A-2) extends from the second signal output bump 123A toward the first chip 110A and extends from one side of the first chip 110A (such as Fig.10 The first chip 110A is provided with a plurality of first chips 110A and a plurality of first chips 110A. The first chip 110A is provided with a plurality of first chips 110A and .... Fig.10 The second signal output line 154A-2 extends below the first side 110a of the first chip 110A. In this embodiment, the second signal output line 154A-2 partially overlaps the first chip 110A. Figure 1A , Figure 1D as well as Figure 1E The second thin film flip chip package structure CFB includes a second circuit substrate 100B, a third chip 110B and a fourth chip 120B. The third circuit substrate 100B is, for example, a flexible printed circuit board, and includes a plurality of input pads 101B, a plurality of third signal output pads 102B, a plurality of fourth signal output pads 104B, a plurality of power transmission pads 106B, a plurality of power transmission lines 132B, a plurality of third power supply lines 136B, a plurality of fourth power supply lines 137B, a plurality of third signal input lines 134B, a plurality of fourth signal input lines 135B, a plurality of third connection lines 142B, a plurality of fourth connection lines 144B, a plurality of third signal output lines 152B and a plurality of fourth signal output lines 154B. In some embodiments, the second circuit substrate 100B includes a flexible substrate and multiple conductive layers and multiple insulating layers disposed on the flexible substrate, and the above-mentioned pads, power transmission lines, power supply lines, signal input lines, connecting lines and signal output lines can be distributed in the same or different conductive layers.

[0171] In some embodiments, the third signal output pad 102B, the fourth signal output pad 104B, and the power transmission pad 106B are arranged along the first direction DR1 near the first side S3 and bonded to the LED display panel 500 .

[0172] The input pads 101B are arranged along the first direction DR1 near the second side S4 and bonded to the first circuit board 200 .

[0173] The power transmission line 132B connects the power transmission pad 106B to the corresponding input pad 101B. For example, the power signal is transmitted to the LED display panel 500 through the corresponding input pad 101B, the power transmission line 132B and the power transmission pad 106B, and further transmitted to the corresponding pixel structure 510.

[0174] The third chip 110B and the fourth chip 120B are bonded to the second circuit substrate 100B. In some embodiments, the third chip 110B and the fourth chip 120B are arranged along the first direction DR1.

[0175] Please refer to Figure 1D and Figure 1E , the third chip 110B includes a plurality of third signal output bumps 112B, 113B, a plurality of third dummy bumps 114B, a plurality of third power input bumps 115B, and a plurality of third signal input bumps 116B. The fourth chip 120B includes a plurality of fourth signal output bumps 122B, 123B, a plurality of fourth dummy bumps 124B, a plurality of fourth power input bumps 125B, and a plurality of fourth signal input bumps 126B. In some embodiments, the third signal output bumps 112B, 113B and the third dummy bumps 114B are arranged in an interlaced manner, and the fourth signal output bumps 122B, 123B and the fourth dummy bumps 124B are arranged in an interlaced manner.

[0176] In some embodiments, the third signal output bumps 112B, 113B and the third dummy bumps 114B are arranged along the first side 110c of the third chip 110B, and the third power input bumps 115B and the third signal input bumps 116B are arranged along the second side 110d of the third chip 110B opposite to the first side 110c. In some embodiments, the fourth signal output bumps 122B, 123B and the fourth dummy bumps 124B are arranged along the first side 120c of the fourth chip 120B, and the fourth power input bumps 125B and the fourth signal input bumps 126B are arranged along the second side 120d of the fourth chip 110B opposite to the first side 120c.

[0177] The third chip 110B outputs signals via the third signal output bumps 112B, 113B, and transmits the signals to the third signal output pad 102B electrically connected thereto through the third signal output line 152B. In the present embodiment, the third connection lines 142B extend from the fourth dummy bumps 124B to at least a portion of the third signal output bumps (i.e., the third signal output bumps 113B). The third signal output bumps 113B are connected to the fourth dummy bumps 124B through the third connection lines 142B, and further electrically connected to the corresponding third signal output lines 152B through the fourth dummy bumps 124B.

[0178] The third power input bump 115B and the third signal input bump 116B are electrically connected to the third power supply line 136B and the third signal input line 134B, respectively.

[0179] The fourth chip 120B outputs signals via the fourth signal output bumps 122B, 123B, and transmits the signals to the fourth signal output pad 104B electrically connected thereto through the fourth signal output line 154B. In the present embodiment, the fourth connection lines 144B extend from the third dummy bumps 114B to at least a portion of the fourth signal output bumps (i.e., the fourth signal output bumps 123B). The fourth signal output bumps 123B are electrically connected to the third dummy bumps 114B through the fourth connection lines 144B, and further connected to the corresponding fourth signal output lines 154B through the third dummy bumps 114B.

[0180] The fourth power input bump 125B and the fourth signal input bump 126B are electrically connected to the fourth power supply line 137B and the fourth signal input line 135B, respectively.

[0181] In some embodiments, the third chip 110B and the fourth chip 120B are a combination of any two of a light emitting signal control chip, a gate signal control chip, a data signal control chip, and a reset signal control chip. For example, the third chip 110B is a gate signal control chip. The third circuit C3 in the third chip 110B is a gate signal control circuit, and the fourth circuit C4 in the fourth chip 120B is a data signal control circuit. In some embodiments, the third circuit C3 is electrically connected to the third signal output bumps 112B, 113B, and the third dummy bump 114B is independent of the third circuit C3. In some embodiments, the fourth circuit C4 is electrically connected to the fourth signal output bumps 122B, 123B, and the fourth dummy bump 124B is independent of the fourth circuit C4.

[0182] In some embodiments, the timing control integrated circuit 410 outputs (see Figure 1A ) is transmitted to the third chip 110B through the third signal input line 134B and the third signal input bump 116B.

[0183] Please refer to Figure 1A , Figure 1F as well as Figure 1GThe third thin film flip chip package structure CFC includes a third circuit substrate 100C, a fifth chip 110C and a sixth chip 120C. The fifth circuit substrate 100C is, for example, a flexible printed circuit board, and includes a plurality of input pads 101C, a plurality of fifth signal output pads 102C, a plurality of sixth signal output pads 104C, a plurality of power transmission pads 106C, a plurality of power transmission lines 132C, a plurality of fifth power supply lines 136C, a plurality of sixth power supply lines 137C, a plurality of fifth signal input lines 134C, a plurality of sixth signal input lines 135C, a plurality of fifth connection lines 142C, a plurality of sixth connection lines 144C, a plurality of fifth signal output lines 152C and a plurality of sixth signal output lines 154C. In some embodiments, the second circuit substrate 100C includes a flexible substrate and multiple conductive layers and multiple insulating layers arranged on the flexible substrate, and the above-mentioned pads, power transmission lines, power supply lines, signal input lines, connecting lines and signal output lines can be distributed in the same or different conductive layers.

[0184] In some embodiments, the fifth signal output pad 102C, the sixth signal output pad 104C, and the power transmission pad 106C are arranged along the first direction DR1 near the first side S5 and are bonded to the LED display panel 500 .

[0185] The input pads 101C are arranged along the first direction DR1 near the second side S6 and bonded to the first circuit board 200 .

[0186] The power transmission line 132C connects the power transmission pad 106C to the corresponding input pad 101C. For example, the power signal is transmitted to the LED display panel 500 through the corresponding input pad 101C, the power transmission line 132C and the power transmission pad 106C, and further transmitted to the corresponding pixel structure 510.

[0187] The fifth chip 110C and the sixth chip 120C are bonded to the second circuit substrate 100C. In some embodiments, the fifth chip 110C and the sixth chip 120C are arranged along the first direction DR1.

[0188] Please refer to Figure 1F and Figure 1G, the fifth chip 110C includes a plurality of fifth signal output bumps 112C, 113C, a plurality of fifth dummy bumps 114C, a plurality of fifth power input bumps 115C, and a plurality of fifth signal input bumps 116C. The sixth chip 120C includes a plurality of sixth signal output bumps 122C, 123C, a plurality of sixth dummy bumps 124C, a plurality of sixth power input bumps 125C, and a plurality of sixth signal input bumps 126C. In some embodiments, the fifth signal output bumps 112C, 113C and the fifth dummy bumps 114C are arranged in an interlaced manner, and the sixth signal output bumps 122C, 123C and the sixth dummy bumps 124C are arranged in an interlaced manner.

[0189] In some embodiments, the fifth signal output bumps 112C, 113C and the fifth dummy bumps 114C are arranged along the first side 110e of the fifth chip 110C, and the fifth power input bumps 115C and the fifth signal input bumps 116C are arranged along the second side 110f of the fifth chip 110C opposite to the first side 110e. In some embodiments, the sixth signal output bumps 122C, 123C and the sixth dummy bumps 124C are arranged along the first side 120e of the sixth chip 120C, and the sixth power input bumps 125C and the sixth signal input bumps 126C are arranged along the second side 120f of the sixth chip 110C opposite to the first side 120e.

[0190] The fifth chip 110C outputs signals via the fifth signal output bumps 112C, 113C, and transmits the signals to the fifth signal output pad 102C electrically connected thereto through the fifth signal output line 152C. In the present embodiment, the fifth connection lines 142C extend from the sixth dummy bumps 124C to at least a portion of the fifth signal output bumps (i.e., the fifth signal output bumps 113C). The fifth signal output bumps 113C are connected to the sixth dummy bumps 124C through the fifth connection lines 142C, and further electrically connected to the corresponding fifth signal output lines 152C through the sixth dummy bumps 124C.

[0191] The fifth power input bump 115C and the fifth signal input bump 116C are electrically connected to the fifth power supply line 136C and the fifth signal input line 134C, respectively.

[0192] The sixth chip 120C outputs signals via the sixth signal output bumps 122C, 123C, and transmits the signals to the sixth signal output pad 104C electrically connected thereto through the sixth signal output line 154C. In the present embodiment, the sixth connection lines 144C extend from the fifth dummy bumps 114C to at least a portion of the sixth signal output bumps (i.e., the sixth signal output bumps 123C). The sixth signal output bumps 123C are electrically connected to the fifth dummy bumps 114C through the sixth connection lines 144C, and further connected to the corresponding sixth signal output lines 154C through the fifth dummy bumps 114C.

[0193] The sixth power input bump 125C and the sixth signal input bump 126C are electrically connected to the sixth power supply line 137C and the sixth signal input line 135C, respectively.

[0194] In some embodiments, the fifth chip 110C and the sixth chip 120C are a combination of any two of a light emitting signal control chip, a gate signal control chip, a data signal control chip, and a reset signal control chip. For example, the fifth chip 110C is a reset signal control chip. The fifth circuit C5 in the fifth chip 110C is a reset signal control circuit, and the sixth circuit C6 in the sixth chip 120C is a data signal control circuit. In some embodiments, the fifth circuit C5 is electrically connected to the fifth signal output bumps 112C, 113C, and the fifth dummy bump 114C is independent of the fifth circuit C5. In some embodiments, the sixth circuit C6 is electrically connected to the sixth signal output bumps 122C, 123C, and the sixth dummy bump 124C is independent of the sixth circuit C6.

[0195] For example, the timing control integrated circuit 410 (see Figure 1A ) is transmitted to the fifth chip 110C through the fifth signal input line 134C and the fifth signal input bump 116C.

[0196] In this embodiment, multiple chips are integrated into one thin film flip package structure, which can reduce the total number of thin film flip package structures and reduce the number and cost of thin film flip package structures compared to arranging multiple chips in different thin film flip package structures. Since the number of thin film flip package structures can be reduced, the frame size of the light emitting diode display device can be reduced, thereby reducing the splicing seam of the spliced ​​display device.

[0197] Figure 2A is a top view of a light emitting diode display device 10B according to an embodiment of the present invention. Figure 2AThe LED display device 10B is a spliced ​​display device, and includes a plurality of LED display panels 500 spliced ​​together. Each LED display panel 500 includes a plurality of pixel structures 510 .

[0198] In some embodiments, each light emitting diode display panel 500 is electrically connected to the first thin film flip packaging structure CFD, the second thin film flip packaging structure CFE, and the third thin film flip packaging structure CFF. The first thin film flip packaging structure CFD, the second thin film flip packaging structure CFE, and the third thin film flip packaging structure CFF may have the same or different structures. Figure 2A Each light emitting diode display panel 500 is electrically connected to three thin film flip-chip packaging structures, but the present invention is not limited thereto.

[0199] Each of the light emitting diode display panels 500 is electrically connected to the first circuit board 200 through the first thin film flip chip packaging structure CFD, the second thin film flip chip packaging structure CFE, and the third thin film flip chip packaging structure CFF.

[0200] Please refer to Figure 2A , Figure 2B as well as Figure 2C The first thin film flip chip packaging structure CFD includes a first circuit substrate 100D, a first chip 110D and a second chip 120D. The first circuit substrate 100D is, for example, a flexible circuit board, and includes a plurality of input pads 101D, a plurality of first signal output pads 102D, a plurality of second signal output pads 104D, a plurality of power transmission pads 106D, a plurality of power transmission lines 132D, a plurality of first power supply lines 136D, a plurality of second power supply lines 137D, a plurality of first signal input lines 134D, a plurality of second signal input lines 135D, a plurality of connection lines 144D, a plurality of first signal output lines 152D and a plurality of second signal output lines 154D. In some embodiments, the first circuit substrate 100D includes a flexible substrate and a plurality of conductive layers and a plurality of insulating layers disposed on the flexible substrate, and the pads, power transmission lines, power supply lines, signal input lines, connection lines and signal output lines may be distributed in the same or different conductive layers.

[0201] The first signal output pad 102D, the second signal output pad 104D, and the power transmission pad 106D are arranged along the first side S7 of the first thin film flip chip packaging structure CFD, and bonded to the LED display panel 500. For example, the first signal output pad 102D, the second signal output pad 104D, and the power transmission pad 106D are arranged along the first direction DR1 near the first side S7.

[0202] The input pads 101D are arranged along a second side S8 of the first flip chip package structure CFD opposite to the first side S7 and bonded to the first circuit board 200. For example, the input pads 101D are arranged along the first direction DR1 near the second side S8.

[0203] The power transmission line 132D connects the power transmission pad 106D to the corresponding input pad 101D. For example, the power signal is transmitted to the LED display panel 500 through the corresponding input pad 101D, the power transmission line 132D and the power transmission pad 106D, and further transmitted to the corresponding pixel structure 510.

[0204] The first chip 110D and the second chip 120D are bonded to the first circuit substrate 100D. In this embodiment, the arrangement direction of the first chip 110D and the second chip 120D is staggered on the virtual line between the first side S7 and the second side S8 (for example, the virtual line parallel to the second direction DR2). In some embodiments, the second direction DR2 is perpendicular to the first direction DR1. In some embodiments, the first chip 110D and the second chip 120D are arranged along the second direction DR2. The first chip 110D is located between the second chip 120D and the second signal output pad 104D and between the second chip 120D and the first signal output pad 102D.

[0205] Please refer to Figure 2B and Figure 2C , the first chip 110D includes a plurality of first signal output bumps 112D, a plurality of first dummy bumps 114D, a plurality of first power input bumps 115D, and a plurality of first signal input bumps 116D. The second chip 120D includes a plurality of second signal output bumps 122D, a plurality of second power input bumps 125D, a second signal input bump 126D, and a plurality of power output bumps 127D. In some embodiments, the first signal output bumps 112D and the first dummy bumps 114D are arranged alternately.

[0206] In some embodiments, the first signal output bumps 112D and the first dummy bumps 114D are arranged along the first side 110g of the first chip 110D, and the first power input bumps 115D and a portion of the first signal input bumps 116D are arranged along the second side 110h of the first chip 110D opposite to the first side 110g. In some embodiments, the second signal output bumps 122D and the power output bumps 127D are arranged along the first side 120g of the second chip 120D, and the second power input bumps 125D and the second signal input bumps 126D are arranged along the second side 120h of the second chip 120D opposite to the first side 120g.

[0207] In the present embodiment, the first signal output lines 152D are electrically connected to the first signal output bumps 112D, respectively. Specifically, the first chip 110D outputs signals via the first signal output bumps 112D, and transmits the signals to the first signal output pads 102D electrically connected thereto through the first signal output lines 152D. In the present embodiment, the connection lines 144D extend from the second signal output bumps 122D to the first dummy bumps 114D, respectively, and then are electrically connected to the corresponding second signal output lines 154D through the first dummy bumps 114D.

[0208] The first power supply line 136D electrically connects the power output bump 127D of the second chip 120D to the first power input bump 115D of the first chip 110D. The first signal input bump 116D is electrically connected to the first signal input line 134D. The second power input bump 125D is electrically connected to the second power supply line 137D. The second signal input bump 126D is electrically connected to the second signal input line 135D.

[0209] In some embodiments, one of the first chip 110D and the second chip 120D is a light emitting signal control chip, and the other is a gate signal control chip, a data signal control chip, or a reset signal control chip. For example, the first chip 110D is a light emitting signal control chip. The first circuit C7 in the first chip 110D is a light emitting signal control circuit, and the second circuit C8 in the second chip 120D is a gate signal control circuit, a data signal control circuit, or a reset signal control circuit. In some embodiments, the first circuit C7 (e.g., a light emitting signal control circuit) is electrically connected to the first signal output bump 112D, and the first dummy bump 114D is independent of the first circuit C7. In some embodiments, the second circuit C8 is electrically connected to the second signal output bump 122D.

[0210] In some embodiments, the timing control integrated circuit 410 (see Figure 2A ) is transmitted to the first chip 110D through the first signal input line 134D and the first signal input bump 116D.

[0211] exist Figure 2C In the embodiment, the first chip 110D includes the first dummy bump 114D, but the present invention is not limited thereto. In other embodiments, part or all of the first dummy bump 114D may be omitted, and part or all of the connecting wire 144D may also be omitted, such as Fig.11 Please refer to Fig.11 In this embodiment, at least part of the second signal output line 154D extends from the second signal output bump 122D to the first chip 110D, and extends from one side of the first chip 110D (eg Fig.11The second side 110h in FIG. 1 extends from below the first chip 110D to below the first chip 110D, and extends from another side (eg, Fig.10 The second signal output line 154D extends below the first side 110g of the first chip 110D and exceeds the first chip 110D. In this embodiment, the second signal output line 154D partially overlaps the first chip 110D.

[0212] Please refer to Figure 2A , Figure 2D as well as Figure 2E , the second thin film flip-chip packaging structure CFE includes a second circuit substrate 100E, a third chip 110E and a fourth chip 120E. The second circuit substrate 100E is, for example, a flexible circuit board, and includes a plurality of input pads 101E, a plurality of third signal output pads 102E, a plurality of fourth signal output pads 104E, a plurality of power transmission pads 106E, a plurality of power transmission lines 132E, a plurality of third power supply lines 136E, a plurality of fourth power supply lines 137E, a plurality of third signal input lines 134E, a plurality of fourth signal input lines 135E, a plurality of connection lines 144E, a plurality of third signal output lines 152E and a plurality of fourth signal output lines 154E. In some embodiments, the second circuit substrate 100E includes a flexible substrate and a plurality of conductive layers and a plurality of insulating layers disposed on the flexible substrate, and the pads, power transmission lines, power supply lines, signal input lines, connection lines and signal output lines may be distributed in the same or different conductive layers.

[0213] The third signal output pad 102E, the fourth signal output pad 104E and the power transmission pad 106E are arranged along the first side S9 of the second flip-chip package structure CFE and bonded to the LED display panel 500. For example, the third signal output pad 102E, the fourth signal output pad 104E and the power transmission pad 106E are arranged along the first direction DR1 near the first side S9.

[0214] The input pads 101E are arranged along the second side S10 of the second flip-chip package structure CFE opposite to the first side S9 and bonded to the first circuit board 200. For example, the input pads 101E are arranged along the first direction DR1 near the second side S8.

[0215] The power transmission line 132E connects the power transmission pad 106E to the corresponding input pad 101E. For example, the power signal is transmitted to the LED display panel 500 through the corresponding input pad 101E, the power transmission line 132E and the power transmission pad 106E, and further transmitted to the corresponding pixel structure 510.

[0216] The third chip 110E and the fourth chip 120E are bonded to the second circuit substrate 100E. In the present embodiment, the arrangement direction of the third chip 110E and the fourth chip 120E is staggered on the virtual line between the first side S9 and the second side S10 (for example, the virtual line parallel to the second direction DR2). In some embodiments, the second direction DR2 is perpendicular to the first direction DR1. In some embodiments, the third chip 110E and the fourth chip 120E are arranged along the second direction DR2. The third chip 110E is located between the fourth chip 120E and the fourth signal output pad 104E and between the fourth chip 120E and the third signal output pad 102E.

[0217] Please refer to Figure 2D and Figure 2E , the third chip 110E includes a plurality of third signal output bumps 112E, a plurality of third dummy bumps 114E, a plurality of third power input bumps 115E, and a plurality of third signal input bumps 116E. The fourth chip 120E includes a plurality of fourth signal output bumps 122E, a plurality of fourth power input bumps 125E, a fourth signal input bump 126E, and a plurality of power output bumps 127E. In some embodiments, the third signal output bumps 112E and the third dummy bumps 114E are arranged alternately.

[0218] In some embodiments, the third signal output bumps 112E and the third dummy bumps 114E are arranged along the first side 110i of the third chip 110E, and the third power input bumps 115E and a portion of the third signal input bumps 116E are arranged along the second side 110j of the third chip 110E opposite to the first side 110i. In some embodiments, the fourth signal output bumps 122E and the power output bumps 127E are arranged along the first side 120i of the fourth chip 120E, and the fourth power input bumps 125E and the fourth signal input bumps 126E are arranged along the second side 120j of the fourth chip 120E opposite to the first side 120i.

[0219] In the present embodiment, the third signal output lines 152E are electrically connected to the third signal output bumps 112E, respectively. Specifically, the third chip 110E outputs signals via the third signal output bumps 112E, and transmits the signals to the third signal output pads 102E electrically connected thereto through the third signal output lines 152E. In the present embodiment, the connection lines 144E extend from the fourth signal output bumps 122E to the third dummy bumps 114E, respectively, and then are electrically connected to the corresponding fourth signal output lines 154E through the third dummy bumps 114E.

[0220] The third power supply line 136E electrically connects the power output bump 127E of the fourth chip 120E to the third power input bump 115E of the third chip 110E. The third signal input bump 116E is electrically connected to the third signal input line 134E. The fourth power input bump 125E is electrically connected to the fourth power supply line 137E. The fourth signal input bump 126E is electrically connected to the fourth signal input line 135E.

[0221] In some embodiments, the third chip 110E and the fourth chip 120E are a combination of any two of a light emitting signal control chip, a gate signal control chip, a data signal control chip, and a reset signal control chip. For example, the third chip 110E is a gate signal control chip. The third circuit C9 in the third chip 110E is a gate signal control circuit, and the fourth circuit C10 in the fourth chip 120E is a data signal control circuit. In some embodiments, the third circuit C9 is electrically connected to the third signal output bump 112E, and the third dummy bump 114E is independent of the third circuit C9. In some embodiments, the fourth circuit C10 is electrically connected to the fourth signal output bump 122E.

[0222] In some embodiments, the timing control integrated circuit 410 outputs (see Figure 2A ) is transmitted to the third chip 110E through the third signal input line 134E and the third signal input bump 116E.

[0223] Please refer to Figure 2A , Figure 2F as well as Figure 2G The third thin film flip chip package structure CFF includes a third circuit substrate 100F, a fifth chip 110F and a sixth chip 120F. The third circuit substrate 100F is, for example, a flexible circuit board, and includes a plurality of input pads 101F, a plurality of fifth signal output pads 102F, a plurality of sixth signal output pads 104F, a plurality of power transmission pads 106F, a plurality of power transmission lines 132F, a plurality of fifth power supply lines 136F, a plurality of sixth power supply lines 137F, a plurality of fifth signal input lines 134F, a plurality of sixth signal input lines 135F, a plurality of connection lines 144F, a plurality of fifth signal output lines 152F and a plurality of sixth signal output lines 154F. In some embodiments, the third circuit substrate 100F includes a flexible substrate and a plurality of conductive layers and a plurality of insulating layers disposed on the flexible substrate, and the pads, power transmission lines, power supply lines, signal input lines, connection lines and signal output lines may be distributed in the same or different conductive layers.

[0224] The fifth signal output pad 102F, the sixth signal output pad 104F, and the power transmission pad 106F are arranged along the first side S11 of the third flip-chip package structure CFF, and bonded to the LED display panel 500. For example, the fifth signal output pad 102F, the sixth signal output pad 104F, and the power transmission pad 106F are arranged along the first direction DR1 near the first side S11.

[0225] The input pads 101F are arranged along the second side S12 of the third flip-chip package structure CFF opposite to the first side S11 and bonded to the first circuit board 200. For example, the input pads 101F are arranged along the first direction DR1 near the second side S12.

[0226] The power transmission line 132F connects the power transmission pad 106F to the corresponding input pad 101F. For example, the power signal is transmitted to the LED display panel 500 through the corresponding input pad 101F, the power transmission line 132F and the power transmission pad 106F, and further transmitted to the corresponding pixel structure 510.

[0227] The fifth chip 110F and the sixth chip 120F are bonded to the third circuit substrate 100F. In the present embodiment, the arrangement direction of the fifth chip 110F and the sixth chip 120F is staggered on the virtual line between the first side S11 and the second side S12 (for example, the virtual line parallel to the second direction DR2). In some embodiments, the second direction DR2 is perpendicular to the first direction DR1. In some embodiments, the fifth chip 110F and the sixth chip 120F are arranged along the second direction DR2. The fifth chip 110F is located between the sixth chip 120F and the sixth signal output pad 104F and between the sixth chip 120F and the fifth signal output pad 102F.

[0228] Please refer to Figure 2F and Figure 2G , the fifth chip 110F includes a plurality of fifth signal output bumps 112F, a plurality of fifth dummy bumps 114F, a plurality of fifth power input bumps 115F, and a plurality of fifth signal input bumps 116F. The sixth chip 120F includes a plurality of sixth signal output bumps 122F, a plurality of sixth power input bumps 125F, a sixth signal input bump 126F, and a plurality of power output bumps 127F. In some embodiments, the fifth signal output bumps 112F and the fifth dummy bumps 114F are arranged alternately.

[0229] In some embodiments, the fifth signal output bump 112F and the fifth dummy bump 114F are arranged along the first side 110k of the fifth chip 110F, and the fifth power input bump 115F and a portion of the fifth signal input bump 116F are arranged along the second side 110l of the fifth chip 110F opposite to the first side 110k. In some embodiments, the sixth signal output bump 122F and the power output bump 127F are arranged along the first side 120k of the sixth chip 120F, and the sixth power input bump 125F and the sixth signal input bump 126F are arranged along the second side 120l of the sixth chip 120F opposite to the first side 120k.

[0230] In the present embodiment, the fifth signal output lines 152F are electrically connected to the fifth signal output bumps 112F, respectively. Specifically, the fifth chip 110F outputs signals via the fifth signal output bumps 112F, and transmits the signals to the fifth signal output pads 102F electrically connected thereto through the fifth signal output lines 152F. In the present embodiment, the connection lines 144F extend from the sixth signal output bumps 122F to the fifth dummy bumps 114F, respectively, and then are electrically connected to the corresponding sixth signal output lines 154F through the fifth dummy bumps 114F.

[0231] The fifth power supply line 136F electrically connects the power output bump 127F of the sixth chip 120F to the fifth power input bump 115F of the fifth chip 110F. The fifth signal input bump 116F is electrically connected to the fifth signal input line 134F. The sixth power input bump 125F is electrically connected to the sixth power supply line 137F. The sixth signal input bump 126F is electrically connected to the sixth signal input line 135F.

[0232] In some embodiments, the fifth chip 110F and the sixth chip 120F are a combination of any two of a light emitting signal control chip, a gate signal control chip, a data signal control chip, and a reset signal control chip. For example, the fifth chip 110F is a gate signal control chip. The fifth circuit C11 in the fifth chip 110F is a reset signal control circuit, and the sixth circuit C12 in the sixth chip 120F is a data signal control circuit. In some embodiments, the fifth circuit C11 is electrically connected to the fifth signal output bump 112F, and the fifth dummy bump 114F is independent of the fifth circuit C11. In some embodiments, the sixth circuit C12 is electrically connected to the sixth signal output bump 122F.

[0233] In some embodiments, the timing control integrated circuit 410 outputs (see Figure 2A ) is transmitted to the fifth chip 110F through the fifth signal input line 134F and the fifth signal input bump 116F.

[0234] Figure 3A FIG. 1 is a schematic top view of a light emitting diode display device 10C according to an embodiment of the present invention. Figure 3B yes Figure 3A A top view of the thin film flip chip packaging structure CFG. Please refer to Figure 3A The LED display device 10C is a spliced ​​display device, and includes a plurality of LED display panels 500 spliced ​​together. Each LED display panel 500 includes a plurality of pixel structures 510 .

[0235] In some embodiments, each LED display panel 500 is electrically connected to a plurality of thin film flip-chip packaging structures CFG, and these thin film flip-chip packaging structures CFG may contain the same or different circuits. Figure 3A Each LED display panel 500 is electrically connected to three thin film flip-chip packaging structures CFG, but the present invention is not limited thereto. In other embodiments, one thin film flip-chip packaging structure CFG is connected to the LED display panel 500, such as Figure 4 In other embodiments, two thin film flip-chip packaging structures CFG are connected to the light emitting diode display panel 500, such as Figure 5 shown.

[0236] The thin film flip chip packaging structure CFG includes an integrated chip 160 and a circuit substrate 100G. The integrated chip 160 includes a first circuit 162 and a second circuit 164. The first circuit 162 and the second circuit 164 are any two combinations of a light emitting signal control circuit, a gate signal control circuit, a data signal control circuit, and a reset signal control circuit. For example, the first circuit 162 is a light emitting signal control circuit, and the second circuit 164 is a gate signal control circuit, a data signal control circuit, or a reset signal control circuit.

[0237] In some embodiments, the first circuit 162 is a light signal control circuit, and the second circuit 164 is a data signal control circuit. In this case, the integrated chip 160 has the functions of outputting light signals and data signals. For example, Figure 3A The integrated chip 160 of one of the three thin film flip-chip packaging structures CFG connected to each light emitting diode display panel 500 has the function of outputting a light emitting signal and a data signal.

[0238] In some embodiments, the first circuit 162 is a reset signal control circuit, and the second circuit 164 is a data signal control circuit. In this case, the integrated chip 160 has the function of outputting a reset signal and outputting a data signal. For example, Figure 3AThe integrated chip 160 on another one of the three thin film flip-chip packaging structures CFG connected to each light emitting diode display panel 500 has the function of outputting a reset signal and outputting a data signal.

[0239] In some embodiments, the first circuit 162 is a gate signal control circuit, and the second circuit 164 is a data signal control circuit. In this case, the integrated chip 160 has the functions of outputting gate signals and outputting data signals. For example, Figure 3A The integrated chip 160 on the last one of the three thin film flip-chip packaging structures CFG connected to each light emitting diode display panel 500 has the function of outputting gate signals and data signals.

[0240] Each of the light emitting diode display panels 500 is electrically connected to the first circuit board 200 through a plurality of thin film flip chip packaging structures CFG.

[0241] Please refer to Figure 3A as well as Figure 3B , the thin film flip-chip packaging structure CFG includes an integrated chip 160 and a circuit substrate 100G. The circuit substrate 100G is, for example, a flexible circuit board, and includes a plurality of input pads 101G, a plurality of first signal output pads 102G, a plurality of second signal output pads 104G, a plurality of power transmission pads 106G, a plurality of power transmission lines 132G, a plurality of first signal output lines 152G, and a plurality of second signal output lines 154G. In some embodiments, the circuit substrate 100G includes a flexible substrate and a plurality of conductive layers and a plurality of insulating layers disposed on the flexible substrate, and the pads, power transmission lines, and signal output lines may be distributed in the same or different conductive layers.

[0242] In some embodiments, the first signal output pad 102G, the second signal output pad 104G, and the power transmission pad 106G are arranged along the first direction DR1 near the first side S13 and are bonded to the LED display panel 500 .

[0243] The input pads 101G are arranged along the first direction DR1 near the second side S14 and bonded to the first circuit board 200 .

[0244] The power transmission line 132G connects the power transmission pad 106G to the corresponding input pad 101G. For example, the power signal is transmitted to the LED display panel 500 through the corresponding input pad 101G, the power transmission line 132G and the power transmission pad 106G, and further transmitted to the corresponding pixel structure 510.

[0245] The integrated chip 160 is bonded to the circuit substrate 100G. In some embodiments, the first circuit 162 in the integrated chip 160 is electrically connected to the first signal output line 152G, and outputs a signal (e.g., a light signal) to the first signal output pad 102G through the first signal output line 152G; the second circuit 164 in the integrated chip 160 is electrically connected to the second signal output line 154G, and outputs a signal (e.g., a gate signal, a data signal, or a reset signal) to the second signal output pad 104G through the second signal output line 154G. In some embodiments, the circuit substrate 100G further includes a plurality of signal input lines (not shown). Some of the input pads 101G provide clock control signals and / or data signals to the integrated chip 160 through the signal input lines.

[0246] In this embodiment, multiple circuits with different functions are integrated into an integrated chip, and the integrated chip is disposed on a thin film flip-chip packaging structure. Compared with disposing multiple chips with different functions in different thin film flip-chip packaging structures, the total number of thin film flip-chip packaging structures can be reduced, thereby reducing the number and cost of thin film flip-chip packaging structures. Since the number of thin film flip-chip packaging structures can be reduced, the frame size of the light-emitting diode display device can be reduced, thereby reducing the splicing seam of the spliced ​​display device.

[0247] Figures 6 to 8 FIG. 4 is a partial top view of a thin film flip chip packaging structure according to some embodiments of the present invention. Figures 6 to 8 The first signal output pad and the second signal output pad in the thin film flip-chip packaging structure can be arranged in various ways. Figures 6 to 8 Layout as shown.

[0248] Please refer to Figure 6 as well as Figure 7 , the first region R1, the second region R2 and the third region R3 are arranged along the first side of the thin film flip chip packaging structure. In the first region R1 and the third region R3, the number of the first signal output pads 102 is different from the number of the second signal output pads 104. For example, in the first region R1 and the third region R3, the first signal output pads 102 are staggered in a manner that every two to five (e.g., two to three or three to five) first signal output pads 102 are accompanied by one second signal output pad 104. In the second region R2, the second signal output pads 104 are staggered in a manner that every first signal output pad 102 is accompanied by one second signal output pad 104. Figure 6 as well as Figure 7In the first region R1 and the third region R3, the number of the first signal output pads 102 is greater than the number of the second signal output pads 104, but the present invention is not limited thereto. In other embodiments, in the first region R1 and the third region R3, the number of the first signal output pads 102 is less than the number of the second signal output pads 104. For example, the second signal output pads 104 are arranged in a staggered manner with one first signal output pad 102 accompanying every two to five (e.g., two to three or three to five) second signal output pads 104.

[0249] Please refer to Figure 8 , in the first region R1 and the third region R3, all are first signal output pads 102, and in the second region R2, all are second signal output pads 104. In other embodiments, in the second region R2, all are first signal output pads 102, and in the first region R1 and the third region R3, all are second signal output pads 104.

[0250] In any of the above embodiments, the pad layouts of the first region R1 and the third region R3 and the pad layout of the second region R2 can be swapped with each other.

[0251] Fig. 9A FIG. 5 is a circuit diagram of a pixel structure 510 according to an embodiment of the present invention. For example, the pixel structure 510 in any of the above embodiments may have the following features: Fig. 9A Please refer to the circuit diagram shown in Fig. 9A The pixel structure 510 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a capacitor CA and a light emitting diode L.

[0252] The gate of the first transistor T1 is connected to a reset signal line Reset (for example, used to transmit a reset signal output by the thin film flip-chip packaging structure in the aforementioned embodiment). The first end of the first transistor T1 is connected to a start signal line Vinit, and the second end is connected to a first end of the second transistor T2, a first end of the capacitor CA, and a gate of the third transistor T3.

[0253] The gate of the second transistor T2 is connected to the gate signal line Gate (eg, used to transmit the gate signal output by the thin film flip chip packaging structure in the above embodiment). The second end of the second transistor T2 is connected to the first end of the sixth transistor T6 and the first end of the third transistor T3.

[0254] A second end of the third transistor T3 is connected to a first end of the seventh transistor T7 and the first power signal line VDD.

[0255] The gate of the fourth transistor T4 is connected to the gate signal line Gate. The first end of the fourth transistor T4 is connected to the data signal line Data (for example, for transmitting the data signal output by the thin film flip chip packaging structure in the above embodiment). The second end of the fourth transistor T4 is connected to the first end of the fifth transistor T5, the second end of the seventh transistor T7 and the second end of the capacitor CA.

[0256] The gate of the fifth transistor T5 is connected to the light emitting signal line EM (for example, used to transmit the light emitting signal output by the thin film flip chip packaging structure in the above embodiment). The second end of the fifth transistor T5 is connected to the reference voltage signal line Vref.

[0257] The gate of the sixth transistor T6 is connected to the light emitting signal line EM. The second end of the sixth transistor T6 is connected to the first end of the light emitting diode L.

[0258] A gate of the seventh transistor T7 is connected to the reset signal line Reset.

[0259] The second end of the light emitting diode L is connected to the second power signal line VSS.

[0260] In this embodiment, the pixel structure 510 includes a 7T1C (7 transistors and 1 capacitor) architecture as an example, but the present invention is not limited thereto. The pixel structure 510 may also include other circuit architectures, such as a 2T1C architecture, a 6T1C architecture, a 7T1C architecture, a 7T2C architecture, an 8T1C architecture, or any possible architecture.

[0261] Fig. 9B is a timing diagram of a signal for operating a pixel structure according to an embodiment of the present invention. In this embodiment, taking a P-type channel metal-oxide-semiconductor (PMOS) transistor architecture as an example, providing a low potential to the gate of the transistor can turn on the transistor, and providing a high potential to the gate of the transistor can turn off the transistor, but the present invention is not limited thereto. In other embodiments, an N-type channel metal-oxide-semiconductor (NMOS) transistor architecture is selected, and providing a low potential to the gate of the transistor can turn off the transistor, and providing a high potential to the gate of the transistor can turn on the transistor. Please refer to Fig. 9A as well as Fig. 9BWhen the light emitting diode display device displays a picture, each frame includes a reset phase, a signal control phase, and a light emitting phase. In the reset phase, the reset signal line Reset provides a low potential to turn on the first transistor T1 and the seventh transistor T7, and the gate signal line Gate and the light emitting signal line EM both provide a high potential to turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. In this way, the potentials at both ends of the capacitor CA are provided by the first power signal line VDD and the start signal line Vinit, respectively. This process is to reset the potential stored in the capacitor CA in the previous frame.

[0262] In the signal control stage, the reset signal line Reset and the light-emitting signal line EM both provide a high potential to turn off the first transistor T1, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7, and the gate signal line Gate provides a low potential to turn on the second transistor T2 and the fourth transistor T4, so that the data signal line Data can input the data line signal to the capacitor CA, so that the capacitor CA stores the light-emitting voltage of the light-emitting stage.

[0263] In the light-emitting stage, the light-emitting signal line EM provides a low potential to turn on the fifth transistor T5 and the sixth transistor T6, and the gate signal line Gate and the reset signal line Reset both provide a high potential to turn off the first transistor T1, the second transistor T2, the fourth transistor T4 and the seventh transistor T7. In this way, the reference voltage signal line Vref can provide a reference voltage signal to the capacitor CA.

[0264] Based on the above, the pixel structure can be operated by various signals provided by the thin film flip package structure. Since multiple chips or circuits are integrated into one thin film flip package structure, the number and cost of thin film flip package structures can be reduced.

Claims

1. A light emitting diode display device, comprising: Light emitting diode display panel; as well as The first thin film flip chip packaging structure is bonded to the light emitting diode display panel and includes: A first chip includes a plurality of first signal output bumps and a plurality of first dummy bumps; A second chip including a plurality of second signal output bumps; and The first circuit substrate comprises: A plurality of first signal output lines are electrically connected to the first signal output bumps respectively; and A plurality of second signal output lines are electrically connected to the second signal output bumps, and at least part of the second signal output lines are electrically connected to the first dummy bumps, wherein one of the first chip and the second chip is a light emitting signal control chip. 2 . The light emitting diode display device as claimed in claim 1 , wherein the other of the first chip and the second chip is a gate signal control chip, a data signal control chip or a reset signal control chip. 3 . The light emitting diode display device as claimed in claim 1 , wherein the second chip comprises a plurality of second dummy bumps, and at least a portion of the first signal output lines are electrically connected to the second dummy bumps, respectively.

4. The light emitting diode display device according to claim 3, further comprising: A plurality of first connection lines respectively extend from the second dummy bumps to a portion of the first signal output bumps; and A plurality of second connection lines respectively extend from the first dummy bumps to a portion of the second signal output bumps.

5. The light emitting diode display device according to claim 1, further comprising: A second thin film flip-chip packaging structure is bonded to the light emitting diode display panel, wherein the second thin film flip-chip packaging structure comprises: A third chip includes a plurality of third signal output bumps and a plurality of third dummy bumps; a fourth chip comprising a plurality of fourth signal output bumps; and The second circuit substrate comprises: A plurality of third signal output lines are electrically connected to the third signal output bumps respectively; and A plurality of fourth signal output lines are electrically connected to the fourth signal output bumps, and at least some of the fourth signal output lines are electrically connected to the third dummy bumps, wherein the third chip is a gate signal control chip, and the fourth chip is a data signal control chip. 6 . The light emitting diode display device as claimed in claim 1 , wherein the first signal output bumps and the first dummy bumps are arranged alternately. 7 . The light emitting diode display device as claimed in claim 1 , wherein the first chip is a light emitting signal control chip, and the first chip comprises a light emitting signal control circuit, wherein the light emitting signal control circuit is electrically connected to the first signal output bumps.

8. The light emitting diode display device as claimed in claim 1, wherein the first circuit substrate further comprises: A plurality of first signal output pads electrically connected to the first signal output lines; A plurality of second signal output pads electrically connected to the second signal output lines, wherein the first signal output pads and the second signal output pads are arranged along the first side of the first thin film flip-chip packaging structure and bonded to the light emitting diode display panel; as well as A plurality of input pads are arranged along a second side of the first thin film flip-chip packaging structure opposite to the first side, wherein the arrangement directions of the first chip and the second chip are interlaced with a virtual connection line from the first side to the second side.

9. The light emitting diode display device as claimed in claim 1, wherein the first circuit substrate further comprises: A plurality of first signal output pads electrically connected to the first signal output lines; A plurality of second signal output pads electrically connected to the second signal output lines, wherein the first signal output pads and the second signal output pads are arranged along the first side of the first thin film flip-chip packaging structure and bonded to the light emitting diode display panel; as well as A plurality of input pads are arranged along a second side of the first thin film flip-chip packaging structure opposite to the first side, wherein the first chip is located between the second chip and the second signal output pads.

10. A light emitting diode display device, comprising: Light emitting diode display panel; as well as The first thin film flip chip packaging structure is bonded to the light emitting diode display panel and includes: A first chip including a plurality of first signal output bumps; A second chip includes a plurality of second signal output bumps, wherein one of the first chip and the second chip is a light emitting signal control chip; and The first circuit substrate comprises: A plurality of first signal output lines are electrically connected to the first signal output bumps respectively; and A plurality of second signal output lines are electrically connected to the second signal output bumps respectively, and at least part of the second signal output lines extend from under one side of the first chip to under the first chip, and extend from under another side of the first chip beyond the first chip.

11. A light emitting diode display device, comprising: Light emitting diode display panel; as well as A thin film flip chip packaging structure is bonded to the light emitting diode display panel and comprises: An integrated chip includes a first circuit and a second circuit, wherein the first circuit is a light emitting signal control circuit, and wherein the second circuit is a gate signal control circuit, a data signal control circuit or a reset signal control circuit; and Circuit board, comprising: a plurality of first signal output lines electrically connected to the first circuit, wherein the first circuit outputs light emitting signals to the first signal output lines; and A plurality of second signal output lines are electrically connected to the second circuit, and the second circuit outputs a gate signal, a data signal or a reset signal to the second signal output lines.

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