Gate driving section and display device including same

Abstract

The invention discloses a gate driving section and a display device including the same. The gate drive unit includes first to sixth transistors and a first capacitor, a clock signal is applied to a control electrode of the first transistor, a gate output signal of a previous stage is applied to a first electrode of the first transistor, and a second electrode of the first transistor, control electrodes of the second transistor, the third transistor, and the fifth transistor are connected to a Q node. A first power supply voltage is applied to first electrodes of the second transistor, the fourth transistor and the first capacitor, a second electrode of the second transistor, a second electrode of the first capacitor, a first electrode of the third transistor and a control electrode of the fourth transistor are connected to a QB node, and a second power supply voltage is applied to second electrodes of the third transistor, the fifth transistor and the sixth transistor. The second electrode of the fourth transistor, the first electrode of the fifth transistor and the first electrode of the sixth transistor are connected to a GO node. The gate drive unit outputs the voltage of the GO node as a gate output signal.

Description

Technical Field

[0001] The present invention relates to a gate driving unit and a display device including the same, and more particularly to a gate driving unit that stably outputs a gate output signal by changing the structure of a pull-down unit and a display device including the same. Background Art

[0002] Generally, a display device includes a display panel and a display panel driving unit. The display panel includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels. The display panel driving unit includes a gate driving unit that provides gate signals to the plurality of gate lines, a data driving unit that provides data voltages to the data lines, and a driving control unit that controls the data driving unit and the gate driving unit.

[0003] Generally, the pull-down portion of the gate driving portion may be formed of a P-type transistor, and thus, a gate output signal of the gate driving portion may be unstable. Summary of the invention

[0004] Therefore, the technical problem of the present invention is focused on these aspects, and an object of the present invention is to provide a gate driving unit that stably outputs a gate output signal.

[0005] Another object of the present invention is to provide a display device including the gate driving unit.

[0006] A gate driving unit according to one embodiment for achieving the purpose of the present invention includes a plurality of stages, at least any one of the plurality of stages includes: a first transistor including a control electrode to which a clock signal is applied, a first electrode to which a gate output signal of a previous stage is applied, and a second electrode connected to a Q node; a second transistor including a control electrode connected to the Q node, a first electrode to which a first power supply voltage is applied, and a second electrode connected to a QB node; a third transistor including a control electrode connected to the Q node, a first electrode connected to the QB node, and a second electrode to which a second power supply voltage is applied; a fourth transistor including a control electrode connected to the QB node, a first electrode to which the first power supply voltage is applied, and a second electrode connected to a GO node for outputting a gate output signal; a fifth transistor including a control electrode connected to the Q node, a first electrode connected to the GO node, and a second electrode to which the second power supply voltage is applied; a sixth transistor including a first electrode connected to the GO node and a second electrode to which the second power supply voltage is applied; and a first capacitor including a first electrode to which the first power supply voltage is applied, and a second electrode connected to the QB node.

[0007] In one embodiment of the present invention, the sixth transistor may be an N-type transistor.

[0008] In one embodiment of the present invention, the sixth transistor may further include a control electrode connected to the QB node.

[0009] In one embodiment of the present invention, a ratio of the channel width to the channel length (W / L) of the fifth transistor may be different from a ratio of the channel width to the channel length (W / L) of the sixth transistor.

[0010] In one embodiment of the present invention, the channel length of the sixth transistor may be longer than the channel length of the fifth transistor.

[0011] In an embodiment of the present invention, the channel width of the sixth transistor may be shorter than the channel width of the fifth transistor.

[0012] In an embodiment of the present invention, when the gate output signal outputs a low voltage, the sixth transistor remains in a turned-on state.

[0013] In one embodiment of the present invention, the gate driving unit may further include: a ninth transistor including a control electrode to which an initialization signal is applied, a first electrode to which the first power supply voltage is applied, and a second electrode connected to the Q node.

[0014] In one embodiment of the present invention, the at least one stage may also include: a seventh transistor, including a control electrode connected to the Q node, a first electrode to which a third power supply voltage is applied, and a second electrode connected to the N node; and an eighth transistor, including a control electrode connected to the Q node, a first electrode connected to the N node, and a second electrode to which the second power supply voltage is applied, and the sixth transistor also includes a control electrode connected to the N node.

[0015] In an embodiment of the present invention, when the gate output signal has a low voltage, the sixth transistor remains in a turned-on state.

[0016] In an embodiment of the present invention, the third power supply voltage may be lower than the first power supply voltage.

[0017] In one embodiment of the present invention, the at least any one stage may further include: a ninth transistor including a control electrode to which an initialization signal is applied, a first electrode to which the first power supply voltage is applied, and a second electrode connected to the Q node.

[0018] A gate driving unit according to an embodiment for achieving the object of the present invention includes a plurality of stages, at least any one of the plurality of stages includes: a first transistor, applying a gate output signal of a previous stage to a Q node in response to a clock signal; a second transistor, applying a first power supply voltage to a QB node in response to a voltage of the Q node; a third transistor, applying a second power supply voltage to the QB node in response to a voltage of the Q node; a fourth transistor, applying the first power supply voltage to a GO node outputting a gate output signal in response to a voltage of the QB node; a fifth transistor, applying the second power supply voltage to the GO node in response to a voltage of the Q node; and a sixth transistor, applying the second power supply voltage to the GO node. The sixth transistor is an N-type transistor.

[0019] In an embodiment of the present invention, the sixth transistor may apply the second power supply voltage to the GO node in response to the voltage of the QB node.

[0020] In one embodiment of the present invention, a ratio of the channel width to the channel length (W / L) of the fifth transistor may be different from a ratio of the channel width to the channel length (W / L) of the sixth transistor.

[0021] In one embodiment of the present invention, it may be that the at least any one stage further includes: a seventh transistor, which applies a third power supply voltage lower than the first power supply voltage to the N node in response to the voltage of the Q node; and an eighth transistor, which applies the second power supply voltage to the N node in response to the voltage of the Q node, and the sixth transistor applies the second power supply voltage to the GO node in response to the voltage of the N node.

[0022] In an embodiment of the present invention, the at least any one stage may further include: a ninth transistor for applying the first power supply voltage to the Q node in response to an initialization signal.

[0023] In an embodiment of the present invention, when the output signal outputs a low voltage, the sixth transistor remains in a turned-on state.

[0024] A display device according to an embodiment for achieving the above-mentioned purpose of the present invention includes a display panel, a gate driving unit and a data driving unit. The data driving unit outputs a data voltage to a data line of the display panel. The gate driving unit outputs a gate output signal to a gate line of the display panel. The gate driving unit includes a plurality of stages, at least any one of the plurality of stages includes: a first transistor including a control electrode to which a clock signal is applied, a first electrode to which a gate output signal of a previous stage is applied, and a second electrode connected to a Q node; a second transistor including a control electrode connected to the Q node, a first electrode to which a first power supply voltage is applied, and a second electrode connected to a QB node; a third transistor including a control electrode connected to the Q node, a first electrode connected to the QB node, and a second electrode to which a second power supply voltage is applied; a fourth transistor including a control electrode connected to the QB node, a first electrode to which the first power supply voltage is applied, and a second electrode connected to a GO node outputting the gate output signal; a fifth transistor including a control electrode connected to the Q node, a first electrode connected to the GO node, and a second electrode to which the second power supply voltage is applied; a sixth transistor including a first electrode connected to the GO node and a second electrode to which the second power supply voltage is applied; and a first capacitor including a first electrode to which the first power supply voltage is applied, and a second electrode connected to the QB node. The gate driving unit outputs the voltage of the GO node as the gate output signal. The sixth transistor is an N-type transistor.

[0025] In an embodiment of the present invention, when the output signal outputs a low voltage, the sixth transistor remains in a turned-on state.

[0026] According to this gate driving unit and the display device including the same, since the pull-down transistor of the pull-down portion of the gate driving unit is formed by an N-type transistor, the gate output signal of the gate driving unit can be stably output as the power supply voltage rather than as a voltage obtained by subtracting the threshold voltage of the pull-down transistor from the power supply voltage.

[0027] In addition, in the case where the pull-down transistor is formed of an N-type transistor and the gate output signal outputs a low voltage when operating in a low frequency mode, the gate output signal can be stably output as the power supply voltage.

[0028] However, the effects of the present invention are not limited to the above-mentioned effects, and various extensions can be made within the scope not departing from the concept and field of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a block diagram showing a display device according to an embodiment of the present invention.

[0030] Figure 2 is a circuit diagram showing a gate driving unit according to an embodiment of the present invention.

[0031] Figure 3 FIG. 1 is a timing diagram showing an input signal applied to a gate driving unit and a gate output signal according to an embodiment of the present invention.

[0032] Figure 4 is a circuit diagram showing a gate driving unit according to an embodiment of the present invention.

[0033] Figure 5 is a circuit diagram showing a gate driving unit according to an embodiment of the present invention.

[0034] Figure 6 is a circuit diagram showing a gate driving unit according to an embodiment of the present invention.

[0035] Figure 7 is a circuit diagram showing a gate driving unit according to an embodiment of the present invention.

[0036] Figure 8 is a block diagram showing an electronic device according to an embodiment of the present invention.

[0037] Fig. 9 It is shown Figure 8 FIG. 1 is a diagram showing an example of an electronic device implemented as a smart phone.

[0038] (Explanation of Reference Numerals)

[0039] 100: Display panel

[0040] 200: Drive control unit

[0041] 300, 300A, 300B, 300C, 300D: Gate drive unit

[0042] 400: Gamma reference voltage generation unit

[0043] 500: Data-driven department DETAILED DESCRIPTION

[0044] Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

[0045] Figure 1 is a block diagram showing a display device according to an embodiment of the present invention.

[0046] Reference Figure 1 The display device includes a display panel 100 and a display panel driving unit. The display panel driving unit includes a driving control unit 200, a gate driving unit 300, a gamma reference voltage generating unit 400 and a data driving unit 500.

[0047] The display panel 100 includes a display portion that displays an image and a peripheral portion that is disposed adjacent to the display portion.

[0048] The display panel 100 includes gate lines, data lines, and pixel circuits P electrically connected to each of the gate lines and the data lines. The gate lines may extend in a first direction D1, and the data lines may extend in a second direction D2 crossing the first direction D1.

[0049] The drive control unit 200 receives input image data IMG and input control signal CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a main clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0050] The driving control unit 200 generates a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , and a data signal DATA according to the input image data IMG and the input control signal CONT.

[0051] The driving control unit 200 generates the first control signal CONT1 for controlling the operation of the gate driving unit 300 according to the input control signal CONT and outputs the first control signal CONT1 to the gate driving unit 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0052] The driving control unit 200 generates the second control signal CONT2 for controlling the operation of the data driving unit 500 according to the input control signal CONT and outputs the second control signal CONT2 to the data driving unit 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0053] The driving control unit 200 generates the data signal DATA according to the input image data IMG and outputs the data signal DATA to the data driving unit 500 .

[0054] The driving control unit 200 generates the third control signal CONT3 for controlling the operation of the gamma reference voltage generating unit 400 according to the input control signal CONT, and outputs the third control signal CONT3 to the gamma reference voltage generating unit 400 .

[0055] The gate driving part 300 generates a gate output signal G[N] for driving the gate line in response to the first control signal CONT1 received from the driving control part 200. The gate driving part 300 may output the gate output signal G[N] to the gate line.

[0056] In one embodiment of the present invention, the gate driving unit 300 may be integrated in the peripheral portion of the display panel 100. In one embodiment of the present invention, the gate driving unit 300 may be installed in the peripheral portion of the display panel 100.

[0057] The gamma reference voltage generating part 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving control part 200. The gamma reference voltage generating part 400 provides the gamma reference voltage VGREF to the data driving part 500. The gamma reference voltage VGREF has a value corresponding to each of the data signals DATA.

[0058] For example, the gamma reference voltage generating section 400 may be disposed in the driving control section 200 or in the data driving section 500 .

[0059] The data driving part 500 receives the second control signal CONT2 and the data signal DATA from the driving control part 200 , and receives the gamma reference voltage VGREF from the gamma reference voltage generating part 400 .

[0060] In one embodiment of the present invention, the data driving unit 500 may be integrated in the peripheral portion of the display panel 100. In one embodiment of the present invention, the data driving unit 500 may be installed in the peripheral portion of the display panel 100.

[0061] Figure 2 FIG. 4 is a circuit diagram showing a gate driving unit 300 according to an embodiment of the present invention. Figure 3 is a timing diagram showing an input signal applied to the gate driving unit 300 and a gate output signal according to an embodiment of the present invention.

[0062] Reference Figure 2In this embodiment, the gate driving unit 300 may include a plurality of stages, and any one of the plurality of stages may include: a first transistor T1, including a control electrode to which a clock signal CLK is applied, a first electrode to which a gate output signal G[N-1] of a previous stage is applied, and a second electrode connected to a Q node Q; a second transistor T2, including a control electrode connected to the Q node Q, a first electrode to which a first power supply voltage VDD1 is applied, and a second electrode connected to a QB node QB; a third transistor T3, including a control electrode connected to the Q node Q, a first electrode connected to the QB node QB, and a second electrode to which a second power supply voltage VSS is applied; a fourth transistor T4, The gate driving unit 300 includes a control electrode connected to the QB node QB, a first electrode to which the first power supply voltage VDD1 is applied, and a second electrode connected to the GO node GO; a fifth transistor T5 includes a control electrode connected to the Q node Q, a first electrode connected to the GO node GO, and a second electrode to which the second power supply voltage VSS is applied; a sixth transistor T6 includes a control electrode connected to the QB node QB, a first electrode connected to the GO node GO, and a second electrode to which the second power supply voltage VSS is applied; and a first capacitor C1 includes a first electrode to which the first power supply voltage VDD1 is applied, and a second electrode connected to the QB node QB. In addition, the gate driving unit 300 can output the voltage of the GO node GO as the gate output signal G[N]. For example, any one of the stages can have a 6T1C structure including six transistors and one capacitor. In this embodiment, the first power supply voltage VDD1 can have a high voltage VGH. In addition, in this embodiment, the second power supply voltage VSS can have a low voltage VGL lower than the high voltage VGH. In this embodiment, the clock signal CLK can periodically transition between the high voltage VGH and the low voltage VGL. However, the present invention is not limited to the voltage level of the clock signal CLK. In one embodiment, the gate output signal G[N-1] of the previous stage may be the horizontal start signal.

[0063] The first transistor T1 may apply the gate output signal G[N-1] of the previous stage to the Q node Q in response to the clock signal CLK. The second transistor T2 may apply the first power supply voltage VDD1 to the QB node QB in response to the voltage of the Q node Q. The third transistor T3 may apply the second power supply voltage VSS to the QB node QB in response to the voltage of the Q node Q. The fourth transistor T4 may apply the first power supply voltage VDD1 to the GO node GO in response to the voltage of the QB node QB. The fifth transistor T5 may apply the second power supply voltage VSS to the GO node GO in response to the voltage of the Q node Q. The sixth transistor T6 may apply the second power supply voltage VSS to the GO node GO.

[0064] In this embodiment, the first transistor T1, the second transistor T2, the fourth transistor T4 and the fifth transistor T5 may be P-type transistors. In addition, in this embodiment, the third transistor T3 and the sixth transistor T6 may be N-type transistors.

[0065] In the case of the existing gate driving unit, since the pull-down transistor included in the existing gate driving unit is formed by a P-type transistor, the gate output signal output by the existing gate driving unit is output as a voltage that rises at the threshold voltage of the pull-down transistor. Different from this, the gate driving unit 300 according to the present invention includes the sixth transistor T6, and the sixth transistor T6 is formed by an N-type transistor. Since the sixth transistor T6 is formed by an N-type transistor, the gate output signal G[N] can be stably output as the second power supply voltage VSS, rather than being output as a voltage obtained by subtracting the threshold voltage of the sixth transistor T6 from the second power supply voltage VSS.

[0066] Reference Figure 2 as well as Figure 3 , the driving timing of the gate driving part 300 may include a first period TP1, a second period TP2, a third period TP3, a fourth period TP4, a fifth period TP5 and a sixth period TP6.

[0067] In the first period TP1, the gate output signal G[N-1] of the previous stage may have the low voltage VGL, and the clock signal CLK may have the low voltage VGL. In the first period TP1, the gate output signal G[N-1] of the previous stage having the low voltage VGL may be applied to the Q node Q in response to the clock signal CLK having the low voltage VGL. Thus, the voltage of the Q node Q may be the low voltage VGL. In response to the voltage of the Q node Q, the second transistor T2 may be turned on, the third transistor T3 may be turned off, and the fifth transistor T5 may be turned on. As the second transistor T2 is turned on, the first power supply voltage VDD1 may be applied to the QB node QB. In response to the voltage of the QB node QB, the fourth transistor T4 may be turned off, and the sixth transistor T6 may be turned on. As the fourth transistor T4 is turned off and the fifth transistor T5 and the sixth transistor T6 are turned on, the second power supply voltage VSS may be applied to the GO node GO. Thus, in the first period TP1 , the gate output signal G[N] may have the low voltage VGL.

[0068] In the second period TP2, the gate output signal G[N-1] of the previous stage may have the high voltage VGH, and the clock signal CLK may have the high voltage VGH. In the second period TP2, the first transistor T1 may be kept in a cut-off state in response to the clock signal CLK having the high voltage VGH. Thus, the gate output signal G[N] may have the low voltage VGL.

[0069] In the third period TP3, the gate output signal G[N-1] of the previous stage may have the high voltage VGH, and the clock signal CLK may have the low voltage VGL. In the third period TP3, the gate output signal G[N-1] of the previous stage having the high voltage VGH may be applied to the Q node Q in response to the clock signal CLK having the low voltage VGL. Thus, the voltage of the Q node Q may be the high voltage VGH. In response to the voltage of the Q node Q, the second transistor T2 may be turned off, the third transistor T3 may be turned on, and the fifth transistor T5 may be turned off. As the third transistor T3 is turned on, the second power supply voltage VSS may be applied to the QB node QB. In response to the voltage of the QB node QB, the fourth transistor T4 may be turned on, and the sixth transistor T6 may be turned off. As the fourth transistor T4 is turned on and the fifth transistor T5 and the sixth transistor T6 are turned off, the first power supply voltage VDD1 may be applied to the GO node GO. Thus, in the third period TP3 , the gate output signal G[N] may have the high voltage VGH.

[0070] In the fourth period TP4 , the gate output signal G[N−1] of the previous stage has the high voltage VGH, so the gate output signal G[N] may have the high voltage VGH.

[0071] In the fifth period TP5, the gate output signal G[N-1] of the previous stage may have the low voltage VGL, and the clock signal CLK may have the high voltage VGH. In response to the clock signal CLK having the high voltage VGH, the first transistor T1 may be turned off. Thus, in the fifth period TP5, the gate output signal G[N] may be the high voltage VGH.

[0072] In the sixth period TP6, the gate output signal G[N-1] of the previous stage may have the low voltage VGL, and the clock signal CLK may have the low voltage VGL. In the sixth period TP6, the gate output signal G[N-1] of the previous stage having the low voltage VGL may be applied to the Q node Q in response to the clock signal CLK having the low voltage VGL. Thus, the voltage of the Q node Q may be the low voltage VGL. In response to the voltage of the Q node Q, the second transistor T2 may be turned on, the third transistor T3 may be turned off, and the fifth transistor T5 may be turned on. As the second transistor T2 is turned on, the first power supply voltage VDD1 may be applied to the QB node QB. In response to the voltage of the QB node QB, the fourth transistor T4 may be turned off, and the sixth transistor T6 may be turned on. As the fourth transistor T4 is turned off and the fifth transistor T5 and the sixth transistor T6 are turned on, the second power supply voltage VSS may be applied to the GO node GO. Therefore, in the sixth period TP6 , the gate output signal G[N] may be the low voltage VGL.

[0073] When the conventional gate driving unit operates in a low frequency mode, the gate output signal may be inaccurate in the sixth period TP6 due to the leakage current of the transistor. In contrast, the gate driving unit 300 according to the present embodiment can stably output the gate output signal G[N] in the sixth period TP6 by means of the sixth transistor T6 including an N-type transistor.

[0074] In one embodiment, the ratio (W / L) of the channel width and channel length of the sixth transistor T6 may be different from that of the fifth transistor T5. For example, the on-resistance of the sixth transistor T6 may be less than the on-resistance of the fifth transistor T5. For example, the on-resistance may generally refer to the resistance of a transistor when it is in an on state. In addition, the channel length of the sixth transistor T6 may be longer than the channel length of the fifth transistor T5. Moreover, the channel width of the sixth transistor may be shorter than the channel width of the fifth transistor.

[0075] In the sixth period TP6, since the on-resistance of the sixth transistor T6 is less than the fifth transistor T5, the current may flow preferentially to the fifth transistor T5. Thus, when the voltage of the GO node GO is a voltage obtained by subtracting the threshold voltage of the fifth transistor T5 from the low voltage VGL, the fifth transistor T5 may be turned off. According to the turning off of the fifth transistor T5, the resistance of the fifth transistor T5 may be greater. Since the resistance of the fifth transistor T5 becomes larger, the current may flow to the sixth transistor T6. Since the current flows to the sixth transistor T6, the voltage of the GO node GO may be the low voltage VGL.

[0076] Since the on-resistance of the sixth transistor T6 is smaller than that of the fifth transistor T5, the current of the sixth transistor T6 may flow less in the sixth period TP6. Therefore, the stress applied to the sixth transistor T6 can be reduced. Thus, the reliability and stability of the gate driving unit 300 can be improved.

[0077] Figure 4 is a circuit diagram showing a gate driving unit 300A according to an embodiment of the present invention.

[0078] The gate driving unit 300A is based on Figure 2 The gate driving unit 300A further includes a seventh transistor T7 and an eighth transistor T8, and the control electrode of the sixth transistor T6 is connected to the N node N instead of the QB node QB, which may be similar to the gate driving unit 300. Accordingly, the same reference numerals are used for the same or similar components, and repeated descriptions are omitted.

[0079] Reference Figure 3 as well as Figure 4 In the present embodiment, the gate driving unit 300A may further include: a seventh transistor T7, including a control electrode connected to the Q node Q, a first electrode to which the first power supply voltage VDD1 is applied, and a second electrode connected to the N node N; and an eighth transistor T8, including a control electrode connected to the Q node Q, a first electrode connected to the N node N, and a second electrode to which the second power supply voltage VSS is applied.

[0080] In this embodiment, the seventh transistor T7 may apply the first power supply voltage VDD1 to the N node N in response to the voltage of the Q node Q. The eighth transistor T8 may apply the second power supply voltage VSS to the N node N in response to the voltage of the Q node Q.

[0081] In the first period TP1, the gate output signal G[N-1] of the previous stage may have the low voltage VGL, and the clock signal CLK may have the low voltage VGL. In the first period TP1, the gate output signal G[N-1] of the previous stage having the low voltage VGL may be applied to the Q node Q in response to the clock signal CLK having the low voltage VGL. Thus, the voltage of the Q node Q may be the low voltage VGL. In response to the voltage of the Q node Q, the second transistor T2 may be turned on, the third transistor T3 may be turned off, the fifth transistor T5 may be turned on, the seventh transistor T7 may be turned on, and the eighth transistor T8 may be turned off. As the seventh transistor T7 is turned on, the first power supply voltage VDD1 may be applied to the N node N. As the second transistor T2 is turned on, the first power supply voltage VDD1 may be applied to the QB node QB. In response to the voltage of the QB node QB, the fourth transistor T4 may be turned off. The sixth transistor T6 may be turned on in response to the voltage of the N node N having the high voltage VGH. As the fourth transistor T4 is turned off and the fifth transistor T5 and the sixth transistor T6 are turned on, the second power supply voltage VSS may be applied to the GO node GO. Thus, in the first period TP1, the gate output signal G[N] may have the low voltage VGL.

[0082] In the second period TP2, the gate output signal G[N-1] of the previous stage may have the high voltage VGH, and the clock signal CLK may have the high voltage VGH. In the second period TP2, the first transistor T1 may be kept in a cut-off state in response to the clock signal CLK having the high voltage VGH. Thus, the gate output signal G[N] may have the low voltage VGL.

[0083] In the third period TP3, the gate output signal G[N-1] of the previous stage may have the high voltage VGH, and the clock signal CLK may have the low voltage VGL. In the third period TP3, the gate output signal G[N-1] of the previous stage having the high voltage VGH may be applied to the Q node Q in response to the clock signal CLK having the low voltage VGL. Thus, the voltage of the Q node Q may be the high voltage VGH. In response to the voltage of the Q node Q, the second transistor T2 may be turned off, the third transistor T3 may be turned on, the fifth transistor T5 may be turned off, the seventh transistor T7 may be turned off, and the eighth transistor T8 may be turned on. As the seventh transistor T7 is turned off and the eighth transistor T8 is turned on, the second power supply voltage VSS may be applied to the N node N. In response to the N node N having the second power supply voltage VSS, the sixth transistor T6 may be turned off. As the third transistor T3 is turned on, the second power supply voltage VSS may be applied to the QB node QB. In response to the voltage of the QB node QB, the fourth transistor T4 may be turned on. As the fourth transistor T4 is turned on and the fifth transistor T5 and the sixth transistor T6 are turned off, the first power supply voltage VDD1 may be applied to the GO node GO. Thus, in the third period TP3, the gate output signal G[N] may be the high voltage VGH.

[0084] In the fourth period TP4 , the gate output signal G[N−1] of the previous stage has the high voltage VGH, so the gate output signal G[N] may be the high voltage VGH.

[0085] In the fifth period TP5, the gate output signal G[N-1] of the previous stage may be the low voltage VGL, and the clock signal CLK may be the high voltage VGH. In response to the clock signal CLK having the high voltage VGH, the first transistor T1 may be turned off. Thus, in the fifth period TP5, the gate output signal G[N] may be the high voltage VGH.

[0086] In the sixth period TP6, the gate output signal G[N-1] of the previous stage may have the low voltage VGL, and the clock signal CLK may have the low voltage VGL. In the sixth period TP6, the gate output signal G[N-1] of the previous stage having the low voltage VGL may be applied to the Q node Q in response to the clock signal CLK having the low voltage VGL. Thus, the voltage of the Q node Q may be the low voltage VGL. In response to the voltage of the Q node Q, the second transistor T2 may be turned on, the third transistor T3 may be turned off, the fifth transistor T5 may be turned on, the seventh transistor T7 may be turned on, and the eighth transistor T8 may be turned off. As the seventh transistor T7 is turned on, the first power supply voltage VDD1 may be applied to the N node N. As the second transistor T2 is turned on, the first power supply voltage VDD1 may be applied to the QB node QB. In response to the voltage of the QB node QB, the fourth transistor T4 may be turned off. The sixth transistor T6 may be turned on in response to the voltage of the N node N having the high voltage VGH. As the fourth transistor T4 is turned off and the fifth transistor T5 and the sixth transistor T6 are turned on, the second power supply voltage VSS may be applied to the GO node GO. Thus, in the sixth period TP6, the gate output signal G[N] may be the low voltage VGL.

[0087] When the conventional gate driving unit operates in a low frequency mode, the gate output signal may be inaccurate in the sixth period TP6 due to the leakage current of the transistor. In contrast, the gate driving unit 300 according to the present embodiment can stably output the gate output signal G[N] in the sixth period TP6 by means of the sixth transistor T6 including an N-type transistor.

[0088] Figure 5 FIG. 4 is a circuit diagram showing a gate driving unit 300B according to an embodiment of the present invention.

[0089] The gate driving unit 300B applies the third power supply voltage VDD2 instead of the first power supply voltage VDD1 to the Figure 4 Except for the first electrode of the seventh transistor T7 of the gate driving unit 300A, the gate driving unit 300A may be similar to the gate driving unit 300A. Accordingly, the same reference numerals are used for the same or similar components, and repeated descriptions are omitted.

[0090] Reference Figure 5 , the third power supply voltage VDD2 instead of the first power supply voltage VDD1 may be applied to the first electrode of the seventh transistor T7 of the gate driving part 300B.

[0091] In this embodiment, the third power supply voltage VDD2 may be a voltage lower than the first power supply voltage VDD1. For example, the third power supply voltage VDD2 may have a voltage lower than the high voltage VGH.

[0092] Since the third power supply voltage VDD2 is a voltage lower than the high voltage VGH, a voltage lower than the high voltage VGH can be applied to the control electrode of the sixth transistor T6. Thus, the stress applied to the sixth transistor T6 can be relieved. Therefore, the stability and reliability of the gate driving unit 300B can be further improved.

[0093] Figure 6 is a circuit diagram showing a gate driving unit 300C according to an embodiment of the present invention.

[0094] The gate driving unit 300C is based on Figure 2 The gate driving unit 300C may be similar to the gate driving unit 300 except that the gate driving unit 300C further includes a ninth transistor T9. Accordingly, the same reference numerals are used for the same or similar components, and repeated descriptions are omitted.

[0095] Reference Figure 6 The gate driving unit 300C may further include: a ninth transistor T9 including a control electrode to which an initialization signal NESR is applied, a first electrode to which the first power supply voltage VDD1 is applied, and a second electrode connected to the Q node Q.

[0096] In this embodiment, when the initialization signal NESR has an active level, the first power supply voltage VDD1 may be applied to the Q node Q. Thus, the gate output signal G[N] of the gate driving part 300C may have the high voltage VGH.

[0097] In one embodiment, the initialization signal NESR may be a global signal applied to all stages of the gate driving unit 300C. Thus, the gate output signals G[N] of all stages of the gate driving unit 300C may have the high voltage VGH.

[0098] Figure 7 FIG. 4 is a circuit diagram showing a gate driving unit 300D according to an embodiment of the present invention.

[0099] The gate driving unit 300D is based on Figure 5 The gate driving unit 300D may be similar to the gate driving unit 300B except that the gate driving unit 300D further includes a ninth transistor T9. Accordingly, the same reference numerals are used for the same or similar components, and repeated descriptions are omitted.

[0100] Reference Figure 7 The gate driving unit 300D may further include: a ninth transistor T9 including a control electrode to which the initialization signal NESR is applied, a first electrode to which the first power supply voltage VDD1 is applied, and a second electrode connected to the Q node Q.

[0101] In this embodiment, when the initialization signal NESR has an active level, the first power supply voltage VDD1 may be applied to the Q node Q. Thus, the gate output signal G[N] of the gate driving part 300D may be the high voltage VGH.

[0102] In one embodiment, the initialization signal NESR may be a global signal applied to all stages of the gate driving unit 300D. Thus, the gate output signals G[N] of all stages of the gate driving unit 300D may output the high voltage VGH.

[0103] Figure 8 is a block diagram showing an electronic device 1000 according to an embodiment of the present invention. Fig. 9 It is shown Figure 8 FIG. 1 is a diagram showing an example of an electronic device implemented as a smart phone.

[0104] Reference Figure 8 as well as Fig. 9 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output device 1040, a power supply 1050, and a display device 1060. In this case, the display device 1060 may be Figure 1 In addition, the electronic device 1000 may further include various ports that can communicate with a graphics card, a sound card, a memory card, a USB device, etc. or communicate with other systems.

[0105] According to one embodiment, Fig. 9 As shown, the electronic device 1000 can be implemented as a smart phone. However, these are exemplary, and the electronic device 1000 is not limited thereto. For example, the electronic device 1000 can be implemented as a portable phone, a video phone, a smart tablet, a smart watch, a tablet PC, a car navigation system, a computer display, a notebook computer, a head-mounted display device, etc.

[0106] The processor 1010 may perform a specific calculation or task. According to an embodiment, the processor 1010 may be a microprocessor, a central processing unit, an application processor, etc. The processor 1010 may be connected to other components via an address bus, a control bus, and a data bus, etc. According to an embodiment, the processor 1010 may also be connected to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0107] The processor 1010 may Figure 1 The driving control unit 200 outputs the input image data IMG and the input control signal CONT.

[0108] The memory device 1020 may store data required for the operation of the electronic device 1000 . For example, the memory device 1020 may include an Erasable Programmable Read-Only Memory (EPROM) device, an Electrically Erasable Programmable Read-Only Memory (EEPROM) device, a flash memory device, a Phase Change Random Access Memory (PRAM) device, a Resistance Random Access Memory (RRAM) device, a Nano Floating Gate Memory (NFGM) device, a Polymer Random Access Memory (PoRAM) device, a Magnetic Random Access Memory (MRAM), a Ferroelectric Random Access Memory (FRAM) device, and / or a non-volatile memory device such as a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, or a DRAM device. Access Memory; SRAM) devices, mobile DRAM devices and other volatile memory devices.

[0109] The storage device 1030 may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc. The input-output device 1040 may include an input mechanism such as a keyboard, a numeric keypad, a touch pad, a touch screen, a mouse, and an output mechanism such as a speaker and a printer. According to an embodiment, the display device 1060 may also be included in the input-output device 1040. The power supply 1050 may supply the power required for the operation of the electronic device 1000. The display device 1060 may be connected to other components through the bus or other communication links.

[0110] Through the gate driving unit according to the present invention and the display device including the same as described above, a display device that outputs a stable gate output signal can be provided.

[0111] Although the above description is made with reference to the embodiments, it will be understood by those skilled in the art that the present invention can be modified and varied in various ways without departing from the concept and scope of the present invention described in the appended claims.

Claims

1. A gate driving unit, characterized in that: The method comprises a plurality of stages, wherein at least any one of the plurality of stages comprises: A first transistor including a control electrode to which a clock signal is applied, a first electrode to which a gate output signal of a previous stage is applied, and a second electrode connected to a Q node; A second transistor including a control electrode connected to the Q node, a first electrode to which a first power supply voltage is applied, and a second electrode connected to the QB node; a third transistor including a control electrode connected to the Q node, a first electrode connected to the QB node, and a second electrode to which a second power supply voltage is applied; a fourth transistor including a control electrode connected to the QB node, a first electrode to which the first power supply voltage is applied, and a second electrode connected to a GO node for outputting a gate output signal; a fifth transistor including a control electrode connected to the Q node, a first electrode connected to the GO node, and a second electrode to which the second power supply voltage is applied; a sixth transistor including a first electrode connected to the GO node and a second electrode to which the second power supply voltage is applied; and The first capacitor includes a first electrode to which the first power supply voltage is applied and a second electrode connected to the QB node.

2. The gate driving unit according to claim 1, characterized in that: The sixth transistor is an N-type transistor, and the fifth transistor is a P-type transistor.

3. The gate driving unit according to claim 2, characterized in that: The sixth transistor also includes a control electrode connected to the QB node.

4. The gate driving unit according to claim 3, characterized in that: A ratio of a channel width to a channel length of the fifth transistor is different from a ratio of a channel width to a channel length of the sixth transistor.

5. The gate driving unit according to claim 4, characterized in that: A channel length of the sixth transistor is longer than a channel length of the fifth transistor.

6. The gate driving unit according to claim 4, characterized in that: A channel width of the sixth transistor is shorter than a channel width of the fifth transistor.

7. The gate driving unit according to claim 3, characterized in that: When the gate output signal has a low voltage, the sixth transistor maintains a turned-on state.

8. The gate driving unit according to claim 3, characterized in that: The at least one level also includes: The ninth transistor includes a control electrode to which an initialization signal is applied, a first electrode to which the first power supply voltage is applied, and a second electrode connected to the Q node.

9. The gate driving unit according to claim 2, characterized in that: The at least one level also includes: a seventh transistor including a control electrode connected to the Q node, a first electrode to which a third power supply voltage is applied, and a second electrode connected to the N node; and an eighth transistor including a control electrode connected to the Q node, a first electrode connected to the N node, and a second electrode to which the second power supply voltage is applied, The sixth transistor further includes a control electrode connected to the N node.

10. The gate driving unit according to claim 9, characterized in that: When the gate output signal has a low voltage, the sixth transistor maintains a turned-on state.

11. The gate driving unit according to claim 9, characterized in that: The third power supply voltage is lower than the first power supply voltage.

12. The gate driving unit according to claim 9, characterized in that: The at least one level also includes: The ninth transistor includes a control electrode to which an initialization signal is applied, a first electrode to which the first power supply voltage is applied, and a second electrode connected to the Q node.

13. A gate driving unit, characterized in that: The method comprises a plurality of stages, wherein at least any one of the plurality of stages comprises: a first transistor that applies a gate output signal of a previous stage to a Q node in response to a clock signal; a second transistor that applies a first power supply voltage to a QB node in response to a voltage at the Q node; a third transistor that applies a second power supply voltage to the QB node in response to the voltage of the Q node; a fourth transistor that applies the first power supply voltage to a GO node in response to a voltage at the QB node; a fifth transistor that applies the second power supply voltage to the GO node in response to the voltage of the Q node; and a sixth transistor, applying the second power supply voltage to the GO node, Outputting the voltage of the GO node as a gate output signal, The sixth transistor is an N-type transistor.

14. The gate driving unit according to claim 13, characterized in that: The sixth transistor applies the second power supply voltage to the GO node in response to the voltage of the QB node.

15. The gate driving unit according to claim 14, characterized in that: A ratio of a channel width to a channel length of the fifth transistor is different from a ratio of a channel width to a channel length of the sixth transistor.

16. The gate driving unit according to claim 13, characterized in that: The at least one level also includes: a seventh transistor that applies a third power supply voltage lower than the first power supply voltage to an N node in response to the voltage of the Q node; and an eighth transistor that applies the second power supply voltage to the N node in response to the voltage of the Q node, The sixth transistor applies the second power supply voltage to the GO node in response to a voltage of the N node.

17. The gate driving unit according to claim 13, characterized in that: The at least one level also includes: A ninth transistor applies the first power supply voltage to the Q node in response to an initialization signal.

18. The gate driving unit according to claim 13, characterized in that: When the gate output signal has a low voltage, the sixth transistor maintains a turned-on state.

19. A display device, characterized in that: include: Display panel; A gate driving unit, outputting a gate output signal to a gate line of the display panel; as well as A data driving unit outputs a data voltage to the data line of the display panel, The gate driving unit includes a plurality of stages, and at least any one of the plurality of stages includes: A first transistor including a control electrode to which a clock signal is applied, a first electrode to which a gate output signal of a previous stage is applied, and a second electrode connected to a Q node; A second transistor including a control electrode connected to the Q node, a first electrode to which a first power supply voltage is applied, and a second electrode connected to the QB node; a third transistor including a control electrode connected to the Q node, a first electrode connected to the QB node, and a second electrode to which a second power supply voltage is applied; a fourth transistor including a control electrode connected to the QB node, a first electrode to which the first power supply voltage is applied, and a second electrode connected to a GO node outputting the gate output signal; a fifth transistor including a control electrode connected to the Q node, a first electrode connected to the GO node, and a second electrode to which the second power supply voltage is applied; a sixth transistor including a first electrode connected to the GO node and a second electrode to which the second power supply voltage is applied; and a first capacitor including a first electrode to which the first power supply voltage is applied and a second electrode connected to the QB node, The sixth transistor is an N-type transistor.

20. The display device according to claim 19, characterized in that When the gate output signal has a low voltage, the sixth transistor maintains a turned-on state.

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