Gate driving circuit, driving circuit of display panel and display device

Abstract

The invention provides a gate drive circuit, a drive circuit of a display panel and a display device.The gate drive circuit comprises a plurality of gate drive units, clock signal lines, repair lines and a plurality of thrust circuits which are cascaded in sequence; the clock signal lines comprise first clock signal lines arranged side by side in the first direction and second clock signal lines arranged side by side in the second direction, the repair lines comprise a first repair line and a second repair line, and the second repair line comprises a first repair section and a second repair section. The first repairing line and the second repairing line are in short circuit with the corresponding first clock signal line and the second clock signal line on the abnormal clock path correspondingly, the thrust circuit converts the input first clock signal line, improves thrust and then outputs the thrust to the clock path of the second clock signal, and therefore the abnormal clock signal line is replaced. The problems of picture transverse lines and abnormity are avoided, and the yield of the display panel is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of display panels, and in particular relates to a gate driving circuit, a driving circuit of a display panel, and a display device. Background Art

[0002] The driving circuit of the display panel usually includes a gate driving circuit, which includes multiple cascaded gate driving units and is connected to the scanning lines of the display panel. When driving scanning, the cascaded gate driving units receive corresponding clock signals and output row scanning signals line by line to scan the display panel line by line.

[0003] When the clock signal line input by the gate driving circuit is broken or short-circuited with another clock line, it will cause horizontal lines and abnormal images on the display panel, and even cause the display panel to be scrapped. Summary of the invention

[0004] The object of the present invention is to provide a gate driving circuit, aiming to solve the problem that when a clock signal line is abnormal in a traditional gate driving circuit, a horizontal line or an abnormal picture appears on a display panel.

[0005] A first aspect of an embodiment of the present invention provides a gate driving circuit, comprising: A plurality of gate driving units cascaded in sequence, wherein the plurality of gate driving units are used to be sequentially connected to a plurality of scanning lines of the display panel respectively to sequentially output row scanning signals; The clock signal lines include a plurality of first clock signal lines arranged in parallel along a first direction and a plurality of second clock signal lines arranged in parallel along a second direction, each of the second clock signal lines is connected to a first clock signal line and a gate driving unit, and the first direction and the second direction intersect; A repair line, comprising a plurality of first repair lines and a plurality of second repair lines, wherein the second repair line comprises a first repair section and a second repair section connected to each other, wherein the plurality of first repair lines and the plurality of first repair sections are arranged on both sides of a plurality of second clock signal lines along the second direction, are insulated from the plurality of first clock signal lines and are arranged in a stacked manner, and the plurality of second repair sections are insulated from the plurality of second clock signal lines and are arranged in a stacked manner, respectively; wherein the first repair line and the first repair section are respectively used to short-circuit the first clock signal lines stacked in an abnormal clock path, and the second repair section is used to short-circuit the second clock signal lines stacked in an abnormal clock path, and the clock path is a first clock signal line and a second clock signal line connected to each other; A plurality of thrust circuits, each of which is connected to a first patch line and a second patch segment respectively, and the thrust circuit is used to input a first clock signal corresponding to the first patch line and output a second clock signal corresponding to the thrust to the second patch segment.

[0006] Optionally, the thrust circuit includes a first operational amplifier, a first resistor, a second resistor, a third resistor, a first capacitor and a second capacitor; The non-phase input terminal of the first operational amplifier constitutes the signal input terminal of the thrust circuit and is used to connect the first repair line, the inverting input terminal of the first operational amplifier, the first end of the first capacitor and the first end of the first resistor are connected, the output terminal of the first operational amplifier is connected to the first end of the second resistor, the second end of the second resistor, the second end of the first resistor, the second end of the first capacitor and the first end of the third resistor are connected, the second end of the third resistor and the first end of the second capacitor are connected to constitute the signal output terminal of the thrust circuit and are used to connect the second repair segment, and the second end of the second capacitor is grounded.

[0007] Optionally, the thrust circuit further includes a fourth resistor, a fifth resistor, a first transistor and a second transistor; The first end of the fourth resistor is used to input the first row start signal, the second end of the fourth resistor is connected to the collector of the first transistor, the base of the first transistor, the base of the second transistor and the first end of the first resistor are connected, the emitter of the first transistor, the collector of the second transistor and the second end of the first resistor are connected, the emitter of the second transistor is connected to the first end of the fifth resistor, the second end of the fifth resistor is used to input the first row close signal, and the voltage of the first row start signal is greater than the voltage of the first row close signal.

[0008] Optionally, the thrust circuit includes a second operational amplifier, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a third capacitor, a fourth capacitor, a first diode, a second diode, a third transistor and a fourth transistor; The non-inverting input terminal of the second operational amplifier constitutes the signal input terminal of the thrust circuit and is used to connect the first repair line, the inverting input terminal of the second operational amplifier, the first end of the third capacitor and the first end of the sixth resistor are connected, the output terminal of the second operational amplifier, the first end of the seventh resistor, the cathode of the first diode and the anode of the second diode are connected, the second end of the seventh resistor, the second end of the sixth resistor, the second end of the third capacitor, the first end of the eighth resistor, the emitter of the third transistor and the collector of the fourth transistor are connected, the anode of the first diode, the base of the third transistor and the collector of the ninth resistor are connected. The first end is connected, the base of the fourth transistor, the cathode of the second diode and the first end of the tenth resistor are connected, the second end of the ninth resistor is connected to the first end of the eleventh resistor and is used to input the second row start signal, the second end of the eleventh resistor is connected to the collector of the third transistor, the second end of the tenth resistor is connected to the first end of the twelfth resistor and is used to input the second row close signal, the second end of the twelfth resistor is connected to the emitter of the fourth transistor, the second end of the eighth resistor is connected to the first end of the fourth capacitor to form the signal output end of the thrust circuit and is used to connect the second patching section, and the second end of the fourth capacitor is grounded; The second row on signal is a positive voltage signal, the second row off signal is a negative voltage signal, and the absolute value of the voltage of the second row on signal is equal to the absolute value of the voltage of the second row off signal.

[0009] Optionally, the thrust circuit includes a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a first field effect transistor and a second field effect transistor; The first end of the thirteenth resistor is connected to the power management integrated circuit and is used to input the third row start signal, the first end of the fourteenth resistor is connected to the power management integrated circuit and is used to input the third row shutdown signal, the second end of the thirteenth resistor is connected to the drain of the first field effect transistor, the source of the first field effect transistor, the drain of the second field effect transistor and the first end of the fifteenth resistor are connected, the gate of the first field effect transistor and the gate of the second field effect transistor are connected to form the signal input end of the thrust circuit and are used to connect the first patch line, and the second end of the fifteenth resistor constitutes the signal output end of the thrust circuit and is used to connect the second patch segment; The voltage of the third row on signal is greater than the voltage of the third row off signal.

[0010] Optionally, the gate drive circuit further includes: an inverting circuit, connected to the thrust circuit, for inverting an output signal of the thrust circuit and outputting a third clock signal; A third repair line is arranged in parallel with the second repair line and spaced apart from each other, and the third repair line is connected to the inverter circuit.

[0011] Optionally, an isolation layer is further provided between the third repairing line and the second repairing line.

[0012] Optionally, the inverting circuit includes a third operational amplifier, a sixteenth resistor and a seventeenth resistor; The first end of the sixteenth resistor is used to connect to the output end of the thrust circuit, the second end of the sixteenth resistor, the inverting input end of the third operational amplifier and the first end of the seventeenth resistor are connected, the non-inverting input end of the third operational amplifier is grounded, and the output end of the third operational amplifier and the second end of the seventeenth resistor are connected to form the output end of the inverting circuit.

[0013] A second aspect of an embodiment of the present invention proposes a driving circuit for a display panel, comprising a power management integrated circuit, a timing controller, a source driving circuit and a gate driving circuit as described above, wherein the source driving circuit and the gate driving circuit are respectively connected to the display panel, and the timing controller is respectively connected to the power management integrated circuit, the source driving circuit and the gate driving circuit.

[0014] A third aspect of an embodiment of the present invention provides a display device, including a display panel and a driving circuit of the display panel as described above, wherein the driving circuit of the display panel is connected to the display panel.

[0015] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: the above-mentioned gate driving circuit includes a plurality of gate driving units, clock signal lines, repair lines and a plurality of thrust circuits cascaded in sequence, the clock signal lines include a first clock signal line arranged side by side along a first direction and a second clock signal line arranged side by side along a second direction, the repair lines include a first repair line and a second repair line, the second repair line includes a first repair section and a second repair section, when an abnormal clock path occurs, the first repair line and the second repair line are short-circuited with respect to the first clock signal line and the second clock signal line corresponding to the abnormal clock path, the thrust circuit converts the input first clock signal line and increases the thrust and then outputs the second clock signal on the clock path, thereby replacing the abnormal clock signal line, avoiding horizontal lines and abnormal problems on the screen, and improving the yield of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A first structural schematic diagram of a gate driving circuit provided in Embodiment 1 of the present invention; Figure 2 A second structural schematic diagram of the gate driving circuit provided in the first embodiment of the present invention; Figure 3 A third structural schematic diagram of the gate driving circuit provided in the first embodiment of the present invention; Figure 4 A fourth structural schematic diagram of the gate driving circuit provided in the first embodiment of the present invention; Figure 5 A first circuit diagram of a thrust circuit provided in Embodiment 2 of the present invention; Figure 6 A second circuit diagram of a thrust circuit provided in Embodiment 2 of the present invention; Figure 7 A waveform diagram of a second clock signal in a thrust circuit provided in Embodiment 3 of the present invention; Figure 8 A circuit diagram of a thrust circuit provided in Embodiment 3 of the present invention; Fig. 9 A circuit diagram of a thrust circuit provided in Embodiment 4 of the present invention; Fig.10 A schematic diagram of the structure of a gate drive circuit provided in Embodiment 5 of the present invention; Fig.11 A circuit diagram of a thrust circuit and an inverting circuit provided in Embodiment 5 of the present invention; Fig.12 This is a schematic structural diagram of a display panel driving circuit and a display device provided in Embodiment 6 and Embodiment 7 of the present invention.

[0017] Among them, the reference numerals in the figures are: 1. Driving circuit of display panel; 2. Display panel; 100. Gate driving circuit; 200. Source driving circuit; 300. Timing controller; 400. Power management integrated circuit; 110. Driving module; 120. Clock signal line; 130. First repair line; 140. Second repair line; 150. Thrust circuit; 160. Inverting circuit; 170. Third repair line; 180. Isolation layer; 111. Gate driving unit; 121. First clock signal line; 122. Second clock signal line; 131. Third repair section; 132. Fourth repair section; 141. First repair section; 142. Second repair section; 101. Break point; 102. Short circuit point; 103. Laser point; U1, the first operational amplifier; U2, the second operational amplifier; U3, the third operational amplifier; R1, the first resistor; R2, the second resistor; R3, the third resistor; R4, the fourth resistor; R5, the fifth resistor; R6, the sixth resistor; R7, the seventh resistor; R8, the eighth resistor; R9, the ninth resistor; R10, the tenth resistor; R11, the eleventh resistor; R12, the twelfth resistor; R13, the thirteenth resistor; R14, the fourteenth resistor; R15, the fifteenth resistor; R16, the sixteenth resistor; R17, the seventeenth resistor; C1, the first capacitor; C2, the second capacitor; C3, the third capacitor; C4, the fourth capacitor; Q1, the first triode; Q2, the second triode; Q3, the third triode; Q4, the fourth triode; D1, the first diode; D2, the second diode; M1, the first field effect transistor; M2, the second field effect transistor; clk1, first clock signal; clk2, second clock signal; clk3, third clock signal; VGH1, first row start signal; VGH2, second row start signal; VGH3, third row start signal; VGL1, first row close signal; VGL2, second row close signal; VGL3, third row close signal. DETAILED DESCRIPTION

[0018] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0019] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0020] Embodiment 1 The first aspect of the embodiment of the present invention proposes a gate driving circuit 100 for outputting row scanning signals to the display panel 2 row by row to drive the display panel 2 to turn on row by row. The row turn-on signals cooperate with the data signals input to the display panel 2 to drive the display panel 2 to display corresponding image information.

[0021] like Figure 1 and Figure 2 As shown, the gate driving circuit 100 includes: A plurality of gate driving units 111 cascaded in sequence, the plurality of gate driving units 111 being used to be sequentially connected to a plurality of scanning lines of the display panel 2 respectively, so as to sequentially output row scanning signals; The clock signal line 120 includes a plurality of first clock signal lines 121 arranged in parallel along a first direction and a plurality of second clock signal lines 122 arranged in parallel along a second direction, each second clock signal line 122 is connected to a first clock signal line 121 and a gate driving unit 111, and the first direction and the second direction intersect; A repair line, comprising a plurality of first repair lines 130 and a plurality of second repair lines 140, wherein the second repair line 140 comprises a first repair section 141 and a second repair section 142 connected to each other, wherein the plurality of first repair lines 130 and the plurality of first repair sections 141 are arranged on both sides of a plurality of second clock signal lines 122 along a second direction, and are insulated from the plurality of first clock signal lines 121 and are arranged in a stacked manner, and the plurality of second repair sections 142 are insulated from the plurality of second clock signal lines 122 and are arranged in a stacked manner, respectively; wherein the first repair line 130 and the first repair section 141 are respectively used to short-circuit the stacked first clock signal lines 121 in an abnormal clock path, and the second repair section 142 is used to short-circuit the stacked second clock signal lines 122 in the abnormal clock path, and the clock path is a first clock signal line 121 and a second clock signal line 122 connected to each other; A plurality of thrust circuits 150 are each connected to a first patch line 130 and a second patch section 142 . The thrust circuit 150 is used to input a first clock signal clk1 corresponding to the first patch line 130 and output a second clock signal clk2 corresponding to the thrust to the second patch section 142 .

[0022] In this embodiment, the gate driving circuit 100 is a GOA (Gate Driver on Array) circuit. The GOA circuit integrates the TFT (Thin Film Transistor) in the gate driving circuit 100 on the array substrate, thereby eliminating the gate driving integrated circuit part originally arranged outside the array substrate, thereby reducing the cost of the product from two aspects of material cost and process steps.

[0023] The GOA circuit usually includes a plurality of cascaded gate driving units 111, which may be a shift register or other structure. The plurality of cascaded gate driving units 111 constitute a driving module 110, and the gate driving unit 111 is connected to a scanning line located in a display area of ​​the display panel 2. When the gate driving circuit 100 is working normally, the front-end timing controller 300 outputs control signals such as a clock signal, a row start signal, and a row close signal to the gate driving circuit 100, and multiple clock signals are transmitted to the gate driving circuit 100 through a first clock signal line 121 and a second clock signal line 122. Each gate driving unit 111 receives one or more clock signals, and converts them into row start signals, which are output to each row of pixel units of the display panel 2, so as to turn on each row of pixel units row by row.

[0024] Among them, the diameter of the first clock signal line 121 is larger than that of the second clock signal line 122. The first clock signal line 121 can be connected to one or more second clock signal lines 122 and transmit the same clock signal to the connected second clock signal lines 122 and the rear-end gate driving unit 111. The multiple first clock signal lines 121 can respectively receive clock signals of different phases.

[0025] The abnormal situation of the clock signal line 120 may include a disconnection or a short circuit, such as Figure 2 As shown in the figure, the line break mainly occurs on the first clock signal line 121, for example, a line break point 101 appears in the middle of the first clock signal line 121 of the first path, or a line break point 101 appears in the middle of the first clock signal line 121 of the second path, and the short circuit mainly occurs at the second clock signal line 122 at the overlapping position of the first clock signal line 121, for example, when the second clock line of the first path connected to the first clock signal line 121 of the first path crosses the first clock signal line 121 of the second path, a short circuit point 102 appears at the overlapping position, or the second clock line of the first path connected to the first clock signal line 121 of the second path crosses the first clock signal line 121 of the second path. When the second clock line of the third path crosses the first clock signal line 121 of the third path, a short-circuit point 102 appears at the overlapping position. When a break point 101 appears, the original corresponding input clock signal cannot be effectively transmitted to the gate driving unit 111 at the back end, and the gate driving unit 111 cannot effectively output the row start signal, resulting in horizontal lines and picture abnormalities on the display panel 2. When the short-circuit point 102 appears, crosstalk will occur between the clock signals of the two adjacent paths, resulting in the gate driving unit 111 at the back end receiving a non-matching clock signal, which in turn causes the display panel 2 to have a picture abnormality or multiple horizontal lines, causing display abnormalities.

[0026] In order to solve the problem of a break point 101 or a short circuit point 102 on the display panel 2, a corresponding repair line and a thrust circuit 150 are also provided in the gate drive circuit 100. The repair line is used to short-circuit the corresponding first clock signal line 121 and the second clock line, and transfer the clock signal originally input to the abnormal clock path to the corresponding second clock signal line 122 and the gate drive unit 111 at the rear end. At the same time, since the repair line is longer than the original clock path, the signal is attenuated, which will cause the gate drive unit 111 at the rear end to be unable to drive normally, resulting in an abnormal picture. For this reason, the thrust circuit 150 is connected between the first repair line 130 and the second repair line 140, and the clock signal is amplified and the amplitude is increased to improve the driving force of the clock signal.

[0027] by Figure 2 For example, assuming that the first clock signal line 121 includes 8 routes, and the second clock signal line 122 includes 10 routes, when the first clock signal line 121 on the left is the first clock signal line 121 of the first route, the first clock signal line 121 on the right is the first clock signal line 121 of the eighth route, the second clock signal line 122 at the top is the second clock signal line 122 of the first route, and the second clock signal line 122 at the bottom is the second clock signal line 122 of the tenth route.

[0028] like Figure 3 As shown, when a line break abnormality occurs in the first clock path, the first clock path includes a first clock signal line 121 of the first path and a second clock signal line 122 of the first path that are connected, and a line break point 101 occurs in the middle of the first clock signal line 121 of the first path. At this time, the second clock signal line 122 of the first path connected to the first clock signal line 121 of the first path has no clock signal input.

[0029] In order to solve this problem, the first repair line 130 at the laser connection stacking position and the first clock signal line 121 of the first path, as well as the first repair section 141 at the laser connection stacking position and the first clock signal line 121 of the first path, the laser point 103 located at the lower part and the first repair line 130 transmit the first clock signal clk1 input to the first clock signal line 121 of the first path to the thrust circuit 150, the thrust circuit 150 realizes the amplification and amplitude enhancement of the first clock signal clk1, and outputs the second clock signal clk2 with the same phase, the amplitude of the second clock signal clk2 is greater than the amplitude of the first clock signal clk1, thereby improving the driving force of the clock signal and realizing clock signal compensation.

[0030] The second clock signal clk2 output by the thrust circuit 150 is transmitted to the upper laser point 103 via the second patch section 142 and the first patch section 141, and is transmitted to the second clock signal line 122 of the first path connected to the first clock signal line 121 of the first path. The second clock signal clk2 is output to the rear gate driving unit 111 via the second clock signal line 122, so as to ensure that the rear gate driving unit 111 is driven normally and improve the display effect.

[0031] like Figure 4 As shown, when a short-circuit point 102 appears, for example, the second clock signal line 122 of the tenth path connected to the first clock signal line 121 of the second path is short-circuited with the first clock signal line 121 of the third path, and the abnormal clock path is the first clock signal line 121 of the second path and the second clock signal line 122 of the tenth path. At this time, the second clock signal line 122 before and after the short-circuit point 102 is firstly disconnected by laser, and at the same time, the first clock signal line 121 of the second path and the first repair line 130 at the stacking position of the laser short circuit, and the second clock signal line 122 and the second repair section 142 of the tenth path at the stacking position of the laser short circuit, the first clock signal clk1 input to the first clock signal line 121 of the second path is transferred and output to the first repair line 130 and the thrust circuit 150, the thrust circuit 150 realizes the amplification and amplitude enhancement of the first clock signal clk1, and outputs the second clock signal clk2 with the same phase, the amplitude of the second clock signal clk2 is greater than the amplitude of the first clock signal clk1, the driving force of the clock signal is improved, and the clock signal compensation is realized.

[0032] The second clock signal clk2 output by the thrust circuit 150 is transmitted to the second clock signal line 122 of the tenth path via the second patch section 142 and the laser point 103 located at the lower right corner. The second clock signal clk2 is output to the rear gate driving unit 111 via the second clock signal line 122 to ensure that the rear gate driving unit 111 is driven normally and improve the display effect.

[0033] The first repair line 130 may include a third repair segment 131 and a fourth repair segment 132 connected to each other. The third repair segment 131 is stacked on the plurality of first clock signal lines 121 . The fourth repair segment 132 is used to connect the third repair segment 131 and the fourth repair segment 132 .

[0034] The first repair line 130, the second repair line 140 and the thrust circuit 150 constitute a repair unit for replacing an abnormal clock path. When multiple abnormal clock paths appear, multiple repair units may be set, and the specific number is not limited.

[0035] The thrust circuit 150 may adopt a corresponding signal amplification circuit, a push-pull circuit, etc., and the specific structure is not limited.

[0036] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: the gate drive circuit 100 includes a plurality of gate drive units 111, a clock signal line 120, a repair line and a plurality of thrust circuits 150 which are cascaded in sequence; the clock signal line 120 includes a first clock signal line 121 arranged side by side along a first direction and a second clock signal line 122 arranged side by side along a second direction; the repair line includes a first repair line 130 and a second repair line 140; the second repair line 140 includes a first repair section 141 and a second repair section 142; when an abnormal clock path occurs, the first repair line 130 and the second repair line 140 are short-circuited with respect to the first clock signal line 121 and the second clock signal line 122 corresponding to the abnormal clock path; the thrust circuit 150 converts the input first clock signal line 121 and increases the thrust and then outputs the second clock signal clk2 on the clock path, thereby replacing the abnormal clock signal line 120, avoiding horizontal lines and abnormal problems on the screen, and improving the yield of the display panel 2.

[0037] Embodiment 2 like Figure 5 As shown, in an optional embodiment, the thrust circuit 150 includes a first operational amplifier U1, a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1 and a second capacitor C2; The non-inverting input terminal of the first operational amplifier U1 constitutes the signal input terminal of the thrust circuit 150 and is used to connect the first repair line 130, the inverting input terminal of the first operational amplifier U1, the first end of the first capacitor C1 and the first end of the first resistor R1 are connected, the output terminal of the first operational amplifier U1 is connected to the first end of the second resistor R2, the second end of the second resistor R2, the second end of the first resistor R1, the second end of the first capacitor C1 and the first end of the third resistor R3 are connected, the second end of the third resistor R3 and the first end of the second capacitor C2 are connected to constitute the signal output terminal of the thrust circuit 150 and are used to connect the second repair section 142, and the second end of the second capacitor C2 is grounded.

[0038] In this embodiment, the first operational amplifier U1, the first resistor R1, the second resistor R2 and the first capacitor C1 constitute a positive phase amplifier, and amplify the input first clock signal clk1. The third resistor R3 and the second capacitor C2 constitute a filter circuit, which is used to filter out noise in the amplified first clock signal clk1 and filter and output the second clock signal clk2.

[0039] Among them, the gain of the positive-phase amplifier formed by the operational amplifier is limited. When the break point 101 or the short-circuit point 102 appears at different positions of the first clock signal line 121, the repair line after the laser short-circuit may be different, the attenuation degree of the first clock signal clk1 is different, and the amplitude of the second clock signal clk2 output to the gate drive unit 111 is different. Therefore, it is necessary to set a thrust circuit 150 with different gains.

[0040] In an alternative embodiment, if Figure 6 As shown, the thrust circuit 150 further includes a fourth resistor R4, a fifth resistor R5, a first transistor Q1 and a second transistor Q2; A first end of the fourth resistor R4 is used to input a first row start signal VGH1, a second end of the fourth resistor R4 is connected to the collector of the first transistor Q1, a base of the first transistor Q1, a base of the second transistor Q2 and a first end of the first resistor R1 are connected, an emitter of the first transistor Q1, a collector of the second transistor Q2 and a second end of the first resistor R1 are connected, an emitter of the second transistor Q2 is connected to a first end of the fifth resistor R5, a second end of the fifth resistor R5 is used to input a first row stop signal VGL1, a voltage of the first row start signal VGH1 is greater than a voltage of the first row stop signal VGL1.

[0041] In this embodiment, the fourth resistor R4, the fifth resistor R5, the first transistor Q1 and the second transistor Q2 constitute a push-pull circuit, which converts the input clock signal into a second clock signal clk2 composed of a first row start signal VGH1 and a first row stop signal VGL1. The first row start signal VGH1 constitutes a high potential of the second clock signal clk2, and the first row stop signal VGL1 constitutes a low potential of the second clock signal clk2.

[0042] The first transistor Q1 may be an NPN transistor, and the second transistor Q2 may be a PNP transistor.

[0043] The push-pull circuit can further amplify the input clock signal and further increase the amplitude of the clock signal.

[0044] When different abnormal images are visually observed or different disconnection points 101 or short-circuit points 102 are detected, the required thrust magnitude is determined, and a selection is made accordingly as to whether to switch to a different thrust circuit 150 .

[0045] For example Figure 2As shown, after the clock path corresponding to the laser abnormality is followed, the path of the repair line through which the break point 101 of the first clock signal line 121 located in the first path passes is smaller than that of the break point 101 of the first clock signal line 121 located in the second path. For the break point 101 of the first clock signal line 121 located in the first path, the clock signal attenuation is small, and a thrust circuit 150 with smaller thrust can be selected. For this purpose, the first repair line 130 and the second repair segment 142 can be directly connected first. When it is detected that the brightness of the display screen is slightly dim, the thrust required by the thrust circuit 150 is small, and the push-pull circuit can be exited by welding or laser, and the thrust circuit 150 is connected between the first repair line 130 and the second repair segment 142. The thrust circuit 150 composed of the first operational amplifier U1, the first resistor R1, the second resistor R2 and the first capacitor C1 performs signal amplification, thereby improving the brightness of the current display screen.

[0046] Alternatively, after the clock path corresponding to the laser abnormality, the path of the repair line through which the break point 101 of the first clock signal line 121 located in the first path passes is smaller than that of the break point 101 of the first clock signal line 121 located in the second path. For the break point 101 of the first clock signal line 121 located in the second path, the clock signal attenuation is large, and a thrust circuit 150 with a larger thrust can be selected. When it is detected that the display screen brightness is dark, the thrust circuit 150 requires a large thrust, and the push-pull circuit can be connected to the thrust circuit 150 by welding or laser. The thrust circuit 150 is connected between the first repair line 130 and the second repair segment 142, and the positive phase amplifier and push-pull circuit composed of the first operational amplifier U1, the first resistor R1, the second resistor R2 and the first capacitor C1 perform two signal amplifications, thereby greatly improving the brightness of the current display screen, so that the thrust circuit 150 after repairing different break points 101 or short-circuit points 102 provides a second clock signal clk2 of a similar size, ensuring that the rear-end gate driving unit 111 is driven normally and the display panel 2 displays a brightness of a similar size.

[0047] Embodiment 3 When the push-pull circuit 150 adopts the above-mentioned push-pull circuit, when the first clock signal clk1 is a high-frequency signal, since the conduction voltage of the triode needs to be greater than the threshold turn-on voltage, for example, greater than 0.7V, when the voltage of the high-frequency input first clock signal clk1 is between -0.7V and 0.7V, the first electronic switch tube and the second electronic switch tube will be in the off state, and the push-pull amplification effect cannot be achieved, resulting in no output of the second clock signal clk2, and there is Figure 7The high potential dead zone shown in the figure, wherein the dotted square wave represents the waveform of the normally compensated second clock signal clk2, and the solid line waveform represents the second clock signal clk2 after dead time compensation. When the dead zone appears, at high and low temperatures, the gate driving unit 111 may fail to turn on due to insufficient high potential of the second clock signal clk2. In order to solve this problem, as shown in FIG. Figure 8 As shown, in another optional embodiment, the thrust circuit 150 includes a second operational amplifier U2, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a third capacitor C3, a fourth capacitor C4, a first diode D1, a second diode D2, a third transistor Q3 and a fourth transistor Q4; The non-inverting input terminal of the second operational amplifier U2 constitutes the signal input terminal of the thrust circuit 150 and is used to connect the first repair line 130, the inverting input terminal of the second operational amplifier U2, the first end of the third capacitor C3 and the first end of the sixth resistor R6 are connected, the output terminal of the second operational amplifier U2, the first end of the seventh resistor R7, the cathode of the first diode D1 and the anode of the second diode D2 are connected, the second end of the seventh resistor R7, the second end of the sixth resistor R6, the second end of the third capacitor C3, the first end of the eighth resistor R8, the emitter of the third transistor Q3 and the collector of the fourth transistor Q4 are connected, the anode of the first diode D1, the base of the third transistor Q3 and the first end of the ninth resistor R9 are connected, and the The base of the fourth transistor Q4, the cathode of the second diode D2 and the first end of the tenth resistor R10 are connected, the second end of the ninth resistor R9 and the first end of the eleventh resistor R11 are connected and used to input the second row start signal VGH2, the second end of the eleventh resistor R11 is connected to the collector of the third transistor Q3, the second end of the tenth resistor R10 and the first end of the twelfth resistor R12 are connected and used to input the second row shutdown signal VGL2, the second end of the twelfth resistor R12 is connected to the emitter of the fourth transistor Q4, the second end of the eighth resistor R8 is connected to the first end of the fourth capacitor C4 to form a signal output end of the thrust circuit 150 and used to connect the second patching section 142, and the second end of the fourth capacitor C4 is grounded; The second row opening signal VGH2 is a positive voltage signal, the second row closing signal VGL2 is a negative voltage signal, and the voltage absolute value of the second row opening signal VGH2 is equal to the voltage absolute value of the second row closing signal VGL2.

[0048] In this embodiment, compared with the second embodiment, two diodes and two resistors are additionally provided, and the second row turn-on signal VGH2 and the second row turn-off signal VGL2 are voltage signals of opposite polarities, wherein the resistance values ​​of the ninth resistor R9 and the tenth resistor R10 are equal, and the voltage value of the connection node of the first diode D1 and the second diode D2 is zero.

[0049] When the first clock signal clk1 is input to the push-pull circuit, when the high potential of the first clock signal clk1 is greater than zero, due to the presence of the first diode D1, the base of the third transistor Q3 can be greater than 0.7V, the third electronic switch tube is turned on, and the second row start signal VGH2 is output, and the second row start signal VGH2 constitutes the high potential of the output second clock signal clk2. When the low potential of the first clock signal clk1 is less than zero, due to the presence of the second diode D2, the base voltage of the fourth transistor Q4 is less than -0.7V, the fourth transistor Q4 is turned on, and the second row shutdown signal VGL2 is output, and the second row shutdown signal VGL2 constitutes the low potential of the output second clock signal clk2.

[0050] By setting two diodes and two resistors, when the voltage of the high-frequency input first clock signal clk1 is between -0.7V and 0.7V, the third transistor Q3 and the fourth transistor Q4 can be normally alternately turned on, thereby outputting the second clock signal clk2 with the same phase but different amplitude as the first clock signal clk1, realizing proportional signal amplification, ensuring that the back-end gate driving unit 111 is normally turned on, and further ensuring the display effect of the display panel 2.

[0051] Embodiment 4 In order to solve the high potential dead zone problem in the second embodiment, in another optional embodiment, as Fig. 9 As shown, the thrust circuit 150 includes a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a first field effect transistor M1 and a second field effect transistor M2; A first end of the thirteenth resistor R13 is connected to the power management integrated circuit 400 and is used to input the third row start signal VGH3, a first end of the fourteenth resistor R14 is connected to the power management integrated circuit 400 and is used to input the third row shutdown signal VGL3, a second end of the thirteenth resistor R13 is connected to the drain of the first field effect transistor M1, a source of the first field effect transistor M1, a drain of the second field effect transistor M2 and a first end of the fifteenth resistor R15 are connected, a gate of the first field effect transistor M1 and a gate of the second field effect transistor M2 are connected to form a signal input end of the thrust circuit 150 and are used to connect the first repair line 130, and a second end of the fifteenth resistor R15 forms a signal output end of the thrust circuit 150 and is used to connect the second repair section 142; The voltage of the third row turn-on signal VGH3 is greater than the voltage of the third row turn-off signal VGL3.

[0052] In this embodiment, the first row start signal VGH1, the second row start signal VGH2, the first row close signal VGL1 and the second row close signal VGL2 are provided by the front-end timing controller 300. The timing controller 300 obtains the operating voltage through the power management integrated circuit 400, and converts and outputs the corresponding row start signal and row close signal. The output voltage is small and the driving force is small.

[0053] The first field effect transistor M1 and the second field effect transistor M2 form a signal amplifying circuit, and when the first clock signal clk1 is at a high level, the first field effect transistor M1 is turned on and outputs a third row turn-on signal VGH3, and the third row turn-on signal VGH3 constitutes a high potential of the second clock signal clk2. When the first clock signal clk1 is at a low level, the second field effect transistor M2 is turned on and outputs a third row turn-off signal VGL3, and the third row turn-off signal VGL3 constitutes a low potential of the second clock signal clk2. The third row turn-on signal VGH3 and the third row turn-off signal VGL3 are directly provided by the power management integrated circuit 400, and have a large voltage amplitude, thereby improving the thrust of the thrust circuit 150.

[0054] Embodiment 5 Since the repair line is added to the circuit board or the display panel 2, it may cause electromagnetic radiation. In order to solve this problem, in an optional embodiment, as shown in FIG. Fig.10 As shown, the gate driving circuit 100 further includes: The inverting circuit 160 is connected to the thrust circuit 150 and is used to invert the output signal of the thrust circuit 150 and output a third clock signal clk3; The third repairing line 170 is disposed in parallel with the second repairing line 140 and spaced apart from each other. The third repairing line 170 is connected to the inverter circuit 160 .

[0055] In this embodiment, the second clock signal clk2 is inverted and outputted through the inverting circuit 160, and the second clock signal clk2 and the third clock signal clk3 are respectively transmitted in the second repair line 140 and the third repair line 170 and superimposed on each other, thereby offsetting the electromagnetic radiation effect brought by the second repair line 140 and improving the electromagnetic protection capability of the gate drive circuit 100.

[0056] Among them, the third repair line 170 and the second repair line 140 are stacked, and the third repair line 170 is routed on the upper layer of the second repair line 140 and is arranged in parallel. In order to achieve isolation of the two repair lines, in an optional embodiment, an isolation layer 180 is also provided between the third repair line 170 and the second repair line 140 to avoid short-circuiting of the two repair lines and causing signal crosstalk.

[0057] The inverting circuit 160 may be an inverter or the like. In an optional embodiment, Fig.11As shown, the inverting circuit 160 includes a third operational amplifier U3, a sixteenth resistor R16 and a seventeenth resistor R17; The first end of the sixteenth resistor R16 is used to connect to the output end of the thrust circuit 150, the second end of the sixteenth resistor R16, the inverting input end of the third operational amplifier U3 and the first end of the seventeenth resistor R17 are connected, the non-inverting input end of the third operational amplifier U3 is grounded, and the output end of the third operational amplifier U3 and the second end of the seventeenth resistor R17 are connected to form the output end of the inverting circuit 160.

[0058] In this embodiment, the third operational amplifier U3, the sixteenth resistor R16 and the seventeenth resistor R17 form an inverting amplifier to amplify the second clock signal clk2 and flip the polarity. The third clock signal clk3 has the same phase but opposite polarity as the second clock signal clk2. The two clock signals are superimposed on each other to eliminate the influence of electromagnetic radiation of the patch circuit.

[0059] Embodiment 6 The present invention also provides a driving circuit 1 of a display panel, such as Fig.12 As shown, the driving circuit 1 of the display panel includes a power management integrated circuit 400, a timing controller 300, a source driving circuit 200 and the above-mentioned gate driving circuit 100. The specific structure of the gate driving circuit 100 refers to the above-mentioned embodiment. Since the driving circuit 1 of the display panel adopts all the technical solutions of all the above-mentioned embodiments, it at least has all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here. Among them, the source driving circuit 200 and the gate driving circuit 100 are respectively connected to the display panel 2, and the timing controller 300 is respectively connected to the power management integrated circuit 400, the source driving circuit 200 and the gate driving circuit 100.

[0060] In this embodiment, the power management integrated circuit 400 can output corresponding voltage signals to one or more of the timing controller 300, the gate drive circuit 100 and the source drive circuit 200. The timing control is used to output corresponding control signals to the gate drive circuit 100 and the source drive circuit 200. The gate drive circuit 100 is used to output row scan signals to the display panel 2 line by line. The source drive circuit 200 is used to output multiple data signals to the display panel 2. The display panel 2 displays corresponding image information under the drive of the row scan signals and the data signals.

[0061] Embodiment 7 The present invention also provides a display device, such as Fig.12As shown, the display device includes a display panel 2 and a driving circuit 1 for the display panel. The specific structure of the driving circuit 1 for the display panel refers to the above embodiment. Since the display device adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here. Among them, the driving circuit 1 for the display panel is connected to the display panel 2.

[0062] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A gate drive circuit, characterized in that: include: A plurality of gate driving units cascaded in sequence, wherein the plurality of gate driving units are used to be sequentially connected to a plurality of scanning lines of the display panel respectively to sequentially output row scanning signals; The clock signal lines include a plurality of first clock signal lines arranged in parallel along a first direction and a plurality of second clock signal lines arranged in parallel along a second direction, each of the second clock signal lines is connected to a first clock signal line and a gate driving unit, and the first direction and the second direction intersect; A repair line, comprising a plurality of first repair lines and a plurality of second repair lines, wherein the second repair line comprises a first repair section and a second repair section connected to each other, wherein the plurality of first repair lines and the plurality of first repair sections are arranged on both sides of a plurality of second clock signal lines along the second direction, are insulated from the plurality of first clock signal lines and are arranged in a stacked manner, and the plurality of second repair sections are insulated from the plurality of second clock signal lines and are arranged in a stacked manner, respectively; wherein the first repair line and the first repair section are respectively used to short-circuit the first clock signal lines stacked in an abnormal clock path, and the second repair section is used to short-circuit the second clock signal lines stacked in an abnormal clock path, and the clock path is a first clock signal line and a second clock signal line connected to each other; A plurality of thrust circuits, each of which is connected to a first patch line and a second patch segment respectively, and the thrust circuit is used to input a first clock signal corresponding to the first patch line and output a second clock signal corresponding to the thrust to the second patch segment.

2. The gate driving circuit according to claim 1, wherein: The thrust circuit includes a first operational amplifier, a first resistor, a second resistor, a third resistor, a first capacitor and a second capacitor; The non-phase input terminal of the first operational amplifier constitutes the signal input terminal of the thrust circuit and is used to connect the first repair line, the inverting input terminal of the first operational amplifier, the first end of the first capacitor and the first end of the first resistor are connected, the output terminal of the first operational amplifier is connected to the first end of the second resistor, the second end of the second resistor, the second end of the first resistor, the second end of the first capacitor and the first end of the third resistor are connected, the second end of the third resistor and the first end of the second capacitor are connected to constitute the signal output terminal of the thrust circuit and are used to connect the second repair segment, and the second end of the second capacitor is grounded.

3. The gate driving circuit according to claim 2, characterized in that: The thrust circuit further includes a fourth resistor, a fifth resistor, a first triode and a second triode; The first end of the fourth resistor is used to input the first row start signal, the second end of the fourth resistor is connected to the collector of the first transistor, the base of the first transistor, the base of the second transistor and the first end of the first resistor are connected, the emitter of the first transistor, the collector of the second transistor and the second end of the first resistor are connected, the emitter of the second transistor is connected to the first end of the fifth resistor, the second end of the fifth resistor is used to input the first row close signal, and the voltage of the first row start signal is greater than the voltage of the first row close signal.

4. The gate driving circuit according to claim 1, wherein: The thrust circuit includes a second operational amplifier, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a third capacitor, a fourth capacitor, a first diode, a second diode, a third transistor and a fourth transistor; The non-inverting input terminal of the second operational amplifier constitutes the signal input terminal of the thrust circuit and is used to connect the first repair line, the inverting input terminal of the second operational amplifier, the first end of the third capacitor and the first end of the sixth resistor are connected, the output terminal of the second operational amplifier, the first end of the seventh resistor, the cathode of the first diode and the anode of the second diode are connected, the second end of the seventh resistor, the second end of the sixth resistor, the second end of the third capacitor, the first end of the eighth resistor, the emitter of the third transistor and the collector of the fourth transistor are connected, the anode of the first diode, the base of the third transistor and the collector of the ninth resistor are connected. The first end is connected, the base of the fourth transistor, the cathode of the second diode and the first end of the tenth resistor are connected, the second end of the ninth resistor is connected to the first end of the eleventh resistor and is used to input the second row start signal, the second end of the eleventh resistor is connected to the collector of the third transistor, the second end of the tenth resistor is connected to the first end of the twelfth resistor and is used to input the second row close signal, the second end of the twelfth resistor is connected to the emitter of the fourth transistor, the second end of the eighth resistor is connected to the first end of the fourth capacitor to form the signal output end of the thrust circuit and is used to connect the second patching section, and the second end of the fourth capacitor is grounded; The second row on signal is a positive voltage signal, the second row off signal is a negative voltage signal, and the absolute value of the voltage of the second row on signal is equal to the absolute value of the voltage of the second row off signal.

5. The gate driving circuit according to claim 1, wherein: The thrust circuit includes a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a first field effect transistor and a second field effect transistor; The first end of the thirteenth resistor is connected to the power management integrated circuit and is used to input the third row start signal, the first end of the fourteenth resistor is connected to the power management integrated circuit and is used to input the third row shutdown signal, the second end of the thirteenth resistor is connected to the drain of the first field effect transistor, the source of the first field effect transistor, the drain of the second field effect transistor and the first end of the fifteenth resistor are connected, the gate of the first field effect transistor and the gate of the second field effect transistor are connected to form the signal input end of the thrust circuit and are used to connect the first patch line, and the second end of the fifteenth resistor constitutes the signal output end of the thrust circuit and is used to connect the second patch segment; The voltage of the third row on signal is greater than the voltage of the third row off signal.

6. The gate drive circuit according to any one of claims 1 to 5, characterized in that: The gate drive circuit further includes: an inverting circuit, connected to the thrust circuit, for inverting an output signal of the thrust circuit and outputting a third clock signal; A third repair line is arranged in parallel with the second repair line and spaced apart from each other, and the third repair line is connected to the inverter circuit.

7. The gate driving circuit according to claim 6, characterized in that: An isolation layer is further provided between the third repairing line and the second repairing line.

8. The gate driving circuit according to claim 6, wherein: The inverting circuit includes a third operational amplifier, a sixteenth resistor and a seventeenth resistor; The first end of the sixteenth resistor is used to connect to the output end of the thrust circuit, the second end of the sixteenth resistor, the inverting input end of the third operational amplifier and the first end of the seventeenth resistor are connected, the non-inverting input end of the third operational amplifier is grounded, and the output end of the third operational amplifier and the second end of the seventeenth resistor are connected to form the output end of the inverting circuit.

9. A driving circuit for a display panel, characterized in that: It includes a power management integrated circuit, a timing controller, a source drive circuit and a gate drive circuit as described in any one of claims 1 to 8, the source drive circuit and the gate drive circuit are respectively connected to the display panel, and the timing controller is respectively connected to the power management integrated circuit, the source drive circuit and the gate drive circuit.

10. A display device, characterized in that: The invention comprises a display panel and a driving circuit of the display panel as claimed in claim 9, wherein the driving circuit of the display panel is connected to the display panel.

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