Gate driving circuit, driving circuit of display panel, and display device

Abstract

The present invention provides a gate driving circuit, a driving circuit of a display panel, and a display device. The gate driving circuit includes a plurality of gate driving units cascaded in sequence, a clock signal line, a repair line, and a plurality of thrust circuits. The clock signal line includes a first clock signal line arranged side by side along a first direction and a second clock signal line arranged side by side along a second direction. The repair line includes a first repair line and a second repair line. The second repair line includes a first repair segment and a second repair segment. When an abnormal clock path occurs, the first repair line and the second repair line are correspondingly short-circuited with the corresponding first clock signal line and the second clock signal line on the abnormal clock path. The thrust circuit converts the input first clock signal line and outputs a second clock signal on the clock path after increasing the thrust, thereby replacing the abnormal clock signal line, avoiding the problems of horizontal lines and abnormalities in the picture, and improving the yield of the display panel.

Description

Technical Field

[0001] The present invention belongs to the technical field of display panels, and particularly relates to a gate driving circuit, a driving circuit of a display panel, and a display device. Background Art

[0002] The driving circuit of a display panel usually includes a gate driving circuit. The gate driving circuit includes multiple cascaded gate driving units and is connected to the scan lines of the display panel. When driving the scan, the cascaded gate driving units receive corresponding clock signals and output row scan signals row by row to perform row-by-row scanning on the display panel.

[0003] When the clock signal line input to the gate driving circuit is broken or short-circuited with another clock trace, it will cause problems such as horizontal lines and abnormal images on the display panel, and even cause the display panel to be scrapped. Summary of the Invention

[0004] An object of the present invention is to provide a gate driving circuit, aiming to solve the problem that when the clock signal line in the traditional gate driving circuit is abnormal, horizontal lines or abnormal images appear on the display panel.

[0005] A first aspect of an embodiment of the present invention provides a gate driving circuit, including:

[0006] Multiple cascaded gate driving units, which are respectively used to be sequentially connected to multiple scan lines of the display panel to sequentially output row scan signals;

[0007] A clock signal line, including multiple first clock signal lines arranged side by side along a first direction and multiple second clock signal lines connected in parallel along a second direction. Each second clock signal line is correspondingly connected to a first clock signal line and a gate driving unit, and the first direction and the second direction intersect;

[0008] A repair line, including several first repair lines and several second repair lines. The second repair line includes a first repair segment and a second repair segment connected to each other. The several first repair lines and the several first repair segments are relatively arranged on both sides of the multiple second clock signal lines along the second direction, are insulated from the multiple first clock signal lines and are stacked. The several second repair segments are respectively insulated from and stacked with the multiple second clock signal lines; wherein, the first repair line and the first repair segment are respectively used to short-circuit the stacked first clock signal lines in an abnormal clock path, and the second repair segment is used to short-circuit the stacked second clock signal lines in an abnormal clock path. The clock path is a connected first clock signal line and a second clock signal line;

[0009] A plurality of thrust circuits, each of the thrust circuits is respectively connected to one of the first repair lines and one of the second repair segments. The thrust circuit is configured to input a corresponding first clock signal through the first repair line and output a second clock signal corresponding to the thrust to the second repair segment.

[0010] Optionally, the thrust circuit includes a first operational amplifier, a first resistor, a second resistor, a third resistor, a first capacitor, and a second capacitor;

[0011] The non-inverting input terminal of the first operational amplifier forms the signal input terminal of the thrust circuit and is configured to be connected to the first repair line. The inverting input terminal of the first operational amplifier, the first terminal of the first capacitor, and the first terminal of the first resistor are connected. The output terminal of the first operational amplifier is connected to the first terminal of the second resistor. The second terminal of the second resistor, the second terminal of the first resistor, the second terminal of the first capacitor, and the first terminal of the third resistor are connected. The second terminal of the third resistor and the first terminal of the second capacitor are connected to form the signal output terminal of the thrust circuit and are configured to be connected to the second repair segment. The second terminal of the second capacitor is grounded.

[0012] Optionally, the thrust circuit further includes a fourth resistor, a fifth resistor, a first triode, and a second triode;

[0013] The first terminal of the fourth resistor is configured to input a first row enable signal. The second terminal of the fourth resistor is connected to the collector of the first triode. The base of the first triode, the base of the second triode, and the first terminal of the first resistor are connected. The emitter of the first triode, the collector of the second triode, and the second terminal of the first resistor are connected. The emitter of the second triode is connected to the first terminal of the fifth resistor. The second terminal of the fifth resistor is configured to input a first row disable signal. The voltage of the first row enable signal is greater than the voltage of the first row disable signal.

[0014] Optionally, the thrust circuit includes a second operational amplifier, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a third capacitor, a fourth capacitor, a first diode, a second diode, a third triode, and a fourth triode;

[0015] The non-inverting input terminal of the second operational amplifier forms the signal input terminal of the thrust circuit and is used to connect to the first repair line. The inverting input terminal of the second operational amplifier, the first terminal of the third capacitor, and the first terminal of the sixth resistor are connected. The output terminal of the second operational amplifier, the first terminal of the seventh resistor, the cathode of the first diode, and the anode of the second diode are connected. The second terminal of the seventh resistor, the second terminal of the sixth resistor, the second terminal of the third capacitor, the first terminal of the eighth resistor, the emitter of the third triode, and the collector of the fourth triode are connected. The anode of the first diode, the base of the third triode, and the first terminal of the ninth resistor are connected. The base of the fourth triode, the cathode of the second diode, and the first terminal of the tenth resistor are connected. The second terminal of the ninth resistor and the first terminal of the eleventh resistor are connected and are used to input the second row enable signal. The second terminal of the eleventh resistor is connected to the collector of the third triode. The second terminal of the tenth resistor and the first terminal of the twelfth resistor are connected and are used to input the second row disable signal. The second terminal of the twelfth resistor is connected to the emitter of the fourth triode. The second terminal of the eighth resistor and the first terminal of the fourth capacitor are connected to form the signal output terminal of the thrust circuit and are used to connect to the second repair segment. The second terminal of the fourth capacitor is grounded;

[0016] The second row enable signal is a positive voltage signal, the second row disable signal is a negative voltage signal, and the absolute value of the voltage of the second row enable signal is equal to the absolute value of the voltage of the second row disable signal.

[0017] Optionally, the thrust circuit includes a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a first field effect transistor, and a second field effect transistor;

[0018] The first terminal of the thirteenth resistor is connected to the power management integrated circuit and is used to input the third row enable signal. The first terminal of the fourteenth resistor is connected to the power management integrated circuit and is used to input the third row disable signal. The second terminal of the thirteenth resistor is connected to the drain of the first field effect transistor. The source of the first field effect transistor, the drain of the second field effect transistor, and the first terminal of the fifteenth resistor are connected. The gate of the first field effect transistor and the gate of the second field effect transistor are connected to form the signal input terminal of the thrust circuit and are used to connect to the first repair line. The second terminal of the fifteenth resistor forms the signal output terminal of the thrust circuit and is used to connect to the second repair segment;

[0019] The voltage of the third row enable signal is greater than the voltage of the third row disable signal.

[0020] Optionally, the gate drive circuit further includes:

[0021] An inverting circuit, connected to the thrust circuit, for inverting the output signal of the thrust circuit and outputting a third clock signal;

[0022] A third repair line, which is arranged in parallel and spaced apart from the second repair line, and the third repair line is connected to the inverting circuit.

[0023] Optionally, an isolation layer is further arranged between the third repair line and the second repair line.

[0024] Optionally, the inverting circuit includes a third operational amplifier, a sixteenth resistor, and a seventeenth resistor;

[0025] The first end of the sixteenth resistor is used to connect to the output end of the thrust circuit, the second end of the sixteenth resistor, the inverting input end of the third operational amplifier, and the first end of the seventeenth resistor are connected, the non-inverting input end of the third operational amplifier is grounded, and the output end of the third operational amplifier and the second end of the seventeenth resistor are connected to form the output end of the inverting circuit.

[0026] A second aspect of the embodiment of the present invention provides a driving circuit for a display panel, including a power management integrated circuit, a timing controller, a source driving circuit, and the gate driving circuit as described above. The source driving circuit and the gate driving circuit are respectively connected to the display panel, and the timing controller is respectively connected to the power management integrated circuit, the source driving circuit, and the gate driving circuit.

[0027] A third aspect of the embodiment of the present invention provides a display device, including a display panel and the driving circuit of the display panel as described above, and the driving circuit of the display panel is connected to the display panel.

[0028] The beneficial effects of the embodiment of the present invention compared with the prior art are as follows: The above-mentioned gate driving circuit includes a plurality of cascaded gate driving units, a clock signal line, a repair line, and several thrust circuits in sequence. The clock signal line includes a first clock signal line arranged side by side in a first direction and a second clock signal line arranged side by side in a second direction. The repair line includes a first repair line and a second repair line. The second repair line includes a first repair segment and a second repair segment. When an abnormal clock path occurs, the first repair line and the second repair line are correspondingly short-circuited with the corresponding first clock signal line and the second clock signal line on the abnormal clock path. The thrust circuit converts the input first clock signal line, increases the thrust, and then outputs it on the second clock signal clock path, thereby replacing the abnormal clock signal line, avoiding the problems of horizontal lines and abnormalities in the picture, and improving the yield of the display panel. Description of the Drawings

[0029] Figure 1The first structural schematic diagram of the gate driving circuit provided by Embodiment 1 of the present invention;

[0030] Figure 2 The second structural schematic diagram of the gate driving circuit provided by Embodiment 1 of the present invention;

[0031] Figure 3 The third structural schematic diagram of the gate driving circuit provided by Embodiment 1 of the present invention;

[0032] Figure 4 The fourth structural schematic diagram of the gate driving circuit provided by Embodiment 1 of the present invention;

[0033] Figure 5 The first circuit schematic diagram of the thrust circuit provided by Embodiment 2 of the present invention;

[0034] Figure 6 The second circuit schematic diagram of the thrust circuit provided by Embodiment 2 of the present invention;

[0035] Figure 7 The waveform schematic diagram of the second clock signal in the thrust circuit provided by Embodiment 3 of the present invention;

[0036] Figure 8 The circuit schematic diagram of the thrust circuit provided by Embodiment 3 of the present invention;

[0037] Figure 9 The circuit schematic diagram of the thrust circuit provided by Embodiment 4 of the present invention;

[0038] Figure 10 The structural schematic diagram of the gate driving circuit provided by Embodiment 5 of the present invention;

[0039] Figure 11 The circuit schematic diagram of the thrust circuit and the inverting circuit provided by Embodiment 5 of the present invention;

[0040] Figure 12 The structural schematic diagram of the driving circuit of the display panel and the display device provided by Embodiments 6 and 7 of the present invention.

[0041] Among them, the reference numerals in the figures are as follows:

[0042] 1. Driving circuit of display panel; 2. Display panel; 100. Gate driving circuit; 200. Source driving circuit; 300. Timing controller; 400. Power management integrated circuit; 110. Driving module; 120. Clock signal line; 130. First repair line; 140. Second repair line; 150. Thrust circuit; 160. Inverting circuit; 170. Third repair line; 180. Isolation layer; 111. Gate driving unit; 121. First clock signal line; 122. Second clock signal line; 131. Third repair segment; 132. Fourth repair segment; 141. First repair segment; 142. Second repair segment; 101. Broken wire point; 102. Short circuit point; 103. Laser point;

[0043] U1. First operational amplifier; U2. Second operational amplifier; U3. Third operational amplifier; R1. First resistor; R2. Second resistor; R3. Third resistor; R4. Fourth resistor; R5. Fifth resistor; R6. Sixth resistor; R7. Seventh resistor; R8. Eighth resistor; R9. Ninth resistor; R10. Tenth resistor; R11. Eleventh resistor; R12. Twelfth resistor; R13. Thirteenth resistor; R14. Fourteenth resistor; R15. Fifteenth resistor; R16. Sixteenth resistor; R17. Seventeenth resistor; C1. First capacitor; C2. Second capacitor; C3. Third capacitor; C4. Fourth capacitor; Q1. First triode; Q2. Second triode; Q3. Third triode; Q4. Fourth triode; D1. First diode; D2. Second diode; M1. First field effect transistor; M2. Second field effect transistor;

[0044] clk1. First clock signal; clk2. Second clock signal; clk3. Third clock signal; VGH1. First row enable signal; VGH2. Second row enable signal; VGH3. Third row enable signal; VGL1. First row disable signal; VGL2. Second row disable signal; VGL3. Third row disable signal. Detailed implementation manners

[0045] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0046] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined.

[0047] Embodiment 1

[0048] In a first aspect of the embodiment of the present invention, a gate driving circuit 100 is proposed, which is used to output a line scan signal to the display panel 2 line by line to drive the display panel 2 to be turned on line by line, and the line turn-on signal is input in cooperation with the data signal input to the display panel 2 to drive the display panel 2 to display corresponding image information.

[0049] As Figure 1 and Figure 2 shown, the gate driving circuit 100 includes:

[0050] A plurality of cascaded gate driving units 111, and the plurality of gate driving units 111 are respectively used to be sequentially connected to a plurality of scan lines of the display panel 2 to sequentially output line scan signals;

[0051] A clock signal line 120, which includes a plurality of first clock signal lines 121 arranged side by side along a first direction and a plurality of second clock signal lines 122 arranged in parallel along a second direction. Each second clock signal line 122 is correspondingly connected to a first clock signal line 121 and a gate driving unit 111, and the first direction and the second direction intersect;

[0052] A repair line, which includes a plurality of first repair lines 130 and a plurality of second repair lines 140. The second repair line 140 includes a connected first repair segment 141 and a second repair segment 142. The plurality of first repair lines 130 and the plurality of first repair segments 141 are oppositely arranged along the second direction on both sides of the plurality of second clock signal lines 122, are insulated from the plurality of first clock signal lines 121 and are stacked. The plurality of second repair segments 142 are respectively insulated from and stacked with the plurality of second clock signal lines 122; wherein, the first repair line 130 and the first repair segment 141 are respectively used to short-circuit the stacked first clock signal lines 121 in an abnormal clock path, and the second repair segment 142 is used to short-circuit the stacked second clock signal lines 122 in an abnormal clock path. The clock path is a connected first clock signal line 121 and a second clock signal line 122;

[0053] A plurality of thrust circuits 150, each thrust circuit 150 is respectively connected to a first repair line 130 and a second repair segment 142. The thrust circuit 150 is used to input a corresponding first clock signal clk1 through the first repair line 130 and output a second clock signal clk2 with a corresponding thrust to the second repair segment 142.

[0054] In this embodiment, the gate driving circuit 100 is a GOA (Gate Driver on Array) circuit. The GOA circuit integrates the TFTs (Thin Film Transistors) in the gate driving circuit 100 onto the array substrate, thus eliminating the gate driving integrated circuit part originally provided outside the array substrate, and reducing the cost of the product in terms of both material cost and process steps.

[0055] The GOA circuit generally includes a plurality of cascaded gate driving units 111. The gate driving unit 111 can be a structure such as a shift register. The plurality of cascaded gate driving units 111 constitute a driving module 110. The gate driving unit 111 is connected to the scan lines in the display area of the display panel 2. When the gate driving circuit 100 operates normally, the front-end timing controller 300 outputs control signals such as a clock signal, a row start signal, and a row stop signal to the gate driving circuit 100. The multiplexed clock signals are transmitted to the gate driving circuit 100 through the first clock signal line 121 and the second clock signal line 122. Each gate driving unit 111 receives one or more clock signals and converts them into row start signals to be output to each row of pixel units of the display panel 2 to sequentially turn on each row of pixel units.

[0056] Among them, the diameter of the first clock signal line 121 is greater than that of the second clock signal line 122. The first clock signal line 121 can be connected to one or more second clock signal lines 122 and transmit the same clock signal to the connected second clock signal lines 122 and the subsequent gate driving units 111. The multiplexed first clock signal lines 121 can respectively receive clock signals with different phases.

[0057] Among them, the abnormal conditions of the clock signal line 120 may include disconnection or short-circuit conditions, such as Figure 2As shown, the disconnection mainly occurs on the first clock signal line 121. For example, a disconnection point 101 appears at the middle position of the first clock signal line 121 in the first path, or a disconnection point 101 appears at the middle position of the first clock signal line 121 in the second path. The short circuit mainly occurs at the overlapping position where the second clock signal line 122 crosses the first clock signal line 121. For example, when the second clock line of the first path connected to the first clock signal line 121 of the first path crosses the first clock signal line 121 of the second path, a short circuit point 102 appears at the overlapping position. Or, when the second clock line of the tenth path connected to the first clock signal line 121 of the second path crosses the first clock signal line 121 of the third path, a short circuit point 102 appears at the overlapping position. When the disconnection point 101 appears, the original corresponding input clock signal cannot be effectively transmitted to the backend gate driving unit 111, and the gate driving unit 111 cannot effectively output the row enable signal, resulting in horizontal lines and abnormal images on the display panel 2. When the short circuit point 102 appears, crosstalk occurs between adjacent two paths of clock signals, causing the backend gate driving unit 111 to receive non-matching clock signals, and further resulting in abnormal images or multiple horizontal lines on the display panel 2, causing display anomalies.

[0058] To solve the problem of the appearance of the disconnection point 101 or the short circuit point 102 on the display panel 2, the gate driving circuit 100 is also provided with corresponding repair lines and a boosting circuit 150. The repair lines are used to short-circuit with the corresponding first clock signal lines 121 and second clock lines, and transfer the original input clock signal to the abnormal clock path to the corresponding second clock signal line 122 and the gate driving unit 111 at the backend. At the same time, since the repair lines are longer than the original clock path and the signal is attenuated, the gate driving unit 111 at the backend cannot be normally driven, resulting in abnormal images. Therefore, the boosting circuit 150 is connected between the first repair line 130 and the second repair line 140 to amplify and boost the amplitude of the clock signal, improving the driving force of the clock signal.

[0059] Take Figure 2 as an example. Assume that the first clock signal line 121 includes 8 paths, and the second clock signal line 122 includes 10 paths. When the first clock signal line 121 on the left is the first clock signal line 121 of the first path, and the first clock signal line 121 on the right is the eighth clock signal line 121 of the eighth path, and the second clock signal line 122 on the upper part is the first clock signal line 121 of the first path, and the second clock signal line 122 at the bottom is the tenth clock signal line 122 of the tenth path.

[0060] Such as Figure 3As shown, when a disconnection anomaly occurs in the first clock path, the first clock path includes the first clock signal line 121 of the first path and the second clock signal line 122 of the first path that are connected. The disconnection point 101 occurs in the middle of the first clock signal line 121 of the first path. At this time, there is no clock signal input to the second clock signal line 122 of the first path connected to the first clock signal line 121 of the first path.

[0061] To solve this problem, the first repair line 130 at the laser connection stack position and the first clock signal line 121 of the first path, as well as the first repair segment 141 at the laser connection stack position and the first clock signal line 121 of the first path, the lower laser point 103 and the first repair line 130 transmit the first clock signal clk1 input to the first clock signal line 121 of the first path to the thrust circuit 150. The thrust circuit 150 amplifies and boosts the amplitude of the first clock signal clk1 and outputs a second clock signal clk2 with the same phase. The amplitude of the second clock signal clk2 is greater than the amplitude of the first clock signal clk1, improving the driving force of the clock signal and achieving clock signal compensation.

[0062] The second clock signal clk2 output by the thrust circuit 150 is transmitted to the upper laser point 103 through the second repair segment 142 and the first repair segment 141, and is transmitted to the second clock signal line 122 of the first path connected to the first clock signal line 121 of the first path. The second clock signal clk2 is output to the gate driving unit 111 at the backend through the second clock signal line 122, ensuring the normal driving of the gate driving unit 111 at the backend and improving the display effect.

[0063] As Figure 4 shown, when a short - circuit point 102 occurs, for example, the second clock signal line 122 of the tenth path connected to the first clock signal line 121 of the second path is short - circuited across the line with the first clock signal line 121 of the third path. The abnormal clock path is the first clock signal line 121 of the second path and the second clock signal line 122 of the tenth path. At this time, first, the second clock signal line 122 before and after the short - circuit point 102 is laser - cut. At the same time, the first clock signal line 121 of the second path at the laser short - circuit stack position and the first repair line 130, as well as the second clock signal line 122 of the tenth path at the laser short - circuit stack position and the second repair segment 142 are laser - short - circuited. The first clock signal clk1 input to the first clock signal line 121 of the second path is transferred and output to the first repair line 130 and the thrust circuit 150. The thrust circuit 150 amplifies and boosts the amplitude of the first clock signal clk1 and outputs a second clock signal clk2 with the same phase. The amplitude of the second clock signal clk2 is greater than the amplitude of the first clock signal clk1, improving the driving force of the clock signal and achieving clock signal compensation.

[0064] The second clock signal clk2 output by the thrust circuit 150 is transmitted to the second clock signal line 122 of the tenth path through the second repair segment 142 and the laser point 103 located at the lower right corner. The second clock signal clk2 is output to the gate driving unit 111 at the back end through the second clock signal line 122, ensuring the normal driving of the gate driving unit 111 at the back end and improving the display effect.

[0065] Among them, the first repair line 130 may include a connected third repair segment 131 and a fourth repair segment 132. The third repair segment 131 is stacked on multiple first clock signal lines 121, and the fourth repair segment 132 is used to connect the third repair segment 131 and the fourth repair segment 132.

[0066] Among them, the first repair line 130, the second repair line 140, and the thrust circuit 150 form a repair unit for replacing an abnormal clock path. When there are multiple abnormal clock paths, multiple repair units can be set, and the specific number of settings is not limited.

[0067] The thrust circuit 150 can adopt corresponding signal amplification circuits, push-pull circuits, etc., and the specific structure is not limited.

[0068] The beneficial effects of the embodiment of the present invention compared with the prior art are as follows: The above-mentioned gate driving circuit 100 includes a plurality of gate driving units 111, clock signal lines 120, repair lines, and several thrust circuits 150 cascaded in sequence. The clock signal lines 120 include first clock signal lines 121 arranged side by side in the first direction and second clock signal lines 122 arranged side by side in the second direction. The repair lines include a first repair line 130 and a second repair line 140. The second repair line 140 includes a first repair segment 141 and a second repair segment 142. When there is an abnormal clock path, the first repair line 130 and the second repair line 140 are correspondingly short-circuited with the corresponding first clock signal line 121 and the second clock signal line 122 on the abnormal clock path. The thrust circuit 150 converts the input first clock signal line 121 and outputs it on the second clock signal clk2 clock path after increasing the thrust, thereby replacing the abnormal clock signal line 120, avoiding the problems of horizontal lines and abnormalities in the picture, and improving the yield of the display panel 2.

[0069] Embodiment 2

[0070] As Figure 5 shown, in an alternative embodiment, the thrust circuit 150 includes a first operational amplifier U1, a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, and a second capacitor C2;

[0071] The non-inverting input terminal of the first operational amplifier U1 constitutes the signal input terminal of the thrust circuit 150 and is used to connect to the first repair line 130. The inverting input terminal of the first operational amplifier U1, the first terminal of the first capacitor C1, and the first terminal of the first resistor R1 are connected. The output terminal of the first operational amplifier U1 is connected to the first terminal of the second resistor R2. The second terminal of the second resistor R2, the second terminal of the first resistor R1, the second terminal of the first capacitor C1, and the first terminal of the third resistor R3 are connected. The second terminal of the third resistor R3 and the first terminal of the second capacitor C2 are connected to form the signal output terminal of the thrust circuit 150 and are used to connect to the second repair segment 142. The second terminal of the second capacitor C2 is grounded.

[0072] In this embodiment, the first operational amplifier U1, the first resistor R1, the second resistor R2, and the first capacitor C1 form a non-inverting amplifier, which amplifies the input first clock signal clk1. The third resistor R3 and the second capacitor C2 form a filter circuit, which is used to filter out the clutter in the amplified first clock signal clk1 and filter and output the second clock signal clk2.

[0073] Among them, the gain of the non-inverting amplifier composed of the operational amplifier is limited. When the disconnection point 101 or the short-circuit point 102 appears at different positions on the first clock signal line 121, the repaired lines after laser short-circuiting may be different, the attenuation degree of the first clock signal clk1 is different, and there is a difference in the amplitude of the second clock signal clk2 output to the gate driving unit 111. Therefore, it is necessary to set the thrust circuit 150 with different gains.

[0074] In an alternative embodiment, as Figure 6 shown, the thrust circuit 150 further includes a fourth resistor R4, a fifth resistor R5, a first triode Q1, and a second triode Q2;

[0075] The first terminal of the fourth resistor R4 is used to input the first row turn-on signal VGH1. The second terminal of the fourth resistor R4 is connected to the collector of the first triode Q1. The base of the first triode Q1, the base of the second triode Q2, and the first terminal of the first resistor R1 are connected. The emitter of the first triode Q1, the collector of the second triode Q2, and the second terminal of the first resistor R1 are connected. The emitter of the second triode Q2 is connected to the first terminal of the fifth resistor R5. The second terminal of the fifth resistor R5 is used to input the first row turn-off signal VGL1. The voltage of the first row turn-on signal VGH1 is greater than the voltage of the first row turn-off signal VGL1.

[0076] In this embodiment, the fourth resistor R4, the fifth resistor R5, the first triode Q1, and the second triode Q2 form a push-pull circuit. The push-pull circuit converts the input clock signal into a second clock signal clk2 composed of a first row enable signal VGH1 and a first row disable signal VGL1. The first row enable signal VGH1 constitutes the high potential of the second clock signal clk2, and the first row disable signal VGL1 constitutes the low potential of the second clock signal clk2.

[0077] The first triode Q1 can be an NPN triode, and the second triode Q2 can be a PNP triode.

[0078] The push-pull circuit can further amplify the input clock signal to further increase the amplitude of the clock signal.

[0079] When different abnormal pictures are visually observed or different break points 101 or short-circuit points 102 are detected, the required thrust magnitude is determined, and whether to switch different thrust circuits 150 is correspondingly selected.

[0080] For example Figure 2 As shown, when corresponding to the clock path of the laser anomaly, the path of the repair wire passed by the break point 101 of the first clock signal line 121 in the first path is smaller than that of the break point 101 of the first clock signal line 121 in the second path. For the break point 101 of the first clock signal line 121 in the first path, the attenuation of the clock signal is small, and a thrust circuit 150 with a smaller thrust can be selected. To this end, the first repair wire 130 and the second repair section 142 can be directly connected first. When it is detected that the brightness of the display picture is slightly dim and the required thrust of the thrust circuit 150 is small, the push-pull circuit can be exited by soldering or laser, and the thrust circuit 150 is connected between the first repair wire 130 and the second repair section 142. The thrust circuit 150 composed of the first operational amplifier U1, the first resistor R1, the second resistor R2, and the first capacitor C1 amplifies the signal, thereby increasing the brightness of the current display picture.

[0081] Alternatively, after the clock path corresponding to the laser anomaly, the path of the repair line passed by the break point 101 of the first clock signal line 121 on the first path is smaller than that of the break point 101 of the first clock signal line 121 on the second path. For the break point 101 of the first clock signal line 121 on the second path, the clock signal attenuation is large. A thrust circuit 150 with a greater thrust can be selected. When it is detected that the brightness of the display screen is relatively dim and the thrust required by the thrust circuit 150 is large, the push-pull circuit can be connected to the thrust circuit 150 by soldering or laser, and the thrust circuit 150 is connected between the first repair line 130 and the second repair section 142. The non-inverting amplifier and the push-pull circuit composed of the first operational amplifier U1, the first resistor R1, the second resistor R2, and the first capacitor C1 perform signal amplification twice, thereby greatly enhancing the brightness of the current display screen, so that the thrust circuit 150 provides second clock signals clk2 with similar magnitudes after repairing different break points 101 or short-circuit points 102, ensuring that the subsequent gate driving unit 111 can drive normally and the display panel 2 can display with similar brightness.

[0082] Embodiment III

[0083] When the above push-pull circuit is adopted in the thrust circuit 150, when the first clock signal clk1 is a high-frequency signal, since the conduction voltage of the triode needs to be greater than the threshold turn-on voltage, for example, greater than 0.7V. When the voltage of the high-frequency input first clock signal clk1 is between -0.7V and 0.7V, both the first electronic switch tube and the second electronic switch tube will be in the off state, and thus the push-pull amplification function cannot be achieved, resulting in no output of the second clock signal clk2, there is Figure 7 the high-potential dead zone shown in the figure. Among them, the dotted square wave represents the waveform of the second clock signal clk2 with normal compensation, and the solid waveform represents the second clock signal clk2 with dead-time compensation. When a dead zone appears, at high and low temperatures, due to the insufficient high potential of the second clock signal clk2, it is easy to cause the gate driving unit 111 to fail to turn on. To solve this problem, as Figure 8 shown in the figure, in another alternative embodiment, the thrust circuit 150 includes a second operational amplifier U2, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a third capacitor C3, a fourth capacitor C4, a first diode D1, a second diode D2, a third triode Q3, and a fourth triode Q4;

[0084] The non-inverting input terminal of the second operational amplifier U2 forms the signal input terminal of the thrust circuit 150 and is used to connect to the first repair line 130. The inverting input terminal of the second operational amplifier U2, the first terminal of the third capacitor C3, and the first terminal of the sixth resistor R6 are connected. The output terminal of the second operational amplifier U2, the first terminal of the seventh resistor R7, the cathode of the first diode D1, and the anode of the second diode D2 are connected. The second terminal of the seventh resistor R7, the second terminal of the sixth resistor R6, the second terminal of the third capacitor C3, the first terminal of the eighth resistor R8, the emitter of the third triode Q3, and the collector of the fourth triode Q4 are connected. The anode of the first diode D1, the base of the third triode Q3, and the first terminal of the ninth resistor R9 are connected. The base of the fourth triode Q4, the cathode of the second diode D2, and the first terminal of the tenth resistor R10 are connected. The second terminal of the ninth resistor R9 and the first terminal of the eleventh resistor R11 are connected and are used to input the second row enable signal VGH2. The second terminal of the eleventh resistor R11 is connected to the collector of the third triode Q3. The second terminal of the tenth resistor R10 and the first terminal of the twelfth resistor R12 are connected and are used to input the second row disable signal VGL2. The second terminal of the twelfth resistor R12 is connected to the emitter of the fourth triode Q4. The second terminal of the eighth resistor R8 and the first terminal of the fourth capacitor C4 are connected to form the signal output terminal of the thrust circuit 150 and are used to connect to the second repair segment 142. The second terminal of the fourth capacitor C4 is grounded;

[0085] The second row enable signal VGH2 is a positive voltage signal, and the second row disable signal VGL2 is a negative voltage signal. The absolute value of the voltage of the second row enable signal VGH2 is equal to the absolute value of the voltage of the second row disable signal VGL2.

[0086] In this embodiment, compared with the second embodiment, two diodes and two resistors are added, and the second row enable signal VGH2 and the second row disable signal VGL2 are voltage signals with opposite polarities. Among them, the resistance values of the ninth resistor R9 and the tenth resistor R10 are equal, and the voltage value of the connection node of the first diode D1 and the second diode D2 is zero.

[0087] When the first clock signal clk1 is input to the push-pull circuit, when the high potential of the first clock signal clk1 is greater than zero, due to the existence of the first diode D1, the base of the third triode Q3 can be greater than 0.7V, and the third electronic switch is turned on, and the second row enable signal VGH2 is output. The second row enable signal VGH2 constitutes the high potential of the output second clock signal clk2. When the low potential of the first clock signal clk1 is less than zero, due to the existence of the second diode D2, the base voltage of the fourth triode Q4 is less than -0.7V, and the fourth triode Q4 is turned on, and the second row disable signal VGL2 is output. The second row disable signal VGL2 constitutes the low potential of the output second clock signal clk2.

[0088] By setting two diodes and two resistors, when the voltage of the first clock signal clk1 with high-frequency input is between -0.7V and 0.7V, the third triode Q3 and the fourth triode Q4 can conduct alternately normally, so as to output a second clock signal clk2 with the same phase and different amplitudes as the first clock signal clk1, realize signal amplification in proportion, ensure the normal turn-on of the gate driving unit 111 at the back end, and further ensure the display effect of the display panel 2.

[0089] Embodiment 4

[0090] To solve the high-potential dead zone problem existing in Embodiment 2, in another optional embodiment, as Figure 9 shown, the thrust circuit 150 includes a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a first field-effect transistor M1 and a second field-effect transistor M2;

[0091] The first end of the thirteenth resistor R13 is connected to the power management integrated circuit 400 and is used for inputting the third row turn-on signal VGH3. The first end of the fourteenth resistor R14 is connected to the power management integrated circuit 400 and is used for inputting the third row turn-off signal VGL3. The second end of the thirteenth resistor R13 is connected to the drain of the first field-effect transistor M1. The source of the first field-effect transistor M1, the drain of the second field-effect transistor M2 and the first end of the fifteenth resistor R15 are connected. The gates of the first field-effect transistor M1 and the second field-effect transistor M2 are connected to form the signal input end of the thrust circuit 150 and are used for connecting the first repair line 130. The second end of the fifteenth resistor R15 forms the signal output end of the thrust circuit 150 and is used for connecting the second repair segment 142;

[0092] The voltage of the third row turn-on signal VGH3 is greater than the voltage of the third row turn-off signal VGL3.

[0093] In this embodiment, the first row turn-on signal VGH1, the second row turn-on signal VGH2, the first row turn-off signal VGL1 and the second row turn-off signal VGL2 are provided by the front-end timing controller 300. The timing controller 300 obtains the working voltage through the power management integrated circuit 400, and converts and outputs the corresponding row turn-on signal and row turn-off signal, and the output voltage is small and the driving force is small.

[0094] The first field-effect transistor M1 and the second field-effect transistor M2 form a signal amplification circuit. When the first clock signal clk1 is at a high level, the first field-effect transistor M1 is turned on to output the third row enable signal VGH3. The third row enable signal VGH3 constitutes the high potential of the second clock signal clk2. When the first clock signal clk1 is at a low level, the second field-effect transistor M2 is turned on to output the third row disable signal VGL3. The third row disable signal VGL3 constitutes the low potential of the second clock signal clk2. The third row enable signal VGH3 and the third row disable signal VGL3 are directly provided by the power management integrated circuit 400, and the voltage amplitude is large, thereby increasing the driving force of the driving force circuit 150.

[0095] Embodiment 5

[0096] Since adding repair lines on the circuit board or the display panel 2 may cause electromagnetic radiation effects, to solve this problem, in an alternative embodiment, as Figure 10 shown, the gate driving circuit 100 further includes:

[0097] An inverting circuit 160, connected to the driving force circuit 150, for inverting the output signal of the driving force circuit 150 and outputting a third clock signal clk3;

[0098] A third repair line 170, which is arranged in parallel and spaced apart from the second repair line 140, and the third repair line 170 is connected to the inverting circuit 160.

[0099] In this embodiment, the second clock signal clk2 is inverted and output by the inverting circuit 160. The second clock signal clk2 and the third clock signal clk3 are respectively transmitted in the second repair line 140 and the third repair line 170 and superimposed on each other to cancel the electromagnetic radiation effect brought by the second repair line 140 and improve the electromagnetic protection ability of the gate driving circuit 100.

[0100] Among them, the third repair line 170 and the second repair line 140 are stacked. The third repair line 170 runs on the upper layer of the second repair line 140 and is arranged in parallel. To achieve isolation between the two repair lines, in an alternative embodiment, an isolation layer 180 is further provided between the third repair line 170 and the second repair line 140 to prevent short-circuiting of the two repair lines and signal crosstalk.

[0101] The inverting circuit 160 can adopt a structure such as an inverter. In an alternative embodiment, as Figure 11 shown, the inverting circuit 160 includes a third operational amplifier U3, a sixteenth resistor R16, and a seventeenth resistor R17;

[0102] The first end of the sixteenth resistor R16 is used to connect to the output end of the thrust circuit 150. The second end of the sixteenth resistor R16, the inverting input end of the third operational amplifier U3, and the first end of the seventeenth resistor R17 are connected. The non-inverting input end of the third operational amplifier U3 is grounded. The output end of the third operational amplifier U3 and the second end of the seventeenth resistor R17 are connected to form the output end of the inverting circuit 160.

[0103] In this embodiment, the third operational amplifier U3, the sixteenth resistor R16, and the seventeenth resistor R17 form an inverting amplifier to amplify the second clock signal clk2 and invert its polarity. The third clock signal clk3 has the same phase as the second clock signal clk2 but opposite polarity. The two clock signals are superimposed on each other to eliminate the electromagnetic radiation influence of the repair circuit.

[0104] Embodiment Six

[0105] The present invention also provides a driving circuit 1 for a display panel, as Figure 12 shown. The driving circuit 1 of the display panel includes a power management integrated circuit 400, a timing controller 300, a source driving circuit 200, and the above-mentioned gate driving circuit 100. The specific structure of the gate driving circuit 100 refers to the above embodiment. Since the driving circuit 1 of the present display panel adopts all the technical solutions of the above-mentioned all embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be elaborated here one by one. Among them, the source driving circuit 200 and the gate driving circuit 100 are respectively connected to the display panel 2, and the timing controller 300 is respectively connected to the power management integrated circuit 400, the source driving circuit 200, and the gate driving circuit 100.

[0106] In this embodiment, the power management integrated circuit 400 can output corresponding voltage signals to one or more of the timing controller 300, the gate driving circuit 100, and the source driving circuit 200. The timing control is used to output corresponding control signals to the gate driving circuit 100 and the source driving circuit 200. The gate driving circuit 100 is used to output row scanning signals to the display panel 2 row by row. The source driving circuit 200 is used to output multiple data signals to the display panel 2. The display panel 2 displays corresponding image information under the drive of the row scanning signal and the data signal.

[0107] Embodiment Seven

[0108] The present invention also provides a display device, as Figure 12As shown in the figure, the display device includes a display panel 2 and a driving circuit 1 of the display panel. For the specific structure of the driving circuit 1 of the display panel, please refer to the above embodiments. Since this display device adopts all the technical solutions of the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be elaborated here one by one. Among them, the driving circuit 1 of the display panel is connected to the display panel 2.

[0109] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A gate driving circuit, characterized in that, Including: A plurality of cascaded gate driving units, which are respectively used to be sequentially connected to a plurality of scan lines of a display panel to sequentially output row scan signals; A clock signal line, including a plurality of first clock signal lines arranged side by side in a first direction and a plurality of second clock signal lines arranged in parallel in a second direction. Each of the second clock signal lines is correspondingly connected to one of the first clock signal lines and one of the gate driving units, and the first direction and the second direction intersect; A repair line, including a plurality of first repair lines and a plurality of second repair lines. The second repair line includes a connected first repair segment and a second repair segment. The plurality of first repair lines and the plurality of first repair segments are oppositely arranged on both sides of the plurality of second clock signal lines along the second direction, are insulated from the plurality of first clock signal lines and are stacked. The plurality of second repair segments are respectively insulated from the plurality of second clock signal lines and are stacked; wherein, the first repair line and the first repair segment are respectively used to short-circuit the stacked first clock signal lines in an abnormal clock path, and the second repair segment is used to short-circuit the stacked second clock signal lines in an abnormal clock path. The clock path is a connected first clock signal line and a second clock signal line; A plurality of thrust circuits, each of the thrust circuits is respectively connected to one of the first repair lines and one of the second repair segments. The thrust circuit is used to input a corresponding first clock signal through the first repair line and output a second clock signal with a corresponding thrust to the second repair segment.

2. The gate driving circuit according to claim 1, wherein The thrust circuit includes a first operational amplifier, a first resistor, a second resistor, a third resistor, a first capacitor and a second capacitor; The positive input terminal of the first operational amplifier constitutes the signal input terminal of the thrust circuit and is used to connect the first repair line. The negative input terminal of the first operational amplifier, the first end of the first capacitor and the first end of the first resistor are connected. The output terminal of the first operational amplifier is connected to the first end of the second resistor. The second end of the second resistor, the second end of the first resistor, the second end of the first capacitor and the first end of the third resistor are connected. The second end of the third resistor and the first end of the second capacitor are connected to constitute the signal output terminal of the thrust circuit and are used to connect the second repair segment, and the second end of the second capacitor is grounded.

3. The gate driving circuit according to claim 2, wherein The thrust circuit further includes a fourth resistor, a fifth resistor, a first triode and a second triode; The first end of the fourth resistor is used to input a first row start signal. The second end of the fourth resistor is connected to the collector of the first triode. The base of the first triode, the base of the second triode and the first end of the first resistor are connected. The emitter of the first triode, the collector of the second triode and the second end of the first resistor are connected. The emitter of the second triode is connected to the first end of the fifth resistor. The second end of the fifth resistor is used to input a first row stop signal, and the voltage of the first row start signal is greater than the voltage of the first row stop signal.

4. The gate driving circuit according to claim 1, wherein The thrust circuit includes a second operational amplifier, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a third capacitor, a fourth capacitor, a first diode, a second diode, a third triode, and a fourth triode; The non-inverting input terminal of the second operational amplifier forms the signal input terminal of the thrust circuit and is used to connect to the first repair line. The inverting input terminal of the second operational amplifier, the first terminal of the third capacitor, and the first terminal of the sixth resistor are connected. The output terminal of the second operational amplifier, the first terminal of the seventh resistor, the cathode of the first diode, and the anode of the second diode are connected. The second terminal of the seventh resistor, the second terminal of the sixth resistor, the second terminal of the third capacitor, the first terminal of the eighth resistor, the emitter of the third triode, and the collector of the fourth triode are connected. The anode of the first diode, the base of the third triode, and the first terminal of the ninth resistor are connected. The base of the fourth triode, the cathode of the second diode, and the first terminal of the tenth resistor are connected. The second terminal of the ninth resistor and the first terminal of the eleventh resistor are connected and are used to input the second row enable signal. The second terminal of the eleventh resistor is connected to the collector of the third triode. The second terminal of the tenth resistor and the first terminal of the twelfth resistor are connected and are used to input the second row disable signal. The second terminal of the twelfth resistor is connected to the emitter of the fourth triode. The second terminal of the eighth resistor and the first terminal of the fourth capacitor are connected to form the signal output terminal of the thrust circuit and are used to connect to the second repair segment. The second terminal of the fourth capacitor is grounded; The second row enable signal is a positive voltage signal, the second row disable signal is a negative voltage signal, and the absolute value of the voltage of the second row enable signal is equal to the absolute value of the voltage of the second row disable signal.

5. The gate driving circuit according to claim 1, wherein The thrust circuit includes a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a first field effect transistor, and a second field effect transistor; The first terminal of the thirteenth resistor is connected to the power management integrated circuit and is used to input the third row enable signal. The first terminal of the fourteenth resistor is connected to the power management integrated circuit and is used to input the third row disable signal. The second terminal of the thirteenth resistor is connected to the drain of the first field effect transistor. The source of the first field effect transistor, the drain of the second field effect transistor, and the first terminal of the fifteenth resistor are connected. The gate of the first field effect transistor and the gate of the second field effect transistor are connected to form the signal input terminal of the thrust circuit and are used to connect to the first repair line. The second terminal of the fifteenth resistor forms the signal output terminal of the thrust circuit and is used to connect to the second repair segment; The voltage of the third row enable signal is greater than the voltage of the third row disable signal.

6. The gate driving circuit according to any one of claims 1 to 5, characterized in that The gate drive circuit further includes: An inverting circuit, connected to the thrust circuit, for inverting the output signal of the thrust circuit and outputting a third clock signal; A third repair line, the third repair line being arranged in parallel and spaced apart from the second repair line, and the third repair line being connected to the inverting circuit.

7. The gate driving circuit according to claim 6, wherein An isolation layer is further provided between the third repair line and the second repair line.

8. The gate driving circuit according to claim 6, wherein The inverting circuit includes a third operational amplifier, a sixteenth resistor, and a seventeenth resistor; The first end of the sixteenth resistor is used to connect to the output end of the thrust circuit, the second end of the sixteenth resistor, the inverting input end of the third operational amplifier, and the first end of the seventeenth resistor are connected, the non-inverting input end of the third operational amplifier is grounded, and the output end of the third operational amplifier and the second end of the seventeenth resistor are connected to form the output end of the inverting circuit.

9. A driving circuit for a display panel, characterized in that, It includes a power management integrated circuit, a timing controller, a source driver circuit, and the gate driver circuit according to any one of claims 1 to 8. The source driver circuit and the gate driver circuit are respectively connected to the display panel, and the timing controller is respectively connected to the power management integrated circuit, the source driver circuit, and the gate driver circuit.

10. A display device, characterized in that, It includes a display panel and a driving circuit of the display panel according to claim 9, and the driving circuit of the display panel is connected to the display panel.

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