Display substrate and display device

Abstract

According to the display substrate and the display device, the display substrate is provided with a display area and a non-display area located on at least one side of the display area, and the display substrate comprises a substrate, pixel driving circuits, a plurality of scanning signal lines and a plurality of light-emitting signal lines, and the pixel driving circuits, the scanning signal lines and the light-emitting signal lines are arranged in the display area in an array mode. At least one pixel driving circuit comprises a write-in transistor, a reset transistor, a compensation transistor and a light-emitting transistor; a control electrode of at least one of the write-in transistor, the reset transistor and the compensation transistor in the at least one pixel driving circuit is electrically connected with the at least one scanning signal line, and the light-emitting transistor in the at least one pixel driving circuit is electrically connected with the at least one light-emitting signal line; at least one of the plurality of scanning signal lines and at least one of the plurality of light-emitting signal lines are arranged in different layers.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the current display field. Summary of the invention

[0003] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

[0004] The present disclosure provides a display substrate and a display device.

[0005] In a first aspect, the present disclosure provides a display substrate having a display area and a non-display area located at least on one side of the display area, comprising: a substrate, and a pixel driving circuit, a plurality of scanning signal lines, and a plurality of light-emitting signal lines arranged in an array and disposed on the substrate and located in the display area, at least one pixel driving circuit comprising: at least one transistor, and at least one transistor comprising: a write transistor, a reset transistor, a compensation transistor, and a light-emitting transistor;

[0006] A control electrode of at least one of a write transistor, a reset transistor and a compensation transistor in at least one pixel driving circuit is electrically connected to at least one scanning signal line, and a light emitting transistor in at least one pixel driving circuit is electrically connected to at least one light emitting signal line;

[0007] The plurality of scanning signal lines and the plurality of light emitting signal lines are arranged in different layers.

[0008] In an exemplary embodiment, the plurality of light emitting signal lines are located on a side of the plurality of scanning signal lines that is away from the substrate.

[0009] In an exemplary embodiment, it also includes: light-emitting devices arranged in an array and located in the substrate and in the display area, the first electrode of at least one light-emitting device is electrically connected to at least one pixel driving circuit, at least one transistor further includes: a driving transistor, the reset transistor includes: an anode reset transistor and a node reset transistor, the anode reset transistor is electrically connected to the first electrode of at least one light-emitting device, the node reset transistor is electrically connected to the control electrode of the driving transistor, the write transistor is electrically connected to the first electrode of the driving transistor, and the compensation transistor is electrically connected to the control electrode and the second electrode of the driving transistor respectively; the scanning signal line includes: a first scanning signal line, a second scanning signal line and a third scanning signal line;

[0010] A control electrode of a node reset transistor of at least one pixel driving circuit is electrically connected to at least one first scanning signal line, a control electrode of a compensation transistor of at least one pixel driving circuit is electrically connected to at least one second scanning signal line, and a control electrode of a write transistor and a control electrode of an anode reset transistor of at least one pixel driving circuit are electrically connected to at least one third scanning signal line respectively;

[0011] The signal received by the first scanning signal line connected to the pixel driving circuit in the nth row is the same as the signal received by the second scanning signal line connected to the pixel driving circuit in the (n-3)th row.

[0012] In an exemplary embodiment, at least one of the first scan signal line, the second scan signal line, and the third scan signal line at least partially extends along a first direction;

[0013] The orthographic projections of the first scanning signal line, the second scanning signal line and the third scanning signal line connected to at least one pixel driving circuit on the substrate are arranged in sequence along a second direction, and the first direction intersects with the second direction.

[0014] In an exemplary embodiment, the light emitting transistor includes: a first light emitting transistor and a second light emitting transistor, the first light emitting transistor is electrically connected to a first electrode of a driving transistor, the second light emitting transistor is electrically connected to a second electrode of the driving transistor and a first electrode of a light emitting device electrically connected to a pixel driving device, respectively, and the light emitting signal line includes: a first light emitting signal line and a second light emitting signal line;

[0015] A control electrode of a first light emitting transistor of at least one pixel driving circuit is electrically connected to at least one first light emitting signal line, and a control electrode of a second light emitting transistor of at least one pixel driving circuit is electrically connected to at least one second light emitting signal line;

[0016] The signal received by the second light emitting signal line connected to the pixel driving circuit in the nth row is the same as the signal received by the first light emitting signal line connected to the pixel driving circuit in the (n-1)th row.

[0017] In an exemplary embodiment, a control electrode of at least one of the first light emitting transistor and the second light emitting transistor is located on a side of at least one of the first light emitting signal line and the second light emitting signal line close to the substrate.

[0018] In an exemplary embodiment, at least one of the first light emitting signal line and the second light emitting signal line at least partially extends along a first direction;

[0019] The orthographic projection of the first light emitting signal line connected to at least one pixel driving circuit on the substrate is located between the orthographic projection of the second scanning signal line on the substrate and the orthographic projection of the third scanning signal line on the substrate;

[0020] The orthographic projection of the second light emitting signal line connected to at least one pixel driving circuit on the substrate is located on a side of the orthographic projection of the third scanning signal line on the substrate away from the orthographic projection of the second scanning signal line on the substrate.

[0021] In an exemplary embodiment, the positive projection of the control electrode of at least one of the first light-emitting transistor and the second light-emitting transistor of at least one pixel driving circuit on the substrate is located between the positive projection of the first light-emitting signal line connected to at least one pixel driving circuit on the substrate and the positive projection of the third scanning signal line on the substrate.

[0022] In an exemplary embodiment, the invention further comprises: a plurality of first connection electrodes disposed on the substrate and located in the display area, wherein the first connection electrodes are located on a side of the plurality of light emitting signal lines away from the substrate;

[0023] At least one first connection electrode is electrically connected to a control electrode of a first light emitting transistor of at least one pixel driving circuit and at least one first light emitting signal line respectively.

[0024] In an exemplary embodiment, the invention further comprises: a plurality of second connection electrodes disposed on the substrate and located in the display area, wherein the second connection electrodes are located on a side of the plurality of light emitting signal lines away from the substrate;

[0025] At least one second connection electrode is electrically connected to a control electrode of a second light emitting transistor of at least one pixel driving circuit and at least one second light emitting signal line respectively.

[0026] In an exemplary embodiment, an orthographic projection of at least one second connection electrode on the substrate at least partially overlaps an orthographic projection of a third scan signal line connected to at least one pixel driving circuit on the substrate.

[0027] In an exemplary embodiment, it further includes: a plurality of first power lines and a plurality of data signal lines disposed on the substrate and located in the display area, a write transistor in at least one pixel driving circuit being electrically connected to at least one data signal line, and a first light emitting transistor in at least one pixel driving circuit being electrically connected to at least one first power line;

[0028] At least one signal line among the plurality of first power lines and the plurality of data signal lines at least partially extends along the second direction, and the plurality of first power lines and at least one signal line among the plurality of data signal lines are arranged in the same layer as a first electrode and a second electrode of at least one transistor in at least one pixel driving circuit;

[0029] The orthographic projection of the first power line connected to at least one pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the control electrode of the first light-emitting transistor on the substrate, and has no overlapping area with the orthographic projection of the control electrode of the second light-emitting transistor on the substrate.

[0030] In an exemplary embodiment, at least one pixel driving circuit further includes: a capacitor, the capacitor includes: a second plate, the second plate of the capacitor of at least one pixel driving circuit is electrically connected to the at least one first power line,

[0031] The second plates of the capacitors of at least two pixel driving circuits located in the same row are arranged along the first direction and are connected to each other.

[0032] In an exemplary embodiment, the present invention further comprises: a plurality of first initial signal lines and a plurality of second initial signal lines disposed on the substrate and located in the display area, a node reset transistor in at least one pixel driving circuit being electrically connected to at least one first initial signal line, and an anode reset transistor in at least one pixel driving circuit being electrically connected to at least one second initial signal line;

[0033] At least one signal line among the plurality of first initial signal lines and the plurality of second initial signal lines at least partially extends along the first direction;

[0034] The orthographic projection of the first initial signal line connected to at least one pixel driving circuit on the substrate is located between the orthographic projection of the first scanning signal line on the substrate and the orthographic projection of the second scanning signal line on the substrate;

[0035] The orthographic projection of the second initial signal line connected to at least one pixel driving circuit on the substrate is located on a side of the orthographic projection of the second light emitting signal line on the substrate away from the orthographic projection of the third scanning signal line on the substrate.

[0036] In an exemplary embodiment, it further includes: a plurality of first connection electrodes, a plurality of second connection electrodes, a plurality of first initial signal lines, a plurality of second initial signal lines, a plurality of first power lines, and a plurality of second power lines disposed on the substrate and located in the display area, and at least one pixel driving circuit further includes: at least one capacitor, and at least one capacitor includes: a first plate and a second plate;

[0037] The display substrate further comprises: a circuit structure layer arranged on the base, the circuit structure layer comprising: a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer sequentially stacked on the base;

[0038] The semiconductor layer includes: an active pattern of at least one transistor of at least one pixel driving circuit;

[0039] The first conductive layer includes: a plurality of scanning signal lines and a control electrode of at least one transistor of at least one pixel driving circuit and a first electrode plate of at least one capacitor;

[0040] The second conductive layer includes: a plurality of light emitting signal lines, a plurality of first initial signal lines, a plurality of second initial signal lines, and a second plate of at least one capacitor of at least one pixel driving circuit;

[0041] The third conductive layer includes: a plurality of first power lines, a plurality of data signal lines, a plurality of first connection electrodes, a plurality of second connection electrodes, and a first electrode and a second electrode of at least one transistor of at least one pixel driving circuit.

[0042] In an exemplary embodiment, the invention further comprises: a first driving circuit, a second driving circuit and a third driving circuit disposed on the substrate and located in the non-display area, the non-display area comprises: a frame area and a binding area, the frame area is located at a first side, a second side and a third side of the display area, the binding area is located at a fourth side of the display area, the first side and the second side of the display area are disposed opposite to each other, and the third side and the fourth side of the display area are disposed opposite to each other;

[0043] The first driving circuit is electrically connected to a plurality of first scanning signal lines and a plurality of second scanning signal lines respectively, the second driving circuit is electrically connected to a plurality of third scanning signal lines, and the third driving circuit is electrically connected to a plurality of light emitting signal lines;

[0044] The second driving circuit is located at a first side of the display area, and the first driving circuit and the third driving circuit are located at the second side of the display area.

[0045] In an exemplary embodiment, the invention further comprises: a first power supply line and a second power supply line disposed on the substrate and located in the non-display area;

[0046] The first power supply line is located in the binding area and is electrically connected to the plurality of first power supply lines. The second power supply line is arranged around the display area and is located in the frame area and the binding area. The second power supply line at least partially surrounds the first power supply line.

[0047] In a second aspect, the present disclosure further provides a display device, comprising: the above-mentioned display substrate.

[0048] Other aspects will be apparent upon reading and understanding the drawings and detailed description.

[0049] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0051] Figure 1 It is a structural schematic diagram of a display substrate;

[0052] Figure 2A A schematic diagram of a planar structure of a display substrate Figure 1 ;

[0053] Figure 2B FIG2 is a second schematic diagram of a planar structure of a display substrate;

[0054] Figure 2C A schematic diagram of a planar structure of a display substrate Figure 3 ;

[0055] Figure 3 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0056] Figure 4 for Figure 3 The working timing diagram of the pixel driving circuit provided;

[0057] Figure 5 A schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure;

[0058] Figure 6 for Figure 5 A partial top view of a display substrate is provided;

[0059] Figure 7 for Figure 6 Schematic diagram of some membrane layers;

[0060] Figure 8 is a schematic diagram of a semiconductor layer pattern;

[0061] Fig. 9 is a schematic diagram of a first conductive layer pattern;

[0062] Fig.10 is a schematic diagram after forming a first conductive layer pattern;

[0063] Fig.11 is a schematic diagram of a second conductive layer pattern;

[0064] Fig.12 is a schematic diagram after forming a second conductive layer pattern;

[0065] Fig.13 is a schematic diagram after forming a first planar layer pattern;

[0066] Fig.14 is a schematic diagram of a pattern of a third conductive layer;

[0067] Fig.15 It is a schematic diagram after forming the third conductive layer pattern. DETAILED DESCRIPTION

[0068] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings hereinafter. Note that the embodiments can be implemented in a number of different forms. A person of ordinary skill in the relevant technical field can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0069] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0070] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0071] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0072] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0073] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0074] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0075] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0076] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0077] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0078] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the materials of the precursors forming the multiple structures arranged in the same layer are the same, and the materials finally formed may be the same or different.

[0079] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0080] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0081] Figure 1 FIG. 1 is a schematic diagram of the structure of a display substrate. Figure 1 As shown, the display substrate may include a timing controller, a data driver, a gate driver and a pixel array, the timing controller is respectively connected to the data driver and the gate driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), and the gate driver is respectively connected to a plurality of gate lines (G1 to Gm). The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a pixel driving circuit and a light-emitting device connected to the pixel driving circuit, and the pixel driving circuit may be respectively connected to the gate line and the data signal line.

[0082] In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, a clock signal, a scan start signal, etc. suitable for the specifications of the scan driver to the scan driver, and a clock signal, an emission stop signal, etc. suitable for the specifications of the light emitting driver to the light emitting driver. The data driver may generate a data voltage to be provided to the data signal lines D1, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller. For example, the data driver may sample the grayscale value using the clock signal, and apply a data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number.

[0083] In an exemplary embodiment, the gate driver may generate a scan signal to be provided to the gate line by receiving a clock signal, a gate start signal, etc. from a timing controller. For example, the scan driver may sequentially provide a scan signal having an on-level pulse to the gate line. For example, the gate driver may be configured in the form of a shift register, and may sequentially transmit a scan start signal provided in the form of an on-level pulse to a next-level circuit under the control of a clock signal to generate a scan signal.

[0084] Figure 2A A schematic diagram of a planar structure of a display substrate Figure 1 , Figure 2B FIG2 is a schematic diagram of a planar structure of a display substrate. Figure 2C A schematic diagram of a planar structure of a display substrate Figure 3 .like FIG. 2A to FIG. 2C As shown, the display substrate may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light, and the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the gate line and the data signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the gate line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuits of the sub-pixels in which they are located, and the light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which they are located.

[0085] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) emitting red light, the second subpixel P2 may be a blue subpixel (B) emitting blue light, and the third subpixel P3 may be a green subpixel (G) emitting green light.

[0086] In an exemplary embodiment, the shape of the sub-pixel may be rectangular, rhombus, pentagonal or hexagonal, and the three sub-pixels may be arranged horizontally, vertically or in a herringbone pattern, which is not limited in the present disclosure.

[0087] In an exemplary embodiment, a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in parallel horizontally, in parallel vertically, or in a herringbone pattern, which is not limited in the present disclosure. Figure 2A and Figure 2B The description is made by taking an example where a pixel unit includes three sub-pixels. Figure 2A The three sub-pixels in the image are arranged horizontally. Figure 2B The three sub-pixels are arranged in a herringbone pattern.

[0088] In an exemplary embodiment, a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in the present disclosure. Figure 2C The description is made by taking an example where a pixel unit includes four sub-pixels, and the four sub-pixels are arranged in a square.

[0089] In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure, which is not limited in the present disclosure.

[0090] Figure 3 FIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. Figure 3 As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 capacitor C. The pixel driving circuit is electrically connected to the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, the third scanning signal terminal Gate3, the first light emitting signal terminal EM1, the second light emitting signal terminal EM2, the first initial signal terminal INIT1, the second initial signal terminal INIT2 and the first power supply terminal VDD.

[0091] like Figure 3As shown, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first initial signal terminal INIT1, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the third scan signal terminal Gate3, the first electrode of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the fourth transistor The second electrode of T4 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the second light-emitting signal terminal EM2, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4; the control electrode of the seventh transistor T7 is electrically connected to the third scanning signal terminal Gate3, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal terminal INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4; the first plate of the capacitor C is electrically connected to the first node N1, and the second plate of the capacitor C is electrically connected to the first power supply terminal VDD.

[0092] In an exemplary embodiment, the first transistor T1 may be referred to as a node reset transistor, the second transistor T2 may be referred to as a compensation transistor, the third transistor T3 may be referred to as a driving transistor, the fourth transistor T4 may be referred to as a write transistor, the fifth transistor T5 may be referred to as a first light emitting transistor, the sixth transistor T6 may be referred to as a second light emitting transistor, and the seventh transistor T7 may be referred to as an anode reset transistor.

[0093] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor. The active pattern of the low-temperature polysilicon thin film transistor adopts low-temperature polysilicon (Low Temperature Poly-Silicon, referred to as LTPS), and the active pattern of the oxide thin film transistor adopts an oxide semiconductor (Oxide). The low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current. The low-temperature polysilicon thin film transistor and the oxide thin film transistor are integrated on a display substrate to form an LTPO display substrate, which can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.

[0094] In an exemplary embodiment, the first to seventh transistors T1 to T7 may be P-type transistors.

[0095] In an exemplary embodiment, the voltage value of the signal at the first initial signal terminal INIT1 is constant and is a DC signal. The voltage value of the signal at the first initial signal terminal INIT1 may be -3V.

[0096] In an exemplary embodiment, the voltage value of the signal at the second initial signal terminal INIT2 is constant and is a DC signal. The voltage value of the signal at the second initial signal terminal INIT2 may be 0V.

[0097] In an exemplary embodiment, the light emitting device L′ may be electrically connected to the fourth node N4 and the second power supply terminal VSS, respectively.

[0098] In an exemplary embodiment, the first power supply terminal VDD continuously provides a high level signal, and the second power supply terminal VSS continuously provides a low level signal.

[0099] In an exemplary embodiment, the signal received by the second light emitting signal terminal to which the pixel driving circuit of the nth row is connected is the same as the signal received by the first light emitting signal terminal to which the pixel driving circuit of the (n-1)th row is connected.

[0100] In an exemplary embodiment, the signal received by the first scanning signal terminal to which the pixel driving circuit of the nth row is connected is the same as the signal received by the second scanning signal terminal to which the pixel driving circuit of the (n-3)th row is connected.

[0101] In an exemplary embodiment, the light emitting device L may include a current driven device, and a current light emitting diode may be used, such as a micro light emitting diode (Micro Light Emitting Diode, Micro LED for short) or a mini light emitting diode (Mini Light Emitting Diode, Mini LED for short) or an organic light emitting diode (Organic Light Emitting Diode, OLED for short) or a quantum dot light emitting diode (Quantum Light Emitting Diode, QLED for short). The typical size (e.g., length) of a Micro LED may be less than 100 μm, such as 10 μm to 50 μm. The typical size (e.g., length) of a Mini LED may be approximately 100 μm to 300 μm, such as 120 μm to 260 μm.

[0102] In an exemplary embodiment, the organic light emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, the hole blocking layers of all sub-pixels may be a common layer connected together, the light emitting layers of adjacent sub-pixels may have a small overlap, or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap, or may be isolated.

[0103] In an exemplary embodiment, the light emitting device L may include a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode). Exemplarily, the first electrode of the light emitting device is electrically connected to the fourth node N4 in the pixel driving circuit, and the second electrode of the light emitting device is electrically connected to the second power supply terminal VSS.

[0104] Figure 4 for Figure 3 The working timing diagram of the pixel driving circuit provided is as follows. Figure 3The operation process of the exemplary pixel driving circuit in the display phase is used to illustrate an exemplary embodiment of the present disclosure. Figure 4 The explanation is given by taking the first transistor T1 to the seventh transistor T7 as P-type transistors as an example. Figure 3 The pixel driving circuit includes a first transistor T1 to a seventh transistor T7, a capacitor C and 9 signal terminals (a data signal terminal Data, a first scan signal terminal Gate1, a second scan signal terminal Gate2, a third scan signal terminal Gate3, a first initial signal terminal INIT1, a second initial signal terminal INIT2, a first light-emitting signal terminal EM1, a second light-emitting signal terminal EM2 and a first power supply terminal VDD).

[0105] Combination Figure 3 and Figure 4 As shown, the working process of the pixel driving circuit may include:

[0106] The first stage P1 is called the initialization stage, the signal of the first scanning signal terminal Gate1 is a low level signal, the signals of the second scanning signal terminal Gate2, the third scanning signal terminal Gate3, the first light emitting signal terminal EM1 and the second light emitting signal terminal EM2 are high level signals. The first transistor T1 is turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T6, the sixth transistor T7 and the seventh transistor T7 are turned off.

[0107] The first transistor T1 is turned on, and the signal of the first initial signal terminal INIT1 is written into the first node N1 through the turned-on first transistor T1, so as to initialize (reset) the first node N1 and clear the pre-stored voltage inside it, thereby completing the initialization.

[0108] The second stage P2 is called the data writing stage or the threshold compensation stage. The signal of the second scanning signal terminal Gate2 is a low level signal, the signals of the first scanning signal terminal Gate1, the first light emitting signal terminal EM1 and the second light emitting signal terminal EM2 are high level signals, the third scanning signal terminal Gate3 is a low level signal in a partial time period, and the data signal terminal Data outputs a data voltage. The second transistor T2, the fourth transistor T4 and the seventh transistor T7 are turned on, and the first transistor T1, the fifth transistor T5 and the sixth transistor T6 are turned off.

[0109] The second transistor T2 and the fourth transistor T4 are turned on, and the data voltage output by the data signal terminal Data is provided to the first node N1 through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage output by the data signal terminal Data and the threshold voltage of the third transistor T3 is charged into the capacitor C until the voltage of the first node N1 is Vdata-|Vth|, where Vdata is the data voltage output by the data signal terminal Data, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, and the signal of the second initial signal terminal INIT2 is written into the fourth node N4 through the turned-on seventh transistor T7, and the fourth node N4 (also the first electrode of the light-emitting device L) is initialized (reset), and the pre-stored voltage inside it is cleared, completing the initialization.

[0110] The third stage P3 is called the light-emitting stage. The signals of the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are low-level signals, the signals of the first scanning signal terminal Gate1, the second scanning signal terminal Gate2 and the third scanning signal terminal Gate3 are high-level signals, the fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4 and the seventh transistor T7 are turned off.

[0111] The fifth transistor T5 and the sixth transistor T6 are turned on, and the power voltage output from the first power supply terminal VDD provides a driving voltage to the first electrode of the light emitting device L through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the light emitting device L to emit light.

[0112] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0113] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vdata+|Vth|)-Vth] 2 =K*(Vdd-Vdata) 2

[0114] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, and Vdd is the power supply voltage output by the first power supply terminal VDD.

[0115] include Figure 3The display substrate of the provided pixel driving circuit will generate redundant transistors during layout design, thereby reducing the reliability of the display substrate.

[0116] Figure 5 A schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure, Figure 6 for Figure 5 A partial top view of a display substrate is provided, Figure 7 for Figure 6 Schematic diagram of some membrane layers. Figures 5 to 7 As shown, the display substrate provided by the embodiment of the present disclosure has a display area AA and a non-display area BB located at least on one side of the display area AA. The display substrate may include: a substrate and a pixel driving circuit arranged in an array on the substrate and located in the display area, a plurality of scanning signal lines and a plurality of light-emitting signal lines. At least one pixel driving circuit includes: at least one transistor, and at least one transistor includes: a write transistor (a fourth transistor T4), a reset transistor (a first transistor T1 and a seventh transistor T7), a compensation transistor (a second transistor T2) and a light-emitting transistor (a fifth transistor T5 and a sixth transistor T6). The control electrode of at least one of the write transistor (the fourth transistor T4), the reset transistor and the compensation transistor (the second transistor T2) in at least one pixel driving circuit is electrically connected to at least one scanning signal line, and the light-emitting transistor in at least one pixel driving circuit is electrically connected to at least one light-emitting signal line. The present disclosure is described by taking the multiple scanning signal lines including: a first scanning signal line GateL1, a second scanning signal line GateL2 and a third scanning signal line GateL3, and the multiple light-emitting signal lines including: a first light-emitting signal line EML1 and a second light-emitting signal line EML2 as an example.

[0117] like Figure 6 and Figure 7 As shown, the plurality of scanning signal lines and the plurality of light emitting signal lines in the present disclosure are arranged in different layers.

[0118] The multiple scanning signal lines and the multiple light-emitting signal lines in the display substrate provided by the present disclosure can avoid the formation of redundant transistors during the layout design of the display substrate, thereby simplifying the layout design of the display substrate and improving the reliability of the display substrate.

[0119] In an exemplary embodiment, the plurality of light emitting signal lines may be located at a side of the plurality of scanning signal lines that is away from the substrate.

[0120] In an exemplary embodiment, the display substrate further includes: light-emitting devices arranged in an array on the substrate and located in the display area, the first electrode of at least one light-emitting device is electrically connected to at least one pixel driving circuit, the at least one transistor further includes: a driving transistor (third transistor T3), the reset transistor includes: an anode reset transistor (seventh transistor T7) and a node reset transistor (first transistor T1), the anode reset transistor (seventh transistor T7) is electrically connected to the first electrode of the at least one light-emitting device, the node reset transistor (first transistor T1) is electrically connected to the control electrode of the driving transistor (third transistor T3), the write transistor (fourth transistor T4) is electrically connected to the first electrode of the driving transistor (third transistor T3), and the compensation transistor (second transistor T2) is electrically connected to the control electrode and the second electrode of the driving transistor (third transistor T3), respectively; the scanning signal line includes: a first scanning signal line GateL1, a second scanning signal line GateL2, and a third scanning signal line GateL3.

[0121] In an exemplary embodiment, the control electrode of the node reset transistor (first transistor T1) of at least one pixel driving circuit is electrically connected to at least one first scanning signal line GateL1, the control electrode of the compensation transistor (second transistor T2) of at least one pixel driving circuit is electrically connected to at least one second scanning signal line GateL2, and the control electrode of the write transistor (fourth transistor T4) and the control electrode of the anode reset transistor (seventh transistor T7) of at least one pixel driving circuit are respectively electrically connected to at least one third scanning signal line GateL3.

[0122] In an exemplary embodiment, the signal received by the first scanning signal line GateL1 to which the pixel driving circuits of the nth row are connected is the same as the signal received by the second scanning signal line GateL2 to which the pixel driving circuits of the n-3th row are connected.

[0123] In an exemplary embodiment, if Figure 6 and Figure 7 As shown, at least one of the first scan signal line GateL1 , the second scan signal line GateL2 , and the third scan signal line GateL3 at least partially extends along the first direction D1 .

[0124] In an exemplary embodiment, if Figure 6 and Figure 7 As shown, the orthographic projection of the first scanning signal line GateL1 connected to at least one pixel driving circuit on the substrate, the orthographic projection of the second scanning signal line GateL2 on the substrate and the orthographic projection of the third scanning signal line GateL3 on the substrate are arranged in sequence along the second direction D2, and the first direction D1 intersects the second direction D2.

[0125] In an exemplary embodiment, the light emitting transistor includes: a first light emitting transistor (fifth transistor T5) and a second light emitting transistor (sixth transistor T6), the first light emitting transistor (fifth transistor T5) is electrically connected to the first electrode of the driving transistor (third transistor T3), the second light emitting transistor (sixth transistor T6) is electrically connected to the second electrode of the driving transistor (third transistor T3) and the first electrode of the light emitting device electrically connected to the pixel drive, respectively, and the light emitting signal line includes: a first light emitting signal line EML1 and a second light emitting signal line EML2.

[0126] In an exemplary embodiment, the control electrode of the first light-emitting transistor (fifth transistor T5) of at least one pixel driving circuit is electrically connected to at least one first light-emitting signal line EML1, and the control electrode of the second light-emitting transistor (sixth transistor T6) of at least one pixel driving circuit is electrically connected to at least one second light-emitting signal line EML2.

[0127] In an exemplary embodiment, the second light emitting signal line EML2 to which the pixel driving circuit of the nth row is connected receives the same signal as the first light emitting signal line EML1 to which the pixel driving circuit of the n-1th row is connected receives.

[0128] In an exemplary embodiment, a control electrode of at least one of the first light emitting transistor (fifth transistor T5) and the second light emitting transistor (sixth transistor T6) is located on a side of at least one of the first light emitting signal line EML1 and the second light emitting signal line EML2 close to the substrate.

[0129] In an exemplary embodiment, if Figure 6 and Figure 7 As shown, at least one of the first light emitting signal line EML1 and the second light emitting signal line EML2 at least partially extends along the first direction D1.

[0130] In an exemplary embodiment, if Figure 6 and Figure 7 As shown, the orthographic projection of the first light emitting signal line EML1 connected to at least one pixel driving circuit on the substrate is located between the orthographic projection of the second scanning signal line GateL2 on the substrate and the orthographic projection of the third scanning signal line GateL3 on the substrate.

[0131] In an exemplary embodiment, if Figure 6 and Figure 7 As shown, the orthographic projection of the second light emitting signal line EML2 connected to at least one pixel driving circuit on the substrate is located on a side of the orthographic projection of the third scanning signal line GateL3 on the substrate away from the orthographic projection of the second scanning signal line GateL2 on the substrate.

[0132] In an exemplary embodiment, if Figure 6and Figure 7 As shown, the positive projection of the control electrode of at least one of the first light-emitting transistor (fifth transistor T5) and the second light-emitting transistor (sixth transistor T6) of at least one pixel driving circuit on the substrate is located between the positive projection of the first light-emitting signal line EML1 connected to at least one pixel driving circuit on the substrate and the positive projection of the third scanning signal line GateL3 on the substrate. Figure 6 In the figure, 52 represents the control electrode of the first light emitting transistor, and 62 represents the control electrode of the second light emitting transistor.

[0133] In an exemplary embodiment, if Figure 6 and Figure 7 As shown, the display substrate further includes: a plurality of first connection electrodes L1 disposed on the base and located in the display area, and the first connection electrodes L1 are located on a side of the plurality of light emitting signal lines away from the base.

[0134] In an exemplary embodiment, if Figure 6 and Figure 7 As shown, at least one first connection electrode L1 is electrically connected to the control electrode 52 of the first light emitting transistor (fifth transistor T5) of at least one pixel driving circuit and at least one first light emitting signal line EML1 respectively.

[0135] In an exemplary embodiment, if Figure 6 and Figure 7 As shown, the display substrate further includes: a plurality of second connection electrodes L2 disposed on the base and located in the display area, and the second connection electrodes L2 are located on a side of the plurality of light emitting signal lines away from the base.

[0136] In an exemplary embodiment, if Figure 6 and Figure 7 As shown, at least one second connection electrode L2 is electrically connected to the control electrode 62 of the second light emitting transistor (sixth transistor T6) of at least one pixel driving circuit and at least one second light emitting signal line EML2 respectively.

[0137] In an exemplary embodiment, if Figure 6 and Figure 7 As shown, the orthographic projection of at least one second connection electrode 62 on the substrate at least partially overlaps with the orthographic projection of at least one third scanning signal line GateL3 connected to the pixel driving circuit on the substrate.

[0138] In an exemplary embodiment, if Figure 6 and Figure 7As shown, the display substrate also includes: a plurality of first power lines VDDL and a plurality of data signal lines DataL arranged on the base and located in the display area, a write transistor (fourth transistor T4) in at least one pixel driving circuit is electrically connected to at least one data signal line DataL, and a first light-emitting transistor (fifth transistor T5) in at least one pixel driving circuit is electrically connected to at least one first power line VDDL.

[0139] In an exemplary embodiment, if Figure 6 and Figure 7 As shown, at least one signal line among the plurality of first power lines VDDL and the plurality of data signal lines DataL at least partially extends along the second direction D2.

[0140] In an exemplary embodiment, if Figure 6 and Figure 7 As shown, at least one of the multiple first power lines VDDL and the multiple data signal lines DataL is arranged in the same layer as the first electrode and the second electrode of at least one transistor in at least one pixel driving circuit, that is, the display substrate in the present disclosure is a single source-drain metal layer structure.

[0141] The first electrode of the write transistor in the present disclosure is the same film layer as the data signal line, that is, the data signal transmitted by the data signal line is transmitted in the film layer where the data signal line is located without jumps, which can ensure the stability of data signal transmission and improve the brightness stability of the display substrate.

[0142] In the present disclosure, at least one signal line among the multiple first power lines VDDL and the multiple data signal lines DataL is arranged on the same layer as the first electrode and the second electrode of at least one transistor in at least one pixel driving circuit, thereby reducing the arrangement space of the film layer where the multiple first power lines VDDL, the multiple data signal lines DataL and the first electrode and the second electrode of at least one transistor in at least one pixel driving circuit are located, and avoiding the short circuit between the scanning signal line, the light-emitting signal line, and the first power line and the data signal line.

[0143] In an exemplary embodiment, if Figure 6 and Figure 7 As shown, the orthographic projection of the first power line VDDL connected to at least one pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the control electrode 52 of the first light-emitting transistor (fifth transistor T5) on the substrate, and there is no overlapping area with the orthographic projection of the control electrode 62 of the second light-emitting transistor (sixth transistor T6) on the substrate.

[0144] In an exemplary embodiment, if Figure 6 and Figure 7As shown, at least one pixel driving circuit further includes: a capacitor C, the capacitor includes: a second plate C2, the second plate C2 of the capacitor of at least one pixel driving circuit is electrically connected to at least one first power line VDDL, and the second plates of the capacitors of at least two pixel driving circuits located in the same row are arranged along the first direction D1 and are connected to each other. The second plates of the capacitors of at least two pixel driving circuits located in the same row are equivalent to the power connection line for transmitting the power signal extending along the first direction and the multiple first power lines extending along the second direction forming a mesh structure, so that the power signals transmitted by different pixel driving circuits are the same, which can improve the brightness uniformity of the display substrate.

[0145] In an exemplary embodiment, if Figure 6 and Figure 7 As shown, the display substrate may further include: a plurality of first initial signal lines INITL1 and a plurality of second initial signal lines INITL2 arranged on the substrate and located in the display area, a node reset transistor (first transistor T1) in at least one pixel driving circuit electrically connected to at least one first initial signal line INITL1, and an anode reset transistor (seventh transistor T7) in at least one pixel driving circuit electrically connected to at least one second initial signal line INITL2.

[0146] In an exemplary embodiment, if Figure 6 and Figure 7 As shown, at least one signal line among the plurality of first initial signal lines INITL1 and the plurality of second initial signal lines INITL2 at least partially extends along the first direction D1.

[0147] In an exemplary embodiment, if Figure 6 and Figure 7 As shown, the orthographic projection of the first initial signal line INITL1 connected to at least one pixel driving circuit on the substrate is located between the orthographic projection of the first scanning signal line GateL1 on the substrate and the orthographic projection of the second scanning signal line GateL2 on the substrate.

[0148] In an exemplary embodiment, if Figure 6 and Figure 7 As shown, the positive projection of the second initial signal line INITL2 connected to at least one pixel driving circuit on the substrate is located on a side of the positive projection of the second light emitting signal line EML2 on the substrate away from the positive projection of the third scanning signal line GateL3 on the substrate.

[0149] In an exemplary embodiment, the display substrate further includes: a circuit structure layer disposed on the base, the circuit structure layer including: a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer sequentially stacked on the base.

[0150] In an exemplary embodiment, the semiconductor layer includes an active pattern of at least one transistor of at least one pixel driving circuit.

[0151] In an exemplary embodiment, the first conductive layer includes: a plurality of scan signal lines, a control electrode of at least one transistor of at least one pixel driving circuit, and a first plate of at least one capacitor.

[0152] In an exemplary embodiment, the second conductive layer includes: a plurality of light emitting signal lines, a plurality of first initial signal lines, a plurality of second initial signal lines, and a second plate of at least one capacitor of at least one pixel driving circuit.

[0153] In an exemplary embodiment, the third conductive layer includes a plurality of first power lines, a plurality of data signal lines, a plurality of first connection electrodes, a plurality of second connection electrodes, and a first electrode and a second electrode of at least one transistor of at least one pixel driving circuit.

[0154] In an exemplary embodiment, the display substrate further includes: a first driving circuit, a second driving circuit, and a third driving circuit disposed on the substrate and located in the non-display area. The non-display area includes: a frame area and a binding area, the frame area is located on the first side, the second side, and the third side of the display area, the binding area is located on the fourth side of the display area, the first side and the second side of the display area are arranged oppositely, and the third side and the fourth side of the display area are arranged oppositely.

[0155] In an exemplary embodiment, the first driving circuit is electrically connected to the plurality of first scanning signal lines GateL1 and the plurality of second scanning signal lines GateL2, respectively, the second driving circuit is electrically connected to the plurality of third scanning signal lines GateL3, and the third driving circuit is electrically connected to the plurality of light emitting signal lines.

[0156] In an exemplary embodiment, the second driving circuit is located at a first side of the display area, and the first driving circuit and the third driving circuit are located at a second side of the display area.

[0157] In an exemplary embodiment, if Figure 5 As shown, the display substrate may further include: a first power supply line VL1 and a second power supply line VL2 disposed on the base and located in the non-display area.

[0158] In an exemplary embodiment, if Figure 5 As shown, the first power supply line VL1 is located in the binding area BB2 and is electrically connected to a plurality of first power lines.

[0159] In an exemplary embodiment, if Figure 5As shown, the second power supply line VL2 is arranged around the display area AA and is located in the frame area BB1 and the binding area BB2. The second power supply line VL2 at least partially surrounds the first power supply line VL1. The second power supply line VL2 is electrically connected to the second electrode of at least one light emitting device.

[0160] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0161] The following is based on Figures 8 to 15 As shown, Figures 8 to 15 The following is explained by taking a pixel driving circuit as an example. The preparation process of the display substrate provided by the present disclosure may include:

[0162] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a semiconductor thin film on a substrate, patterning the semiconductor thin film through a patterning process, and forming a semiconductor layer pattern, such as Figure 8 As shown, Figure 8 Schematic diagram of semiconductor layer pattern.

[0163] In an exemplary embodiment, if Figure 8As shown, the semiconductor layer pattern may include at least: an active pattern of at least one transistor located in at least one pixel driving circuit. The active pattern of at least one transistor may include: an active pattern 11 of a first transistor, an active pattern 21 of a second transistor, an active pattern 31 of a third transistor, an active pattern 41 of a fourth transistor, an active pattern 51 of a fifth transistor, an active pattern 61 of a sixth transistor, and an active pattern 71 of a seventh transistor.

[0164] In an exemplary embodiment, the active pattern 11 of the first transistor to the active pattern 71 of the seventh transistor are an integral structure connected to each other.

[0165] In an exemplary embodiment, for at least one pixel driving circuit, in the first direction D1, the active pattern 21 of the second transistor, the active pattern 61 of the sixth transistor, and the active pattern 71 of the seventh transistor may be located on the same side of the active pattern 31 of the third transistor, the active pattern 41 of the fourth transistor and the active pattern 51 of the fifth transistor may be located on the same side of the active pattern 31 of the third transistor, and the active pattern 21 of the second transistor and the active pattern 41 of the fourth transistor may be located on different sides of the active pattern 31 of the third transistor of the present sub-pixel. In the second direction D2, for at least one pixel driving circuit, the active pattern 11 of the first transistor and the active pattern 21 of the second transistor may be located on a side of the active pattern 31 of the third transistor close to the pixel driving circuit of the previous row, and the active pattern 41 of the fourth transistor, the active pattern 51 of the fifth transistor, the active pattern 61 of the sixth transistor, and the active pattern 71 of the seventh transistor may be located on a side of the active pattern 31 of the third transistor close to the pixel driving circuit of the next row. The active pattern 51 of the fifth transistor and the active pattern 61 of the sixth transistor are arranged along the first direction D1 , and the active pattern 41 of the fourth transistor and the active pattern 71 of the seventh transistor are arranged along the first direction D1 .

[0166] In an exemplary embodiment, the active pattern 11 of the first transistor may be in an "n" shape, the active pattern 41 of the fourth transistor, the active pattern 61 of the sixth transistor, and the active pattern 71 of the seventh transistor may be in an "I" shape. The active pattern 21 of the second transistor may be in a horizontally flipped "7" shape, the active pattern 13 of the third transistor may be in an "S" shape, and the active pattern 51 of the fifth transistor may be in a horizontally flipped "h" shape.

[0167] In an exemplary embodiment, the active pattern of each transistor may include a first region, a second region, and a channel region between the first region and the second region. In an exemplary embodiment, the second region 11-2 of the active pattern 11 of the first transistor may serve as the first region 21-1 of the active pattern 21 of the second transistor, the first region 31-1 of the active pattern 31 of the third transistor may serve as the second region 41-2 of the active pattern 41 of the fourth transistor and the second region 51-2 of the active pattern 51 of the fifth transistor, the second region 31-2 of the active pattern 31 of the third transistor may serve as the second region 21-2 of the active pattern 21 of the second transistor and the first region 61-1 of the active pattern 61 of the sixth transistor, and the second region 61-2 of the active pattern 61 of the sixth transistor may serve as the second region 71-2 of the active pattern 71 of the seventh transistor. The first region 11 - 1 of the active pattern 11 of the first transistor, the first region 41 - 1 of the active pattern 41 of the fourth transistor, the first region 51 - 1 of the active pattern 51 of the fifth transistor, and the first region 71 - 1 of the active pattern 71 of the seventh transistor may be separately provided.

[0168] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first insulating film and a first conductive film on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process, and forming a first insulating layer and a first conductive layer pattern formed on the first insulating layer. Fig. 9 and Fig.10 As shown, Fig. 9 is a schematic diagram of a first conductive layer pattern, Fig.10 It is a schematic diagram after forming the first conductive layer pattern.

[0169] In an exemplary embodiment, if Fig. 9 and Fig.10 As shown, the first conductive layer pattern may at least include: a first scanning signal line GateL1, a second scanning signal line GateL2, a third scanning signal line GateL3, and a control electrode of at least one transistor located in at least one pixel driving circuit, and a first electrode plate C1 of a capacitor. The control electrode of at least one transistor of at least one pixel driving circuit may include: a control electrode 12 of a first transistor, a control electrode 22 of a second transistor, a control electrode 32 of a third transistor, a control electrode 42 of a fourth transistor, a control electrode 52 of a fifth transistor, a control electrode 62 of a sixth transistor, and a control electrode 72 of a seventh transistor.

[0170] In an exemplary embodiment, the first scanning signal line GateL1 and the second scanning signal line GateL2 connected to at least one pixel driving circuit may be located on a side of the first plate C1 of the capacitor of the pixel driving circuit close to the pixel driving circuit of the previous row, and the first scanning signal line GateL1 connected to at least one pixel driving circuit is located on a side of the second scanning signal line GateL2 away from the first plate C1 of the capacitor.

[0171] In an exemplary embodiment, the shape of the first scan signal line GateL1 may be a line shape in which the main part extends along the first direction D1. The area where the first scan signal line GateL1 overlaps with the active pattern of the first transistor of at least one pixel driving circuit serves as the control electrode 12 of the first transistor. Since the active pattern of the first transistor is in an "n" shape, the area where the first scan signal line GateL1 overlaps with the active pattern of the first transistor of at least one pixel driving circuit includes two areas, and the first transistor has a double-gate structure.

[0172] In an exemplary embodiment, at least one second scan signal line GateL2 is provided with a gate block 25, a first end of the gate block 25 is connected to the second scan signal line GateL2, and a second end of the gate block 25 extends in a direction away from the first electrode plate C1 of the capacitor. An area where the second scan signal line GateL2 and the gate block 25 overlap with an active pattern of a second transistor of at least one pixel driving circuit serves as a control electrode of the second transistor T2 of the double-gate structure.

[0173] In an exemplary embodiment, the shape of the third scan signal line GateL3 can be a line shape in which the main part extends along the first direction D1, and the area where the third scan signal line GateL3 overlaps with the active pattern of the fourth transistor of at least one pixel driving circuit serves as the control electrode 42 of the fourth transistor, and the area where the third scan signal line GateL3 overlaps with the active pattern of the seventh transistor of at least one pixel driving circuit serves as the control electrode 72 of the seventh transistor.

[0174] In an exemplary embodiment, the shape of the first plate C1 of the capacitor may be rectangular, and the corners of the rectangle may be chamfered. In an exemplary embodiment, the first plate C1 of the capacitor may also serve as the control electrode 32 of the third transistor.

[0175] In an exemplary embodiment, the control electrode 62 of the sixth transistor of the at least one pixel driving circuit is located between the control electrode 52 of the fifth transistor and the third scanning signal line GateL3 to which the at least one pixel driving circuit is connected.

[0176] In an exemplary embodiment, the control electrode 52 of the fifth transistor is separately provided. The control electrode 52 of the fifth transistor may be in the shape of a strip extending along the first direction D1.

[0177] In an exemplary embodiment, the control electrode 62 of the sixth transistor is separately provided. The control electrode 62 of the sixth transistor may be in the shape of a strip extending at least partially along the first direction D1.

[0178] In an exemplary embodiment, the first scanning signal line GateL1, the second scanning signal line GateL2, and the third scanning signal line GateL3 can be designed with equal width, or can be designed with unequal width, can be straight lines, or can be broken lines, which can not only facilitate the layout of the pixel structure but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.

[0179] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform a conductor processing on the semiconductor layer, and the semiconductor layer in the area shielded by the first conductive layer forms the channel area of ​​the first transistor T1 to the seventh transistor T7, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of ​​the first transistor T1 to the seventh active layer are both conductorized. The second area of ​​the active pattern of the second transistor (also the second area of ​​the active pattern of the third transistor and the first area of ​​the active pattern of the sixth transistor) can be used as the second electrode 24 of the second transistor (also the second electrode 34 of the third transistor and the first electrode 63 of the sixth transistor), and the first area of ​​the active pattern of the third transistor (also the second area of ​​the active pattern of the fourth transistor and the second area of ​​the active pattern of the fifth transistor) can be used as the first electrode 33 of the third transistor (also the second electrode 44 of the fourth transistor and the second electrode 64 of the fifth transistor).

[0180] In an exemplary embodiment, the control electrode 12 of the first transistor is arranged across the active pattern of the first transistor, the control electrode 22 of the second transistor is arranged across the active pattern of the second transistor, the control electrode 32 of the third transistor is arranged across the active pattern of the third transistor, the control electrode 42 of the fourth transistor is arranged across the active pattern of the fourth transistor, the control electrode 52 of the fifth transistor is arranged across the active pattern of the fifth transistor, the control electrode 62 of the sixth transistor is arranged across the active pattern of the sixth transistor, and the control electrode 72 of the seventh transistor is arranged across the active pattern of the seventh transistor, that is, the extension direction of the control electrode of at least one transistor is perpendicular to the extension direction of the active pattern.

[0181] (3) forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second insulating film and a second conductive film in sequence on the substrate having the aforementioned pattern, patterning the second conductive film by a patterning process, forming a second insulating layer and a second conductive layer pattern on the second insulating layer, such as Fig.11 and Fig.12 As shown, Fig.11 is a schematic diagram of a second conductive layer pattern, Fig.12 It is a schematic diagram after forming the second conductive layer pattern.

[0182] In an exemplary embodiment, if Fig.11 and Fig.12 As shown, the second conductive layer pattern may include: a first initial signal line INITL1, a second initial signal line INITL2, a first light emitting signal line EML1, a second light emitting signal line EML2, and a second plate C2 of a capacitor located in at least one pixel driving circuit.

[0183] In an exemplary embodiment, the outline of the second plate C2 of the capacitor may be rectangular, and the corners of the rectangle may be chamfered, and the orthographic projection of the second plate C2 of the capacitor on the substrate at least partially overlaps with the orthographic projection of the first plate C2 of the capacitor on the substrate. An opening V is provided on the second plate C2 of the capacitor, and the shape of the opening V may be rectangular, and may be located in the middle of the second plate C2 of the capacitor, so that the second plate C2 of the capacitor forms a ring structure. The opening V exposes the second insulating layer covering the first plate of the capacitor, and the orthographic projection of the first plate C2 of the capacitor on the substrate includes the orthographic projection of the opening V on the substrate.

[0184] In an exemplary embodiment, the second plates C2 of the capacitors in two adjacent pixel driving circuits in the same row may be connected to each other. In an exemplary embodiment, since the second plates C2 of the capacitors in each pixel driving circuit are connected to the first power line formed subsequently, by forming the second plates C2 of the capacitors of adjacent pixel driving circuits into an integrated structure connected to each other, the second plates of the integrated structure may be reused as a power signal line, and it may be ensured that the plurality of second plates in the pixel driving circuits in at least one row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0185] In an exemplary embodiment, the shape of the first initial signal line INITL1 may be a line shape whose main portion extends along the first direction D1. The orthographic projection of the first initial signal line INITL1 connected to at least one pixel driving circuit on the substrate is located between the orthographic projection of the first scan signal line on the substrate and the orthographic projection of the second scan signal line on the substrate.

[0186] In an exemplary embodiment, the shape of the second initial signal line INITL2 may be a line shape whose main portion extends along the first direction D1. The positive projection of the second initial signal line INITL2 connected to at least one pixel driving circuit on the substrate is located on a side of the positive projection of the second light emitting signal line EML2 on the substrate away from the positive projection of the third scanning signal line on the substrate.

[0187] In an exemplary embodiment, the shape of the first light emitting signal line EML2 may be a line shape in which the main portion extends along the first direction D1. The positive projection of the first light emitting signal line connected to at least one pixel driving circuit on the substrate is located between the positive projection of the capacitor on the substrate and the positive projection of the control electrode of at least one of the fifth transistor and the sixth transistor on the substrate.

[0188] In an exemplary embodiment, the shape of the second light emitting signal line EML2 may be a line shape in which the main part extends along the first direction D1. The positive projection of the second light emitting signal line EML2 connected to at least one pixel driving circuit on the substrate is located on a side of the positive projection of the third scanning signal line on the substrate away from the positive projection of the first light emitting signal line EML1 on the substrate.

[0189] In an exemplary embodiment, the first initial signal line INITL1, the second initial signal line INITL2, the first light-emitting signal line EML1, and the second light-emitting signal line EML2 can be designed with equal width, or can be designed with unequal width, can be straight ends, or can be folded ends, which can not only facilitate the layout of the pixel structure but also reduce the parasitic capacitance between the signal ends, which is not limited in the present disclosure.

[0190] (4) forming a first planar layer pattern, comprising: depositing a third insulating film on the substrate having the aforementioned pattern, coating the first planar film, patterning the third insulating film and the first planar film by a patterning process to form a third insulating layer pattern and a first planar layer pattern covering the aforementioned pattern, wherein the first planar layer pattern is provided with a plurality of via hole patterns, such as Fig.13 As shown, Fig.13 It is a schematic diagram after forming the first planar layer pattern.

[0191] In an exemplary embodiment, if Fig.13 As shown, the plurality of via holes of the first planar layer pattern at least include: a first via hole V1 to a fourteenth via hole V14.

[0192] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the first transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the first via hole V1 are etched away to expose the surface of the first area of ​​the active pattern of the first transistor, and the first via hole V1 is configured to connect the first electrode of the first transistor formed subsequently to the first area of ​​the active pattern of the first transistor through the via hole.

[0193] In an exemplary embodiment, the orthographic projection of the second via V2 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the first transistor (the first area of ​​the active pattern of the second transistor) on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the second via V2 are etched away to expose the surface of the second area of ​​the active pattern of the first transistor (the first area of ​​the active pattern of the second transistor), and the second via V2 is configured to connect the second electrode of the first transistor (also the first electrode of the second transistor) to be formed subsequently to the second area of ​​the active pattern of the first transistor (the first area of ​​the active pattern of the second transistor) through the via.

[0194] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fourth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the third via hole V3 are etched away to expose the surface of the first area of ​​the active pattern of the fourth transistor, and the third via hole V3 is configured to connect the first electrode of the subsequently formed fourth transistor to the first area of ​​the active pattern of the fourth transistor through the via hole.

[0195] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fifth transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the fourth via V4 are etched away to expose the surface of the first area of ​​the active pattern of the fifth transistor, and the fourth via V4 is configured to connect the first electrode of the subsequently formed fifth transistor to the first area of ​​the active pattern of the fifth transistor through the via.

[0196] In an exemplary embodiment, the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the sixth transistor (also the second area of ​​the active pattern of the seventh transistor) on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the fifth via V5 are etched away to expose the surface of the second area of ​​the active pattern of the sixth transistor (also the second area of ​​the active pattern of the seventh transistor), and the fifth via V5 is configured to connect the second electrode of the subsequently formed sixth transistor (also the second electrode of the seventh transistor) to the second area of ​​the active pattern of the sixth transistor (also the second area of ​​the active pattern of the seventh transistor) through the via.

[0197] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the seventh transistor on the substrate, the first insulating layer, the second insulating layer and the third insulating layer in the sixth via V6 are etched away to expose the surface of the first area of ​​the active pattern of the seventh transistor, and the sixth via V6 is configured to connect the first electrode of the subsequently formed seventh transistor to the first area of ​​the active pattern of the seventh transistor through the via.

[0198] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the first electrode plate of the capacitor (also the control electrode of the third transistor) on the substrate, the second insulating layer and the third insulating layer in the seventh via V7 are etched away to expose the surface of the first electrode plate of the capacitor (also the control electrode of the third transistor), and the seventh via V7 is configured to connect the second electrode of the subsequently formed first transistor (also the first electrode of the second transistor) to the first electrode plate of the first capacitor (also the control electrode of the third transistor) through the via.

[0199] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the control electrode of the fifth transistor on the substrate, the second insulating layer and the third insulating layer in the eighth via V8 are etched away to expose the surface of the control electrode of the fifth transistor, and the eighth via V8 is configured to connect a subsequently formed first connecting electrode to the control electrode of the fifth transistor through the via.

[0200] In an exemplary embodiment, the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the control electrode of the sixth transistor on the substrate, the second insulating layer and the third insulating layer in the ninth via hole V9 are etched away to expose the surface of the control electrode of the sixth transistor, and the ninth via hole V9 is configured to connect a subsequently formed second connecting electrode to the control electrode of the sixth transistor through the via hole.

[0201] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the second plate of the capacitor on the substrate, the third insulating layer in the tenth via hole V10 is etched away to expose the surface of the second plate of the capacitor, and the tenth via hole V10 is configured to connect a subsequently formed first power line to the second plate of the capacitor through the via hole.

[0202] In an exemplary embodiment, the orthographic projection of the eleventh via V11 on the substrate is located within the range of the orthographic projection of the first initial signal line on the substrate, the third insulating layer in the eleventh via V11 is etched away to expose the surface of the first initial signal line, and the eleventh via V11 is configured to connect the first electrode of a subsequently formed first transistor to the first initial signal line through the via.

[0203] In an exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the first light-emitting signal line on the substrate, the third insulating layer in the twelfth via hole V12 is etched away to expose the surface of the first light-emitting signal line, and the twelfth via hole V12 is configured to connect a subsequently formed first connecting electrode to the first light-emitting signal line through the via hole.

[0204] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the second light-emitting signal line on the substrate, the third insulating layer in the thirteenth via hole V13 is etched away to expose the surface of the second light-emitting signal line, and the thirteenth via hole V13 is configured to connect a subsequently formed second connecting electrode to the second light-emitting signal line through the via hole.

[0205] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the second initial signal line on the substrate, the third insulating layer in the fourteenth via V14 is etched away to expose the surface of the second initial signal line, and the fourteenth via V14 is configured to connect the first electrode of the subsequently formed seventh transistor to the second initial signal line through the via.

[0206] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film through a patterning process to form the third conductive layer pattern, Fig.14 and Fig.15 As shown, Fig.14 is a schematic diagram of a pattern of the third conductive layer, Fig.15 FIG. 2 is a schematic diagram of a third conductive layer after patterning. In an exemplary embodiment, the third conductive layer may be referred to as a source-drain metal (SD) layer.

[0207] In an exemplary embodiment, Fig.14 and Fig.15 As shown, the third conductive layer pattern may include: a first power line VDDL, a data signal line DataL, and a first electrode and a second electrode, a first connection electrode L1 and a second connection electrode L2 of at least one transistor located in at least one pixel driving circuit. The first electrode and the second electrode of at least one transistor located in at least one pixel driving circuit include: a first electrode 13 and a second electrode 14 of the first transistor, a first electrode 21 and a second electrode 22 of the second transistor, a first electrode 31 and a second electrode 32 of the third transistor, a first electrode 41 and a second electrode 42 of the fourth transistor, a first electrode 51 and a second electrode 52 of the fifth transistor, a first electrode 61 and a second electrode 62 of the sixth transistor, and a first electrode 71 and a second electrode 72 of the seventh transistor.

[0208] In an exemplary embodiment, the data signal line DataL may be in a line shape with a main portion extending along the second direction D2. A portion of the data signal line VDDL may serve as a first electrode 43 of the fourth transistor. The data signal line DataL is connected to the first region of the active pattern of the fourth transistor through a third via hole.

[0209] In an exemplary embodiment, the shape of the first power line VDDL may be a line shape in which the main portion extends along the second direction D2. A portion of the first power line VDDL may serve as the first electrode 53 of the fifth transistor. The first power line VDDL is connected to the first region of the active pattern of the fifth transistor through the fourth via hole, and is connected to the second plate of the capacitor through the tenth via hole.

[0210] In an exemplary embodiment, the first electrode 13 of the first transistor is separately provided and has a strip shape extending along the first direction D1. The first electrode 13 of the first transistor of at least one pixel driving circuit is connected to the first region of the active pattern of the first transistor through a first via hole.

[0211] In an exemplary embodiment, the second electrode 14 of the first transistor and the first electrode 23 of the second transistor are an integrated structure. The shape of the integrated structure of the second electrode 14 of the first transistor and the first electrode 23 of the second transistor is a strip extending along the second direction D2. The second electrode 14 of the first transistor of at least one pixel driving circuit (also the first electrode 23 of the second transistor) is connected to the second area of ​​the active pattern of the first transistor (also the first area of ​​the active pattern of the second transistor) through the second via hole, and is connected to the control electrode of the third transistor (also the first plate of the capacitor) through the seventh via hole.

[0212] In an exemplary embodiment, the second electrode 64 of the sixth transistor and the second electrode 74 of the seventh transistor are an integrated structure. The shape of the integrated structure of the second electrode 64 of the sixth transistor and the second electrode 74 of the seventh transistor may be a strip extending along the second direction D2. The second electrode 64 of the sixth transistor of at least one pixel driving circuit (also the second electrode 74 of the seventh transistor) is connected to the second area of ​​the active pattern of the sixth transistor (also the second area of ​​the active pattern of the seventh transistor) through the fifth via.

[0213] In an exemplary embodiment, the first electrode 73 of the seventh transistor is in the shape of a strip extending along the second direction D2. The first electrode of the seventh transistor of at least one pixel driving circuit is connected to the first region of the active pattern of the seventh transistor through the sixth via hole, and is electrically connected to the second initial signal line through the fourteenth via hole.

[0214] In an exemplary embodiment, the first connection electrode L1 is in the shape of a strip extending along a third direction, and the third direction intersects the first direction D1 and the second direction D2. The first connection electrode L1 of at least one pixel driving circuit is connected to the control electrode of the fifth transistor through the eighth via hole, and is electrically connected to the first light emitting signal line through the twelfth via hole.

[0215] In an exemplary embodiment, the second connection electrode L2 is in the shape of a strip extending along the second direction D2. The second connection electrode L2 of at least one pixel driving circuit is connected to the control electrode of the sixth transistor through the ninth via hole and is electrically connected to the second light emitting signal line through the thirteenth via hole.

[0216] At this point, the circuit structure layer is prepared on the substrate. In a plane parallel to the display substrate, the circuit structure layer may include a plurality of pixel driving circuits and a plurality of signal lines connected to the pixel driving circuits. In a plane perpendicular to the display substrate, the circuit structure layer may be arranged on the substrate. At least one pixel driving circuit includes at least one transistor and at least one capacitor, and the capacitor includes: a first plate and a second plate.

[0217] The pixel driving circuit layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a first planar layer, a third conductive layer and a second planar layer sequentially disposed on a substrate.

[0218] In an exemplary embodiment, the semiconductor layer may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0219] In an exemplary embodiment, at least one of the first to third conductive layers may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or the above conductive alloy materials, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. Exemplarily, the material of the first conductive layer may include: molybdenum.

[0220] In an exemplary embodiment, the first insulating layer, the second insulating layer, and the third insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0221] In an exemplary embodiment, the first planarization layer and the second planarization layer may employ an organic material.

[0222] In an exemplary embodiment, after the circuit structure layer is prepared, a light emitting structure layer is prepared on the circuit structure layer. The preparation process of the light emitting structure layer may include the following operations.

[0223] Forming a light-emitting structure layer. In an exemplary embodiment, forming a light-emitting structure layer pattern includes: depositing a fourth conductive film on a substrate having the aforementioned pattern, patterning the fourth conductive film using a patterning process to form a fourth conductive layer pattern, depositing a pixel definition film on a substrate having the fourth conductive layer pattern, patterning the pixel definition film using a patterning process to form a pixel definition layer pattern, coating an organic light-emitting material on a substrate having the pixel definition layer pattern, patterning the organic light-emitting material using a patterning process to form an organic structure layer pattern, depositing a fifth conductive film on a substrate having the organic material layer pattern, patterning the fifth conductive film using a patterning process to form a fifth conductive layer.

[0224] In an exemplary embodiment, the fourth conductive layer pattern includes at least: an anode of at least one light emitting device.

[0225] In an exemplary embodiment, the shape of the anode of the at least one light emitting device may be a polygon. The anode of the at least one light emitting device is connected to the second electrode of the sixth transistor (also the second electrode of the seventh transistor) of the at least one pixel driving circuit.

[0226] In an exemplary embodiment, the pixel definition layer pattern includes a plurality of via holes, and at least one via hole exposes an anode of at least one light emitting device.

[0227] In an exemplary embodiment, the organic structure layer includes: an organic light emitting layer of at least one light emitting device. The organic light emitting layer of at least one light emitting device is connected to an anode of at least one light emitting device through a via hole of at least one pixel definition layer.

[0228] In an exemplary embodiment, the fifth conductive layer may include at least cathodes of the plurality of light emitting devices.

[0229] At this point, the light-emitting structure layer is prepared on the substrate.

[0230] In an exemplary embodiment, the fourth conductive layer has a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0231] In an exemplary embodiment, the fifth conductive layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or the above conductive alloy materials, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. Exemplarily, the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum and titanium.

[0232] In an exemplary embodiment, the subsequent preparation process may include: forming a packaging structure layer on the fifth conductive layer, the packaging structure layer may include a stacked first packaging layer, a second packaging layer and a third packaging layer, the first packaging layer and the third packaging layer may be made of inorganic materials, the second packaging layer may be made of organic materials, and the second packaging layer is arranged between the first packaging layer and the third packaging layer, which can ensure that external water vapor cannot enter the light-emitting structure layer.

[0233] The display substrate adopted in the embodiment of the present disclosure can be applied to display products with any resolution.

[0234] An embodiment of the present disclosure further provides a display device, comprising: a display substrate provided by any one of the aforementioned embodiments.

[0235] In an exemplary embodiment, the display device can be any product or component with a display function, such as electronic paper, OLED panel, active-matrix organic light emitting diode (AMOLED) panel, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, etc.

[0236] The drawings in the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0237] For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness and size of the layer or microstructure are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or there may be intermediate elements.

[0238] Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any technician in the field to which the present disclosure belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the scope of patent protection of the present disclosure shall still be subject to the scope defined in the attached claims.

[0239] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A display substrate, comprising a display area and a non-display area located at least on one side of the display area, characterized in that: The invention comprises: a substrate and a pixel driving circuit, a plurality of scanning signal lines and a plurality of light emitting signal lines arranged in an array and arranged on the substrate and located in a display area, wherein at least one pixel driving circuit comprises: at least one transistor, and at least one transistor comprises: a writing transistor, a reset transistor, a compensation transistor and a light emitting transistor; A control electrode of at least one of a write transistor, a reset transistor and a compensation transistor in at least one pixel driving circuit is electrically connected to at least one scanning signal line, and a light emitting transistor in at least one pixel driving circuit is electrically connected to at least one light emitting signal line; The plurality of scanning signal lines and the plurality of light emitting signal lines are arranged in different layers.

2. The display substrate according to claim 1, characterized in that: The plurality of light emitting signal lines are located at a side of the plurality of scanning signal lines away from the substrate.

3. The display substrate according to claim 1, characterized in that: Also includes: The light-emitting devices arranged in an array and located in the substrate and the display area, the first electrode of at least one light-emitting device is electrically connected to at least one pixel driving circuit, the at least one transistor further includes: a driving transistor, the reset transistor includes: an anode reset transistor and a node reset transistor, the anode reset transistor is electrically connected to the first electrode of at least one light-emitting device, the node reset transistor is electrically connected to the control electrode of the driving transistor, the write transistor is electrically connected to the first electrode of the driving transistor, and the compensation transistor is electrically connected to the control electrode and the second electrode of the driving transistor respectively; the scanning signal line includes: a first scanning signal line, a second scanning signal line and a third scanning signal line; A control electrode of a node reset transistor of at least one pixel driving circuit is electrically connected to at least one first scanning signal line, a control electrode of a compensation transistor of at least one pixel driving circuit is electrically connected to at least one second scanning signal line, and a control electrode of a write transistor and a control electrode of an anode reset transistor of at least one pixel driving circuit are electrically connected to at least one third scanning signal line respectively; The signal received by the first scanning signal line connected to the pixel driving circuit in the nth row is the same as the signal received by the second scanning signal line connected to the pixel driving circuit in the (n-3)th row.

4. The display substrate according to claim 3, characterized in that: At least one of the first scan signal line, the second scan signal line and the third scan signal line at least partially extends along a first direction; The orthographic projections of the first scanning signal line, the second scanning signal line and the third scanning signal line connected to at least one pixel driving circuit on the substrate are arranged in sequence along a second direction, and the first direction intersects with the second direction.

5. The display substrate according to claim 4, characterized in that: The light emitting transistor includes: a first light emitting transistor and a second light emitting transistor, the first light emitting transistor is electrically connected to the first electrode of the driving transistor, the second light emitting transistor is electrically connected to the second electrode of the driving transistor and the first electrode of the light emitting device electrically connected to the pixel driving device, respectively, and the light emitting signal line includes: a first light emitting signal line and a second light emitting signal line; A control electrode of a first light emitting transistor of at least one pixel driving circuit is electrically connected to at least one first light emitting signal line, and a control electrode of a second light emitting transistor of at least one pixel driving circuit is electrically connected to at least one second light emitting signal line; The signal received by the second light emitting signal line connected to the pixel driving circuit in the nth row is the same as the signal received by the first light emitting signal line connected to the pixel driving circuit in the (n-1)th row.

6. The display substrate according to claim 5, characterized in that: A control electrode of at least one of the first light emitting transistor and the second light emitting transistor is located on a side of at least one of the first light emitting signal line and the second light emitting signal line close to the substrate.

7. The display substrate according to claim 5, characterized in that: At least one of the first light emitting signal line and the second light emitting signal line at least partially extends along a first direction; The orthographic projection of the first light emitting signal line connected to at least one pixel driving circuit on the substrate is located between the orthographic projection of the second scanning signal line on the substrate and the orthographic projection of the third scanning signal line on the substrate; The orthographic projection of the second light emitting signal line connected to at least one pixel driving circuit on the substrate is located on a side of the orthographic projection of the third scanning signal line on the substrate away from the orthographic projection of the second scanning signal line on the substrate.

8. The display substrate according to claim 7, characterized in that: The positive projection of the control electrode of at least one of the first light-emitting transistor and the second light-emitting transistor of at least one pixel driving circuit on the substrate is located between the positive projection of the first light-emitting signal line connected to at least one pixel driving circuit on the substrate and the positive projection of the third scanning signal line on the substrate.

9. The display substrate according to claim 5, characterized in that: Also includes: A plurality of first connection electrodes are disposed on the substrate and located in the display area, wherein the first connection electrodes are located on a side of the plurality of light-emitting signal lines away from the substrate; At least one first connection electrode is electrically connected to a control electrode of a first light emitting transistor of at least one pixel driving circuit and at least one first light emitting signal line respectively.

10. The display substrate according to claim 5, characterized in that: Also includes: A plurality of second connection electrodes are disposed on the substrate and located in the display area, wherein the second connection electrodes are located on a side of the plurality of light-emitting signal lines away from the substrate; At least one second connection electrode is electrically connected to a control electrode of a second light emitting transistor of at least one pixel driving circuit and at least one second light emitting signal line respectively.

11. The display substrate according to claim 10, characterized in that: An orthographic projection of at least one second connection electrode on the substrate at least partially overlaps with an orthographic projection of at least one third scanning signal line connected to the pixel driving circuit on the substrate.

12. The display substrate according to claim 5, characterized in that: Also includes: A plurality of first power lines and a plurality of data signal lines are disposed on the substrate and located in the display area, a write transistor in at least one pixel driving circuit is electrically connected to at least one data signal line, and a first light emitting transistor in at least one pixel driving circuit is electrically connected to at least one first power line; At least one signal line among the plurality of first power lines and the plurality of data signal lines at least partially extends along the second direction, and the plurality of first power lines and at least one signal line among the plurality of data signal lines are arranged in the same layer as a first electrode and a second electrode of at least one transistor in at least one pixel driving circuit; The orthographic projection of the first power line connected to at least one pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the control electrode of the first light-emitting transistor on the substrate, and has no overlapping area with the orthographic projection of the control electrode of the second light-emitting transistor on the substrate.

13. The display substrate according to claim 12, characterized in that: At least one pixel driving circuit further includes: a capacitor, the capacitor includes: a second plate, the second plate of the capacitor of at least one pixel driving circuit is electrically connected to at least one first power line, The second plates of the capacitors of at least two pixel driving circuits located in the same row are arranged along the first direction and are connected to each other.

14. The display substrate according to claim 5, characterized in that: Also includes: A plurality of first initial signal lines and a plurality of second initial signal lines are disposed on the substrate and located in the display area, a node reset transistor in at least one pixel driving circuit is electrically connected to at least one first initial signal line, and an anode reset transistor in at least one pixel driving circuit is electrically connected to at least one second initial signal line; At least one signal line among the plurality of first initial signal lines and the plurality of second initial signal lines at least partially extends along the first direction; The orthographic projection of the first initial signal line connected to at least one pixel driving circuit on the substrate is located between the orthographic projection of the first scanning signal line on the substrate and the orthographic projection of the second scanning signal line on the substrate; The orthographic projection of the second initial signal line connected to at least one pixel driving circuit on the substrate is located on a side of the orthographic projection of the second light emitting signal line on the substrate away from the orthographic projection of the third scanning signal line on the substrate.

15. The display substrate according to claim 1, characterized in that: Also includes: A plurality of first connection electrodes, a plurality of second connection electrodes, a plurality of first initial signal lines, a plurality of second initial signal lines, a plurality of first power supply lines, and a plurality of second power supply lines are arranged on the substrate and located in the display area, and at least one pixel driving circuit further includes: at least one capacitor, and at least one capacitor includes: a first electrode plate and a second electrode plate; The display substrate further comprises: a circuit structure layer arranged on the base, the circuit structure layer comprising: a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer sequentially stacked on the base; The semiconductor layer includes: an active pattern of at least one transistor of at least one pixel driving circuit; The first conductive layer includes: a plurality of scanning signal lines and a control electrode of at least one transistor of at least one pixel driving circuit and a first electrode plate of at least one capacitor; The second conductive layer includes: a plurality of light emitting signal lines, a plurality of first initial signal lines, a plurality of second initial signal lines, and a second plate of at least one capacitor of at least one pixel driving circuit; The third conductive layer includes: a plurality of first power lines, a plurality of data signal lines, a plurality of first connection electrodes, a plurality of second connection electrodes, and a first electrode and a second electrode of at least one transistor of at least one pixel driving circuit.

16. The display substrate according to claim 5, characterized in that: Also includes: A first driving circuit, a second driving circuit and a third driving circuit are arranged on the substrate and located in the non-display area, wherein the non-display area includes a frame area and a binding area, wherein the frame area is located on a first side, a second side and a third side of the display area, and the binding area is located on a fourth side of the display area, wherein the first side and the second side of the display area are arranged opposite to each other, and the third side and the fourth side of the display area are arranged opposite to each other; The first driving circuit is electrically connected to a plurality of first scanning signal lines and a plurality of second scanning signal lines respectively, the second driving circuit is electrically connected to a plurality of third scanning signal lines, and the third driving circuit is electrically connected to a plurality of light emitting signal lines; The second driving circuit is located at a first side of the display area, and the first driving circuit and the third driving circuit are located at the second side of the display area.

17. The display substrate according to claim 16, characterized in that: Also includes: A first power supply line and a second power supply line are disposed on the substrate and located in the non-display area; The first power supply line is located in the binding area and is electrically connected to the plurality of first power supply lines. The second power supply line is arranged around the display area and is located in the frame area and the binding area. The second power supply line at least partially surrounds the first power supply line.

18. A display device, characterized in that: include: A display substrate as claimed in any one of claims 1 to 17.

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