Memory device and operating method thereof

Abstract

A memory device includes a plurality of word lines, a bit line, a memory array, a control circuit, and a current summing circuit. The memory array includes a plurality of memory cells coupled to bit lines. Each of the plurality of memory cells includes an access transistor coupled to a respective word line among the plurality of word lines. The control circuit is configured to provide a plurality of word line voltages different from each other to the access transistors through the plurality of word lines, respectively. The current summing path is configured to be coupled to a bit line and detect a bit line current on the bit line. The embodiment of the invention also discloses a method for operating the memory device.

Description

Technical Field

[0001] Embodiments of the present application relate to a memory device and an operating method thereof. Background Art

[0002] Recent developments in the field of artificial intelligence have resulted in a variety of products and / or applications, including but not limited to speech recognition, image processing, machine learning, natural language processing, etc. Such products and / or applications typically use neural networks to process large amounts of data for learning, training, cognitive computing, etc. Memory devices configured to perform computation in memory (CIM) operations (also referred to herein as CIM memory devices) are useful neural network applications as well as other applications. The CIM memory device includes a memory array that is configured to store weight data and / or input data used together in one or more CIM operations. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a memory device is provided, comprising: a plurality of word lines; a bit line; a memory array comprising a plurality of memory cells coupled to the bit lines, wherein each of the plurality of memory cells comprises an access transistor coupled to a corresponding word line among the plurality of word lines; a control circuit configured to provide a plurality of word line voltages different from each other to the access transistor through the plurality of word lines accordingly; and a current summing circuit configured to be coupled to the bit line and detect a bit line current on the bit line.

[0004] According to another aspect of an embodiment of the present application, a memory device is provided, comprising: a plurality of word lines; a bit line; a memory array, comprising a plurality of memory cells coupled to the bit lines, wherein each of the plurality of memory cells comprises an access transistor coupled to a corresponding word line among the plurality of word lines; and a control circuit, configured to: in a digital-to-analog conversion operation, provide a plurality of word line voltages to the access transistors of the plurality of memory cells through the plurality of word lines, respectively, the plurality of word line voltages being lower than a threshold voltage of the access transistor, and configured to: in a read operation of a selected memory cell among the plurality of memory cells, provide a read voltage to the access transistor of the selected memory cell through the corresponding word line, the read voltage being equal to or higher than a threshold voltage.

[0005] According to another aspect of an embodiment of the present application, a method for operating a memory device is provided, comprising: in a computing operation in the memory of the memory device, accessing multiple memory cells of the memory device by providing corresponding different gate voltages lower than the threshold voltage of the access transistors to the gates of the access transistors of the multiple memory cells, and performing calculations based on respective currents flowing through the multiple memory cells in response to the corresponding different gate voltages. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a schematic diagram of a memory device according to some embodiments.

[0008] Figure 2 is a graph showing current-voltage characteristics of a transistor according to some embodiments.

[0009] Figure 3A and Figure 3B is a schematic circuit diagram of a portion of a memory device in various operations according to some embodiments.

[0010] Figure 4 is a schematic diagram of a memory device according to some embodiments.

[0011] Figure 5A and Figure 5B is a schematic diagram of a memory device according to some embodiments.

[0012] Fig. 6A and Figure 6B is a schematic cross-sectional view of a portion of a memory device according to some embodiments.

[0013] Fig. 7A and Figure 7B is a schematic diagram of a memory device in various operations according to some embodiments.

[0014] Fig. 8A is a schematic diagram of a memory device according to some embodiments.

[0015] Figure 8B is a schematic diagram of a neural network according to some embodiments.

[0016] Figure 8C is a schematic diagram of an integrated circuit (IC) device according to some embodiments.

[0017] Fig.8D is a circuit diagram of an integrator circuit according to some embodiments.

[0018] Fig. 9 is a flow chart of a method according to some embodiments. DETAILED DESCRIPTION

[0019] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0020] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0021] In some cases, the CIM operation involves an analog signal obtained by converting digital data into an analog signal by performing a digital-to-analog conversion (DAC) operation. In some embodiments, a subthreshold region of an access transistor in a memory cell of a memory array is used in a DAC operation. For example, various gate voltages below the threshold voltage of the access transistor are provided to the gate of the access transistor by a control circuit. In response to the corresponding gate voltage, a separate current corresponding to the data stored in each memory cell and the corresponding gate voltage is allowed to flow through each memory cell. The individual currents of the memory cells are collected on a bit line, and the individual currents are summed to obtain an analog signal. As a result, the digital data stored in the memory cell is converted into an analog signal. In some embodiments, the described DAC operation is performed without requiring or involving one or more separate DAC circuits (i.e., digital-to-analog converters). In at least one embodiment, this is improved at least in terms of power consumption, chip area, or design simplicity compared to other methods that use or require separate DAC circuits to perform DAC operations.

[0022] In some embodiments, in addition to the DAC operation, the memory array is configured to perform other operations, such as a read operation, a program operation (or a write operation), without changing the arrangement of bit lines and / or word lines in the memory array.

[0023] In some embodiments, considering that the subthreshold region of the access transistor is temperature-dependent, a temperature sensor is provided to detect the temperature of the memory array during operation. In one or more embodiments, based on the detected temperature and predetermined calibration data, the gate voltage provided to the access transistor during DAC operation is adjusted to ensure the accuracy of the DAC operation.

[0024] In some embodiments, the memory array includes a specific area configured to perform a DAC operation. Such a specific area is sometimes referred to as a DAC area. The digital data to be converted is stored in a different area of ​​the memory array, sometimes referred to as a data storage area, and is copied to the DAC area for conversion to an analog signal. As a result, in one or more embodiments, data interference in the data storage area can be avoided, and / or the temperature dependency adjustment described can be simplified. In some embodiments, one or more devices, methods, operations, and advantages described herein are applicable to or can be implemented in applications other than CIM applications.

[0025] Figure 1 1 is a schematic diagram of a memory device 100 according to some embodiments. The memory device is an integrated circuit (IC) device. In at least one embodiment, the memory device is a separate IC device. In some embodiments, the memory device is included as part of a larger IC device that includes circuits other than the memory device for other functions.

[0026] The memory device 100 includes a memory macro 110 and a memory controller 120. The memory macro 110 includes a memory array 112 of memory cells MC, a bit line (BL) selection circuit 115, a current summing circuit 117, and a sensing circuit 119. In some embodiments, the memory macro 110 also includes one or more computing circuits configured to perform one or more CIM operations. Examples of computing circuits include multiplication and accumulation circuits (MACs). Other computing circuit configurations are within the scope of various embodiments. In at least one embodiment, for applications other than CIM applications, the computing circuit is omitted in the memory device 100. The memory controller 120 includes a word line driver 122 and a control logic 123. The memory controller 120 is sometimes referred to as a control circuit. In some embodiments, one or more elements in the memory controller 120 are included in the memory macro 110, and / or one or more elements of the memory macro 110 (except the memory array 112) are included in the memory controller 120.

[0027] Macros have reusable configurations and can be used for IC devices of various types or designs. In some embodiments, macros are understood to be similar to the architectural hierarchy of modular programming, where subroutines / procedures are called by main programs (or other subroutines) to perform given computing functions. In this case, the IC device uses macros to perform one or more given functions. Therefore, in this case, the IC device is similar to the main program and the macro is similar to the subroutine / procedure in terms of the architectural hierarchy. In some embodiments, the macro is a soft macro. In some embodiments, the macro is a hard macro described digitally in register transfer level (RTL) code. In some embodiments, synthesis, placement, and routing have not yet been performed on the macro, so the soft macro can be synthesized, placed, and routed for various process nodes. In some embodiments, the macro is a hard macro digitally described in a binary file format (e.g., a graphic database system II (GDSII) stream format), wherein the binary file format represents the plane geometry of one or more layout diagrams of the macro in a hierarchical form, text labels, other information, etc. In some embodiments, the macro is synthesized, placed, and routed so that the hard macro is specific to a specific process node.

[0028] A memory macro is a macro that includes addressable memory cells to allow data to be written to or read from the memory cells. In some embodiments, the memory macro also includes a circuit configured to provide access to the memory cells and / or perform further functions associated with the memory cells. For example, one or more weight buffers (not shown), one or more logic circuits (not shown), and one or more computational circuits (not shown) form a circuit configured to provide a CIM function associated with the memory cells MC in the memory macro 110. In at least one embodiment, a memory macro configured to provide a CIM function is referred to as a CIM macro. The described macro configuration is an example. Other configurations are within the scope of various embodiments.

[0029] The memory cells MC are arranged in a plurality of columns and rows of the memory array 112. The memory controller 120 is electrically coupled to the memory cells MC and configured to control operations of the memory cells MC, including but not limited to read operations, write operations, DAC operations, CIM operations, and the like.

[0030] The memory array 112 includes rows along the row direction (ie, Figure 1 A plurality of word lines (also referred to as "address lines") WL0, WL1 to WLr extending in the horizontal direction (in the horizontal direction), and a plurality of word lines (also referred to as "address lines") WL0, WL1 to WLr extending in the column direction (i.e., Figure 1A plurality of bit lines (also referred to as “data lines”) BL0, BL1 to BLt extending in a vertical direction (in a vertical direction), where r and t are natural numbers. The word lines are generally referred to as WLs herein, and the bit lines are generally referred to as BLs herein. The memory cells MC in each row are electrically coupled to the storage controller 120 through the corresponding word lines. In some example operations, the word lines are configured to transmit the addresses of the memory cells MC to be read therefrom, or to transmit the addresses of the memory cells MC to be written thereto, etc. In some example operations, the bit lines are configured to transmit data read from the memory cells MC indicated by the corresponding word lines, or to transmit data to be written to the memory cells MC indicated by the corresponding word lines, etc. In some embodiments, the memory array 112 further includes a plurality of source lines (not shown) coupled to the memory cells MC along the rows or along the columns. Various numbers of word lines and / or bit lines and / or source lines in the memory array 112 are within the scope of various embodiments. In some embodiments, the memory cells MC are dynamic random access memory (DRAM) cells, and the memory device 100 is a DRAM device.

[0031] Figure 1 An example DRAM configuration 113 of each memory cell MC is shown in FIG. In the DRAM configuration 113, each memory cell MC includes a transistor T and a capacitor C. The gate of the transistor T is coupled to a word line WL, which corresponds to any one of the word lines WL0, WL1 to WLr in the memory array 112. The first source / drain of the transistor is coupled to a bit line BL, which corresponds to any one of the bit lines BL0, BL1 to BLt in the memory array 112. The second source / drain of the transistor is coupled to one terminal of the capacitor C. The other terminal of the capacitor C is coupled to a node of a reference voltage, at Figure 1 In the example configuration of , the node is ground. Capacitor C is configured to store data of a logic state (e.g., logic "0" or logic "1"). For example, when capacitor C is charged, it stores logic "1". When capacitor C is not charged, it stores logic "0". Transistor T, also known as an access transistor, is configured to allow access to capacitor C and / or data stored therein in an access operation. Examples of access operations include, but are not limited to, read operations, write operations, DAC operations, CIM operations, and the like. In DRAM configuration 113, access transistor T is an N-type transistor. In one or more embodiments, a P-type access transistor is possible. In DRAM configuration 113, capacitor C is read and written by access transistor T. In other DRAM configurations having separate transistors for reading and writing, the transistor where reading occurs is considered an access transistor. The described DRAM configuration 113 having one transistor and one capacitor is sometimes referred to as a 1T1C configuration. Other DRAM configurations are within the scope of various embodiments.

[0032] exist Figure 1 In an example configuration, the controller 120 includes a word line driver 122 and a control logic 123. In some embodiments, the memory controller 120 also includes one or more of a bit line driver, a buffer, a precharge circuit, one or more clock generators for providing clock signals to various components of the memory device 100, a global address decoder circuit, a predecoder circuit, an address latch, a pulse generator, a timing circuit, one or more input / output (I / O) circuits for exchanging data, address, clock and / or control with an external circuit, a sub-controller for controlling various operations in the memory device 100, and the like.

[0033] The word line driver 122 is coupled to the memory array 112 via the word line WL. The word line driver 122 is configured to decode the row address of the memory cell MC to be accessed in the access operation. The word line driver 122 is sometimes referred to as a word line decoder. The word line driver 122 is configured to provide a voltage to the selected word line WL corresponding to the decoded row address, and to supply a different voltage to other unselected word lines WL. In at least one embodiment, the word line driver 122 includes one or more drive circuits or inverters.

[0034] The bit line driver (not shown) is coupled to the memory array 112 via the bit line BL. In some embodiments, the bit line driver is part of the memory macro 110 and / or is coupled to the bit line BL through the BL selection circuit 115. The bit line driver is configured to decode the column address of the memory cell MC to be accessed in the access operation. The bit line driver is sometimes referred to as a bit line decoder. The bit line driver 124 is configured to provide a voltage to the selected bit line BL corresponding to the decoded column address and to provide a different voltage to other unselected bit lines BL. In at least one embodiment, the bit line driver includes one or more drive circuits or inverters. In some embodiments, the memory controller 120 also includes a source line driver (not shown) coupled to the memory cell MC via a source line (not shown). In one or more embodiments, one or more of the word line driver 122, the bit line driver, and the source line driver are part of a circuit referred to as a read / write driver or a read / write decoder.

[0035] The control logic 123 is an example of one or more sub-controllers included in the memory controller 120, and is configured to control other components and various operations in the memory device 100. Figure 1In the example configuration of , the control logic 123 is coupled to the word line driver 122 and is configured to control the word line driver 112 in access operations (including DAC operations and / or CIM operations described herein). The control logic 123 or one or more additional sub-controllers of the memory controller 120 are coupled to one or more of the BL selection circuit 115, the current summing circuit 117, the sensing circuit 119, the bit line driver, the buffer, the calculation circuit, the I / O circuit, etc. and is configured to control these circuits to coordinate the operation of these circuits in such access operations of the memory device 100. In one or more embodiments, the control logic 123 includes one or more circuits of transistors, switches, logic gates, multiplexers, flip-flops, latches, etc.

[0036] The BL selection circuit 115 is configured to selectively couple one or more bit lines BL to one of the current summing circuit 117 and the sensing circuit 119. In some embodiments, the BL selection circuit 115 is configured to switch between the current summing circuit 117, the sensing circuit 119, and the bit line driver. In at least one embodiment, the BL selection circuit 115 is configured to have a switch state in which one or more bit lines BL are not coupled to any of the current summing circuit 117, the sensing circuit 119, and the bit line driver. The BL selection circuit 115 is coupled to the memory controller 120, and the memory controller 120 is configured to output a control signal Sel to the BL selection circuit 115 to control the switching of the BL selection circuit 115. In one or more embodiments, the BL selection circuit 115 includes a switch, a transistor, a multiplexer, etc. The memory controller 120 is configured to provide the control signal Sel to the gate or control terminal / pin / input of the BL selection circuit 115.

[0037] The current summing circuit 117 is configured to sum the bit line currents on the bit lines coupled to the current summing circuit 117 by the BL selection circuit 115 in the DAC operation as described herein. In some embodiments, the current summing circuit 117 includes an integrator circuit. Fig.8D An example integrator circuit is described. Other configurations of current summing circuit 117 are within the scope of various embodiments.

[0038] The sensing circuit 119 is configured to perform a read operation when coupled to the bit line through the BL selection circuit 115. In some embodiments, the sensing circuit 119 includes a sense amplifier configured to determine the data stored in the selected memory cell MC based on the read current on the bit line coupled to the selected memory cell MC and the sense amplifier. In at least one embodiment, the sensing circuit 119 also includes a buffer for temporarily storing the read data. Example buffers include, but are not limited to, registers, memory cells, or other circuit elements configured for data storage. Other configurations of the sensing circuit 119 and / or the buffer are within the scope of various embodiments. The memory circuit configurations described are examples, and other memory circuit configurations are within the scope of various embodiments.

[0039] Figure 2 is a graph showing a current-voltage characteristic 200 of a transistor according to some embodiments. In some embodiments, the transistor 200 having the current-voltage characteristic corresponds to Figure 1 The access transistor T of any one or more of the memory cells MC.

[0040] In the current-voltage characteristic 200, the horizontal axis represents the voltage between the gate and the source of the access transistor T, also referred to herein as the gate voltage. The gate voltage is labeled Vgs and is Figure 2 The vertical axis represents the current between the drain and source of the access transistor T, also referred to herein as the channel current. The channel current is labeled Ids and is shown in Figure 2 The values ​​are displayed in logarithmic scale (log scale).

[0041] When the gate voltage Vgs of the access transistor T is equal to or higher than the threshold voltage Vth, the access transistor T is turned on. When the gate voltage Vg of the access transistor T is lower than the threshold voltage Vth, the access transistor T is turned off. The current value of the channel current Ids at the threshold voltage Vth is the threshold voltage current Ith. The current-voltage characteristic 200 has a subthreshold region 210 that is lower than the threshold voltage Vth. In the subthreshold region 210, although the access transistor T is turned off, a small amount of channel current Ids flows through the access transistor T. This small amount of channel current Ids is sometimes referred to as a leakage current. In a non-limiting example, the leakage current in the subthreshold region 210 is 1 μA (uA, or microamperes, or 10 -6 A) and below.

[0042] The subthreshold region 210 of the current-voltage characteristic 200 includes a linear region 220, in which the channel current Ids (on a logarithmic scale) increases linearly with increasing gate voltage Vgs. The actual current value of the channel current Ids in the linear region 220 (on a linear scale) increases exponentially with increasing gate voltage Vgs. The linear region 220 varies from transistor to transistor and depends on various factors, including but not limited to the size, material, manufacturing process, etc. of the transistor. Figure 2 In the example configuration, the linear region 220 is defined at the upper limit I of the channel current Ids. U and lower limit I L In some embodiments, the upper limit I U A few nA (nanoamperes, or 10 -9 A) to several hundred nA. In at least one embodiment. Lower limit I L The current noise level is equal to or higher than the current noise level of the access transistor T. In a non-limiting example, the current noise level is 1 pA (picoampere, or 10 -12 A).

[0043] In some embodiments, the linear region 220 in the subthreshold region 210 of the access transistor T will perform a DAC operation. Figure 2 As shown, when the gate voltage V0, V1, V2, V3, etc. in the linear region 220 is provided to the gate of the access transistor T, the access transistor T remains off, but allows the corresponding channel current or leakage current I0, I1, I2, I3, etc. to flow through the access transistor T. In some embodiments, the same predetermined voltage difference is between V0 and V1, between V1 and V2, between V2 and V3, etc. As a result, V0, V1, V2, V3, etc. differ from each other by a multiple of the predetermined voltage difference. For example, assuming that the predetermined voltage difference is b (mV or millivolts), V0 differs from V1 by b, differs from V2 by 2×b, differs from V3 by 3×b, and so on.

[0044] In some embodiments, V0, V1, V2, V3, etc. are predetermined so that each leakage current of I0, I1, I2, I3, etc. is k times greater or k times less than another leakage current of I0, I1, I2, I3. For example, I1 = k×I0, I2 = k×I1, I3 = k×I2, etc. In some embodiments, k is 2, resulting in I1 = 2×I0, I2 = 4×I0, I3 = 8×I0, etc. This value of k=2 is used to refer to Figure 3A Example DAC operations are described. Other values ​​of k for the DAC operations are within the scope of various embodiments.

[0045] In some embodiments, the same predetermined voltage difference b between V0 and V1, between V1 and V2, between V2 and V3, etc., results in I1=k×I0, I2=k×I1, I3=k×I2, etc. In at least one embodiment, the voltage value of the voltage difference b between adjacent gate voltages in V0, V1, V2, V3, etc., results in a specific k value between adjacent leakage currents in I0, I1, I2, I3, etc. corresponding to the slope of the linear region 220 in the current-voltage characteristic 200, sometimes referred to as the slope of the linear region 220 or the subthreshold slope. The number of four gate voltages V0, V1, V2, V3 described and the four corresponding leakage currents I0, I1, I2, I3 are examples. Other numbers of gate voltages and corresponding leakage currents are within the scope of various embodiments.

[0046] In at least one embodiment, the current-voltage characteristic 200 is predetermined by measuring the current value of the channel current Ids of the actual transistor at different voltage values ​​of the gate voltage Vgs. In some embodiments, the current-voltage characteristic 200 is predetermined by a simulation performed by a computer system. In some embodiments, based on the predetermined current-voltage characteristic, in particular, based on the linear region in the subthreshold region of the current-voltage characteristic, V0, V1, V2, V3, etc. and the corresponding I0, I1, I2, I3, etc. are predetermined by one or more of actual measurements, simulation results, interpolation, extrapolation, etc. The process of predetermining a set of V0, V1, V2, V3, etc. and the corresponding I0, I1, I2, I3, etc. for a transistor is sometimes referred to as a calibration process. In some embodiments, a database is developed in advance and various sets of V0, V1, V2, V3, etc. and the corresponding I0, I1, I2, I3, etc. of different transistors are stored, and these transistors are different from each other in one or more aspects of size, material, manufacturing process, etc. Such a database is stored in a non-transitory computer-readable storage medium and is consulted, for example, during the design phase of a memory device to configure control circuitry of the memory device to control DAC operations in a memory array of the memory device, as described herein.

[0047] Figure 3A 3 is a schematic circuit diagram of a portion of a memory device 300 in DAC operation according to some embodiments. In at least one embodiment, the memory device 300 corresponds to the memory device 100.

[0048] Figure 3AThe memory device 300 in FIG. 3 includes memory cells MC0-MC3 coupled to a bit line BL0 and correspondingly coupled to word lines WL0-WL3. The memory device 300 also includes a BL selection circuit 315 configured to selectively couple the bit line BL0 to a current summing circuit 317 or a sensing circuit 319 in response to a control signal Sel. In DAC operation, the BL selection circuit 315 couples the bit line BL0 to the current summing circuit 317, as shown in FIG. Figure 3A As shown. Memory cells MC0-MC3 have the described DRAM configuration 113 and include access transistors T0-T3 and capacitors C0-C3 accordingly. In at least one embodiment, word lines WL0-WL3, bit lines BL0, memory cells MC0-MC3, access transistors T0-T3, capacitors C0-C3, BL selection circuit 315, current summing circuit 317, and sensing circuit 319 correspond to word lines, bit lines, memory cells, access transistors, capacitors, BL selection circuit 115, current summing circuit 117, and sensing circuit 119 in memory device 100. As shown Figure 3A As shown schematically in the example configuration of , the sensing circuit 319 includes a sense amplifier. In some embodiments, the access transistors T0 - T3 have current-voltage characteristics corresponding to the current-voltage characteristic 200 .

[0049] exist Figure 3A In the example configuration of , digital data 330 stored in memory cells MC0-MC3 will be converted into analog signals in a DAC operation. Each memory cell MC0-MC3 stores corresponding data or bits Bit0-Bit3 of data 330 in corresponding capacitors C0-C3. Each of Bit0-Bit3 is a logic "0" (e.g., the corresponding capacitor is not charged) or a logic "1" (e.g., the corresponding capacitor is charged). Bit0-Bit3 are arranged in order of importance in data 330. For example, Bit0 is the least significant bit, Bit1 is higher than Bit0, Bit2 is higher than Bit1, and Bit3 is higher than Bit2 and is the most significant bit.

[0050] In order to convert the data 330 into an analog signal, the bit line BL0 is biased to a predetermined voltage, such as VSS or 0V. Different word line voltages V0-V3 are provided, for example, by a word line driver (not shown) of the memory device 300 and are provided to the gates of the corresponding access transistors T0-T3 through the corresponding word lines WL0-WL3. The word line voltages V0-V3 correspond to the reference Figure 2The gate voltage V0-V3 described is in the subthreshold region of the current-voltage characteristic of the access transistor T0-T3. The access transistor T0-T3 remains off. However, leakage currents I0-I3 of different current values ​​corresponding to different voltage values ​​of the word line voltage V0-V3 are allowed to flow through the corresponding access transistor T0-T3. The individual current of each memory cell MC0-MC3 actually flowing to the bit line BL0 depends on the corresponding leakage current I0-I3 of the corresponding access transistor T0-T3 and the data stored in the corresponding capacitor C0-C3. Specifically, the individual current of the memory cell MC0 flowing through the access transistor T0 to the bit line BL0 is I0×Bit0, the individual current of the memory cell MC1 flowing through the access transistor T1 to the bit line BL0 is I1×Bit1, the individual current of the memory cell MC2 flowing through the access transistor T2 to the bit line BL0 is I2×Bit2, and the individual voltage of the memory cell MC3 flowing through the access transistor T3 to the bit line BL0 is I3×Bit3. Therefore, the bit line current I is the sum of the individual currents of the memory cells MC0-MC3. BL On the bit line BL0, the current flows through the BL selection circuit 315 to the current summing circuit 317, that is, I BL =I0×Bit0+I1×Bit1+I2×Bit2+I3×Bit3.

[0051] In a non-limiting example, data 330 includes binary "1101", i.e., Bit3 is logic "1", Bit2 is logic "1", Bit1 is logic "0", and Bit0 is logic "1". For Bit3, Bit2, and Bit0 which are logic "1", the corresponding capacitors C3, C2, and C0 are charged, and the charging voltages of the charging capacitors C3, C2, and C0 cause the corresponding individual currents I3 (i.e., I3×Bit3=I3×1=I3), I2 (i.e., I2×Bit2=I2×1=I2), and I0 (i.e., I0×Bit0=I0×1=I0) to flow to the bit line BL0. For Bit1 which is logic "0", the corresponding capacitor C1 is not charged, and the corresponding individual current is zero (i.e., I1×Bit1=I1×0=0). As a result, the bit line current I BL =I3+I2+I0. Figure 2 In some embodiments described with k=2, I3=8×I0, I2=4×I0, resulting in I BL =8×I0+4×I0+I0=13×I0. Bit line current I BL The current value 13×I0 corresponds to the decimal value 13 of the binary number “1101” in the data 330 .

[0052] Bit line current I BLis an example of an analog signal into which the data 330 is converted in the DAC operation. In at least one embodiment, the bit line current I BL is considered the result of a DAC operation and / or can be used directly for further processing. Figure 3A In the example configuration, the bit line current I BL The current is provided to the current summing circuit 317 through the BL selection circuit 315. The current summing circuit 317 is configured to generate a current that is equal to the bit line current I BL The corresponding analog signal S DAC , and is therefore also considered to be the result of the DAC operation. In some embodiments, the analog signal S DAC With the bit line current I BL In some cases, although the bit line current I BL The current value and analog signal S DAC The voltage values ​​of the data 330 correspond to each other, but in the subsequent processing, the analog signal S DAC The voltage value is greater than the bit line current I BL The current value of the current summing circuit 317 is easier to understand. Fig.8D Give a description.

[0053] In some embodiments, the number of memory cells involved in the described DAC operation is equal to the number of bits in the digital data to be converted, without the need for a separate DAC circuit. This is an improvement over other methods that require one or more separate DAC circuits in addition to the memory cells storing the digital data to be converted. In some cases, such separate DAC circuits include an additional memory cell array that occupies a large amount of chip area. For example, in order to convert 4 bits of data (e.g., Bit0-Bit3 as described above), according to other methods, a separate DAC circuit or DAC array requires at least 8 memory cells for Bit3, 4 memory cells for Bit2, 2 memory cells for Bit1, and one memory cell for Bit0. Therefore, according to other methods, in addition to the four memory cells storing the digital data to be converted, a total of 15 (i.e., 8+4+2+1=15) additional memory cells are required. In addition, the routing of the memory cells in the DAC circuit or DAC array according to other methods is different from the routing of the memory array (such as memory array 112). This different routing requires additional effort in the design and / or manufacturing process. According to one or more embodiments, in a memory device configured to perform the described DAC operation, such additional memory cells, DAC arrays, or additional design and / or manufacturing work are not required. Therefore, in one or more embodiments, circuit complexity, power consumption, and chip area may be reduced.

[0054] To perform DAC operation according to some embodiments, it is only necessary to predetermine the current-voltage characteristics and / or the various gate voltages in the subthreshold region and / or subthreshold region for the access transistor of the memory cell in the memory device, and configure the control circuit of the memory device as described to provide the predetermined gate voltage (e.g., V0-V3) to the access transistor in the DAC operation. In one or more embodiments, there is no need to reconfigure the bit lines and / or word lines. In some embodiments, there is already a BL selection circuit for switching between the sensing circuit and the bit line driver, so only a simple change is required to the configuration of the BL selection circuit to switch to the current summing circuit in addition. In at least one embodiment, the current summing circuit includes an integrator circuit, which, if not already included in the memory device, occupies a much smaller area than a separate DAC circuit required by other methods. Therefore, the DAC operation according to some embodiments requires minimal changes to the existing memory device design, and even reduces the complexity of the memory device by omitting or not requiring a separate DAC circuit.

[0055] Figure 3B is a schematic circuit diagram of a portion of a memory device 300 in a read operation according to some embodiments.

[0056] exist Figure 3BIn the example of , the memory cell MC0 to be read is selected in the read operation. The control circuit of the memory device 300 controls the BL selection circuit 315 through an appropriate control signal Sel to couple the sensing circuit 319 to the bit line BL0, and the bit line BL0 is coupled to the selected memory cell MC0. The control circuit of the memory device 300 also controls the precharge circuit to precharge the bit line BL0 to a precharge voltage between a power supply voltage (e.g., VDD) and a reference voltage (e.g., VSS or ground). In one example, the precharge voltage is VDD / 2. Other bit lines (not shown) not selected for this read operation are grounded or floating. In some embodiments, multiple memory cells are accessed in the same read operation, and multiple corresponding bit lines are coupled to corresponding sense amplifiers in the sensing circuit 319 and precharged. The control circuit also controls the word line driver of the memory device 300 to provide a read voltage or access voltage Va to the word line WL0 coupled to the selected memory cell MC0. The access voltage Va is equal to or higher than the threshold voltage Vth of the access transistor T0 of the memory cell MC0 to turn on the access transistor T0. In one example, the access voltage Va is VDD greater than the threshold voltage Vth. Other word lines not selected for this read operation are grounded or floating. In some embodiments, multiple memory cells are accessed in the same read operation, and the access voltage Va is provided to multiple corresponding word lines. In some embodiments, all memory cells coupled to the word line WL0 are accessed in the same read operation, and all corresponding bit lines are coupled to corresponding sense amplifiers.

[0057] When the access transistor T0 is turned on, the precharge voltage on the bit line BL0 changes according to the charging state of the capacitor C0 data stored in the memory cell MC0. For example, when the memory cell MC0 stores logic "1", the capacitor C0 is charged with the charging voltage VDD between its terminals. As a result, the precharge voltage on the bit line BL0 increases from VDD / 2 to VDD by the charging voltage. In this process, the capacitor C0 loses at least a portion of the charge. In the sensing circuit 319, the sense amplifier coupled to the bit line BL0 detects and amplifies the voltage increase on the bit line, and outputs a read signal Qr with a voltage VDD, indicating that the data or bit read from the memory cell MC0 is a logic "1". In this amplification process, the sense amplifier 319 also provides VDD to the bit line BL0 to restore the capacitor C0 to a charging state with the charging voltage VDD between its terminals, that is, to rewrite the read logic "1" back to the memory cell MC0.

[0058] When the memory cell MC0 stores a logic "0", the capacitor C0 is not charged or discharged, and there is no charge voltage between its terminals. As a result, the precharge voltage on the bit line BL0 decreases from VDD / 2 to VSS. In this process, the capacitor C0 is partially charged. In the sensing circuit 319, the sense amplifier coupled to the bit line BL0 detects and amplifies the voltage reduction on the bit line BL0, and outputs a read signal Qr with a voltage VSS, indicating that the data or bit read from the memory cell MC0 is a logic "0". In this amplification process, the sense amplifier 319 also provides VSS to the bit line BL0 to release any charge accumulated in the capacitor C0 due to the read operation, and restore the capacitor C0 to a discharged state with no charge voltage between its terminals, that is, rewrite the read logic "0" back to the memory cell MC0. In some embodiments, the read operation is periodically performed on all memory cells, not to output data from the memory cell, but to refresh the data stored therein. One reason is that over time, the capacitors in the memory cells may lose charge and stored data.

[0059] In a write operation of the memory cell MC0, a write circuit or a bit line driver is coupled to the corresponding bit line BL0 through the BL selection circuit 315. The access voltage Va is provided to the gate of the access transistor T0 to turn on the access transistor T0. In order to write a logic "1" to the memory cell MC0, the write circuit or the bit line driver provides VDD to the bit line BL0 to charge the corresponding capacitor C0 to the charging voltage VDD between its terminals. In order to write a logic "0" to the memory cell MC0, the bit line BL0 is grounded to release any charge in the capacitor C0 and put the capacitor C0 in a discharged state with no charging voltage between its terminals.

[0060] In some embodiments, read operations and write operations in the memory device 300 are not affected by the ability / function of the memory device 300 to also perform DAC operations. Therefore, in one or more embodiments, it may be possible to convert the design of an existing memory device to DAC operation according to some embodiments with minimal effort without changing the design of the functions (e.g., read operations and write operations) of the existing memory device.

[0061] In some cases, reference Figure 2 At least one of the described current-voltage characteristics 200, the subthreshold region 210, or the linear region 220 is temperature dependent and varies with the operating temperature of the memory array or the access transistor therein. For example, the same set of gate voltages or word line voltages (e.g., V0-V3, etc.) provided to the gate of the access transistor in DAC operation will result in a different set of leakage currents (e.g., I0-I3) as the slope of the linear region 220 varies. This variation in leakage current results in a change in the bit line current IBL changes and may cause inaccurate DAC operation results. Figure 4 In some described embodiments, the memory device is configured to provide compensation for the potentially adverse effects of the temperature-dependent conditions.

[0062] Figure 4 is a schematic diagram of a memory device 400 according to some embodiments. Figure 4 Zhongyu Figure 1 Components with corresponding components in are represented by Figure 1 The same reference numerals are used.

[0063] Compared to the memory device 100, the memory device 400 also includes a temperature sensor 423 and a storage circuit 433. An example temperature sensor is a bandgap temperature sensor including a bipolar junction transistor (BJT) and other circuits such as a current source, an operational amplifier, a voltage adder, and control logic. Fig. 6A An example BJT is described. Other temperature sensor configurations are within the scope of various embodiments. Examples of storage circuit 433 include, but are not limited to, registers, memory cells, or other circuit elements configured for data storage. In some embodiments, storage circuit 433 is omitted or incorporated into control logic 123.

[0064] The temperature sensor 423 is configured to detect the temperature of the memory device 400 in operation. Figure 4 In the example configuration in FIG. 4 , the temperature sensor 423 is physically located in the memory array 112. One reason is that since the temperature sensor 423 is physically close to the access transistor of the memory cell configured to perform the DAC operation, the temperature sensor 423 can accurately detect the operating temperature that affects the access transistor. In some embodiments, the memory device 400 includes multiple temperature sensors 423 physically arranged at different locations in the memory device 400. Other locations and / or numbers of temperature sensors are within the scope of various embodiments.

[0065] The temperature sensor 423 is coupled to the memory controller 120, for example, to the control logic 123, to provide the detected temperature to the control logic 123 in the operation of the memory device 400. The control logic 123 is configured to adjust one or more predetermined word line voltages (e.g., V0-V3) based on the temperature detected by the temperature sensor 423, and control the word line driver 122 to provide the adjusted word line voltage to the gate of the access transistor in the DAC operation. For example, in one or more embodiments, V0 (i.e., the lowest predetermined word line voltage) may not be adjusted; the other word line voltages V1-V3 are adjusted based on the detected temperature. In another example, all word line voltages V0-V3 are adjusted. In at least one embodiment where there is the same voltage difference b between adjacent word line voltages in V0-V3, as described herein, the control logic 123 is configured to adjust one or more word line voltages V0-V3 by adjusting the voltage difference b based on the detected temperature. As described herein, the voltage difference b corresponds to the slope of the linear region 220 in the subthreshold region 210 of the current-voltage characteristic 200, and adjusting the voltage difference b corresponds to adjusting the slope of the linear region 220. In some embodiments, the control logic 123 is configured to perform adjustments of one or more of the word line voltages V0-V3 and / or the voltage difference b so that the corresponding set of leakage currents I0-I3 remains unchanged or substantially unchanged when the operating temperature of the memory device 400 changes. In some embodiments, the leakage currents I0-I3 are considered substantially unchanged when any changes in one or more leakage currents I0-I3 due to the temperature dependency and the result of the adjustment are small enough not to affect the result of the DAC operation.

[0066] exist Figure 4 In the example configuration of , the control logic 123 is configured to perform the adjustment by referring to a storage circuit 433, which stores a predetermined relationship between different voltage data and corresponding different operating temperature values. Figure 4 In the example configuration of , the relationship is stored in the storage circuit 433 in the form of a lookup table 434. The lookup table 434 includes various temperature values ​​t0, t1, t2, etc. of the operating temperature. For each temperature value t0, t1, t2, etc., the lookup table 434 includes corresponding voltage data that the control logic 123 can use to perform the adjustment. Figure 4In the example configuration in, the voltage data stored in the lookup table 434 includes different values ​​b0, b1, b2, etc. of the voltage difference b. Upon receiving the detected temperature from the temperature sensor 423, the control logic 123 is configured to look up the lookup table 434 to find a temperature value that matches the detected temperature. For example, upon determining that the detected temperature is one of the temperature values ​​(e.g., t0), the control logic 123 is configured to extract the corresponding voltage difference b0 from the lookup table 434 and use b0 to generate a corresponding set of word line voltages, such as having a fixed predetermined V0, V1=V0+b0, V2=V1+b0, etc. When an exact match for the detected temperature is not found in the lookup table 434, the control logic 123 is configured to determine the corresponding voltage difference by, for example, interpolation or extrapolation. For example, when the detected temperature is between t0 and t1, the control logic 123 is configured to determine the corresponding voltage difference by interpolation based on at least b0 and b1.

[0067] In some embodiments, the temperature values ​​and corresponding voltage data in the lookup table 434 are predetermined, for example, by actual measurements of channel currents (or leakage currents) of actual transistors at different gate voltages and different operating temperatures. In some embodiments, the temperature values ​​and voltage data in the lookup table 434 are predetermined by simulations performed by a computer system. In at least one embodiment, additional temperature values ​​and corresponding voltage data are predetermined by interpolation, extrapolation, etc. based on actual measurements and / or simulation results. In some embodiments, the predetermined temperature values ​​and corresponding voltage data of the lookup table 434 are hardwired, for example, by a circuit designer in the storage circuit 433. In at least one embodiment, at least a portion or all of the temperature values ​​and corresponding voltage data of the lookup table 434 are provided or updated from an external device, for example, by an operator of the memory device 400 of a computer system including the memory device 400 through an I / O circuit in the memory device 400 to the storage circuit 433. The described process of predetermining the relationship between different voltage data and corresponding different temperature values ​​is sometimes referred to as a temperature compensation process.

[0068] The described voltage data including different values ​​of the voltage difference b constitute an example. Other voltage data are within the scope of various embodiments. For example, in one or more embodiments, the voltage data includes different groups of word line voltages V0-V3, etc., each group of word line voltages V0-V3 corresponds to one of the temperature values ​​t0, t1, t2, etc. The described lookup table is an example for presenting a predetermined relationship between different voltage data and corresponding different temperature values. Other ways for presenting a predetermined relationship are within the scope of various embodiments. For example, in one or more embodiments, the relationship is represented by at least one formula or function of the operating temperature. As described herein, the formula or function is pre-developed based on actual measurements and / or simulation results and stored in the control logic 123. After receiving the detected temperature from the temperature sensor 423, the control logic 123 is configured to calculate the corresponding value of the voltage difference b or the corresponding set of word line voltages, such as V0-V3, by inputting the detected temperature into the stored formula or function. In some embodiments, the accuracy of the DAC operation can be ensured by adjusting the word line voltage provided to the access transistor in the DAC operation based on the operating temperature of the memory device. According to some embodiments, one or more advantages described herein can also be achieved by the memory device 400.

[0069] As about Figure 3B As described above, a read operation of a memory cell may destroy the data stored in the capacitor of the memory cell, and in various cases the memory cell needs to be refreshed periodically to maintain the data stored therein. In other words, potential data disturbance is a problem in memory devices. Figure 5A-Figure 5B In some described embodiments, one or more memory devices are configured to perform DAC operations on data copied from a data source. As a result, in one or more embodiments, data disturbances at the source can be avoided.

[0070] Figure 5A is a schematic diagram of a memory device 500A according to some embodiments. In some embodiments, the memory device 500A corresponds to one or more of the memory devices 100 , 300 , 400 .

[0071] The memory device 500A includes a source memory array 532 and a DAC memory array 542. In some embodiments, the source memory array 532 and the DAC memory array 542 are regions of a larger memory array. In at least one embodiment, the source memory array 532 and the DAC memory array 542 are separate memory arrays, for example, in different memory banks. Figure 5AIn each memory array in FIG. 5 , horizontal lines schematically represent word lines, vertical lines schematically represent bit lines, and the intersections of bit lines and word lines schematically represent memory cells. For example, in source memory array 532, word lines are designated by label 502, bit lines are designated by label 504, and two example memory cells are designated by labels 533, 534. In DAC memory array 542, word lines and bit lines are not numbered, and two example memory cells are designated by labels 543, 544.

[0072] The source memory array 532 is configured to store digital source data 535 to be converted into analog signals. The source memory array 532 is configured with a sensing circuit 539, which is configured to perform a read operation similar to the reference Figure 3B The manner of the described read operation reads source data 535 from the source memory array 532 .

[0073] The DAC memory array 542 is configured to perform DAC operations. In at least one embodiment, the DAC memory array 542 corresponds to the memory array 112 and is configured with BL selection circuits, current summing circuits, and / or sensing circuits corresponding to the BL selection circuits 115, the current summing circuits 117, and the sensing circuits 119. The DAC memory array 542 is also configured with a bit line driver 548, which is configured to operate similarly to the reference Figure 3B The write operation is performed in the manner described above to write the data to be converted to the DAC memory array 542. In some embodiments, the bit line driver 548 is selectively coupled to the sense circuit 539 through the internal bus of the memory device 500B, for example, under the control of the control circuit of the memory device 500A. Other configurations are within the scope of various embodiments.

[0074] In some embodiments, when the source data 535 is to be converted to an analog signal, a DAC operation is not performed directly in the source memory array 532. Instead, as shown in FIG. Figure 3A As described above, before a DAC operation is performed at the DAC memory array 542, the source data 535 is copied to the DAC memory array 542. For example, in a read operation, the bit stored in the memory cell 533 is read by the sensing circuit 539, and the read bit is transmitted to the bit line driver 548. Then, the bit line driver 548 writes the bit to the corresponding memory cell 543 in the DAC memory array 542 in a write operation. Similarly, the remaining bits of the source data 535 (e.g., in the memory cell 534, etc.) are copied to the corresponding memory cells in the DAC memory array 542, such as the memory cell 544, etc. As a result, the DAC memory array 542 stores the copied data 545 corresponding to the source data 535. Then, as described with reference to Figure 3A As described above, the DAC memory array 542 performs a DAC operation on the copied data 545 .

[0075] In at least one embodiment, by performing the DAC operation on the copied data instead of the source data, the source data may be prevented from being disturbed by the DAC operation.

[0076] In some cases, due to process variations, the subthreshold slopes of access transistors in different regions of a memory device or its memory array may be different from each other. Potentially different subthreshold slopes in different regions complicate the calibration process of predetermining the word line voltages used in DAC operations, because different regions may require different sets of predetermined word line voltages. In some embodiments, by performing DAC operations in specific regions (e.g., DAC memory array 542), only the word line voltages to be used in DAC operations need to be predetermined for the specific region, thereby simplifying the calibration process.

[0077] In some embodiments where adjustments are to be made to compensate for temperature-related effects, when DAC operations are to be performed in a particular region of the memory array, the following is simplified: Figure 4 The temperature compensation process of determining the relationship between different voltage data and corresponding different temperature values.

[0078] In some embodiments, the specific region where the DAC operation is to be performed includes a single row or column of memory cells, for example, memory cells (including memory cells 543, 544) coupled to bit line 550 in DAC memory array 542. In at least one embodiment, the specific region where the DAC operation is to be performed includes several rows or columns of memory cells, each row or column being similar to the row or column corresponding to bit line 550. In at least one embodiment, by configuring the specific region where the DAC operation is to be performed as one row / column or several rows / columns, the calibration process and / or the temperature compensation process can be further simplified.

[0079] Figure 5B is a schematic diagram of a memory device 500B according to some embodiments. In some embodiments, the memory device 500B corresponds to one or more of the memory devices 100, 300, 400, 500A. Figure 5A Similar, in Figure 5B , horizontal lines schematically represent word lines, vertical lines schematically represent bit lines, and intersections of bit lines and word lines schematically represent memory cells.

[0080] The memory device 500B includes a source memory array 562 and a DAC memory array 572. The source memory array 562 and the DAC memory array 572 are regions of a larger memory array and share a set of bit lines 576 and a sense circuit 579. Similar to the source memory array 532, the source memory array 562 is configured to store digital source data 565 to be converted into analog signals. The DAC memory array 572 is configured to perform DAC operations, similar to the DAC memory array 542. In some embodiments, when the source data 565 is to be converted into an analog signal, the DAC operation is not performed directly in the source memory array 562. Instead, the source data 565 is first copied to the DAC memory array 572, where the DAC operation will be performed later, as described in reference to FIG. Figure 3A described.

[0081] In one or more embodiments, the data replication (or data replication) in the memory device 500B is different from the method described with respect to the memory device 500A. Figure 3B As described above, in a read operation, the sensing circuit amplifies and outputs the read data while also restoring or rewriting the read data back to the memory cell storing and reading the data. In one or more embodiments, the rewriting process is used to copy from the source memory array 562 to the DAC memory array 572.

[0082] For example, as referenced Figure 3BAs described above, in a read operation, by providing an access voltage Va to a word line 563 in a source memory array 562, the bit line 576 is precharged, and data in a memory cell coupled to the word line 563 is read out. The read data (i.e., the voltage on the bit line 576 increases or decreases) is detected or sensed by a sensing circuit 579. By providing VDD to one or more bit lines 576 where a logic "1" is detected, and providing VSS to one or more bit lines 576 where a logic "0" is detected, the sensing circuit 579 amplifies the detected read data and rewrites it back to the memory cell coupled to the word line 563. In this rewriting process, the control circuit controls the word line driver of the memory device 500B to provide the access voltage Va to the corresponding word line 573 of the DAC memory array 572. The access transistor of the memory cell coupled to the word line 573 is turned on, and the voltage VDD or VSS on the bit line 576 is allowed to write the corresponding logic "1" or logic "0" to the memory cell coupled to the word line 573. As a result, in a single read operation, data in memory cells coupled to word line 563 of source memory array 562 is copied to corresponding memory cells of word line 573 coupled to DAC memory array 572. Similarly and sequentially, data in memory cells coupled to each additional word line of source memory array 562 is copied to corresponding memory cells of corresponding word lines coupled to DAC memory array 572. When data in memory cells coupled to the last word line 564 of source memory array 562 is copied to corresponding memory cells of corresponding word line 574 coupled to DAC memory array 572, the data copy process is complete. Data in source memory array 562, including source data 565 to be converted into analog signals, is copied to DAC memory array 572 (including copied data 575 of source data 565). Then, as described with reference to Figure 3A As described above, the DAC memory array 572 performs a DAC operation on the copied data 575 .

[0083] In at least one embodiment, memory device 500B allows large amounts of data to be quickly copied from a source memory array to a DAC memory array. This configuration is advantageous in one or more embodiments where large amounts of data are to be converted to analog signals, such as in multiple rows or columns of memory cells. According to some embodiments, one or more of the advantages described herein with respect to memory device 500A may be realized by memory device 500B.

[0084] In some embodiments, the data replication configurations described with respect to memory device 500A and memory device 500B can both be implemented in a single memory device. For example, the data replication configuration of memory device 500A is performed when the source memory array and the DAC memory array do not share a set of common bit lines, and the data replication configuration of memory device 500B is performed when the source memory array and the DAC memory array share a set of common bit lines.

[0085] Fig. 6A is a schematic cross-sectional view of a portion of a memory device 600A according to some embodiments. In some embodiments, the memory device 600A corresponds to one or more of the memory devices 100, 300, 400, 500A, 500B.

[0086] The memory device 600A includes a substrate 640, at least one transistor 650 on the substrate 640, an interconnect structure 660 between the transistor 650 and the substrate 640, and a metal-insulator-metal (MIM) structure 670 on the transistor 650 and the substrate 640. The MIM structure 670 includes a capacitor coupled to the transistor 650 to form a memory cell having a 1T1C configuration as described herein. The transistor 650 is an example of an access transistor as described herein. The transistor 650 is also used as an example of a transistor constituting various circuits in the memory device 600A, including but not limited to a BL selection circuit, a current summing circuit, a sensing circuit, a 1T1C configuration as described herein, and a 1T1C configuration as described herein. Figure 1 The memory controller of the component, such as Figure 4 The storage circuit, such as Figure 7A-7B The multiplication and accumulation circuit (MAC) and the like.

[0087] In some embodiments, substrate 640 is a semiconductor substrate. N-type and P-type dopants are added to the substrate to form N-wells 651, 652 and a P-well (not shown) respectively. In some embodiments, an isolation structure is formed between adjacent P-wells and N-wells. For simplicity, Fig. 6A Several features such as the P-well and isolation structures are omitted.

[0088] The transistor 650 includes a gate and a source / drain. N wells 651, 652 constitute the source / drain of the transistor 650. The gate of the transistor 650 includes a stack of gate dielectric layers 653, 654 and a gate electrode 655. In at least one embodiment, the transistor 650 includes a gate dielectric layer instead of multiple gate dielectrics. Example materials of the gate dielectric layer include HfO2, ZrO2, etc. Example materials of the gate electrode 655 include polysilicon, metal, etc.

[0089] The memory device 600A also includes a contact structure configured to electrically couple the transistor 650 to other circuits in the memory device 600B. The contact structure includes source / drain (metal to device, or MD) contacts 656, 657 located above and electrically in contact with the source / drain 651, 652, respectively. The contact structure also includes various vias. For example, the via to gate (VG) via 645 is located above and electrically in contact with the gate electrode 655, and is configured to couple the gate electrode 655 to the word line WL in the interconnect structure 660. The via to device (VD) vias 658, 659 are located above and electrically in contact with the MD contacts 656, 657, respectively. The VD via 658 is configured to couple the source / drain 651 to a capacitor in the MIM structure 670, as described herein. The VD via 659 is configured to couple the source / drain 652 to the bit line BL in the interconnect structure 660.

[0090] The interconnect structure 660 includes a plurality of metal layers M0, M1, ... and a plurality of via layers VIA0, VIA1, ..., which are alternately arranged in the thickness direction (i.e., the Z direction) of the substrate 640. The interconnect structure 660 also includes various interlayer dielectric (ILD) layers (not shown) in which the metal layers and via layers are embedded. The M0 layer, i.e., the metal zero (M0) layer, is the lowest metal layer adjacent to and electrically connected to the VD and VG vias. Fig. 6A The M1 layer is a metal layer adjacent to the M0 layer. The interconnect structure 660 also includes other metal layers sequentially stacked on the M1 layer and Fig. 6A Schematically illustrated with corresponding labels such as "M5", "M6", and "M7". The interconnect structure 660 also includes a via layer arranged between and electrically coupled to consecutive metal layers. The via layer VIAn is arranged between and electrically coupled to the Mn layer and the Mn+1 layer, where n is an integer of zero or greater. For example, the via zero (VIA0) layer is the lowest via layer arranged between and electrically coupled to the M0 layer and the M1 layer. Fig. 6A Several via layers are schematically shown in FIG. 6 and are labeled accordingly, such as “VIA5” and “VIA6”. The metal layers and via layers of interconnect structure 660 are configured to electrically couple various components or circuits of memory device 600A to each other and to external circuits. Fig. 6A The M7 layer is shown as the top layer of the interconnect structure 660 , but in at least one embodiment, the interconnect structure 660 includes other metal layers and / or via layers higher than the M7 layer.

[0091] exist Fig. 6AIn the example configuration in FIG. 1 , the interconnect structure 660 includes the following structures stacked sequentially upward in the Z direction and electrically coupled to the VD via 658: an M0 pattern 661, various patterns and vias (not shown) in layers VIA0, M1, ... VIA4, an M5 pattern 662, a VIA5 via 663, an M6 pattern 664, and a VIA6 via 665. The VIA6 layer also includes VIA6 vias 666, 667. The overlying M7 layer includes M7 patterns 668, 669 that are electrically isolated from each other. The M7 pattern 668 electrically couples the VIA6 via 665 and the VIA6 via 666. The M7 pattern 669 is coupled to the VIA6 via 667 and is configured as or coupled to a power rail carrying VSS.

[0092] The MIM structure 670 is arranged on the M6 ​​layer and includes a multi-layer structure. Fig. 6A In the example configuration in , the MIM structure 670 includes the following layers stacked sequentially upward in the Z direction on the M6 ​​layer: one or more passivation layers (not shown), a lower conductive layer (or electrode layer) 673, an insulating layer 674, an upper conductive layer 675, and one or more passivation layers (not shown). Example materials of the passivation layer include, but are not limited to, TEOS (tetraethyl orthosilicate), SBL (silicide barrier layer), etc. Example materials of the conductive layers 673, 675 include, but are not limited to, TiN, TaN, etc. Example materials of the insulating layer 674 include, but are not limited to, silicon dioxide, ZrO, TiO2, HfOx, high-k dielectrics, etc. Examples of high-k dielectrics include, but are not limited to, zirconium dioxide, hafnium dioxide, zirconium silicate, hafnium silicate, etc. The lower conductive layer 673 is coupled to the M7 pattern 669 for VSS through the VIA6 through hole 667. The insulating layer 674, the upper conductive layer 675, and the one or more passivation layers are patterned to exist below the VIA6 via 666, but not below the VIA6 via 667. The VIA6 via 666 extends through the one or more passivation layers to electrically couple the upper conductive layer 675 to the M7 pattern 668, and thus to the source / drain 651 of the transistor 650 through various patterns and vias in the various metal layers and via layers described herein. The lower conductive layer 673, the insulating layer 674, and the upper conductive layer 675 below the VIA6 via 666 together form a capacitor that is coupled in series with the transistor 650 between the bit line BL and VSS to configure the memory cell. The capacitor and the transistor 650 in the MIM structure 670 at least partially overlap each other in the Z direction, as shown in FIG. Fig. 6A Schematically shown in .

[0093] exist Fig. 6AIn the example configuration of , the MIM structure 670 is arranged between the M6 ​​layer and the M7 layer. However, other arrangements in which the MIM structure 670 is arranged between any two metal layers of the interconnect structure 660 are also within the scope of various embodiments. In some embodiments, the pattern 668 coupled to the transistor 650 and the pattern 669 for VSS are arranged in different metal layers.

[0094] The configuration of transistor 650 described is an example. Various transistor configurations are within the scope of various embodiments, including but not limited to metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, P-channel metal oxide semiconductors (PMOS), N-channel metal oxide semiconductors (NMOS), bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, P-channel and / or N-channel field effect transistors (PFET / NFET), FinFETs, planar MOS transistors with raised source / drain, nanosheet FETs, nanowire FETs, etc. The capacitor configuration described as a MIM structure is an example. Other capacitor configurations, such as MOS capacitors, trench capacitors, etc., are also within the scope of various embodiments.

[0095] exist Fig. 6A In the example configuration of , the memory device 600A also includes a bipolar junction transistor (BJT) 630, which is configured as at least a portion of a bandgap temperature sensor corresponding to the temperature sensor 423. In some embodiments where a temperature sensor is not required, the BJT 630 is omitted. Fig. 6AIn the example configuration in FIG. 6 , BJT 630 is a PNP BJT. In some embodiments, BJT 630 is an NPN BJT. BJT 630 includes a P-well (not shown), an N-well 631 within the P-well, a P-doped region 632 within the N-well 631, and contact structures 633-635 located above and electrically contacting the P-well, N-well 633, and P-doped region 632, respectively. In some embodiments, N-well 631 corresponds to or is similar to N-wells 651, 652, and contact structures 633-635 correspond to or are similar to MD contacts 656, 657. Memory device 600A also includes various vias corresponding to or similar to VD vias 658, 659 for coupling BJT 630 to other circuit elements of the bandgap temperature sensor. In at least one embodiment, by arranging the BJT 630 on the same substrate 640 as the access transistor of one or more memory cells and / or in close proximity to the access transistor, operating temperature changes that may affect the access transistor are reflected in one or more temperature-related characteristics of the BJT 630, which allows other circuit elements of the bandgap temperature sensor to accurately detect the operating temperature for temperature-related adjustments, as described herein. In at least one embodiment, one or more advantages described herein may be achieved in the memory device 600A according to some embodiments.

[0096] The structure below the M0 layer and including transistor 650 is manufactured by a front-end-of-line (FEOL) process and is sometimes referred to as a FEOL structure. For example, transistor 650 is a FEOL transistor. The structure including the M0 layer and above is manufactured by a back-end-of-line (BEOL) process and is sometimes referred to as a BEOL structure. For example, MIM structure 670 is a BEOL capacitor.

[0097] In the memory device 600A, the access transistors of the memory cells are FEOL transistors, which occupy chip area on the substrate 640, which chip area could otherwise be configured to form other circuits. In some embodiments, the access transistors of the memory cells are BEOL transistors, which do not occupy chip area on the substrate 640, thereby freeing up chip area on the substrate 640 for other circuits.

[0098] Figure 6B is a schematic cross-sectional view of a portion of a memory device 600B according to some embodiments. In some embodiments, the memory device 600B corresponds to one or more of the memory devices 100, 300, 400, 500A, 500B. Figure 6B Zhongyu Fig. 6A Components with corresponding components in are represented by Fig. 6A The same reference numerals are used.

[0099] Compared to memory device 600A, memory device 600B includes BEOL transistors, each of which is coupled to a BEOL capacitor to form a BEOL memory cell. For example, transistor 680 in memory device 600B is a BEOL transistor, which is coupled to a BEOL capacitor in MIM structure 670 to form a BEOL memory cell. Figure 6B In the example configuration in FIG. 6 , transistor 650 is an example of a FEOL transistor constituting various circuits other than a memory cell in the memory device 600B.

[0100] Transistor 680 includes a metal oxide layer 681, a gate dielectric layer 682 lining an opening formed in a dielectric layer above the metal oxide layer 681, and a gate electrode 683 filling the remainder of the opening. A portion of the metal oxide layer 681 below the gate electrode 683 defines a channel of the transistor 680. Portions of the metal oxide layer 681 on opposite sides of the channel define source / drain electrodes 684, 685. Contact structures 686, 687 are respectively located above and in electrical contact with the source / drain electrodes 684, 685. Vias 663, 688, 689 are respectively located above and in electrical contact with the contact structure 686, the gate electrode 683, and the contact structure 687. The via 663 is configured to couple the source / drain electrode 684 to a capacitor in the MIM structure 670, as described with reference to FIG. Fig. 6A The via 688 is configured to couple the gate electrode 683 to the word line WL in the interconnect structure 660. The via 689 is configured to couple the source / drain 685 to the bit line BL in the interconnect structure 660. In some embodiments, the metal oxide layer 681 includes InGaZnO4 (IGZO), the gate dielectric layer 682 includes SiO2, and the gate electrode 683 and the contact structures 686, 687 include TiN. Other materials are within the scope of various embodiments.

[0101] exist Figure 6B In the example configuration in , transistor 680 is arranged below the M6 ​​layer and the MIM structure 670. However, other arrangements in which transistor 680 is arranged at another layer or level in the interconnect structure 660 and / or above the MIM structure 670 are also within the scope of various embodiments. Although BJT 630 is a FEOL device and transistor 680 (i.e., an access transistor) is a BEOL device at a different level, in one or more embodiments, the operating temperature detected using BJT 630 is still sufficiently accurate for the expected temperature-related adjustments, as described herein. In some embodiments, BJT 630 is replaced by a BEOL BJT or a BEOL PN junction (arranged closer to transistor 680 for more accurate temperature detection). In some embodiments, BJT 630 is omitted from the memory device 600B when a temperature sensor is not required.

[0102] As described herein, a memory device 600B having BEOL access transistors, ie, BEOL memory cells and BEOL memory arrays, can free up additional chip area for other circuits. In at least one embodiment, one or more advantages described herein can be achieved in a memory device 600B according to some embodiments.

[0103] Fig. 7A and Figure 7B 7 is a schematic diagram of a memory device 700 in various operations according to some embodiments. In some embodiments, the memory device 700 corresponds to one or more of the memory devices 100, 300, 400, 500A, 500B, 600A, 600B.

[0104] The memory device 700 includes a DAC memory array 710, a memory array 720, and a multiply-accumulate circuit (MAC) 730. In some embodiments, the DAC memory array 710 and the memory array 720 are regions of a larger memory array. In at least one embodiment, the DAC memory array 710 and the memory array 720 are separate memory arrays, for example, in different memory banks. Figure 7A-7B In each memory array in FIG. 1 , horizontal lines schematically represent word lines, vertical lines schematically represent bit lines, and intersections of bit lines and word lines schematically represent memory cells.

[0105] The DAC memory array 710 is configured to perform a DAC operation on the first digital data stored therein. The DAC memory array 710 is configured with a current summing circuit 717, which outputs an analog signal 718 corresponding to the first digital data to the MAC 730. In some embodiments, the DAC memory array 710 and the current summing circuit 717 correspond to the memory array 112 and the current summing circuit 117, and are configured to perform as described in reference Figure 3A The DAC operation described.

[0106] The memory array 720 is configured to store the second digital data to be operated together with the first digital data in the CIM operation. The memory array 720 is configured with a sensing circuit 729, which reads the second digital data from the memory array 720 and outputs the read second digital data 728 to the MAC 730. In some embodiments, the DAC memory array 720 and the sensing circuit 729 are configured to perform as described with reference to Figure 3B The read operation described.

[0107] The MAC 730 is an example of a computing circuit configured to perform a CIM operation on the first digital data converted into the analog signal 718 and the read second digital data 728, and output the result of the CIM operation as an output 733. Examples of the CIM operation include, but are not limited to, mathematical operations, logical operations, combinations thereof, and the like. In some embodiments, the MAC 730 is configured to multiply each analog signal 718 by a corresponding row of the read second digital data 728, and to accumulate or sum the multiplication results to obtain the output 733. For example, the MAC 730 is configured to multiply, among the analog signals 718, an analog signal corresponding to data in a column 711 of the DAC memory array 710 by data in a row 721 of the memory array 720. Next, the MAC 730 is configured to multiply, among the analog signals 718, an analog signal corresponding to data in a column 712 of the DAC memory array 710 by data in a row 722 of the memory array 720. The described multiplications are similarly repeated for the remaining columns of the DAC memory array 710 and the remaining corresponding rows of the memory array 720. The MAC 730 is also configured to accumulate or sum the multiplication results to obtain an output 733.

[0108] In at least one embodiment, the output 733 includes one or more analog signals. In at least one embodiment, the analog signal in the output 733 is directly provided to another MAC for further CIM operation. In some embodiments, the memory device 700 also includes one or more analog-to-digital converters (ADCs) configured to convert the analog signal in the output 733 into digital data for output or for further processing, such as another CIM operation, etc. Example ADCs include, but are not limited to, logic, integrated circuits, comparators, counters, registers, combinations thereof, and the like. In some embodiments, the MAC 730 includes one or more of an accumulator, a multiplier, an adder, and the like. Example accumulators include, but are not limited to, resistors, capacitors, integrator circuits, operational amplifiers, combinations thereof, and the like. Example multipliers include, but are not limited to, NOR gates, AND gates, any other logic gates, combinations of logic gates, and the like. Example adders include, but are not limited to, full adders, half adders, and the like. In some embodiments, adders are coupled to each other to form an adder tree having multiple levels. Other MAC configurations are within the scope of various embodiments.

[0109] In some embodiments, one of the first and second digital data comprises weight data and the other comprises input data. Fig. 7A In the embodiment, the first digital data to be converted into an analog signal stored in the DAC memory array 710 includes input data, and the second digital data stored in the memory array 720 includes weight data. Figure 7BIn the embodiment, the first digital data to be converted into an analog signal stored in the DAC memory array 710 includes weight data, and the second digital data stored in the memory array 720 includes input data. Figure 7A-7B As an example, according to some embodiments, the weight data or input data may be converted into an analog signal through a DAC operation. Figure 8A-8B Further examples of weight data and input data are described. In some embodiments, at least one of the first digital data or the second digital data includes data other than the weight data and the input data. According to some embodiments, the memory device 700 can achieve one or more advantages described herein.

[0110] Fig. 8A is a schematic diagram of a memory device 800A according to some embodiments.

[0111] The memory device 800A includes memory macros 802, 804, 806, 808 and a memory controller 820. In some embodiments, one or more of the memory macros 802, 804, 806, 808 correspond to the memory macro 110, and / or the memory controller 820 corresponds to the memory controller 120. Fig. 8A In the example configuration of , memory controller 820 is a common memory controller for memory macros 802, 804, 806, 808. In at least one embodiment, at least one of memory macros 802, 804, 806, 808 has its own memory controller. The number of four memory macros in memory device 800A is an example. Other configurations are within the scope of various embodiments.

[0112] Memory macros 802, 804, 806, and 808 are coupled to each other in sequence, and the output data of the previous memory macro is the input data of the subsequent memory macro. For example, input data DIN is input into memory macro 802. Memory macro 802 performs one or more CIM operations based on input data DIN and weight data stored in memory macro 802, and generates output data DOUT2 as a result of the CIM operation. Output data DOUT2 is provided as input data DIN4 of memory macro 804. Memory macro 804 performs one or more CIM operations based on input data DIN4 and weight data stored in memory macro 804, and generates output data DOUT4 as a result of the CIM operation. Output data DOUT4 is provided as input data DIN6 of memory macro 806. Memory macro 806 performs one or more CIM operations based on input data DIN6 and weight data stored in memory macro 806, and generates output data DOUT6 as a result of the CIM operation. Output data DOUT6 is provided as input data DIN8 of memory macro 808. The memory macro 808 performs one or more CIM operations based on the input data DIN8 and the weight data stored in the memory macro 808, and generates output data DOUT as a result of the CIM operation. One or more of the input data DIN, DIN4, DIN6, DIN8 corresponds to the weight data about Figure 7A-7B The input data described, and / or one or more of the output data DOUT2, DOUT4, DOUT6, DOUT corresponds to the Figure 7A-7B The output data described. In at least one embodiment, the configuration of memory macros 802, 804, 806, 808 implements a neural network. In at least one embodiment, one or more advantages described herein can be achieved by the memory device 800A.

[0113] Figure 8B is a schematic diagram of a neural network 800B according to some embodiments.

[0114] The neural network 800B includes a plurality of layers AE, each of which includes a plurality of nodes (or neurons). The nodes in the consecutive layers of the neural network 800B are connected to each other through a matrix or connection array. For example, the nodes in layer A and layer B are connected to each other through the connections in the matrix 812, the nodes in layer B and layer C are connected to each other through the connections in the matrix 814, the nodes in layer C and layer D are connected to each other through the connections in the matrix 816, and the nodes in layer D and layer E are connected to each other through the connections in the matrix 818. Layer A is an input layer configured to receive input data 811. The input data 811 is propagated from one layer to the next layer through the neural network 800B via the corresponding connection matrix between the layers. When the data propagates through the neural network 800B, the data undergoes one or more calculations and is output as output data 819 from the layer E which is the output layer of the neural network 800B. The layers B, C, and D between the input layer A and the output layer E are sometimes referred to as hidden layers or intermediate layers. Figure 8B The number of layers, the number of connection matrices, and the number of nodes in each layer are examples. Other configurations are within the scope of various embodiments. For example, in at least one embodiment, neural network 800B does not include hidden layers and has an input layer connected to an output layer via a connection matrix. In one or more embodiments, neural network 800B has one, two, or more than three hidden layers.

[0115] In some embodiments, matrices 812, 814, 816, 818 are implemented by memory macros 802, 804, 806, 808 accordingly, input data 811 corresponds to input data DIN, and output data 819 corresponds to output data DOUT. Specifically, in matrix 812, the connection between a node in layer A and another node in layer B has a corresponding weight. For example, the connection between node A1 and node B1 has a weight W (A1, B1), which corresponds to a weight value stored in a row or column of a memory array of memory macro 802, for example. Memory macros 804, 806, 808 are configured in a similar manner. When machine learning is performed using neural network 800B, weight data in one or more of memory macros 802, 804, 806, 808 is updated, for example, by a processor and through memory controller 820. According to some embodiments, one or more advantages described herein are achievable in neural network 800B, which is implemented in whole or in part by one or more memory macros and / or memory devices.

[0116] Figure 8C is a schematic diagram of an integrated circuit (IC) device 800C according to some embodiments.

[0117] The IC device 800C includes one or more hardware processors 832, one or more memory devices 834 coupled to the processors 832 via one or more buses 836. In some embodiments, the IC device 800C includes one or more other circuits, including but not limited to a cellular transceiver, a global positioning system (GPS) receiver, a network interface circuit for one or more of Wi-Fi, USB, Bluetooth, etc. Examples of processors 832 include but are not limited to a central processing unit (CPU), a multi-core CPU, a neural processing unit (NPU), a graphics processing unit (GPU), a digital signal processor (DSP), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), other programmable logic devices, a multimedia processor, an image signal processor (ISP), etc. Examples of memory devices 834 include one or more memory devices and / or memory macros described herein. In at least one embodiment, each processor 832 is coupled to a corresponding memory device in the memory device 834.

[0118] In some embodiments, the memory device 834 is a CIM memory device, and various calculations are performed in the memory device, which reduces the computational workload of the corresponding processor 832, reduces memory access time, and improves performance. In at least one embodiment, the IC device 800C is a system on a chip (SOC). In at least one embodiment, the IC device 800C can achieve one or more advantages described herein.

[0119] Fig.8D is a circuit diagram of an integrator circuit 800D according to some embodiments. In some embodiments, the integrator circuit 800D is an example of one or more of the current summing circuits 117, 317, 717. For example, the integrator circuit 800D is described herein as being applied to Figure 3A The current summing circuit 317 in.

[0120] Integrator circuit 800D includes an operational amplifier 855 and a capacitor 856. As described herein, input 851 of operational amplifier 855 is electrically coupled to bit line BL0 through a BL selection circuit (not shown) to receive a bit line current I BL Another input 854 of the operational amplifier 855 is grounded. The capacitor 856 is electrically coupled between the input 851 and the output 852 of the operational amplifier 855. The operational amplifier 855 and the capacitor 856 are configured to adjust the bit line current I BL Integrate to generate an analog signal S DAC The described configuration of integrator circuit 800D is an example. Other integrator circuit configurations or current summing circuit configurations are within the scope of various embodiments.

[0121] Fig. 9is a flow chart of a method 900 of operating a memory device according to some embodiments. In at least one embodiment, the method 900 is performed in or by one or more memory devices or memory macros described herein. Fig. 9 In the example configuration in , method 900 includes operations 915, 920, 925, 930. In some embodiments, one or more of operations 920, 925, 930 are omitted.

[0122] At operation 915, a plurality of memory cells of the memory device are accessed by providing respective different gate voltages to the gates of the access transistors of the plurality of memory cells that are lower than the threshold voltage of the access transistors. In some embodiments, the different gate voltages are in a linear region of the current-voltage characteristic to allow a single current to flow through each memory cell. The single current corresponds to the data stored in each memory cell and the corresponding gate voltage. For example, as described with reference to Figure 3A As described above, in the DAC operation according to some embodiments, the plurality of memory cells MCO-MC3 of the memory device 300 are accessed by providing corresponding different gate voltages V0-V3 to the gates of the access transistors T0-T3 of the memory cells MC0-MC3. Figure 2 As shown in the example configuration in FIG. 2 , the gate voltages V0 - V3 are located in a linear region 220 of the current-voltage characteristic 200 between the channel current Ids on a logarithmic scale and the gate voltage Vds of the access transistors T0 - T3 .

[0123] At operation 920, calculations are performed based on the respective currents flowing through the plurality of memory cells in response to the respective different gate voltages. Figure 3A As described, in response to the gate voltage (e.g., V0) provided to the gate of the access transistor (e.g., T0) of each memory cell (e.g., MC0), a separate current (e.g., I0×Bit0) corresponding to the data Bit0 stored in the memory cell MC0 and the gate voltage V0 is allowed to flow through the memory cell MC0. The single current allowed to flow through the corresponding memory cell corresponds to an analog signal, which is a result of digital-to-analog conversion of the data stored in the memory cell. In one or more embodiments, the individual currents are collected on the bit lines and summed by the current summing circuit 317 to obtain the analog signal S corresponding to the data stored in the memory cells MC0-MC3. DAC . As about Figure 7A-7B As described, for example, MAC 730 performs calculations based on analog signals (e.g., 718) and other data (e.g., 728) to generate outputs (e.g., 733). The calculations described are one example of CIM operations. In some embodiments, operation 920 is omitted, for example, where the analog signal as a result of the digital-to-analog conversion is used or processed by a process other than a CIM operation.

[0124] At operation 925, before operation 915, the gate voltage to be provided to each memory cell is adjusted based on the temperature of the memory device. Figure 4 As described, in one or more embodiments, the temperature sensor 423 detects the operating temperature of the memory device and provides the detected operating temperature to the control logic 123. The control logic 123 adjusts one or more of the gate voltages V0-V3 based on the detected operating temperature. In an exemplary temperature-dependent adjustment, the control logic 123 refers to a predetermined relationship between different voltage data (e.g., b0, b1, b2) and corresponding different values ​​of the operating temperature (e.g., t0, t1, t2), extracts voltage data corresponding to the detected operating temperature, such as one of b0, b1, b2, and adjusts one or more of the gate voltages V0-V3 based on the extracted voltage data. Then, in operation 915, the adjusted gate voltage is provided to the gate of the access transistor. In some embodiments, for example, when temperature-dependent adjustment is not required, operation 925 is omitted.

[0125] At operation 930, data to be converted into one or more analog signals is copied from a plurality of other memory cells to a plurality of memory cells to perform DAC operations prior to operation 915. For example, as shown in FIG. Figure 5A-Figure 5B As described, in one or more embodiments, the source data 535, 565 to be converted is copied from the memory cells in the source memory array 532, 562 to the corresponding memory cells in the DAC memory array 542, 572. Then, as described with respect to operation 915, a DAC operation is performed on the copied data (e.g., 545, 575). In some embodiments, operation 930 is omitted, for example, when the data to be converted is already in the DAC memory array. According to some embodiments, one or more advantages described herein can be achieved by method 900.

[0126] The described methods and algorithms include example operations, but they do not necessarily need to be performed in the order shown. Operations may be added, replaced, reordered, and / or eliminated as appropriate, in accordance with the spirit and scope of the embodiments of the present disclosure. Embodiments combining different features and / or different embodiments are within the scope of the present disclosure and will be apparent to those of ordinary skill in the art after reading the present disclosure.

[0127] In some embodiments, a memory device includes a plurality of word lines, a bit line, a memory array, a control circuit, and a current summing circuit. The memory array includes a plurality of memory cells coupled to the bit lines. Each of the plurality of memory cells includes an access transistor coupled to a corresponding word line among the plurality of word lines. The control circuit is configured to provide a plurality of word line voltages different from each other to the access transistor through the plurality of word lines, respectively. The current summing circuit is configured to couple to the bit lines and detect a bit line current on the bit lines.

[0128] In some embodiments, the control circuit is configured to provide a plurality of word line voltages that are below a threshold voltage of the access transistor.

[0129] In some embodiments, a plurality of memory cells correspond to a plurality of bits arranged in order of importance, the plurality of bits including a first bit and a second bit, the second bit being higher in order of importance than the first bit, and the control circuit is configured to: provide a first word line voltage among a plurality of word line voltages to an access transistor of a first memory cell among the plurality of memory cells, the first memory cell corresponding to the first bit, and to: provide a second word line voltage among the plurality of word line voltages to an access transistor of a second memory cell among the plurality of memory cells, the second memory cell corresponding to the second bit, the second word line voltage being higher than the first word line voltage.

[0130] In some embodiments, the plurality of word line voltages differ from each other by a multiple of a predetermined voltage difference.

[0131] In some embodiments, the control circuit is configured to provide a plurality of different word line voltages to access transistors of the plurality of memory cells so that the access transistors generate different leakage currents accordingly when storing bits of a first logic state.

[0132] In some embodiments, each leakage current among the different leakage currents is k times greater or k times less than another leakage current among the different leakage currents.

[0133] In some embodiments, k is 2.

[0134] In some embodiments, the memory device further includes: a sensing circuit; and a selection circuit coupled to a bit line and configured to selectively: couple the bit line to a current summing circuit in a digital-to-analog conversion (DAC) operation, in which the control circuit is configured to provide a plurality of word line voltages different from each other to the access transistor, and couple the bit line to the sensing circuit in a read operation, in which the sensing circuit is configured to sense a bit stored in a memory cell among a plurality of memory cells.

[0135] In some embodiments, the memory device further comprises: a temperature sensor configured to detect a temperature of the memory device in operation, wherein the control circuit is configured to adjust one or more word line voltages of the plurality of word line voltages based on the temperature detected by the temperature sensor.

[0136] In some embodiments, the memory device further comprises: a temperature sensor configured to detect a temperature of the memory device in operation, wherein the plurality of word line voltages differ from each other by a multiple of a predetermined voltage difference, and the control circuit is configured to adjust the voltage difference based on the temperature detected by the temperature sensor.

[0137] In some embodiments, a memory device includes a plurality of word lines, a bit line, a memory array, and a control circuit. The memory array includes a plurality of memory cells coupled to the bit lines. Each of the plurality of memory cells includes an access transistor coupled to a corresponding word line among the plurality of word lines. The control circuit is configured to provide a plurality of word line voltages to the access transistors of the plurality of memory cells through the plurality of word lines in a digital-to-analog conversion (DAC) operation, respectively, and the plurality of word line voltages are lower than a threshold voltage of the access transistor. The control circuit is also configured to provide a read voltage to the access transistor of the selected memory cell through the corresponding word line in a read operation of a selected memory cell among the plurality of memory cells, and the read voltage is equal to or higher than the threshold voltage.

[0138] In some embodiments, the memory device further comprises: a temperature sensor coupled to the control circuit and configured to detect a temperature of the memory device in operation, wherein the control circuit is configured to adjust one or more of the plurality of word line voltages based on the temperature detected by the temperature sensor in DAC operation.

[0139] In some embodiments, the memory device further includes: a storage circuit configured to store a relationship between different voltage data and corresponding different temperature values, wherein the control circuit is configured to adjust one or more word line voltages among the plurality of word line voltages based on a temperature detected by a temperature sensor and the relationship stored in the storage circuit during a DAC operation.

[0140] In some embodiments, the plurality of word line voltages differ from each other by a multiple of a predetermined voltage difference, and the different voltage data include different voltage difference values ​​corresponding to different temperature values.

[0141] In some embodiments, the memory device further comprises: additional bit lines, wherein the memory array further comprises a plurality of additional memory cells coupled to the additional bit lines and the plurality of word lines, and the control circuit is configured to copy data from the plurality of additional memory cells to the plurality of memory cells in a DAC operation and before correspondingly providing the plurality of word line voltages to the access transistors of the plurality of memory cells.

[0142] In some embodiments, a method of operating a memory device includes a computation-in-memory (CIM) operation of the memory device. The CIM operation includes accessing a plurality of memory cells of the memory device by providing corresponding different gate voltages to gates of access transistors of the plurality of memory cells that are lower than a threshold voltage of the access transistors. The CIM operation also includes performing a computation based on respective currents flowing through the plurality of memory cells in response to the corresponding different gate voltages.

[0143] In some embodiments, the CIM operation further includes summing the currents to obtain an analog signal corresponding to the digital data stored in the plurality of memory cells.

[0144] In some embodiments, the in-memory calculation includes: multiplying the analog signal with additional data read from multiple additional memory cells of the memory device, the digital data stored in the multiple memory cells includes one of the input data and the weight data, and the additional data read from the multiple additional memory cells includes the other of the input data and the weight data.

[0145] In some embodiments, the CIM operation further comprises adjusting respective different gate voltages provided to the plurality of memory cells based on a temperature of the memory device.

[0146] In some embodiments, the CIM operation further comprises, prior to accessing: copying data from a plurality of additional memory cells in the memory device to the plurality of memory cells, and accessing comprises accessing the copied data.

[0147] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, comprising: multiple word lines; bit line; a memory array comprising a plurality of memory cells coupled to the bit lines, wherein each of the plurality of memory cells comprises an access transistor coupled to a corresponding word line among the plurality of word lines; a control circuit configured to provide a plurality of word line voltages different from each other to the access transistors through the plurality of word lines accordingly; and The current summing circuit is configured to be coupled to the bit line and detect a bit line current on the bit line.

2. The memory device according to claim 1, wherein: The control circuit is configured to provide the plurality of word line voltages below a threshold voltage of the access transistor.

3. The memory device according to claim 1, wherein: The plurality of memory cells correspond to a plurality of bits arranged in order of importance, The plurality of bits include a first bit and a second bit, the second bit being higher in order of importance than the first bit, and The control circuit is configured to: providing a first word line voltage among the plurality of word line voltages to the access transistor of a first memory cell among the plurality of memory cells, the first memory cell corresponding to the first bit, and A second word line voltage among the plurality of word line voltages is provided to the access transistor of a second memory cell among the plurality of memory cells, the second memory cell corresponding to the second bit, the second word line voltage being higher than the first word line voltage.

4. The memory device according to claim 1, wherein: The control circuit is configured to provide the multiple word line voltages different from each other to the access transistors of the multiple memory cells so that the access transistors generate different leakage currents accordingly when storing bits of a first logic state.

5. The memory device according to claim 4, wherein: Each leakage current among the different leakage currents is k times greater or k times less than another leakage current among the different leakage currents.

6. The memory device according to claim 1, further comprising: Sensing circuit; as well as A selection circuit is coupled to the bit line and is configured to selectively: coupling the bit line to the current summing circuit in a digital-to-analog conversion operation, in which the control circuit is configured to provide the plurality of word line voltages different from one another to the access transistor, and The bit line is coupled to the sensing circuit in a read operation in which the sensing circuit is configured to sense a bit stored in a memory cell among the plurality of memory cells.

7. A memory device comprising: multiple word lines; bit line; a memory array comprising a plurality of memory cells coupled to the bit lines, wherein each of the plurality of memory cells comprises an access transistor coupled to a corresponding word line among the plurality of word lines; as well as a control circuit configured to provide a plurality of word line voltages to the access transistors of the plurality of memory cells through the plurality of word lines in a digital-to-analog conversion operation, the plurality of word line voltages being lower than a threshold voltage of the access transistors, and In a read operation of a selected memory cell among the plurality of memory cells, a read voltage is provided to the access transistor of the selected memory cell through the corresponding word line, the read voltage being equal to or higher than the threshold voltage.

8. The memory device according to claim 7, further comprising: a temperature sensor coupled to the control circuit and configured to detect a temperature of the memory device in operation, The control circuit is configured to adjust one or more word line voltages among the plurality of word line voltages based on the temperature detected by the temperature sensor during the digital-to-analog conversion operation.

9. The memory device according to claim 7, further comprising: The other bit lines, in The memory array further includes a plurality of further memory cells coupled to the further bit lines and the plurality of word lines, and The control circuit is configured to, during the digital-to-analog conversion operation and before correspondingly providing the plurality of word line voltages to the access transistors of the plurality of memory cells, Data is copied from the plurality of additional memory cells to the plurality of memory cells.

10. A method of operating a memory device, comprising: In a memory computing operation of a memory device, accessing a plurality of memory cells of the memory device by providing gates of access transistors of the plurality of memory cells with corresponding different gate voltages that are lower than a threshold voltage of the access transistors, and Calculations are performed based on respective currents flowing through the plurality of memory cells in response to the respective different gate voltages.

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