Sensing reverse pulse for read state programmable memory cells

Abstract

Devices, methods, and systems for reading a program state of a memory element are disclosed herein. The method includes setting a bit line to which a memory element is connected to a first voltage, and generating a compensation voltage different from the first voltage to the bit line. The method further includes generating a modified sense voltage to the bit line, the modified sense voltage defined by the compensation voltage and a sense voltage generated from the memory element, and determining a program state based on the modified sense voltage. The complementary memory element may be used to generate the compensation voltage by discharging a complementary plate line to which the second memory element is connected to charge a complementary bit line to which the second memory element is connected, and connecting the bit line to the complementary bit line to generate the compensation voltage to the bit line.

Description

Technical Field

[0001] The present disclosure relates to non-volatile memory, and in particular to memory including state programmable memory elements for storing information in the memory cells. Background Art

[0002] Non-volatile memory allows information to be stored in the memory, wherein the stored information remains in the memory even after external power to the memory has been removed. The memory is typically formed of a plurality of memory cells, each of which is capable of storing information in a state-programmable memory element (e.g., a ferroelectric memory element, such as a ferroelectric capacitor) that is capable of retaining written information based on the programming state of the state-programmable memory element, even after power has been removed therefrom. The programmed state often represents a binary value (e.g., a logical "1" or a logical "0"), which can be read out at a later time by applying a read voltage sufficient to switch the state of the state-programmable memory element, and then determining the read state from the switching charge injected when the state-programmable memory element changes state. However, parasitic capacitance may be present across the state-programmable memory element, which may reduce the switching charge.

[0003] In a typical configuration in which a plate line is connected to one side of a state-programmable memory element and a bit line is connected to the other side of the state-programmable memory element, a read voltage applied to one side of the state-programmable memory element (e.g., at the plate line) can be coupled across a parasitic capacitance, which in turn can significantly reduce the switching charge provided by the state-programmable memory element during a read operation. The reduced switching charge means that the read window can be narrower and the read margin can be reduced (e.g., the difference between the charge associated with a "0" and the charge associated with a "1" is smaller), resulting in potential read errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] In the accompanying drawings, the same reference numerals generally refer to the same parts throughout the different views. The drawings are not necessarily drawn to scale, but emphasis is generally placed on illustrating the principles of the invention. In the following description, various aspects of the invention are described with reference to the following drawings, in which:

[0005] Figure 1 shows an example of a typical memory cell where a plate line is connected to one side of the memory element and the other side of the memory element is connected to a bit line through an access transistor;

[0006] Figure 2 shows an example of a typical hysteresis curve for a state programmable memory element, where the polarization is plotted as a function of the voltage across the memory element;

[0007] Figure 3 depicts an example of a memory cell to which a read voltage is provided during a read operation to generate a switching charge to a sense amplifier, wherein parasitic capacitance can affect the generated switching charge;

[0008] Figure 4 An exemplary two-sided memory architecture is shown having multiple sense amplifiers and multiple arrays of memory cells, wherein each sense amplifier is connected on one side to an even array of memory cells and the other side of the sense amplifier is connected to an odd array of memory cells;

[0009] Figure 5 depicts an exemplary representation of a dual-sided sense amplifier;

[0010] Figure 6 depicts an exemplary representation of a double-sided sense amplifier with a reverse pulse (compensation voltage) generating circuit;

[0011] Figure 7 depicts an exemplary timing diagram of a double-sided sense amplifier with a reverse pulse (compensation voltage) generating circuit in operation;

[0012] Figure 8 depicts an exemplary representation of a double-sided sense amplifier with a reverse pulse (compensation voltage) generating circuit, wherein the double-sided sense amplifier is connected to a first cell array (the "even" cells being read) and a second cell array (the "odd" cells used as a read reference);

[0013] Fig.9A , Fig. 9B and Fig. 9C illustrative read windows of an ideal memory element, a memory element with parasitic capacitance, and a memory element with parasitic capacitance whose effects have been reduced using a reverse pulse generation circuit, respectively;

[0014] Fig.10 exemplary simulation results showing how a compensation voltage can improve a sense amplifier's read window; and

[0015] Fig.11 An exemplary flow chart illustrating a method for using a compensation voltage during a read operation. DETAILED DESCRIPTION

[0016] The following detailed description refers to the accompanying drawings, which show by way of example specific details and aspects that can be practiced in the present invention. These aspects are described in sufficient detail to enable those skilled in the art to practice the present invention. Without departing from the scope of the present invention, other aspects may be utilized, and structural, logical and electrical changes may be made. Various aspects are not necessarily mutually exclusive, because some aspects may be combined with one or more other aspects to form new aspects. Various aspects are described in conjunction with methods, and various aspects are described in conjunction with devices. However, it is to be understood that the aspects described in conjunction with methods may be similarly applied to devices, and vice versa.

[0017] In general, non-volatile memories are typically formed of many memory cells, each of which typically stores one of two states: a first state representing an off state (e.g., representing a digital bit "0") and a second state representing an on state (e.g., representing a digital bit "1"). The individual memory cells forming the memory are typically organized into controlled groups of cells, each of which can be addressed individually but have a common control scheme for biasing the cells via control lines, such as bit lines (e.g., which are used to operate cells grouped in the same column), word lines (e.g., which are used to operate cells grouped in the same row), and / or plate lines (e.g., which are used to operate cells grouped so as to share a common node such as the same "plate"). Among other components, a memory cell may include a state-programmable memory element (e.g., a ferroelectric memory element, such as a ferroelectric capacitor) that is capable of retaining written information by writing one of the remanent states of the memory element so that it can be read out later during a read operation.

[0018] As used throughout this disclosure, the state of a memory element is described as "residual", where the memory element is able to maintain its programmed state even when it is not connected to a power source. Also as used throughout the text, the current residual state to which the memory element has been set can be referred to as a "storage" state, a "write" state, or a "programmed" state. It should be understood that when referring to a state-programmable memory element, the terms "write", "storage" or "programming" are generally used to refer to the residual state of the set state-programmable memory element. As understood, the term "voltage" can be used in this article with respect to "bit line voltage", "word line voltage", "plate line voltage", etc. The "voltage across" of a component can be used in this article to represent the voltage drop from a node on one side of the component (e.g., one side of a capacitor) to a node on the other side of the component (e.g., the other side of a capacitor).

[0019] When the state-programmable memory element comprises a ferroelectric material (e.g., a ferroelectric capacitor), the remanent state is understood to refer to a remanent polarization state set by applying a specific voltage across the element sufficient to set the corresponding polarization state, wherein, once set, the element retains the remanent polarization state even when the voltage across the element has been removed (e.g., it is remanently magnetically polarized). Once such an element state has been programmed to a remanent state, it typically remains in the programmed state until it is reprogrammed by applying a voltage across it sufficient to program the element to a (e.g., new) remanent state. The polarization capability (e.g., remanent polarization capability, e.g., non-remanent spontaneous polarization capability) of a state-programmable memory element can be analyzed using capacitance measurements (e.g., spectroscopy), for example, by static (Capacitance voltage, CV) and / or time-resolved measurements or by polarization-voltage (polarization-voltage, PV) or positive-up-negative-down (PUND) measurements. Another method for determining the polarization capability of a state-programmable memory element can include transmission electron microscopy, for example, electric field-dependent transmission electron microscopy.

[0020] As described above, a typical memory includes a plurality of memory cells, each of which includes a memory element that represents information by being programmable to different states, each state corresponding to different stored information (e.g., a storage value of a digital bit "0" may be represented by a first programming state, and a storage value of a digital bit "1" may be represented by a second programming state). Once the memory element of a memory cell has been programmed, a read operation may be used to read out the programming state. In a read operation, a read voltage sufficient to switch its programming state and generate a charge in a sensing circuit may be applied to the memory element, and its sensing voltage may then be compared to a threshold reference voltage to determine the programming state.

[0021] With certain memory cell configurations, sensing architectures, and memory elements, there can be parasitic capacitance between the plate line and the bit line, and therefore across the state programmable memory element (one terminal of which is typically connected to the bit line through an access transistor, and the other terminal is connected to the plate line). Thus, when a read voltage is applied to one terminal (e.g., the plate line) of the state programmable memory element, the parasitic capacitance can generate a parasitic voltage at the other terminal (e.g., the bit line) of the state programmable memory element. Such parasitic capacitance can be particularly problematic in memories having an "all bitline" (ABL) architecture, in which multiple (e.g., all) bit lines in a group can be read simultaneously by applying a read voltage to a plate line common to the group and then sensing the charge generated on the corresponding bit line of each memory element, which means that all memory elements on the bit lines of the group can be a cause of parasitic capacitance, even those memory cells in the group that have not yet been selected for reading (e.g., via their access transistors).

[0022] The parasitic voltage generated on the bit line due to parasitic capacitance can reduce the switching charge provided by the state-programmable memory element during a read operation. The reduced switching charge means that the read window (e.g., the difference between the voltage formed associated with the "0" bit and the voltage formed associated with the "1" bit) can be narrower and the read margin can be reduced, resulting in potential read errors. Although coupling capacitors can be added to each bit line to offset the parasitic voltage whose capacitance is equal to the parasitic capacitance, due to space limitations, adding additional capacitors is not feasible from a spatial layout / layout perspective. As discussed in more detail below, in order to compensate for the reduction in switching charge caused by parasitic capacitance, a reverse pulse (also called a compensation voltage) can be injected into the bit line that is being actively read, where the reverse pulse (or compensation voltage) can be provided by the corresponding bit line (e.g., the complementary bit line) that is not being actively read.

[0023] Figure 1 A typical memory cell 100 formed by a state programmable memory element 101 is shown, and Figure 2 Graph 200 shows a typical hysteresis curve 210 of such a state programmable memory element (eg, state programmable memory element 101). Figure 1In the embodiment of the present invention, one terminal (side A) of the state programmable memory element is connected to the plate line (PL) of the memory, and the other terminal (side B) is connected to the bit line (BL) of the memory through an access transistor. The access transistor can be controlled by the word line (WL) of the memory. During a read operation, the bit line is first discharged to ground, and then a voltage is applied to the PL terminal. If the access transistor is valid, a switching charge (Qsw) (also called a switching voltage) is generated on BL, which depends on the programming state of the state programmable memory element 101 and its dielectric capacitance. The generated switching charge can then be sensed via a sensing circuit (e.g., as a voltage at a sense amplifier) ​​and compared with a predetermined threshold voltage to determine the read state (e.g., logical state, such as "0" or "1") of the corresponding memory cell.

[0024] Figure 2 Showing the state of a programmable memory element (e.g., Figure 1 Graph 200 of a typical hysteresis curve 210 of a state programmable memory element 101) wherein the polarization (P) of the state programmable memory element is regulated according to the voltage (V AB ) to draw. Figure 1 In the case of the typical memory cell configuration shown in , the voltage applied across the state programmable memory element is the voltage difference between the plate line (PL) and the bit line (BL), or V PL -V BL Graph 200 shows two remanent polarization states (211, 212) of a state-programmable memory element, which can represent programmable states of the memory element. For example, the state-programmable memory element can be programmed to remanent polarization state 211 (e.g., representing a digital information bit having a value of "0") or remanent polarization state 212 (e.g., representing a digital information bit having a value of "1") by applying a programming voltage across the state-programmable memory element sufficient to program the corresponding remanent polarization state.

[0025] Typically, the programming voltage is defined by a threshold voltage (Vth), beyond which the state programmable memory element is programmed to a corresponding remanent polarization state. For example, if the voltage applied across the state programmable memory element is greater than +Vth (e.g., a positive number greater than +Vth), the state programmable memory element will be programmed to remanent polarization state 211. If the voltage applied across the state programmable memory element is greater than -Vth (e.g., a negative number less than -Vth), the state programmable memory element will be programmed to remanent polarization state 212. The hysteresis curve 210 shows the path that the polarization follows when the voltage across the state programmable memory element changes.

[0026] To read the storage state of a state programmable memory element, a read voltage is typically applied across the state programmable memory element sufficient to program the remaining state of the state programmable memory element to a predetermined state. This generates a switching charge that depends on the programming state prior to application of the read voltage, wherein if the read operation causes the state programmable memory element to switch to a new state (e.g., the predetermined state is different from the previously programmed state), a larger switching charge will be provided, whereas if the read operation causes the state programmable memory element to be reprogrammed to the same state (e.g., the predetermined state is the same as the previously programmed state), little or no switching charge will be provided from the state programmable memory element.

[0027] As should be understood, due to the capacitance ratio between the inherent dielectric capacitance of the memory cell and the capacitance of the node to which it is connected (e.g., the bit line), a voltage will also be provided from the state-programmable memory element to the sensing circuit. Therefore, the sensing voltage provided to the sensing circuit during a read operation can depend not only on the switching charge, but also on the capacitance ratio. This is why a voltage is still provided to the sensing circuit when the state is not switched during a read operation (e.g., the read state is the same as the predetermined state, such as "0"). For example, if the memory is configured to generate a switching charge to the bit line by applying a voltage (VPL) to the plate line, the voltage on the bit line will be VPL*C when the memory element does not flip state (e.g., reads a "0" when the predetermined state is also "0") and passes little to no switching charge to the bit line. dielectric / (C dielectric +C BL ), where C dielectric is the dielectric capacitance of the memory element and is the C of the bit line BL In a typical voltage sensing scheme, the resulting voltage can be provided as a voltage at the input of a sense amplifier (e.g., across an input capacitor), where the sense amplifier can compare the sensed voltage to a predetermined voltage to determine the residual state to which the state-programmable memory element has been programmed prior to a read operation.

[0028] Figure 3 3 shows how parasitic capacitance 305 (Cpl_bl) may actually exist across a state programmable memory element 301 (e.g., between a plate line PL and a bit line BL to which the programmable memory element is connected via an access transistor controlled by a word line WL). In a typical read operation, the bit line is first discharged to ground, and then a read voltage (e.g., +VPL) is applied to the plate line, where the read voltage is sufficient to program the state programmable memory element 301 to a predetermined residual state (e.g., a state associated with "0", e.g., in Figure 2211). The switching charge (Qsw) generated to the bit line can then be reduced due to the presence of parasitic capacitance 305. As should be understood, a single sense amplifier can be connected to multiple memory elements that are part of the same group and therefore share a common bit line. Therefore, the effective parasitic capacitance 305 between the plate line and the bit line can be attributed to the multiple memory elements sharing the common bit line. In addition, the sense amplifier 320 can be differential or double-sided, where one side of the sense amplifier 320 is connected to one bit line of one memory cell array (e.g., the bit line of the even cell set) and the other side of the amplifier is connected to the bit line of a different memory cell array (e.g., the bit line of the odd cell set). In a double-sided configuration, one side of the sense amplifier 320 can be effectively operated to read the bit line of one cell set (e.g., the even side), while the other side of the amplifier (its complementary end) acts as a reference (e.g., the bit line of the odd side), or vice versa.

[0029] exist Figure 4 An exemplary memory using dual-sided (also called complementary) sense amplifiers is shown in , where each sense amplifier in a bank of sense amplifiers can be connected on one side of the dual-sided sense amplifier to a common bit line for a row in a set of "even" memory cells (shown by the bold black line), and on the other side of the dual-sided sense amplifier to a common bit line for a row in a set of "odd" memory cells (shown by the light dashed line) (thus, the light line for a given sense amplifier is complementary to the bold line). Figure 4 , eight sense amplifiers are shown in two different rows, with one sense amplifier 420 labeled and its complementary "even" bit line 410a connected to a row of a set of "even" memory cells, and its connection to an "odd" bit line 410b connected to a row of a set of "odd" memory cells labeled. As should be appreciated, this type of pattern can be repeated across a memory, where each memory cell array can have any number of rows of a set of "even" memory cells, each with a (e.g., complementary) row of a set of "odd" memory cells, with each sense amplifier differentially connected to an even / odd bit line pair. It should be appreciated that the terms "even" and "odd" are arbitrary groupings of memory cells to which the sense amplifiers are connected, and do not necessarily refer to any particular numbering scheme for even and odd cells. More broadly, the even / odd configuration or dual-sided configuration described herein can be understood as a complementary configuration, where one side of the amplifier is the side to be read, and the other side serves as its complement. In a typical memory with even and odd groupings of memory cells, for example, the grouping can be layout-based.

[0030] In a double-sided sense amplifier configuration, each sense amplifier can be understood as a latch whose two inputs are the two bit lines of an even / odd bit line pair (eg, an input and its complement), where the latch is enabled by a sense enable (SE) signal. Figure 5 Such an example is shown in , where the dual-sided sense amplifier 520 is shown as a latch 550, one side of which (e.g., the "even" side) is connected to the even bit line (BLE), and the other side (e.g., the "odd" side) is connected to the odd bit line (BLO). The latch 550 can be connected via one or more sense enable transistors / switches 561, 562, which, when the latch 550 is actuated, connect one side of its power supply to the power supply power (Vpwr) and the other side of its power supply to ground. The enable transistors / switches 561, 562 can be operated by a sense enable (SE) signal to supply power to the latch 550 when the SE signal is enabled, and to float the supply when the SE signal is not enabled. The even and odd pre-charge transistors / switches (570e, 570o) may be operated by corresponding signals (PRECHE, PRECHO) which, when enabled, connect the corresponding bit line to its corresponding even / odd source voltage (VSSPRCE, VSSPRCO) for charging / discharging the corresponding bit line.

[0031] Figure 6 A circuit diagram 600 shows a sense amplifier 620 that can be enhanced by configuring the sense amplifier 620 with a reverse pulse (compensation voltage) that can help counteract the undesirable effects of parasitic capacitance between the bit line and the plate line during a read operation. The sense amplifier 620 can be double-sided and similar to Figure 5 The sense amplifier 520 is represented as a latch whose two inputs are the bit lines of the even / odd bit line pair, where the latch is enabled by the sense enable (SE) signal. The even side bit line (BLE) and the odd side bit line (BLO) can be precharged to a common source voltage (VSSPRC) through corresponding precharge transistors / switches, which can be configured between ground voltage (GND) or voltage reference (VREF) via a selection circuit (e.g., a multiplexer) (e.g., mux 680). Figure 6 As shown, parasitic capacitance 605e (Cpl_bl_E) can effectively exist between the bit line and the plate line on the even side (between BLE and PLE), and parasitic capacitance 605o (Cpl_bl_O) can effectively exist between the bit line and the plate line on the odd side (between BLO and PLO). As described above, during a read operation, these parasitic capacitances can reduce the switching charge provided by the memory element being read and therefore reduce the read window.

[0032] To counteract the undesirable effects that this parasitic capacitance may have on the read window, a precharge voltage (e.g., a non-zero voltage) may be applied to the side of the latch being read that is different from ground to compensate for the voltage lost by the parasitic capacitance. This precharge voltage may be provided from the complementary side of the sense amplifier 620 by selectively applying (via a switch or set of switches) a voltage to the complementary side of the sense amplifier 620, and then connecting the complementary side to the side being read via another switch or set of switches (e.g., reverse pulse transistor / switch 670). During a read operation, the reverse pulse transistor / switch 670 may be enabled via a reverse pulse control line (CNTPLSEN). For example, before a read voltage is applied to the bit line being read (e.g., during a read operation), both bit lines are first discharged to ground voltage at mux 680 by first selecting (e.g., based on reference select signal VREFEN) connecting VSSPRC to GND and enabling even and odd precharge transistors / switches (e.g., based on precharge enable signals PRECHE and PRECHO, one signal for the side being read, e.g., sense precharge sense signal, and the other signal for the complementary side, e.g., complementary precharge enable signal). After the bit lines are discharged to ground, a read voltage (+VPL) is pulsed to the plate line of the complementary memory element (e.g., on the odd side of sense amplifier 620), which applies a voltage of -VPL across the odd side parasitic capacitance 605o (because BLO is at ground and PLO is at VPL, V BLO -V PLO = -VPL). The voltage (eg, compensation voltage) effectively generated across the parasitic capacitance 605o when PLO will be discharged to GND will be used to cancel the parasitic capacitance 605e when generating switching charge in a read operation on the even bit lines.

[0033] Next, the even and odd precharge transistors / switches are disabled (e.g., based on precharge enable signals PRECHE and PRECHO) to float the bit lines, and the reverse pulse control line (CNTPLSEN) is enabled to connect the two bit lines via the reverse pulse transistor / switch 670, while the read voltage (VPL) is applied to the plate line of the memory element being read (e.g., on the even side of the sense amplifier 620). At the same time, PLO is discharged from VPL to GND, providing a drop in charge through Cbl_pl_O, which is approximately the same as the parasitic charge on BLE caused by coupling PLE to BLE through Cbl_pl_E. This causes the memory element being read to generate a switching charge to the even bit line (BLE), which depends on the programming state of the memory element being read, offset by the compensation voltage provided via the reverse pulse transistor / switch 670. After generating the switching charge to the even bit line, the reverse pulse control line (CNTPLSEN) is disabled to disconnect the complementary bit line from the bit line being read. Next, the complementary bit line is discharged by selecting ground as the source via mux 680 and enabling the precharge transistor / switch on the complementary line (e.g., based on the corresponding precharge enable signal of the complementary side precharge transistor / switch of either PRECHE or PRECHO), and then the complementary bit line is precharged to VREF by selecting VREF as the source via mux 680. Now, the sense amplifier 620 can be enabled for reading by turning on the sense enable transistor / switch controlled by the sense enable (SE) signal.

[0034] This process Figure 7 6, which plots the voltages on various control lines and various nodes of sense amplifier 620 during the course of a read operation of a memory element connected to an even bit line, where the programmed state of the memory element being read on the even bit line is "1." Starting from the top of the page, the first segment plots the voltages on the word line (WL, plotted along line 702), the odd side plate line (PLO, plotted along line 704), the even side plate line (PLE, plotted along line 706), and the reverse pulse control line (CNTPLSEN, plotted along line 708). The next segment shows the voltage on the sense enable control signal (SE, plotted along line 712) that enables sense amplifier 620 when set to a logic high. The next segment plots the VREFEN reference select signal (along line 722), which connects VSSPRC to (e.g., via a selection circuit such as MUX 680, as shown in FIG. 6A ) when VREFEN is at a logic low. Figure 67) and connects VSSPRC to VREF when VREFEN is at a logic high. The next segment plots the PRECHO control signal (along line 732), which when at a logic high, connects the odd bit lines to VSSPRC and floats the odd bit lines when at a logic low. The next segment plots the PRECHE control signal (along line 742), which when at a logic high connects the even bit lines to VSSPRC and floats the even bit lines when at a logic low. The last segment plots the voltages on the even bit lines (BLE, along line 752) and the odd bit lines (BLE, along line 754).

[0035] refer to Figure 7 , a read operation begins by enabling the WL associated with the cell to be read during the read operation (see line 702). This causes the corresponding access transistor to connect one side of the memory element to the bit line. The precharge signals PRECHO, PRECHE (lines 732, 742) are also set high, and VREFEN is set low (to select ground as VSSPRC), which discharges both bit lines (BLO, BLE) to ground. The plate line of the complementary bit line (in this case the odd bit line PLO, at line 704) is driven to VPL, which applies a voltage of -VPL across the odd side parasitic capacitance 605o. Next, the precharge enable signals PRECHE and PRECHO are disabled to float the bit lines, and the reverse pulse control line (CNTPLSEN) is enabled to connect the even / odd bit line pairs together, while applying a read voltage (VPL) to the even plate line (PLE) of the memory element being read and discharging PLO to ground, where, at the same time, PLE is raised to VPL, as described above. This causes the memory element being read to generate a switching charge to the even bit line (BLE) that depends on the programming state of the memory element being read, offset by the reverse pulse voltage provided from the complementary side bit line. Next, the reverse pulse control line (CNTPLSEN) is disabled to disconnect the complementary bit line (BLO) from the bit line (BLE) being read. Thereafter, PRECHO is enabled on the odd side precharge transistor / switch to discharge the complementary bit line (BLO) to ground, and VREFEN is then pulsed high to set VREF to VSSPRC, thereby biasing BLO to VREF. Now, the sense amplifier 620 can be enabled for reading by setting the sense enable (SE) signal high.

[0036] Figure 8 8 shows an example of how sense amplifiers and control circuitry to provide compensation voltages may be connected to the odd and even side arrays of memory cells. In the middle is a sense amplifier 820 (e.g., Figure 4 The sense amplifier 420, Figure 5The sense amplifier 520, Figure 6 Sense amplifier 820 includes control circuitry including transistor / switch 870 and selection circuitry (e.g., mux 880) for precharging and connecting bit line pairs during read operations, as described above with respect to Figure 6 and Figure 7 as discussed. Each memory cell can include a memory element (e.g., a state-programmable capacitor (e.g., a ferroelectric capacitor)), wherein the memory elements of a given segment share a plate line (on one side of the memory element) common to all memory cells in the segment and a bit line (connectable to the other side of the memory element via an access transistor) common to all memory cells connected to a given sense amplifier (e.g., the first row of cells in an even segment is connected to the sense amplifier 820 via BLE, while the first row of cells in an odd segment is connected to the sense amplifier 820 via BLO) (the sense amplifier for the second row is not shown). Word lines (WL) can be connected to the gates of the access transistors (e.g., one word line per column) to select which column of the segment to read during a read operation (e.g., which cell will be read for each bit line in the segment). In Figure 8 In the example of FIG. 1 , the word line (WL*) marked with an asterisk has been activated to select this column for reading (highlighted in bold). Also shown are the parasitic capacitances (e.g., 805e, 805o) that effectively exist between the even bit line and the even plate line (805e between BLE and PLE) and between the odd bit line and the odd plate line (805o between BLO and PLO). As will be appreciated, each pair of even / odd bit lines (each row) can have its own sense amplifier and reverse pulse circuit (although Figure 8 8 and 9). As will also be appreciated, portions of the control circuitry may be global in the sense that components may be connected to and / or power multiple sense amplifiers. For example, mux 880 may be a global mux where VREFEN controls whether VREF or ground is associated with the VSSPRC of all sense amplifiers in a row (e.g., the group of sense amplifiers connected to the bit line pairs that make up the corresponding even / odd segments).

[0037] In this type of memory arrangement, control circuitry can provide a balance to the reduced switching charge (and therefore lower voltage) caused by capacitive coupling across the memory element between the plate line and the bit line during a read operation. Advantageously, no additional capacitors need to be added (e.g., to each individual bit line, which would be very space consuming), and the control circuitry can be provided by a single transistor / switch that selectively shorts the corresponding bit line pair (BLE to BLO), a separately controllable set of precharge transistors / switches (e.g., separate PRECHE / PRECHO signals), and a global multiplexer on the VSSPRC line.

[0038] By providing a compensation voltage to the bit line being read from the complementary bit line (from BLO to BLE and vice versa), a reduction in the read window can be avoided and the reliability of the sense amplifier can be improved. 9A to 9C Example shows, 9A to 9C Each of the figures plots the voltage (V BL ).exist Fig.9A The "ideal" case is shown in FIG. 9 , where there is a large read window 925A between the voltage produced in the "1" case (curve 910 ) and the voltage produced in the "0" case (curve 930 ). Fig. 9B 920). The parasitic capacitance reduces (as shown by arrow 915) the voltage developed to the bit line compared to the "ideal" case (curve 910). Therefore, the read window 925B is smaller than the read window 925A in the ideal case. Fig. 9C The voltage generated using the reverse pulse / compensation voltage technique described above is shown. The voltage generated to the bit line during the read of a "1" (V BL ) is plotted on curve 911, and the voltage generated to the bit line during the read of "0" is plotted on curve 931. It can be seen that the read window 925C remains large, similar to the ideal read window 925A, avoiding the reduction of the read window and improving the reliability of the sense amplifier. In addition, because both curves are reduced to lower voltage levels (e.g., for both the "0" and "1" cases), this means that the sense amplifier can operate at a lower common mode, which means that a lower voltage (and therefore more efficient) power supply can be used. In addition, even without considering the effects of parasitic capacitance, the lower voltage level means a larger difference across the state-programmable memory element during the read operation (e.g., a larger voltage V across the state-programmable memory element PL -V BL ), which can improve the reliability of read operations.

[0039] This benefit is also Fig.10 It is shown in Fig.10 The voltage generated to the bit line (V BL ) (during the reading of a "1"). The voltage generated across the memory element during reading a "1" (e.g., VPL-VBL) is also plotted for a sense amplifier without a reverse pulse / compensation voltage applied (plotted on curve 1040) and a sense amplifier with a reverse pulse / compensation voltage applied (plotted on curve 1030). It can be seen that the applied compensation voltage reduces the voltage generated to the bit line, and therefore, the voltage across the memory element is larger. This means that the read window can be kept large, thereby improving the reliability of the sense amplifier.

[0040] Fig.11 An exemplary schematic flow chart depicting a method 1100 for reading a programming state of a memory element. The method 1100 may implement any of the features and / or structures described above with respect to a sensing circuit and associated circuits for providing the programming state of a memory element. Figures 1 to 10 The compensation voltage described.

[0041] The method 1100 includes, at 1110, setting a bit line to which the memory element is connected to a first voltage. The method 1100 also includes, at 1120, generating a compensation voltage different from the first voltage to the bit line. The method 1100 also includes, at 1130, generating a modified sensing voltage to the bit line, the modified sensing voltage being defined by the compensation voltage and the sensing voltage generated from the memory element. The method 1100 also includes, at 1140, determining a programming state based on the modified sensing voltage.

[0042] In the following, various examples are provided that may include one or more aspects described above with reference to the sensing circuit and associated circuits described above for providing a compensation voltage. It is contemplated that aspects described with respect to the circuits may also be applied to the described methods, and vice versa.

[0043] Example 1 is a sensing circuit for sensing a programming state of a memory element, the sensing circuit comprising a first switch configured to apply a first voltage (e.g., a ground voltage) to a first terminal of the memory element (e.g., at a bit line). The sensing circuit further comprises a second switch configured to apply a compensation voltage (e.g., a non-ground voltage) different from the first voltage to the first terminal of the memory element, wherein the first terminal is configured to receive a sensing voltage defined by a switching voltage indicating a programming state of the memory element, the switching voltage being compensated by the compensation voltage. The sensing circuit further comprises a sensing amplifier connected to the first terminal of the memory element, wherein the sensing amplifier is configured to determine the programming state based on the sensing voltage.

[0044] Example 2 is the sensing circuit of Example 1, wherein the compensation voltage is configured to cancel parasitic capacitance across the memory element.

[0045] Example 3 is a sensing circuit as described in any one of Examples 1 to 2, wherein a programming state is associated with one of a first logic state at a first voltage and a second logic state at a second voltage, wherein the sensing circuit is configured to determine the programming state including: the sensing circuit is configured to provide a first voltage at a first terminal if the sensing voltage is higher than a threshold voltage, and to provide a second voltage at the first terminal if the sensing voltage is not higher than the threshold voltage.

[0046] Example 4 is the sensing circuit of any one of Examples 1 to 3, wherein the sensing amplifier includes a latch, wherein a first input of the latch is connected to a first terminal of a memory element, wherein a complementary input of the latch is connected to a second memory element.

[0047] Example 5 is the sensing circuit described in Example 4, wherein the second switch is configured to set the first terminal of the memory element to a compensation voltage, including: the second switch is configured to connect the complementary input of the latch to the first input of the latch, wherein the complementary input of the latch is configured to receive the compensation voltage from the second memory element.

[0048] Example 6 is a sensing circuit as described in any one of Examples 1 to 5, wherein the complementary input of the latch is configured to receive a compensation voltage from a second memory element, including: the second memory element is configured to receive a programming voltage at a first terminal (e.g., PL) of the second memory element, while the second terminal (e.g., BL) of the second memory element is connected to the complementary input of the latch.

[0049] Example 7 is a memory comprising a sense amplifier, a latch, and a control circuit. The sense amplifier comprises a readout node connected to a first memory element and a complementary node connected to a second memory element. The latch is connected between the sense node and the complementary node. The control circuit is configured to: apply a voltage to one side of the second memory element to charge the complementary node to a compensation voltage; and connect the complementary node to the sense node during a read operation of the first memory element, wherein during the read operation, the sense amplifier is configured to determine a programming state of the first memory element based on a sense voltage at the sense node, the sense voltage being defined by the compensation voltage and a switching voltage provided from the first memory element.

[0050] Example 8 is the memory of Example 7, wherein the control circuit includes a transistor that selectively connects the complementary node to the sensing node based on a reverse pulse enable signal.

[0051] Example 9 is the memory of any of Examples 7 to 8, wherein the control circuit includes a selection circuit that selectively connects one of the two voltages to the complementary node based on a reference selection signal and a complementary precharge enable signal.

[0052] Example 10 is the memory of Example 9, wherein the two voltages include a bias voltage (eg, VREF) and a ground voltage (eg, GND).

[0053] Example 11 is the memory of any of Examples 9 to 10, wherein the selection circuit is further configured to selectively connect one of the two voltages to the complementary node based on a reference selection signal and a sense precharge enable signal.

[0054] Example 12 is the memory of Example 11, wherein the complementary precharge enable signal is different from the sense precharge enable signal.

[0055] Example 13 is the memory of any of Examples 7 to 12, wherein a read operation includes a control circuit configured to apply a read voltage to a first terminal of a first memory element to deliver a switching voltage to a second terminal of the first memory element, wherein the second terminal is connected to a sensing node.

[0056] Example 14 is the memory of any of Examples 7 to 13, wherein the first memory element comprises a ferroelectric capacitor, wherein the programmed state comprises a remanent polarization state of the ferroelectric capacitor.

[0057] Example 15 is the memory of any of Examples 7 to 14, wherein the sensing node comprises a bit line of a first segment of memory cells of the memory, and wherein the complementary node comprises a bit line of a second segment of memory cells different from the first segment.

[0058] Example 16 is a method for reading a programming state of a memory element, the method comprising setting a bit line to which the memory element is connected to a first voltage. The method further comprises generating a compensation voltage different from the first voltage to the bit line. The method further comprises generating a modified sensing voltage to the bit line, the modified sensing voltage being defined by the compensation voltage and the sensing voltage generated from the memory element. The method further comprises determining a programming state based on the modified sensing voltage.

[0059] Example 17 is the method described in Example 16, wherein generating a compensation voltage to the bit line includes: discharging a complementary plate line connected to the second memory element to charge a complementary bit line connected to the second memory element; wherein generating a compensation voltage to the bit line also includes: connecting the bit line to the complementary bit line to generate a compensation voltage to the bit line.

[0060] Example 18 is the method of Example 17, wherein discharging the complementary plate line to charge the complementary bit line includes applying a compensation voltage pulse (eg, at a level equal to the read voltage) to the complementary plate line.

[0061] Example 19 is a method described in any one of Examples 16 to 18, wherein generating a modified sensing voltage to the bit line includes: charging a plate line to which the memory element is connected to a read voltage; and transmitting a sensing voltage from the memory element to the bit line, wherein the sensing voltage depends on a programming state of the memory element.

[0062] Example 20 is a method according to any one of Examples 16 to 19, wherein the first voltage is a ground voltage and the compensation voltage is a non-ground voltage.

[0063] The terms "at least one of..." and "one or more" may be understood to include any integer greater than or equal to 1, i.e., 1, 2, 3, 4, etc. The terms "plurality" or "several" may be understood to include any integer greater than or equal to 2, i.e., 2, 3, 4, 5, etc. The phrase "at least one of..." with respect to a group of elements may be used herein to mean at least one element from a group consisting of elements. For example, the phrase "at least one of..." with respect to a group of elements may be used herein to mean the following options: one of the listed elements, multiple instances of one of the listed elements, multiple individually listed elements, or multiple instances of multiple listed elements.

[0064] The term "connect" may be used herein with respect to nodes, terminals, integrated circuit elements, etc. to indicate an electrical connection, which may include a direct connection or an indirect connection, wherein an indirect connection may only include additional structures in the current path that do not affect the substantial functioning of the described circuit or device.

[0065] Although the present invention has been specifically shown and described with reference to specific aspects, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the appended claims. Therefore, the scope of the present invention is indicated by the appended claims, and it is therefore intended to cover all changes within the meaning and range of equivalents of the claims.

Claims

1. A sensing circuit for sensing a programming state of a memory element, the sensing circuit comprising: a first switch configured to apply a first voltage to a first terminal of the memory element; a second switch configured to apply a compensation voltage different from the first voltage to the first terminal of the memory element, wherein the first terminal is configured to receive a sensing voltage defined by a switching voltage indicative of the programming state of the memory element, the switching voltage being compensated by the compensation voltage; and A sense amplifier is connected to the first terminal of the memory element, wherein the sense amplifier is configured to determine the programming state based on the sense voltage.

2. The sensing circuit according to claim 1, wherein: The compensation voltage is configured to cancel parasitic capacitance across the memory element.

3. The sensing circuit according to claim 1, wherein: The programming state is associated with one of a first logic state at a first voltage and a second logic state at a second voltage, wherein the sensing circuit is configured to determine the programming state including: the sensing circuit is configured to provide the first voltage at the first terminal if the sensing voltage is higher than a threshold voltage, and to provide the second voltage at the first terminal if the sensing voltage is not higher than the threshold voltage.

4. The sensing circuit according to claim 1, wherein: The sense amplifier includes a latch, wherein a first input of the latch is connected to the first terminal of the memory element, wherein a complementary input of the latch is connected to a second memory element.

5. The sensing circuit according to claim 4, wherein: The second switch is configured to set the first terminal of the memory element to the compensation voltage includes: the second switch is configured to connect the complementary input of the latch to the first input of the latch, wherein the complementary input of the latch is configured to receive the compensation voltage from the second memory element.

6. The sensing circuit according to claim 1, wherein: The complementary input of the latch being configured to receive the compensation voltage from the second memory element includes the second memory element being configured to receive a programming voltage on a first terminal of the second memory element while a second terminal of the second memory element is connected to the complementary input of the latch.

7. A memory comprising: A sense amplifier, the sense amplifier comprising: a sensing node connected to a first memory element; a complementary node connected to a second memory element; and a latch connected between the sensing node and the complementary node; and A control circuit, wherein the control circuit is configured as follows: applying a voltage to one side of the second memory element to charge the complementary node to a compensation voltage; and The complementary node is connected to the sense node during a read operation on the first memory element, wherein, during the read operation, the sense amplifier is configured to determine a programming state of the first memory element based on a sense voltage at the sense node, the sense voltage being defined by the compensation voltage and a switching voltage provided from the first memory element.

8. The memory according to claim 7, wherein: The control circuit includes a transistor that selectively connects the complementary node to the sense node based on a reverse pulse enable signal.

9. The memory according to claim 7, wherein: The control circuit includes a selection circuit that selectively connects one of two voltages to the complementary node based on a reference selection signal and a complementary precharge enable signal.

10. The memory according to claim 9, wherein: The two voltages include a bias voltage and a ground voltage.

11. The memory according to claim 9, wherein: The selection circuit is further configured to selectively connect one of the two voltages to the complementary node based on the reference selection signal and a sense precharge enable signal.

12. The memory according to claim 11, wherein: The complementary precharge enable signal is different from the sense precharge enable signal.

13. The memory according to claim 7, wherein: The read operation includes the control circuit being configured to apply a read voltage to a first terminal of the first memory element to deliver the switching voltage to a second terminal of the first memory element, wherein the second terminal is connected to the sense node.

14. The memory according to claim 7, wherein: The first memory element comprises a ferroelectric capacitor, wherein the programmed state comprises a remnant polarization state of the ferroelectric capacitor.

15. The memory according to claim 7, wherein: The sensing node comprises a bit line of a first segment of memory cells of the memory, wherein the complementary node comprises a bit line of a second segment of memory cells different from the first segment.

16. A method for reading a programming state of a memory element, the method comprising: setting a bit line to which the memory element is connected to a first voltage; generating a compensation voltage different from the first voltage to the bit line; generating a modified sensing voltage to the bit line, the modified sensing voltage being defined by the compensation voltage and a sensing voltage generated from the memory element; as well as The programming state is determined based on the modified sensing voltage.

17. The method according to claim 16, wherein: Generating the compensation voltage to the bit line includes: discharging a complementary plate line connected to the second memory element to charge a complementary bit line connected to the second memory element; and The bit line is connected to the complementary bit line to generate the compensation voltage to the bit line.

18. The method according to claim 17, wherein: Discharging the complementary plate line to charge the complementary bit line includes applying a compensation voltage pulse to the complementary plate line.

19. The method according to claim 16, wherein: Generating the modified sensing voltage to the bit line includes: charging a plate line to which the memory element is connected to a read voltage; and A sensing voltage from the memory element is communicated to the bit line, wherein the sensing voltage is dependent on the programmed state of the memory element.

20. The method according to claim 16, wherein: The first voltage is a ground voltage, and the compensation voltage is a non-ground voltage.

Images