Memory system and memory device

Abstract

A memory system according to an embodiment of the present invention includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to determine the first voltage on the basis of information relating to the gradient of the threshold voltage distribution of each of the plurality of memory cells, and execute a tracking operation. In the tracking operation, the memory controller causes the memory device to execute a plurality of read operations using a plurality of read levels for the plurality of memory cells. The memory controller acquires the number of on-cells at each of a plurality of read-out operations. The memory controller sets a first voltage difference between a plurality of read levels in a voltage range lower than the first voltage and a second voltage difference between a plurality of read levels in a voltage range higher than the first voltage to be different from each other.

Description

Technical Field

[0001] Embodiments relate to a memory system and a memory device. Background Art

[0002] A NAND-type flash memory capable of storing data in a nonvolatile manner is known.

[0003] [Background Technology Literature]

[0004] [Patent Document]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2019-168813

[0006] [Patent Document 2] U.S. Patent Application Publication No. 2022 / 0100413

[0007] [Patent Document 3] U.S. Patent Application Publication No. 2022 / 0262450 Summary of the invention

[0008] [Problems to be solved by the invention]

[0009] At least one embodiment provides a memory system and a memory device with high reliability.

[0010] [Technical means to solve the problem]

[0011] A memory system of an embodiment includes a memory device and a memory controller. The memory device includes a plurality of memory cells configured to store data including at least a first value and a second value in a nonvolatile manner according to threshold voltages. The first value corresponds to a threshold voltage included in a first voltage range. The second value corresponds to a threshold voltage included in a second voltage range different from the first voltage range. The memory controller is configured to write data of a first value to each of a plurality of first memory cells among the plurality of memory cells, write data of a second value to each of a plurality of second memory cells among the plurality of memory cells, and determine the first voltage based on information related to the gradient of the threshold voltage distribution of each of the plurality of memory cells, and perform a tracking operation. The memory controller is configured to, in the tracking operation, cause the memory device to perform a plurality of read operations using a plurality of read levels within a third voltage range including at least a portion of the first voltage range and at least a portion of the second voltage range, and obtain the number of memory cells that are in an on state, that is, the number of on cells, among the plurality of memory cells in each of the plurality of read operations. The memory controller is also configured such that, in a tracking action, a first voltage difference between two adjacent read levels among a plurality of read levels within a fourth voltage range that is lower than the first voltage in the third voltage range and a second voltage difference between two adjacent read levels among a plurality of read levels within a fifth voltage range that is higher than the first voltage in the third voltage range are set to be different from each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a block diagram showing an example of the configuration of the memory system according to the first embodiment.

[0013] Figure 2 This is a block diagram showing an example of the hardware configuration of the memory controller included in the memory system according to the first embodiment.

[0014] Figure 3 This is a block diagram showing an example of the hardware configuration of a memory device included in the memory system according to the first embodiment.

[0015] Figure 4 This is a diagram showing an example of a circuit configuration of a memory cell array included in the memory system according to the first embodiment.

[0016] Figure 5 This is a diagram showing an example of a circuit configuration of a row decoder module included in the memory system according to the first embodiment.

[0017] Figure 6 This is a diagram showing an example of the circuit configuration of the sense amplifier module and the data register included in the memory system according to the first embodiment.

[0018] Figure 7This is a diagram showing an example of threshold voltage distribution and data allocation of memory cell transistors in the memory system according to the first embodiment.

[0019] Figure 8 This is a schematic diagram showing an example of a failure bit count generated in the adjacent state in the memory system according to the first embodiment.

[0020] Fig. 9 This is a schematic diagram showing an example of symmetrical threshold voltage distribution of adjacent states in the memory system according to the first embodiment.

[0021] Fig.10 This is a schematic diagram showing an example of asymmetric threshold voltage distribution of adjacent states in the memory system according to the first embodiment.

[0022] Fig.11 This is a schematic diagram showing an example of a more detailed threshold voltage distribution of the memory cell transistor according to the first embodiment.

[0023] Fig.12 This is a flowchart showing an example of a procedure of Vth tracking executed in the memory system according to the first embodiment.

[0024] Fig.13 This is a schematic diagram showing an example of a method of setting a step value used for Vth tracking executed in the memory system according to the first embodiment.

[0025] Fig.14 This is a schematic diagram showing another example of a method of setting a step value used for Vth tracking executed in the memory system of the first embodiment.

[0026] Fig.15 This is a block diagram showing an example of the functional configuration of the memory system according to the second embodiment.

[0027] Fig.16 This is a diagram showing an example of a start value table included in the memory system according to the second embodiment.

[0028] Fig.17 It is a diagram showing an example of a step value table included in the memory system according to the second embodiment.

[0029] Fig.18 This is a flowchart showing an example of a procedure of Vth tracking executed in the memory system according to the second embodiment.

[0030] Fig.19 This is a schematic diagram showing a specific example of a part of the processing of Vth tracking executed in the memory system according to the second embodiment.

[0031] Fig. 20This is a table showing an example of a command sequence used by the memory system of the second embodiment.

[0032] Fig.21 This is a flowchart showing an example of a procedure of a variation example of Vth tracking executed in the memory system according to the second embodiment.

[0033] Fig. 22 This is a block diagram showing an example of the functional configuration of the memory system according to the third embodiment.

[0034] Fig.23 This is a flowchart showing an example of a procedure for setting initial parameters of Vth tracking executed in the memory system according to the third embodiment.

[0035] Fig.24 This is a block diagram showing an example of the functional configuration of the memory system according to the fourth embodiment.

[0036] Fig.25 It is a diagram showing an example of a step value table included in the memory system according to the fourth embodiment.

[0037] Fig.26 This is a flowchart showing an example of a procedure of Vth tracking executed in the memory system according to the fourth embodiment.

[0038] Fig. 27 This is a flowchart showing an example of a detailed procedure of a part of the processing of Vth tracking executed in the memory system according to the fourth embodiment.

[0039] Fig.28 This is a flowchart showing an example of detailed procedures of another part of the processing of Vth tracking executed in the memory system according to the fourth embodiment.

[0040] Fig.29 This is a flowchart showing an example of detailed procedures of another part of the processing of Vth tracking executed in the memory system according to the fourth embodiment.

[0041] Fig.30 This is a table showing an example of a command sequence used by the memory system of the fourth embodiment.

[0042] Fig.31 This is a diagram showing a specific example of a voltage applied to a word line in the search read of the memory system according to the fourth embodiment.

[0043] Fig.32 This is a schematic diagram showing a specific example of a process for determining an optimum read level in a search read in the memory system according to the fourth embodiment. DETAILED DESCRIPTION

[0044] Hereinafter, each embodiment is described with reference to the accompanying drawings. Each embodiment illustrates an apparatus or method for embodying the technical idea of ​​the invention. The accompanying drawings are schematic or conceptual. The diagrams of the components are appropriately omitted. The same symbols are attached to the components having substantially the same function and structure. The numbers attached to the reference symbols are referenced by the same reference symbols and are used to distinguish similar elements from each other.

[0045] <1> First Embodiment

[0046] The first embodiment relates to a memory system MS using a NAND flash memory capable of storing data in a nonvolatile manner. The memory system MS of the first embodiment is configured to be able to perform Vth tracking in which a plurality of step sizes can be set different from each other. The details of the memory system MS of the first embodiment are described below.

[0047] <1-1>Composition

[0048] First, the configuration of the memory system MS according to the first embodiment will be described.

[0049] <1-1-1> Configuration of the memory system MS

[0050] Figure 1 1 is a block diagram showing an example of the configuration of the memory system MS according to the first embodiment. Figure 1 As shown, the memory system MS can be connected to an external host device HD (also referred to as a host). The host device HD is an electronic device such as a personal computer, a portable information terminal, or a server. The memory system MS is a storage device such as a memory card or an SSD (solid state drive). The memory system MS includes, for example, a memory controller 1 and at least one memory device 2.

[0051] The memory controller 1 is, for example, a semiconductor integrated circuit configured as a SoC (System On a Chip), an ASIC (Application Specific Integrated Circuit), or an FPGA (field-programmable gate array). The memory controller 1 has a function of managing and controlling the memory device 2. The memory controller 1 is configured to be connected to the host device HD via a host bus HB. The memory controller 1 is connected to the memory device 2 via a memory bus MB. The memory controller 1 can control the memory device 2 based on a request received from the host device HD. For example, the memory controller 1 can control the memory device 2 to perform a read operation, a write operation, an erase operation, etc.

[0052] The memory device 2 is a semiconductor memory device configured to store data in a non-volatile manner. The memory device 2 is, for example, a NAND flash memory. In a NAND flash memory, the unit of data read and write operations is called a page. The memory device 2 includes a plurality of memory cell transistors MT, a plurality of bit lines BL, and a plurality of word lines WL. For example, each memory cell transistor MT is associated with one bit line BL and one word line WL. A column address is assigned to each bit line BL. A page address is assigned to each word line WL.

[0053] Alternatively, the memory controller 1 and at least one memory device 2 may be configured as one semiconductor device.

[0054] <1-1-2> Hardware Configuration of Memory Controller 1

[0055] Figure 2 1 is a block diagram showing an example of the hardware configuration of the memory controller 1 included in the memory system MS according to the first embodiment. Figure 2 As shown, the memory controller 1 includes, for example, a host interface circuit (host I / F) 10, a memory interface circuit (memory I / F) 11, a CPU (Central Processing Unit) 12, an ECC (Error Correction Code) circuit 13, a ROM (Read only memory) 14, a RAM (Random access memory) 15, and a buffer memory 16. The host I / F 10, the memory I / F 11, the CPU 12, the ECC circuit 13, the ROM 14, the RAM 15, and the buffer memory 16 may be connected to an internal bus.

[0056] The host I / F 10 controls the communication according to the interface specification between the host device HD and the memory controller 1. The host I / F 10 is configured to be connected to the host device HD via a host bus HB. The host I / F 10 supports, for example, SATA (Serial Advanced Technology Attachment), SAS (Serial Attached SCSI), PCIe TM (PCI Express: Peripheral Component Interconnect Express), NVMe TM (Non-Volatile Memory Express TM: Non-Volatile Memory Fast Channel) and other interface specifications.

[0057] The memory I / F 11 controls communication in accordance with the interface standard between the memory controller 1 and the memory device 2. The memory I / F 11 is connected to the memory device 2 via a memory bus MB. The memory I / F 11 supports interface standards such as Toggle DDR (Double Data Rate) and ONFI (Open NAND Flash Interface).

[0058] The CPU 12 is a processor that controls the overall operation of the memory controller 1. The CPU 12 instructs the memory device 2 to write data via the memory I / F 11 in accordance with a write request received via the host I / F 10. The CPU 12 instructs the memory device 2 to read data via the memory I / F 11 in accordance with a read request received via the host I / F 10.

[0059] The ECC circuit 13 is a circuit that performs an ECC process. The ECC process includes encoding and decoding of data. The ECC circuit 13 encodes data written to the memory device 2 and decodes data read from the memory device 2.

[0060] ROM14 is a non-volatile memory. ROM14 stores programs such as firmware. ROM14 is, for example, an EEPROM. TM (Electrically Erasable Programmable Read-Only Memory) The CPU 12 executes firmware stored in the ROM 14 or the like to perform various processes.

[0061] The RAM 15 is a volatile memory. The RAM 15 is used as a work area of ​​the CPU 12. The RAM 15 is, for example, an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory).

[0062] The buffer memory 16 is, for example, a volatile memory. The buffer memory 16 temporarily stores data received via the host I / F 10 or data received via the memory I / F 11 . The buffer memory 16 is, for example, a DRAM or an SRAM. The buffer memory 16 may be mounted outside the memory controller 1 .

[0063] <1-1-3> Hardware Configuration of Memory Device 2

[0064] Figure 3 1 is a block diagram showing an example of the configuration of the memory device 2 included in the memory system MS according to the first embodiment. Figure 3 As shown, the memory device 2 includes, for example, a memory cell array 20, an input / output circuit 21, a logic controller 22, a register circuit 23, a sequencer 24, a ready / busy controller 25, a driver circuit 26, a row decoder module 27, a data register 28, and a sense amplifier module 29. Signals sent and received via the memory bus MB include, for example, input / output signals I / O0 to I / O7, control signals CEn, CLE, ALE, WEn, REn, and WPn, and a ready / busy signal RBn.

[0065] The memory cell array 20 is a collection of multiple memory cell transistors MT. The memory cell array 20 includes multiple blocks BLK0 to BLKn ("n" is an integer greater than 1). Block BLK is, for example, a unit for erasing data. A block address is assigned to each block BLK. In the memory cell array 20, multiple bit lines BL0 to BLm ("m" is an integer greater than 1) and multiple word lines WL (not shown) are set.

[0066] The input / output circuit 21 controls the transmission and reception (input and output) of input / output signals I / O0 to I / O7. The input / output signal I / O can include, for example, data DAT, status information, address, and instruction. The input / output circuit 21 can input and output data DAT between the data register 28 and the memory controller 1. The input / output circuit 21 can output the status information transmitted from the register circuit 23 to the memory controller 1. The input / output circuit 21 can output the address and instruction transmitted from the memory controller 1 to the register circuit 23.

[0067] The logic controller 22 controls each of the input / output circuit 21 and the sequencer 24 based on the control signals input from the memory controller 1. The logic controller 22 starts the memory device 2 based on the control signal CEn. The logic controller 22 notifies the input / output circuit 21 that the input / output signal I / O received by the memory device 2 is a command and an address, respectively, based on the control signals CLE and ALE. The logic controller 22 instructs the input / output circuit 21 to receive the input / output signal I / O based on the control signal WEn, and instructs the input / output circuit 21 to send the input / output signal I / O based on the control signal REn. The logic controller 22 sets the memory device 2 to a protection state based on the control signal WPn.

[0068] The register circuit 23 temporarily stores status information, addresses, and instructions. The status information indicates the operating state of the memory device 2. The status information is updated based on the control of the sequencer 24 and transmitted to the memory controller 1 via the input / output circuit 21. The address can include a block address, a page address, a column address, etc. The instruction includes commands related to various operations of the memory device 2.

[0069] The sequencer 24 is a controller that controls the overall operation of the memory device 2. The sequencer 24 executes a read operation, a write operation, an erase operation, and the like based on the command and address stored in the register circuit 23.

[0070] The ready busy controller 25 generates a ready busy signal RBn based on the control of the sequencer 24. The ready busy signal RBn is a signal that notifies the memory controller 1 whether the memory device 2 is in a ready state or a busy state. The ready state is a state in which the memory device 2 can accept commands from the memory controller 1, and is notified by the ready busy signal RBn of a high level. The busy state is a state in which the memory device 2 cannot accept commands from the memory controller 1, and is notified by the ready busy signal RBn of a low level.

[0071] The driver circuit 26 generates voltages used in a read operation, a write operation, an erase operation, etc. The driver circuit 26 supplies the generated voltages to the row decoder block 27 or the sense amplifier block 29 .

[0072] The row decoder module 27 is a circuit for selecting a block BLK or supplying a voltage to wirings such as a word line WL. The row decoder module 27 includes a plurality of row decoders RD0 to RDn. The row decoders RD0 to RDn are associated with blocks BLK0 to BLKn, respectively. Each row decoder RD can set the associated block BLK to selected or unselected based on the block address.

[0073] The data register 28 is a circuit for temporarily storing data DAT. The data register 28 can be used to input and output data DAT between the input / output circuit 21 and the sense amplifier module 29. The data register 28 is also called a data latch, a page register, or a cache memory.

[0074] The sense amplifier module 29 is a circuit for supplying voltage to each bit line BL or reading data. The sense amplifier module 29 includes a plurality of sense amplifier units SAU0 to SAUm. The sense amplifier units SAU0 to SAUm are associated with a plurality of bit lines BL0 to BLm, respectively. Each sense amplifier unit SAU can determine the data read from the selected memory cell transistor MT based on the voltage of the associated bit line BL.

[0075] In addition, for example, a group of the memory cell array 20, the row decoder module 27, and the sense amplifier module 29 is also called a plane. The memory device 2 may include a plurality of planes. The sequencer 24 may be configured to control each of the plurality of planes.

[0076] Hereinafter, an example of a detailed circuit configuration of the memory cell array 20 , the row decoder module 27 , the data register 28 , and the sense amplifier module 29 will be described.

[0077] (1: Circuit Configuration of Memory Cell Array 20)

[0078] Figure 4 It is a diagram showing an example of the circuit configuration of the memory cell array 20 according to the first embodiment. Figure 4 FIG. 2 shows one of the plurality of blocks BLK included in the memory cell array 20. Figure 4 As shown, a plurality of bit lines BL0 to BLm, a plurality of word lines WL0 to WL7, selection gate lines SGD0 to SGD4, selection gate lines SGS, and source lines SL are provided in a block BLK. The selection gate lines SGD0 to SGD4 and SGS and the word lines WL0 to WL7 are provided for each block BLK. The bit lines BL0 to BLm are shared by a plurality of blocks BLK. The source line SL may be shared by a plurality of blocks BLK or provided for each block BLK.

[0079] Block BLK includes, for example, 5 string units SU0 to SU4. Each string unit SU includes multiple NAND strings NS. Multiple NAND strings NS are associated with bit lines BL0 to BLm, respectively. In other words, each bit line BL is shared by NAND strings NS assigned the same column address among multiple blocks BLK. Each NAND string NS is connected between the associated bit line BL and the source line SL.

[0080] Each NAND string NS includes, for example, memory cell transistors MT0 to MT7 and selection transistors STD and STS. Each memory cell transistor MT is a memory cell having a control gate and a charge storage layer, and stores (stores) data in a non-volatile manner. The threshold voltage of the memory cell transistor MT can be changed based on the amount of charge injected into the charge storage layer, etc. The memory cell transistor MT stores data corresponding to the threshold voltage. The selection transistors STD and STS are each used to select the string unit SU.

[0081] In each NAND string NS, the selection transistor STD, the memory cell transistors MT7 to MT0, and the selection transistor STS are connected in series in the order described. Specifically, the drain of the selection transistor STD is connected to the associated bit line BL. The source of the selection transistor STD is connected to the drain of the memory cell transistor MT7. The drain of the selection transistor STS is connected to the source of the memory cell transistor MT0. The source of the selection transistor STS is connected to the source line SL. The memory cell transistors MT0 to MT7 are connected in series between the selection transistors STD and STS.

[0082] The selection gate lines SGD0 to SGD4 are associated with the string units SU0 to SU4, respectively. Each selection gate line SGD is connected to the gate of each of the multiple selection transistors STD included in the associated string unit SU. The selection gate line SGS is connected to the gate of each of the multiple selection transistors STS included in the associated block BLK. The word lines WL0 to WL7 are connected to the gates of each of the multiple memory cell transistors MT0 to MT7 included in the associated block BLK.

[0083] In this specification, a set of multiple memory cell transistors MT commonly connected to a word line WL in one string unit SU is referred to as a unit group CU. In this specification, a set of 1-bit data stored in each of the multiple memory cell transistors MT included in the unit group CU is referred to as page data. The unit group CU can store more than 2 pages of data according to the number of bits of data stored in each memory cell transistor MT.

[0084] In addition, the memory cell array 20 may have a circuit configuration other than that described above. For example, the number of string units SU included in each block BLK or the number of memory cell transistors MT and selection transistors STD and STS included in each NAND string NS may be designed to be any number.

[0085] (2: Circuit Configuration of Row Decoder Module 27)

[0086] Figure 5 This is a diagram showing an example of the circuit configuration of the row decoder module 27 according to the first embodiment. Figure 5 The connection relationship between the driver circuit 26 and each of the memory cell array 20 and the row decoder module 27 and the detailed circuit structure of one row decoder RD0 are shown. In addition, the circuit structure of the row decoder RD other than the row decoder RD0 is similar to that of the row decoder RD0. Figure 5As shown, each row decoder RD is connected to signal lines CG0 to CG7, SGDD0 to SGDD4, SGSD, USGD, and USGS connected to the driver circuit 26. In addition, each row decoder RD is connected to word lines WL0 to WL7 and select gate lines SGD0 to SGD4 and SGS of the associated block BLK.

[0087] The row decoder RD0 includes, for example, transistors TR0 to TR19, transmission gate lines TG and bTG, and a block decoder BD. Each of the transistors TR0 to TR19 is an N-type high withstand voltage transistor. The transmission gate line TG is connected to each gate of the transistors TR0 to TR13. The transmission gate line bTG is connected to each gate of the transistors TR14 to TR19. The drains of each of the transistors TR0 to TR13 are connected to the signal lines SGSD, CG0 to CG7, and SGDD0 to SGDD4, respectively. The sources of each of the transistors TR0 to TR13 are connected to the selection gate line SGS of the block BLK0, the word lines WL0 to WL7, and the selection gate lines SGD0 to SGD4, respectively. The drain and source of the transistor TR14 are connected to the signal line USGS and the selection gate line SGS of the block BLK0, respectively. The drains of each of the transistors TR15 to TR19 are connected to the signal line USGD. The sources of each of the transistors TR15 to TR19 are connected to the selection gate lines SGD0 to SGD4 of the block BLK0, respectively.

[0088] The block decoder BD is a circuit that decodes the block address. Based on the decoding result of the block address, the block decoder BD applies one of the high and low voltages to the transmission gate line TG, and applies the other of the high and low voltages to the transmission gate line bTG. Specifically, the block decoder BD of the selected block BLK applies a high voltage to the transmission gate line TG, and a low voltage to the transmission gate line bTG. The block decoder BD of the unselected block BLK applies a low voltage to the transmission gate line TG, and a high voltage to the transmission gate line bTG. As a result, the voltages of the signal lines CG0 to CG7 are respectively applied to the word lines WL0 to WL7 of the selected block BLK, the voltages of the signal lines SGDD0 to SGDD4 and SGSD are respectively applied to the selection gate lines SGD0 to SGD4 and SGS of the selected block BLK, and the voltages of the signal lines USGD and USGS are respectively applied to the selection gate lines SGD and SGS of the unselected block BLK.

[0089] In addition, the row decoder module 27 may also have a circuit configuration other than that described above. For example, the number of transistors TR included in the row decoder module 27 can be appropriately changed according to the number of wirings of each block BLK. Since the signal line CG is shared by multiple blocks BLK, it is also called a global word line. Since the word line WL is set for each block, it is also called a local word line. Since the signal lines SGDD and SGSD are each shared by multiple blocks BLK, they are also called global transfer gate lines. Since the selection gate lines SGD and SGS are each set for each block, they are also called local transfer gate lines.

[0090] (3: Circuit Configuration of Sense Amplifier Module 29 and Data Register 28)

[0091] Figure 6 FIG. 2 is a diagram showing an example of the circuit configuration of the sense amplifier module 29 and the data register 28 according to the first embodiment. Figure 6 As shown, each sense amplifier unit SAU includes, for example, a bit line connection unit BLHU, a sense amplifier unit SA, buses DBUS and LBUS, latch circuits SDL, ADL, BDL and CDL, and a transistor T0. The data register 28 includes a plurality of latch circuits XDL0 to XDLm. The latch circuits XDL0 to XDLm are associated with the sense amplifier units SAU0 to SAUm, respectively. Each of the latch circuits XDL0 to XDLm is connected to the associated sense amplifier unit SAU via the bus DBUS.

[0092] The bit line connection part BLHU is a protection circuit for preventing a high voltage applied to a channel of the NAND string NS from being applied to the sense amplifier part SA during an erase operation, for example. The bit line connection part BLHU may be configured to be able to apply a predetermined voltage to the non-selected bit line BL.

[0093] The sense amplifier unit SA is a circuit for determining data based on the voltage of the bit line BL or applying a voltage to the bit line BL. Each sense amplifier unit SA is connected to the associated bit line BL via the bit line connection unit BLHU. When the control signal STB is asserted during the read operation, the sense amplifier unit SA determines whether the data read from the selected memory cell transistor MT is "0" data or "1" data based on the voltage of the associated bit line BL. For example, the control signal STB is generated by the sequencer 24.

[0094] Each of the latch circuits SDL, ADL, BDL, and CDL can temporarily store data. The latch circuits SDL, ADL, BDL, and CDL and the sense amplifier unit SA are configured to be able to transmit and receive data via the bus LBUS.

[0095] The transistor T0 of each sense amplifier unit SAU controls the signal transmission between the associated buses DBUS and LBUS. One end of the transistor T0 of each sense amplifier unit SAU is connected to the associated bus DBUS. The other end of the transistor T0 of each sense amplifier unit SAU is connected to the associated bus LBUS. A control signal DSW is input to the gate of the transistor T0 of each sense amplifier unit SAU. For example, the control signal DSW is generated by the sequencer 24.

[0096] Each latch circuit XDL can temporarily store data. Each latch circuit XDL is configured to be able to send and receive data with the associated sense amplifier unit SAU via the bus DBUS. Each latch circuit XDL is used to input and output data DAT between the sense amplifier module 29 and the input / output circuit 21. Each latch circuit XDL can be shared by multiple sense amplifier units SAU.

[0097] In addition, the sense amplifier module 29 may have a circuit configuration other than the above. For example, the number of latch circuits included in each sense amplifier unit SAU may be changed as appropriate. The sense amplifier unit SAU may also have an operation circuit capable of performing a logical operation.

[0098] <1-1-4> Threshold voltage distribution of memory cell transistor MT

[0099] Figure 7 1 is a diagram showing an example of the threshold voltage distribution and data allocation of the memory cell transistors MT in the memory system MS of the first embodiment. The vertical axis "NMTs" represents the number of memory cell transistors MT. The horizontal axis "Vth" represents the threshold voltage of the memory cell transistor MT. Figure 7 As shown, when each memory cell transistor MT stores 3 bits of data, the threshold voltage distribution of the plurality of memory cell transistors MT forms 8 states. In this specification, these 8 states are referred to as S0 state, S1 state, S2 state, S3 state, S4 state, S5 state, S6 state, and S7 state in the order of threshold voltage from low to high. Different 3-bit data is assigned to each memory cell transistor MT belonging to the S0 state to the S7 state. In addition, each memory cell transistor MT can store 1 bit, 2 bits, or more than 4 bits of data, and can also be assigned data different from the following description.

[0100] The following is an example of data allocation for the memory cell transistors MT belonging to 8 states. In addition, the 3-bit data stored in each memory cell transistor MT is also referred to as upper bit data, middle bit data, and lower bit data. In addition, one page of data consisting of the upper bit data, middle bit data, and lower bit data stored in each of the plurality of memory cell transistors MT included in each unit group CU is also referred to as upper page data, middle page data, and lower page data, respectively.

[0101] S0 state: "111" data

[0102] S1 status: "110" data

[0103] S2 state: "100" data

[0104] S3 status: "000" data

[0105] S4 status: "010" data

[0106] S5 status: "011" data

[0107] S6 status: "001" data

[0108] S7 status: "101" data

[0109] The read voltage and verification voltage are set for each adjacent state. Specifically, the read voltage R1 is set between the S0 state and the S1 state. Similarly, the read voltages R2 to R7 are set between the S1 state to the S6 state and the S2 state to the S7 state. The read voltage is also called the read level. The verification voltages V1 to V7 are set to correspond to the S1 state to the S7 state, respectively. In addition, the read path voltage VREAD is set to a voltage higher than the state with the highest threshold voltage (S7 state).

[0110] The read voltage is applied to the word line WL selected as the object of the read operation. If the memory cell transistor MT included in the unit group CU of the object of the read operation in the selected word line WL has a threshold voltage lower than the applied read voltage, it becomes turned on. The read path voltage VREAD is applied to the non-selected word line WL. The memory cell transistor MT connected to the word line WL to which the read path voltage VREAD is applied becomes turned on regardless of the stored data.

[0111] In Application Figure 7In the case of the data allocation shown, the lower page data is determined by the read operation using the read voltages R1 and R5. The middle page data is determined by the read operation using the read voltages R2, R4, and R6. The upper page data is determined by the read operation using the read voltages R3 and R7. In the read operation of the page data using the plurality of read voltages, the operation processing is appropriately performed in the sense amplifier unit SAU.

[0112] <1-2>Action

[0113] Next, the operation of the memory system MS according to the first embodiment will be described.

[0114] <1-2-1> Overview of Vth Tracking

[0115] First, the outline of Vth tracking is explained. Vth tracking is the operation of exploring the valley position of the threshold voltage distribution of two adjacent states (hereinafter referred to as adjacent states) and estimating the optimal read level. The optimal read level is the value of the read level with the minimum number of error bits (faulty bits) when performing the read operation. Vth tracking is also called tracking operation.

[0116] For example, in Vth tracking, first, multiple shift reads are performed according to the setting of the preset read level. Each shift read is a read action that specifies the shift amount of the read voltage relative to the start read level. For example, the shift amount is specified by a DAC (Digital Analog Converter) value. In the multiple shift reads in Vth tracking, multiple read levels set at equal intervals can be used respectively. Moreover, the number of memory cell transistors MT that are turned on in each read level (also referred to as the number of turned-on cells) is counted, and the difference in the number of turned-on cells under two adjacent read levels is calculated. Then, the point where the curve of the difference in the number of turned-on cells is determined to bulge downward is the point where the difference in the number of turned-on cells is minimal. Subsequently, the ratio of the two differences adjacent to the minimum point is calculated. In addition, the voltage difference (potential difference) of the two read levels adjacent to the minimum point is divided internally by the calculated ratio. The voltage obtained in this way is estimated to be the optimal read level.

[0117] In the following, two adjacent read levels among the multiple read levels used in the multiple shift reads performed in Vth tracking are also referred to as adjacent read levels. The voltage difference (potential difference) between the adjacent read levels is also referred to as the step length. The value of the step length is also referred to as the step length value. As with the shift amount, the step length value can be specified by the DAC value.

[0118] Figure 8 This is a schematic diagram showing an example of a failure bit count (error bit count) generated in the adjacent state in the memory system MS according to the first embodiment. Figure 8The threshold voltage distribution of adjacent states is shown. In this example, each memory cell transistor MT is configured to store 1-bit data. In this example, adjacent states are associated with "1" data and "0" data in order of threshold voltage from low to high.

[0119] The threshold voltage of the memory cell transistor MT may change due to interference or other reasons. For example, the distribution width of the threshold voltage of each state may expand, or the mode value of the threshold voltage distribution of each state may change. As a result, Figure 8 As shown, there is a case where adjacent states overlap. In the case where adjacent states overlap, there are storage cell transistors MT where "1" data is mistakenly determined as "0" data, and storage cell transistors MT where "0" data is mistakenly determined as "1" data. In this example, the number of storage cell transistors MT where "0" data is mistakenly determined as "1" data is represented as the number of failed bits FBC1. In addition, the number of storage cell transistors MT where "1" data is mistakenly determined as "0" data is represented as the number of failed bits FBC2.

[0120] exist Figure 8 In FIG. 1 , RTRK corresponds to the optimal read level estimated by Vth tracking. RBST corresponds to the actual optimal read level. RBST corresponds to the intersection of adjacent states.

[0121] When "FBC1+FBC2" exceeds the number of bits that can be corrected for errors, the ECC circuit 13 cannot correctly correct the data. Therefore, "FBC1+FBC2" is preferably as small as possible. "FBC1+FBC2" becomes minimum when performing a read operation of the actual optimal read level (RBST). On the other hand, the optimal read level (RTRK) estimated by Vth tracking may become a value different from RBST depending on the shape of the adjacent state. Figure 8 In the above, the difference between "FBC1+FBC2" generated in the read operation using RBST and "FBC1+FBC2" generated in the read operation using RTRK different from RBST is expressed as the number of fault bits FBC3. In the threshold voltage distribution of adjacent states, the number of fault bits FBC3 corresponds to the difference between the area corresponding to "FBC1+FBC2" generated in the read operation using RBST and the area corresponding to "FBC1+FBC2" generated in the read operation using RTRK. The number of fault bits FBC3 can be reduced by making RTRK close to RBST.

[0122] Fig. 9 is a schematic diagram showing an example of a symmetrical threshold voltage distribution of adjacent states. Fig. 9As shown in FIG. 1 , when the S(L-1) state and the S(L) state (L is an integer greater than 1) are roughly symmetrical, the optimal read level can be estimated by the minimum value of the quadratic function of the graph based on the difference in the number of on-cells of multiple adjacent read levels obtained by Vth tracking. In other words, when the adjacent states are symmetrical, the optimal read level (RTRK) estimated by Vth tracking is substantially consistent with the actual optimal read level (RBST).

[0123] Fig.10 is a schematic diagram showing an example of asymmetric threshold voltage distribution of adjacent states. Fig.10 As shown in FIG. 1 , when the S(L-1) state and the S(L) state are asymmetric, the optimal read level cannot be estimated with high accuracy at the minimum value of the quadratic function of the graph of the difference in the number of on-cells of a plurality of adjacent read levels obtained by Vth tracking. In other words, when the adjacent states are asymmetric, the optimal read level (RTRK) estimated by Vth tracking is offset to the positive side or the negative side relative to the actual optimal read level (RBST).

[0124] Fig.11 1 is a schematic diagram showing an example of a more detailed threshold voltage distribution of the memory cell transistor MT. Fig.11 As shown, in this example, the S0 state and the S7 state located at the two ends have a wider shape than the other states. Therefore, the asymmetry of the adjacent S0 state and S1 state group and the adjacent S6 state and S7 state group becomes obvious. In addition, the adjacent S(L-1) state and S(L) state group are referred to as S(L-1)-S(L) state below.

[0125] Fig.11 (1) in FIG. 1 shows the vicinity of the valley position of the S0-S1 state in an amplified manner. Hereinafter, the ratio of the change in threshold voltage to the change in the number of memory cell transistors MT having the threshold voltage is also referred to as the gradient of threshold voltage distribution or simply as gradient. Fig.11 (1) in the figure indicates that the gradient on the S0 state side is gentler than the gradient on the S1 state side. In this case, when Vth tracking using multiple read levels set at equal intervals is performed for the S0-S1 state, the optimal read level (RTRK) estimated by Vth tracking may deviate from the actual optimal read level (RBST).

[0126] Fig.11 (2) in the figure is an enlarged view showing the vicinity of the valley position of the S6-S7 state. Fig.11(2) in the figure indicates that the gradient on the S7 state side is gentler than that on the S6 state side. In this case, when Vth tracking using multiple read levels set at equal intervals is performed for the S6-S7 state, the optimal read level (RTRK) estimated by Vth tracking may deviate from the actual optimal read level (RBST).

[0127] The optimal read level (RTRK) estimated by Vth tracking may shift to the state side with a gentler gradient (the high potential side in the case of the S6-S7 state). In addition, the estimated optimal read level (RTRK) may shift to the state side with a steeper gradient (the low potential side in the case of the S6-S7 state) depending on the method of estimation.

[0128] In addition, in this example, other adjacent states are formed to be roughly symmetrical. In this case, in each of the S1-S2 state, the S2-S3 state, the S3-S4 state, and the S5-S6 state, the optimal read level (RTRK) estimated by Vth tracking may be substantially consistent with the actual optimal read level (RBST).

[0129] In addition, the closer the state is to the two ends of the threshold voltage distribution, the greater the asymmetry of the adjacent states. Therefore, in the S1-S2 state or the S5-S6 state, it is believed that the optimal read level (RTRK) estimated by Vth tracking deviates from the actual optimal read level (RBST). In this way, the adjacent states that produce asymmetry are not limited to the adjacent states at the two ends of the threshold voltage distribution. The tendency to produce asymmetry in adjacent states is also the same when each memory cell transistor MT stores 2 bits of data or 4 bits or more of data.

[0130] In Vth tracking, it is preferable to be able to estimate the optimal read level with high accuracy in consideration of the asymmetry of adjacent states as described above. Therefore, the Vth tracking performed in the memory system MS of the first embodiment has a function of estimating the optimal read level with high accuracy in consideration of the gradient of the threshold voltage distribution as shown below.

[0131] <1-2-2> Vth tracking considering the asymmetry of adjacent states

[0132] Fig.12 This is a flowchart showing an example of a procedure of Vth tracking executed in the memory system MS according to the first embodiment.

[0133] For example, when the error correction of the data read from the memory device 2 fails during the reading operation, or based on a predetermined schedule, the memory system MS starts Fig.12 The series of processes shown (start).

[0134] First, the memory controller 1 selects a Vth tracking parameter based on information associated with the gradient of the threshold voltage distribution of the memory cell transistor MT (ST101). The information associated with the gradient of the threshold voltage distribution of the memory cell transistor MT is, for example, the type of adjacent state, the address of the unit group CU, or information related to the optimal read level of the adjacent state obtained by Vth tracking performed in advance. The gradient tendency of the threshold voltage distribution of the memory cell transistor MT may also change according to the address of the unit group CU (that is, the position of the memory cell transistor MT in the block BLK).

[0135] The Vth tracking parameters (also referred to as search read parameters) include settings related to the read levels (start read levels and step values) used in the multiple shift reads performed in the Vth tracking, or the number of shift reads performed in the Vth tracking (also referred to as the number of search times). The start read level is the read level used in the first shift read among the multiple shift reads. In the Vth tracking of the first embodiment, multiple step values ​​that are different from each other can be used.

[0136] Next, the memory controller 1 performs multiple shift reads according to the selected parameters (ST102). In the process of step ST102, for example, the memory controller 1 sends a parameter setting instruction for the read operation and an execution instruction for the read operation to the memory device 2 each time the multiple shift reads are performed. The parameter setting instruction includes information on the read level used for the shift read. Then, the memory controller 1 obtains the read result from the memory device 2 for each shift read.

[0137] Next, the memory controller 1 calculates the number of cells turned on in each of the multiple shift reads (ST103). For example, the memory controller 1 counts the number of memory cell transistors MT that are turned on based on the read result. In addition, if the memory device 2 has a counter, the memory device 2 may count the number of cells turned on based on the result of the shift read and send the count result to the memory controller 1.

[0138] Next, the memory controller 1 calculates the difference in the number of ON cells for each group of two shift reads using adjacent read levels, based on the results of the multiple shift reads (ST104).

[0139] Next, the memory controller 1 estimates the optimum read level based on the calculated data (graph) of the difference in the number of ON cells (ST105). For example, the method described in "<1-2-1> Overview of Vth Tracking" is used to estimate the optimum read level.

[0140] When the processing of step ST105 is completed, the memory controller 1 ends Fig.12The series of processing shown is completed (end). The memory controller 1 can perform a read operation using the estimated optimum read level after Vth tracking.

[0141] <1-2-3> Specific example of step value set in asymmetric adjacent states

[0142] A specific example of the step value used for Vth tracking of asymmetric adjacent states will be described below. Also, a case where five shift reads are performed in Vth tracking will be described below.

[0143] (1: For the case of S0-S1 status)

[0144] Fig.13 FIG. 1 is a schematic diagram showing an example of a method for setting a step value used for Vth tracking for the S0-S1 state executed in the memory system MS according to the first embodiment. Fig.13 As shown, in Vth tracking for the S0-S1 state, for example, step values ​​SS1, SS2, and SS3 are used. Step value SS1 is greater than step value SS2. Step value SS2 is greater than step value SS3. Then, in Vth tracking for the S0-S1 state, SS1, SS2, SS2, and SS3 are applied as step values ​​of four sets of adjacent read levels in the order from low to high read levels.

[0145] When the gradient on the S0 state side is gentler than the gradient on the S1 state side, in the Vth tracking with the S0-S1 state as the target, at least the step value set on the S0 state side may be set larger than the step value set on the S1 state side. Thus, the change in the number of on-cells can be detected with low resolution in the voltage range on the S0 state side where the gradient is gentler, and the change in the number of on-cells can be detected with high resolution in the voltage range on the S1 state side where the gradient is steeper.

[0146] Thus, the memory system MS of the first embodiment can improve the estimation accuracy of the optimal read level based on the curve (e.g., quadratic function) of the difference in the number of on-cells of a plurality of adjacent read levels obtained by Vth tracking. That is, the memory system MS can make the optimal read level RTRK estimated by Vth tracking for the S0-S1 state closer to the actual optimal read level RBST than the optimal read level RTRK(ref) estimated by Vth tracking using one step value.

[0147] (2: For the case of S6-S7 status)

[0148] Fig.14FIG. 1 is a schematic diagram showing an example of a method for setting a step value used for Vth tracking for the S6-S7 state in the memory system MS according to the first embodiment. Fig.14 As shown in FIG. 1 , in Vth tracking for the S6-S7 state, for example, the same step values ​​SS1, SS2, and SS3 as those for Vth tracking for the S0-S1 state are used. Then, in Vth tracking for the S6-S7 state, SS3, SS2, SS2, and SS1 are applied as the step values ​​of four sets of adjacent read levels in the order from low to high read levels.

[0149] When the gradient on the S7 state side is gentler than the gradient on the S6 state side, in the Vth tracking with the S6-S7 state as the target, at least the step value set on the S7 state side may be set larger than the step value set on the S6 state side. Thus, the change in the number of on-cells can be detected with low resolution in the voltage range on the S7 state side with a gentler gradient, and the change in the number of on-cells can be detected with high resolution in the voltage range on the S6 state side with a steeper gradient.

[0150] Thus, the memory system MS of the first embodiment can improve the estimation accuracy of the optimal read level based on the curve (e.g., quadratic function) of the difference in the number of on-cells of a plurality of adjacent read levels obtained by Vth tracking. That is, the memory system MS can make the optimal read level RTRK estimated by Vth tracking for the S6-S7 state closer to the actual optimal read level RBST than the optimal read level RTRK(ref) estimated by Vth tracking using one step value.

[0151] <1-3> Effects of the First Embodiment

[0152] As described above, the memory system MS of the first embodiment can unequally set the step value of the read level used in the multiple shift reads in the Vth tracking. In other words, for Vth tracking, the memory system MS uses at least two different step values ​​associated with asymmetric adjacent states. In addition, the memory system MS uses an algorithm that explores the voltage range where the gradient of the threshold voltage distribution changes sharply with high resolution (that is, making the step value relatively small) and explores the voltage range where the gradient of the threshold voltage distribution changes slowly with low resolution (that is, making the step value relatively large).

[0153] The memory system MS of the first embodiment can shift the axis of the quadratic curve that is the approximate curve by setting the step value corresponding to the gradient of the threshold voltage distribution in Vth tracking. As a result, the memory system MS of the first embodiment can suppress the optimal read level estimated by Vth tracking from shifting (displacing) to the positive side or negative side relative to the actual optimal read level. In other words, the memory system MS of the first embodiment can make the estimated optimal read level close to the actual optimal read level.

[0154] Furthermore, the memory system MS of the first embodiment can reduce the number of error bits (failure bits) by using the optimal read level estimated by Vth tracking using unequal step values ​​in the read operation targeting asymmetric adjacent states. Therefore, the memory system MS of the first embodiment can obtain high reliability.

[0155] In addition, the number of shift reads performed by the Vth tracking described in the first embodiment is the same when using multiple different step values ​​as when using one step value. That is, the memory system MS of the first embodiment can improve the accuracy of Vth tracking without extending the processing time of Vth tracking.

[0156] <2> Second Embodiment

[0157] The memory system MS of the second embodiment is configured to perform Vth tracking similar to the first embodiment and further have a function of estimating the gradient of the threshold voltage distribution of the memory cell transistor MT. The details of the memory system MS of the second embodiment will be described below, mainly focusing on the differences from the first embodiment.

[0158] <2-1>Composition

[0159] First, the configuration of the memory system MS of the second embodiment is described. The hardware configuration of the memory system MS of the second embodiment is the same as that of the first embodiment. Hereinafter, the functional configuration of the memory system MS of the second embodiment is described. In addition, the memory device 2 is described below as including a core circuit 210 and a peripheral circuit 220. The core circuit 210 corresponds to the memory cell array 20, the row decoder module 27, the data register 28, and the sense amplifier module 29. The peripheral circuit 220 corresponds to the input / output circuit 21, the logic controller 22, the register circuit 23, the sequencer 24, the ready busy controller 25, and the driver circuit 26.

[0160] Fig.15 1 is a block diagram showing an example of the functional configuration of the memory system MS according to the second embodiment. Fig.15As shown, the memory controller 1 of the second embodiment includes a Vth tracking processing unit 110 and a parameter storage unit 120. The parameter storage unit 120 is formed of, for example, an SRAM. The peripheral circuit 220 of the memory device 2 of the second embodiment includes a shift read processing unit 221.

[0161] The Vth tracking processing unit 110 has a function of executing the Vth tracking described in the first embodiment. The parameter storage unit 120 has a function of storing Vth tracking parameters. The Vth tracking processing unit 110 refers to the Vth tracking parameters stored in the parameter storage unit 120 to determine the start reading level and step value used in Vth tracking. In addition, the Vth tracking processing unit 110 estimates the gradient of the threshold voltage distribution of the memory cell transistor MT based on the results of multiple shift readings. Moreover, the Vth tracking processing unit 110 has a function of selecting a more appropriate Vth tracking parameter based on the estimation result of the gradient of the threshold voltage distribution and referring to the parameter storage unit 120.

[0162] The parameter storage unit 120 stores a plurality of Vth tracking parameters. Specifically, the parameter storage unit 120 stores a start value table 121 and a step value table 122. The start value table 121 stores information on the initial value of the read level (that is, the start read level) used for multiple shift reads performed in Vth tracking for each adjacent state that may become the object of Vth tracking. The step value table 122 stores information on the step value of the read level used for multiple shift reads performed in Vth tracking for each adjacent state that may become the object of Vth tracking. For example, the Vth tracking parameters are preset in a plurality of combinations based on information associated with the gradient of the adjacent state.

[0163] The shift read processing section 221 performs shift read using a read level based on an instruction from the Vth tracking processing section 110. Then, the shift read processing section 221 outputs the result of the shift read to the Vth tracking processing section 110. In addition, the shift read processing section 221 can change the setting of the read level used for the shift read based on an instruction from the Vth tracking processing section 110.

[0164] (1: Specific example of the start value table 121)

[0165] Fig.16 1 is a diagram showing an example of a start value table 121 stored in the parameter storage unit 120 of the memory controller 1 included in the memory system MS according to the second embodiment. Fig.16As shown, for example, the start value table 121 stores the start reading level used in the Vth tracking of each of the S0-S1 state, the S1-S2 state, ..., and the S6-S7 state for each index value (e.g., #0 to #4). The start reading level is represented by a voltage value (V), for example. In addition, the start reading level may be specified by a DAC value instead of a voltage value (V). In this case, the value obtained by multiplying the DAC value stored in the start value table 121 by the voltage value of each DAC value corresponds to the start reading level.

[0166] In the start value table 121, in the row of index value #k ("k" is an integer greater than 0), multiple fields are associated with the columns of S0-S1 state, S1-S2 state, ..., S5-S6 state and S6-S7 state, respectively, and the start reading levels RL1_k, RL2_k, ..., RL6_k and RL7_k are stored respectively.

[0167] More specifically, in the row of index value #0, the start reading levels RL1_0, RL2_0, ..., RL6_0, and RL7_0 are stored in the plurality of fields associated with the columns of the S0-S1 state, the S1-S2 state, ..., the S5-S6 state, and the S6-S7 state, respectively. In the row of index value #1, the start reading levels RL1_1, RL2_1, ..., RL6_1, and RL7_1 are stored in the plurality of fields associated with the columns of the S0-S1 state, the S1-S2 state, ..., the S5-S6 state, and the S6-S7 state, respectively. The same applies to index values ​​#2 and later.

[0168] In addition, in the start value table 121 , the start reading levels for the same adjacent state may be the same or different in a plurality of rows.

[0169] (2: Specific example of step value table 122)

[0170] Fig.17 FIG. 1 is a diagram showing an example of a step value table 122 stored in the parameter storage unit 120 of the memory controller 1 included in the memory system MS according to the second embodiment. Fig.17As shown, for example, the step value table 122 stores the step value used in Vth tracking for each of the S0-S1 state, S1-S2 state, ..., S6-S7 state according to each index value (e.g., #0 to #4). The step value is represented by a DAC value, for example, but can also be represented by a voltage value (V) as with the start read level. In this example, it is assumed that 5 shift reads are performed in Vth tracking, and 4 step values ​​are stored for each adjacent state. The 4 step values ​​are respectively corresponding to the 4 adjacent read levels included in the 5 shift reads. Each step value represents the difference in the corresponding DAC value, or the difference in the voltage value of the adjacent read level. In the following, the reference symbols representing the 4 step values ​​set for each adjacent state are respectively added with "a", "b", "c", and "d" in the order from the low side to the high side of the adjacent read level.

[0171] Specifically, in the step value table 122, in the row of index value #k ("k" is an integer greater than 0), the step values ​​SS1a_k, SS1b_k, SS1c_k and SS1d_k are stored in the field associated with the column of the S0-S1 state, the step values ​​SS2a_k, SS2b_k, SS2c_k and SS2d_k are stored in the field associated with the column of the S1-S2 state, and the step values ​​SS7a_k, SS7b_k, SS7c_k and SS7d_k are stored in the field associated with the column of the S6-S7 state.

[0172] More specifically, in the row of index value #0, the step values ​​SS1a_0, SS1b_0, SS1c_0 and SS1d_0 are stored in the field associated with the column of the S0-S1 state, the step values ​​SS2a_0, SS2b_0, SS2c_0 and SS2d_0 are stored in the field associated with the column of the S1-S2 state, and the step values ​​SS7a_0, SS7b_0, SS7c_0 and SS7d_0 are stored in the field associated with the column of the S6-S7 state. In the row of index value #1, the step values ​​SS1a_1, SS1b_1, SS1c_1 and SS1d_1 are stored in the field associated with the column of the S0-S1 state, the step values ​​SS2a_1, SS2b_1, SS2c_1 and SS2d_1 are stored in the field associated with the column of the S1-S2 state, ..., and the step values ​​SS7a_1, SS7b_1, SS7c_1 and SS7d_1 are stored in the field associated with the column of the S6-S7 state.

[0173] Here, the details of the read voltage when the parameter of index value #1 is used in the Vth tracking of the S0-S1 state are described. In this example, in 5 shift reads, 5 read operations using read levels RL1(1) to RL1(5) are performed respectively. The read level RL1(1) used in the first shift read corresponds to the start read level and is set based on the start value table 121. The read level RL1(2) used in the second shift read is set based on "RL1(1)+SS1a_1". The read level RL1(3) used in the third shift read is set based on "RL1(2)+SS1b_1". The read level RL1(4) used in the fourth shift read is set based on "RL1(3)+SS1c_1". The read level RL1(5) used in the fifth shift read is set based on "RL1(4)+SS1d_1". Even in the step value or other index value in other adjacent states, a plurality of read levels respectively used in a plurality of shift reads are set, similarly to the case of using the parameter of index value #1 in the Vth tracking of the S0-S1 state.

[0174] In addition, in the step value table 122 , a plurality of step values ​​for the same adjacent state may be the same or different in a plurality of rows.

[0175] <2-2>Action

[0176] Next, the operation of the memory system MS according to the second embodiment will be described.

[0177] Fig.18 This is a flowchart showing an example of a procedure of Vth tracking executed in the memory system MS according to the second embodiment.

[0178] For example, when the error correction of the data read from the memory device 2 fails during the reading operation, or based on a predetermined schedule, the memory system MS starts Fig.18 The series of processes shown (start).

[0179] First, the Vth tracking processing unit 110 loads initial parameters for Vth tracking from the start value table 121 and the step value table 122 (ST201). For example, the loaded initial parameters can be selected based on the type of adjacent state, the address of the cell group CU, information on the optimal read level of the adjacent state obtained by Vth tracking previously executed, or the operation log of the memory system MS.

[0180] Next, the Vth tracking processing unit 110 performs multiple shift reads according to the loaded parameters (ST202). In the multiple shift reads in the process of step ST202, the Vth tracking processing unit 110 may use one step value or two or more different step values.

[0181] Next, the Vth tracking processing unit 110 calculates the number of ON cells in each of a plurality of shift reads (ST203).

[0182] Next, the Vth tracking processing unit 110 calculates the difference in the number of ON cells for each group of two shift reads using adjacent read levels, based on the results of the multiple shift reads (ST204).

[0183] Next, the Vth tracking processing unit 110 confirms whether the difference curve presents a V shape (ST205). The difference curve corresponds to the curve of the difference in the number of cells turned on obtained by the process of step ST204. For example, in the case where the range of the read level in which the multiple shift reads are performed in the process of step ST202 includes a decreasing voltage range and an increasing voltage range, the difference curve presents a V shape. Here, the decreasing voltage range is a voltage range in which the difference in the number of cells turned on decreases as the read level increases. The increasing voltage range is a voltage range in which the difference in the number of cells turned on increases as the read level increases. For example, in the case of approximating the difference curve with a quadratic function, the V shape can be determined based on whether the minimum point of the quadratic function is included in the range of the read level.

[0184] When it is confirmed in the process of step ST205 that the difference curve does not show a V shape (ST205: NO), the Vth tracking processing unit 110 changes the Vth tracking parameter (ST206). In the process of step ST206, for example, the Vth tracking processing unit 110 changes at least one of the start reading level and the step value. Then, the Vth tracking processing unit 110 proceeds to the process of step ST202. That is, the Vth tracking processing unit 110 uses the changed Vth tracking parameter to perform the processes of step ST202 to step ST205.

[0185] When it is confirmed in the process of step ST205 that the difference curve shows a V shape (ST205: YES), the Vth tracking processing unit 110 calculates the difference DN1 between the minimum value of the plurality of differences obtained and the previous difference, and the difference DN2 between the minimum value and the subsequent difference, and compares the difference DN1 with the difference DN2 (ST207). The details of the process of step ST207 will be described later. Then, based on the comparison result of step ST207, the Vth tracking processing unit 110 confirms whether the absolute value of the difference between DN1 and DN2 is less than a predetermined threshold value (ST208). In addition, a plurality of threshold values ​​may be set for the absolute value of the difference.

[0186] When it is confirmed in the process of step ST208 that the absolute value of the difference between DN1 and DN2 is less than the predetermined threshold value (ST208: Yes), that is, when the asymmetry of the threshold voltage distribution of adjacent states is within the expected range, the Vth tracking processing unit 110 enters the process of step ST211. The absolute value of the difference between DN1 and DN2 is less than the predetermined threshold value, indicating that the preferred Vth tracking parameter is set in the multiple shift reads performed in step ST202.

[0187] When it is confirmed in the process of step ST208 that the absolute value of the difference between DN1 and DN2 is greater than the predetermined threshold value (ST208: No), that is, when the asymmetry of the threshold voltage distribution of the adjacent states is unexpected, the Vth tracking processing unit 110 changes the Vth tracking parameter (ST209). In the process of step ST209, for example, the Vth tracking processing unit 110 changes the row (that is, the index value) of the step value table 122 used in the next Vth tracking. Then, the Vth tracking processing unit 110 performs Vth tracking using the changed Vth tracking parameter (ST210). After the process of step ST210 is completed, the Vth tracking processing unit 110 enters the process of step ST211.

[0188] In the process of step ST211, the Vth tracking processing unit 110 estimates the optimal read level. In addition, in the process of ST211, if the determination in step ST208 is "yes", the Vth tracking processing unit 110 estimates the optimal read level based on the results of the multiple shift readings performed in step ST202. In addition, if the determination in step ST208 is "no", the Vth tracking processing unit 110 estimates the optimal read level based on the results of the multiple shift readings performed by the Vth tracking in step ST210. When the process of step ST211 is completed, the Vth tracking processing unit 110 ends. Fig.18 The series of processing shown (end).

[0189] In addition, when the process of step ST206 is transferred to the process of step ST202, the multiple shift reads in step ST202 may be replaced by one additional shift read. In this case, based on the results of the additional one shift read according to the changed Vth parameter and the multiple shift reads performed before the change of the Vth parameter, the processes of steps ST203 and ST204 are performed again. Then, by the process of step ST205, it is determined again whether the difference curve of the number of on-cells shows a V shape. In this way, the memory system MS can reduce the number of shift reads performed in Vth tracking.

[0190] In addition, the same process as step ST205 may be performed between step ST210 and step ST211. In the same process as step ST205, when it is confirmed that the difference curve shows a V shape, the Vth tracking processing unit 110 proceeds to the process of step ST211. In the same process as step ST205, when it is not confirmed that the difference curve shows a V shape, the Vth tracking processing unit 110 proceeds to the process of step ST206, for example.

[0191] In addition, for the comparison with the prescribed threshold value in step ST208, the difference between the difference DN1 and the difference DN2 may be used instead of the absolute value of the difference between the difference DN1 and the difference DN2. In this case, the difference between the difference DN1 and the difference DN2 is calculated by "DN1-DN2" or "DN2-DN1".

[0192] (1: Specific example of the processing of steps ST207 to ST209)

[0193] Fig.19 It means reference Fig.18 This is a schematic diagram for explaining a specific example of the processing of steps ST207 to ST209. Fig.19 The difference curves corresponding to the (j-1)th (j is an integer greater than or equal to 2), jth, (j+1)th, and (j+2)th shift reads among the multiple shift reads performed while raising the read level are shown. Fig.19 As shown, in the (j-1)th, jth, (j+1)th and (j+2)th shift reads, the read levels RL(j-1), RL(j), RL(j+1) and RL(j+2) are used respectively. The relationship between the read level heights is RL(j-1)<RL(j)<RL(j+1)<RL(j+2). The difference in the number of connected cells corresponding to the (j-1)th and jth shift reads is N3 (difference curve D(j-1)). The difference in the number of connected cells corresponding to the jth and (j+1)th shift reads is N1 (difference curve D(j)). The difference in the number of connected cells corresponding to the (j+1)th and (j+2)th shift reads is N2 (difference curve D(j+1)). The relationship between the differences in the number of connected cells is N1<N2<N3. That is, in this example, the minimum value, the previous difference, and the next difference in step ST207 are N1, N3, and N2, respectively.

[0194] The Vth tracking processing unit 110 detects that the valley position of the difference curve corresponds to the difference curve D(j) based on, for example, that N1-N3 is negative and N2-N1 is positive. In this case, the difference DN1 corresponds to N3-N1. The difference DN2 corresponds to N2-N1. In this example, the Vth tracking processing unit 110 detects that the gradient of the threshold voltage distribution of the difference curves D(j-1) to D(j) is steeper than the difference curves D(j) to D(j+1) based on the fact that the difference DN1 is greater than the difference DN2. Subsequently, the Vth tracking processing unit 110 changes the Vth tracking parameters (ST209) using the same algorithm as in the first embodiment, for example, when the absolute value of the difference between DN1 and DN2 is greater than a predetermined threshold value (ST208: No).

[0195] (2: Specific example of instruction sequence)

[0196] Fig. 20 : is a table showing an example of a command sequence used by the memory system MS of the second embodiment. Fig. 20 As shown, the memory system MS uses, for example, instruction sets CS1 to CS3. The instruction sets CS1 to CS3 are, for example, Fig.18 The instruction set used in the shift read executed in the process of step ST202 will be described.

[0197] The instruction set CS1 includes, for example, "aah", "ADD(LUN)", "ADD(AAh)", and "DAT1". "aah" is an instruction indicating a read level used for a specified shift read. "ADD(LUN)" is a logical unit number (LUN) of an object for specifying the read level. In the case where the memory system MS has a plurality of memory devices 2, the logical unit number is assigned to each of the plurality of memory devices 2. "ADD(AAh)" is the address of a register storing the setting of the read level. "DAT1" is information indicating the shift amount of the read level. "DAT1" includes, for example, a DAC value corresponding to the shift amount. When "aah", "ADD(LUN)", "ADD(AAh)", and "DAT1" are received sequentially from the memory controller 1, the memory device 2 changes to a busy state and sets the parameter "DAT1" to the register specified by "ADD(LUN)" and "ADD(AAh)". When the setting of the parameters is completed, the memory device 2 changes to a ready state. The time tFEAT is the time for the memory device 2 to execute processing based on the instruction set CS1.

[0198] The instruction set CS2 includes, for example, "01h / 02h / 03h", "00h", "ADD(CUsel)", and "30h". "01h / 02h / 03h" is an instruction for specifying the page data of the read object. For example, "01h", "02h" and "03h" correspond to lower-level page data, middle-level page data and upper-level page data, respectively. "00h" is an instruction instructing a read action. "ADD(CUsel)" is the address of the unit group CU of the read object. "30h" is an instruction instructing the start of the read action. When "01h / 02h / 03h", "00h", "ADD(CUsel)", and "30h" are received sequentially from the memory controller 1, the memory device 2 changes to a busy state, and executes a read action of the page data specified by "01h / 02h / 03h" from the unit group CU specified by "ADD(CUsel)". When the read action is completed, the memory device 2 changes to a ready state. The time tR is the time during which the memory device 2 executes the processing based on the instruction set CS2.

[0199] The instruction set CS3 includes, for example, "bbh", "ADD(CUsel)", and "E0h". "bbh" is an instruction for specifying the transfer of data stored in the data register 28 by a read operation such as a shift read. "E0h" is an instruction for instructing the start of data transfer. When "bbh", "ADD(CUsel)", and "E0h" are sequentially received from the memory controller 1, the memory device 2 outputs the data stored in the data register 28 to the memory controller 1 (Data-out).

[0200] Furthermore, in the process of step ST202 , when a read operation targeting a plurality of states is executed, a command set CS1 for parameter setting for shift reading can be issued for each state.

[0201] <2-3> Effects of the Second Embodiment

[0202] As described above, the memory system MS of the second embodiment can detect the gradient near the valley position of the threshold voltage distribution of adjacent states. In the second embodiment, the combination of Vth tracking parameters is selected from at least two groups using the start value table 121 and the step value table 122 .

[0203] As a result, the memory system MS of the second embodiment can change the step value in Vth tracking according to the gradient of the threshold voltage distribution before and after the valley position, as in the first embodiment. That is, the memory system MS of the second embodiment can make the optimal read level estimated by Vth tracking close to the actual optimal read level, as in the first embodiment. Therefore, the memory system MS of the second embodiment can reduce the number of error bits and obtain higher reliability, as in the first embodiment.

[0204] In the second embodiment, Vth tracking parameters are changed based on the comparison result of the gradient magnitude near the valley position of the threshold voltage distribution, and Vth tracking can be retried. Therefore, the memory system MS of the second embodiment can estimate the optimum read level with higher accuracy than the first embodiment.

[0205] <2-4> Modification of the Second Embodiment

[0206] Fig.21 This is a flowchart showing an example of a procedure of a variation example of Vth tracking executed in the memory system according to the second embodiment. Fig.21 The steps shown in the flowchart have the following structure: Fig.18 In the sequence shown in the flowchart of , the processing of step ST207 and step ST208 are replaced by the processing of step ST220 and step ST221, respectively.

[0207] In the process of step ST220, the Vth tracking processing unit 110 calculates the difference DN1 between the minimum value of the obtained multiple differences and the previous difference, and the difference DN2 between the minimum value and the subsequent difference, and calculates the ratio of the difference DN1 to the difference DN2 (ST220). Then, the Vth tracking processing unit 110 confirms whether the absolute value (|DN1 / DN2|) of the ratio of the difference DN1 to the difference DN2 is within a specified range (ST221). Specifically, in the process of step S221, it is confirmed whether the absolute value (|DN1 / DN2|) of the ratio of the difference DN1 to the difference DN2 is between the first threshold TH1 and the second threshold TH2. The first threshold TH1 is, for example, 0.75. The second threshold TH2 is, for example, 1.33. The closer the absolute value of the ratio is to 1, it means that the preferred Vth tracking parameter is set in the multiple shift readings performed in step ST202. For the absolute value of the ratio, multiple threshold ranges can also be set. When it is confirmed in the process of step ST221 that the absolute value of the ratio of the difference DN1 to the difference DN2 is within the prescribed range (ST221: Yes), the Vth tracking processing unit 110 proceeds to the process of step ST211. When it is confirmed in the process of step ST221 that the absolute value of the ratio of the difference DN1 to the difference DN2 is outside the prescribed range (ST221: No), the Vth tracking processing unit 110 proceeds to the process of step ST209.

[0208] Fig.21 Other processing and Fig.18 The processing shown is the same. A variation of the Vth tracking performed in the second embodiment is the same as the Vth tracking performed in the second embodiment, and the optimum read level can be estimated with high accuracy.

[0209] <3> Third embodiment

[0210] The memory system MS of the third embodiment is configured to be able to perform Vth tracking similar to the second embodiment, and further has a function of selecting Vth tracking parameters based on an operation log. The details of the memory system MS of the third embodiment will be described below, mainly focusing on the differences from the first and second embodiments.

[0211] <3-1>Composition

[0212] First, the configuration of the memory system MS according to the third embodiment will be described. The hardware configuration of the memory system MS according to the third embodiment is the same as that of the first embodiment. Hereinafter, the functional configuration of the memory system MS according to the third embodiment will be described.

[0213] Fig. 22 1 is a block diagram showing an example of the functional configuration of the memory system MS according to the third embodiment. Fig. 22As shown, the memory controller 1 of the third embodiment includes a Vth tracking processing unit 110a, a parameter storage unit 120a, and an operation log storage unit 130. The parameter storage unit 120a and the operation log storage unit 130 are composed of, for example, SRAM. The peripheral circuit 220 of the memory device 2 of the third embodiment includes a shift read processing unit 221 similar to the second embodiment.

[0214] The Vth tracking processing unit 110a has the same function as the Vth tracking processing unit 110 described in the second embodiment. In addition, the Vth tracking processing unit 110a refers to the Vth tracking parameters stored in the parameter storage unit 120a based on the operation log of the memory device 2 recorded in the operation log storage unit 130. According to the operation log of the memory device 2, the change in the gradient of the threshold voltage distribution can be estimated. In addition, the Vth tracking processing unit 110a determines the start reading level and step value used in Vth tracking based on the start value table 121 and the step value table 122 corresponding to the operation log.

[0215] The parameter storage unit 120a stores a start value table set 140 and a step value table set 150. The start value table set 140 includes a plurality of start value tables 121. Each of the plurality of start value tables 121 corresponds to a numerical value that can be shown in an action log. The plurality of start value tables 121 include information of a start read level of a gradient of a threshold voltage distribution that is suitable for being estimated from an action log for establishing the corresponding numerical value. The step value table set 150 includes a plurality of step value tables 122. Each of the plurality of step value tables 122 corresponds to a numerical value that can be shown in an action log. The plurality of step value tables 122 include information of a step value of a gradient of a threshold voltage distribution that is suitable for being estimated from an action log for establishing the corresponding numerical value. The configuration of the start value table 121 and the step value table 122 is, for example, the same as that of the second embodiment.

[0216] The action log storage unit 130 stores the action log of the memory system MS. The action log storage unit 130 records, for example, the number of write / erase operations, the data retention period, and the number of read operations according to the operation of the memory system MS. The number of write / erase operations corresponds to the number of groups that perform write operations and erase operations. The number of write / erase operations can be managed in block BLK units, or in chip units, page units, or unit group CU units. The data retention period corresponds to the time elapsed from writing data to the unit group CU in the erased state. The number of read operations corresponds to the number of times the read operation is performed since the data was written.

[0217] When the number of write / erase, readout or data retention period increases, the gradient of the threshold voltage distribution may change. For example, as the data retention period of the unit group CU passes, the threshold voltage distribution in each state is widely distributed relative to the low voltage side. On the contrary, as the number of write / erase or readout increases, the threshold voltage distribution in each state is widely distributed relative to the high voltage side. Therefore, by stressing the unit group CU, adjacent threshold voltage distributions may become asymmetric distributions with different gradients.

[0218] In addition, the operation log of the memory system MS may include other information, such as the number of executions of the Vth tracking, the operation temperature of the memory system MS, or the operation time of the memory system MS.

[0219] Each of the plurality of start value tables 121 and the plurality of step value tables 122 stored in the parameter storage unit 120a can be set, for example, according to the number of write / erase operations, according to the data retention period, or according to the number of read operations. That is, the parameter storage unit 120a can store a plurality of tables for changing the Vth tracking parameter triggered by the number of write / erase operations, a plurality of tables for changing the Vth tracking parameter triggered by the data retention period, or a plurality of tables for changing the Vth tracking parameter triggered by the number of read operations. In each step value table 122, as in the first embodiment, a plurality of different step values ​​can be set. Moreover, it is desirable to set a plurality of step values ​​in a manner corresponding to the shape of the threshold voltage distribution. Each of the start value table 121 and the step value table 122 can be a table containing a read level for the action log of the memory system MS.

[0220] Here, as a more specific example, the case where the Vth tracking parameter is changed based on the number of write / erase times as a trigger, that is, the case where the Vth tracking parameter is changed before and after the number of write / erase times reaches the threshold value is described. When the number of write / erase times increases, as described above, the threshold voltage distribution may become a shape that is widely distributed on the high potential side in each state. In this case, the threshold voltage distribution of adjacent states may become a distribution that is steep on one side (high potential side) and gentle on the other side (low potential side) with the valley position of the adjacent state as the boundary. When the number of write / erase times for the unit group CU increases, for example, the distribution of the state on the low potential side of the threshold voltage distribution, that is, the S0 state, may be widely distributed on the high potential side. At this time, compared with the distribution of the adjacent state of the S0 state, that is, the low potential side of the S1 state, the distribution of the high potential side of the S0 state becomes a relatively gentle gradient. Therefore, the threshold voltage distribution composed of the S0 state and the S1 state becomes an asymmetric distribution, and the optimal read level (RTRK) estimated by Vth tracking deviates from the actual optimal read level (RBST). In contrast, the memory system MS of the present embodiment sets a set of step values ​​such as relatively reducing the step value on the S1 state side where the gradient of the threshold voltage distribution is relatively steep, and relatively increasing the step value on the S0 state side where the gradient of the threshold voltage distribution is relatively gentle. This can improve the estimation accuracy of the optimal read level (RTRK) estimated by Vth tracking. In this way, the memory system MS of the present embodiment can explore the threshold voltage distribution with high accuracy by reducing the step value on the low potential side in the adjacent state of the high potential side and increasing the step value on the high potential side in the adjacent state of the low potential side, as in the second embodiment.

[0221] Next, the case where the Vth tracking parameters are changed with the data retention period as a trigger, that is, the case where the Vth tracking parameters are changed before and after the data retention period reaches the threshold value, is described. When the data retention period increases, for example, the threshold voltage distribution on the high potential side (for example, the S6-S7 state) may become a shape that is widely distributed on the low potential side. The influence of the data retention period may be significantly manifested in the S6 state or the S7 state, for example. Specifically, when the data retention period for the unit group CU increases, the state on the high potential side of the threshold voltage distribution, that is, the distribution of the S7 state, is widely distributed on the low potential side. At this time, compared with the distribution of the high potential side of the adjacent state of the S7 state, that is, the S6 state, the distribution of the low potential side of the S7 state becomes a relatively gentle gradient. Therefore, the threshold voltage distribution composed of the S6 state and the S7 state becomes an asymmetric distribution, and the optimal read level (RTRK) estimated by Vth tracking deviates from the actual optimal read level (RBST). In contrast, the memory system MS of the present embodiment can improve the estimation accuracy of the optimal read level (RTRK) estimated by Vth tracking by setting a set of step values ​​such as relatively reducing the step value on the S6 state side where the gradient of the threshold voltage distribution is relatively steep, and relatively increasing the step value on the S7 state side where the gradient of the threshold voltage distribution is relatively gentle. In other words, the memory system MS of the present embodiment can explore the threshold voltage distribution with high accuracy by reducing the step value on the high potential side in the state adjacent to the low potential side and increasing the step value on the low potential side in the state adjacent to the high potential side.

[0222] Next, the case where the Vth tracking parameter is changed based on the number of readouts as a trigger, that is, the case where the Vth tracking parameter is changed before and after the number of readouts reaches the threshold value, is described. When the number of readouts increases, for example, the threshold voltage distribution may become a shape that is widely distributed on the high potential side in each state. In this case, the threshold voltage distribution of adjacent states may become a distribution with a steep gradient on one side (high potential side) and a gentle gradient on the other side (low potential side) bounded by the valley position of the adjacent state. When the number of readouts for the unit group CU increases, for example, the state on the low potential side of the threshold voltage distribution, that is, the distribution of the S0 state, is widely distributed on the high potential side. At this time, compared with the distribution of the adjacent state of the S0 state, that is, the low potential side of the S1 state, the distribution of the high potential side of the S0 state becomes a relatively gentle gradient. Therefore, the threshold voltage distribution composed of the S0 state and the S1 state becomes an asymmetric distribution, and the optimal read level (RTRK) estimated by Vth tracking deviates from the actual optimal read level (RBST). In contrast, the memory system MS of the present embodiment can improve the estimation accuracy of the optimal read level (RTRK) estimated by Vth tracking by setting a set of step values ​​such as relatively reducing the step value on the S1 state side where the gradient of the threshold voltage distribution is relatively steep, and relatively increasing the step value on the S0 state side where the gradient of the threshold voltage distribution is relatively gentle. In this way, the memory system MS of the present embodiment can explore the threshold voltage distribution with high accuracy by reducing the step value on the low potential side in the adjacent state of the high potential side and increasing the step value on the high potential side in the adjacent state of the low potential side.

[0223] In addition, each of the start value table set 140 and the step value table set 150 can be set according to each stress condition such as the number of write / erase times, data retention time, and the number of read times. Thus, it is possible to select a different start value table 121 and step value table 122 for each stress condition. The memory system MS can also use a combination of different start value table sets 140 and step value table sets 150 for each stress condition.

[0224] For example, it is preferable to assign index numbers according to the range of write / erase counts to the start value table 121 and the step value table 122. By assigning one index number to the range of stress conditions to which the same Vth tracking parameter is applied, the memory system MS can select the optimal Vth tracking parameter for each stress condition.

[0225] <3-2>Action

[0226] Next, the operation of the memory system MS according to the third embodiment will be described.

[0227] Fig.23This is a flowchart showing an example of a procedure for setting initial parameters of Vth tracking executed in the memory system MS according to the third embodiment.

[0228] When reference Fig.18 When the processing of step ST201 described above starts (start), the Vth tracking processing unit 110a checks the stress state by referring to the operation log stored in the operation log storage unit 130 (ST301). The operation log referred to in the processing of step ST301 includes information such as the number of write / erase times, data retention period, or read times.

[0229] Next, the Vth tracking processing unit 110a selects a start value table 121 corresponding to the current stress state from the start value table set 140 (ST302). In addition, the Vth tracking processing unit 110a selects a step value table 122 corresponding to the current stress state from the step value table set 150 (ST303). For example, when the number of write / erase operations does not reach the first threshold, the first start value table 121 and the first step value table 122 are selected, and when the number of write / erase operations is greater than the first threshold, the second start value table 121 and the second step value table 122 are selected. Similarly, when the data retention period does not reach the second threshold, the third start value table 121 and the third step value table 122 may be selected, and when the data retention period is greater than the second threshold, the fourth start value table 121 and the fourth step value table 122 may be selected. Similarly, when the number of readouts does not reach the third threshold, the fifth start value table 121 and the fifth step value table 122 may be selected, and when the number of readouts is greater than the third threshold, the sixth start value table 121 and the sixth step value table 122 may be selected.

[0230] When the processing of step ST303 is completed, the series of processing included in step ST201 ends (ends), and the Vth tracking processing unit 110a enters the reference Fig.18 The processing of step ST202 will be described. The other operations of the memory system MS according to the third embodiment are the same as those of the second embodiment.

[0231] In addition, the order of the processing of step ST302 and the processing of step ST303 may be replaced. The processing of step ST302 and the processing of step ST303 may also be performed in parallel. The threshold value for selecting the action log of the start value table 121 and the threshold value for selecting the action log of the step value table 122 may be different from each other. In addition, the start value table set 140 and the step value table set 150 may be managed in a single chip unit or a plurality of chip units, or a single block unit or a plurality of block units.

[0232] <3-3> Effects of the third embodiment

[0233] The threshold voltage distribution of the memory cell transistor MT has a tendency corresponding to the stress state. Therefore, the memory system MS of the third embodiment monitors the stress state of the memory device 2 with reference to the action log. Moreover, the memory system MS of the third embodiment changes the initial value of the Vth tracking parameter (at least one of the start reading level and the step value) based on the action log. As a result, the memory system MS of the third embodiment can improve the accuracy of estimating the optimal read level in the initial Vth tracking. Therefore, the memory system MS of the third embodiment can reduce the number of error bits and obtain higher reliability.

[0234] In addition, the memory system MS of the third embodiment can reduce the execution reference time by applying the Vth tracking parameter based on the operation log. Fig.18 and Fig.21 The respective flowcharts illustrate the possibility of the processing of step ST209 and step ST210. That is, the memory system MS of the third embodiment can suppress the time required for estimating the optimum read level from being prolonged, and can improve the performance of the memory system MS.

[0235] <4> Fourth embodiment

[0236] In the memory system MS of the fourth embodiment, the memory device 2 executes a part of the Vth tracking process similar to the first embodiment based on the instruction of the memory controller 1. The details of the memory system MS of the fourth embodiment will be described below, mainly focusing on the differences from the first to third embodiments.

[0237] <4-1>Composition

[0238] First, the configuration of the memory system MS according to the fourth embodiment will be described. The hardware configuration of the memory system MS according to the fourth embodiment is the same as that of the first embodiment. Hereinafter, the functional configuration of the memory system MS according to the fourth embodiment will be described.

[0239] Fig.24 1 is a block diagram showing an example of the functional configuration of the memory system MS according to the fourth embodiment. Fig.24 As shown, the memory controller 1 of the fourth embodiment includes a Vth tracking processing unit 110b and a parameter storage unit 120b. The parameter storage unit 120b is composed of, for example, an SRAM. The peripheral circuit 220 of the memory device 2 of the fourth embodiment includes a shift read processing unit 221 and an on-chip Vth tracking processing unit 222. The structure of the shift read processing unit 221 of the fourth embodiment is the same as that of the second embodiment.

[0240] The on-chip Vth tracking processing unit 222 is a functional block that performs processing related to Vth tracking including at least search reading. Search reading is a read operation of multiple read levels performed using the memory device 2 based on a specified instruction set. The on-chip Vth tracking processing unit 222 can uniformly perform processing corresponding to multiple shift reads of Vth tracking described in the first to third embodiments. Moreover, the on-chip Vth tracking processing unit 222 can calculate the detected search number (Detected Search Number) and the adjustment coefficient (Adjustment Coefficient) based on the read results using multiple read levels. The detected search number is information on the read level corresponding to the minimum value of the difference in the number of turned-on cells obtained by reading using multiple read levels. The adjustment coefficient is, for example, information corresponding to the difference between the read level corresponding to the detected search number and the optimal read level. The on-chip Vth tracking processing unit 222 can change the setting of the read level used for the search reading based on the instruction of the Vth tracking processing unit 110b.

[0241] The Vth tracking processing unit 110b has a function of estimating an optimal read level in consideration of the asymmetry of the threshold voltage distribution of the memory cell transistor MT. For example, the Vth tracking processing unit 110b first sends an optimal read level estimation request using a step value corresponding to the symmetrical threshold voltage distribution of the adjacent state to the on-chip Vth tracking processing unit 222. Moreover, the Vth tracking processing unit 110b changes the start read level of the Vth tracking based on the estimation result of the optimal read level performed by the on-chip Vth tracking processing unit 222. Then, the Vth tracking processing unit 110b sends an optimal read level estimation request using a step value corresponding to the asymmetric threshold voltage distribution of the adjacent state to the on-chip Vth tracking processing unit 222.

[0242] The Vth tracking processing unit 110b includes an ECC processing unit 111. The ECC processing unit 111 includes an ECC circuit 13. The ECC processing unit 111 performs a decoding process on the page data received from the shift read processing unit 221. When the decoding process of the ECC processing unit 111 succeeds, the Vth tracking processing unit 110b outputs the corrected page data to the host device HD. On the other hand, when the decoding process of the ECC processing unit 111 fails, the Vth tracking processing unit 110b changes the start read level and step value of the Vth tracking, and sends an optimal read level estimation request to the on-chip Vth tracking processing unit 222.

[0243] The parameter storage unit 120b stores a start value table 121 and a step value table 123. The start value table 121 is configured as follows: Fig.16The second embodiment described is similar to the setting of the start read level for search reading. The step value table 123 stores information of a plurality of step values ​​used for search reading for each adjacent state that may be the object of search reading. The step value stored in the step value table 123 is preset based on information associated with the gradient of the adjacent state, for example.

[0244] (Specific example of step value table 123)

[0245] Fig.25 1 is a diagram showing an example of a step value table 123 stored in the parameter storage unit 120b of the memory controller 1 included in the memory system MS according to the fourth embodiment. Fig.25 As shown, for example, the step value table 123 stores two step values ​​SSa and SSb used for search reading of the S0-S1 state, the S1-S2 state, ..., and the S6-S7 state, for each index value (e.g., #0 to #4). The step value is represented by a DAC value, for example. The step value SSa is a step value for setting the first half (e.g., low voltage side) of the multiple read levels used for the search reading. The step value SSb is a step value for setting the second half (e.g., high voltage side) of the multiple read levels used for the search reading. The switching point of the step values ​​SSa and SSb is specified, for example, by an instruction set from the memory controller 1. In addition, the central value of the number of explorations specified by the instruction set from the memory controller 1 may also be set as the switching point.

[0246] The index value #0 of the step value table 123 corresponds to a symmetrical threshold voltage distribution of adjacent states. The index values ​​#1 and thereafter of the step value table 123 correspond to an asymmetrical threshold voltage distribution of adjacent states.

[0247] Specifically, in the row of index value #0, SSa=8 and SSb=8 correspond to each of the multiple fields associated with the S0-S1 state, the S1-S2 state, the S5-S6 state, and the S6-S7 state. In the row of index value #1, the step value SSb of the S0-S1 state and the step value SSa of the S6-S7 state are changed to 4, respectively, relative to the row of index value #0. In the row of index value #2, the step value SSb of the S1-S2 state and the step value SSa of the S5-S6 state are changed to 4, respectively, relative to the row of index value #1. In the row of index value #3, the step value SSa of the S0-S1 state and the step value SSb of the S5-S6 state are changed to 16, respectively, relative to the row of index value #2. In the row of index value #4, the step value SSa of the S1-S2 state and the step value SSb of the S6-S7 state are changed to 16 respectively, compared with the row of index value #3.

[0248] In this way, in the step value table 123, in the row of index value #0, symmetrical step values ​​SSa and SSb are set in any adjacent state, and after index value #1, asymmetric step values ​​SSa and SSb are set in at least a part of the adjacent states. In addition, in the step value table 123, the step values ​​SSa and SSb of the S2-S3 state, the S3-S4 state, and the S4-S5 state are set to "n / a" in the row of any index value. Here, "n / a" means that a search read using one step value is performed. However, in each of the S2-S3 state, the S3-S4 state, and the S4-S5 state, a search read using multiple step values ​​different from each other can also be performed. The adjacent states to which the search read using multiple step values ​​different from each other and the adjacent states to which the search read using one step value are applied can be appropriately changed according to the gradient of the assumed threshold voltage distribution.

[0249] <4-2>Action

[0250] Next, the operation of the memory system MS according to the fourth embodiment will be described.

[0251] Fig.26 This is a flowchart showing an example of a procedure of Vth tracking executed in the memory system according to the fourth embodiment.

[0252] For example, when the error correction of the data read from the memory device 2 fails during the reading operation, or based on a predetermined schedule, the memory system MS starts Fig.26 A series of processing (start).

[0253] First, the Vth tracking processing unit 110 b sets the index value to a value #0 corresponding to a symmetrical threshold voltage distribution of adjacent states ( ST401 ).

[0254] Next, the Vth tracking processing unit 110b estimates the optimal read level assuming symmetry (ST402). In the process of step ST402, the Vth tracking processing unit 110b uses the parameters corresponding to the index value #0 in the start value table 121 and the step value table 123 to cause the memory device 2 to perform a search read, so that the memory device 2 estimates the optimal read level without considering asymmetry.

[0255] Next, the Vth tracking processing unit 110 b increments the index value in the step value table 123 ( ST403 ).

[0256] Next, the Vth tracking processing unit 110b estimates the optimal read level in consideration of the asymmetry of the threshold voltage distribution (ST404). In the process of step ST404, the Vth tracking processing unit 110b uses, for example, the step value corresponding to the index value #1 in the step value table 123 and a start read level such that the optimal read level estimated by the process of step ST402 coincides with the switching point of the step value, and causes the memory device 2 to perform a search read.

[0257] Next, the Vth tracking processing unit 110b executes page read using the estimated optimum read level (ST405). In the process of step ST405, the Vth tracking processing unit 110b causes the memory device 2 to execute page read using the optimum read level estimated by the process of step ST404.

[0258] Next, the Vth tracking processing unit 110 b checks whether error correction of the page data obtained by the page reading in step ST405 is successful ( ST406 ).

[0259] If the error correction is not confirmed to be successful in the process of step ST406, that is, if the error correction fails (ST406: No), the Vth tracking processing unit 110b proceeds to the process of step ST403. That is, the Vth tracking processing unit 110b uses the parameters of the step value table 123 corresponding to the incremented index value and executes the process of steps ST404 to ST406 again.

[0260] When it is confirmed in the process of step ST406 that the error correction is successful ( ST406 : Yes), the Vth tracking processing unit 110 b outputs the corrected page data to the host device HD ( ST407 ).

[0261] (1: Specific example of the process of step ST402)

[0262] Fig. 27 It means reference Fig.26 This is a flowchart illustrating an example of a detailed procedure of the processing of step ST402.

[0263] When the process of step ST402 starts (start), the Vth tracking processing unit 110b of the memory controller 1 issues a setting request (ST411) for a search read parameter assuming symmetry associated with the current index value (#0) to the on-chip Vth tracking processing unit 222. In the search read parameter setting request included in the process of step ST411, the step value SSa is equal to the step value SSb.

[0264] Next, the on-chip Vth tracking processing unit 222 of the memory device 2 sets the search read parameter based on the setting request (ST412). This allows a plurality of read levels based on one step value to be used in the search read.

[0265] Next, the Vth tracking processing unit 110b issues a search read request to the on-chip Vth tracking processing unit 222 (ST413). Then, the on-chip Vth tracking processing unit 222 performs a search read based on the search read request (ST414). In the search read in the process of step ST414, a plurality of read levels based on one step value are used. In addition, the on-chip Vth tracking processing unit 222 obtains a detection search number and an adjustment coefficient based on the result of the search read.

[0266] Next, the on-chip Vth tracking processing section 222 outputs the valley position information (detection search number and adjustment coefficient) acquired by the search read to the Vth tracking processing section 110 b ( ST415 ).

[0267] Next, the Vth tracking processing unit 110b estimates the valley position (that is, the optimal read level) of the threshold voltage distribution of the adjacent state based on the valley position information (ST416). When the processing of step ST416 is completed, the series of processing included in step ST402 ends (end).

[0268] In addition, the estimation of the optimal read level in the process of step ST402 is not limited to the method of searching and reading using the on-chip Vth tracking processing unit 222. As a method of estimating the optimal read level, multiple shift readings by the Vth tracking processing unit 110b may be used. In addition, the Vth tracking processing unit 110b may estimate the optimal read level using other mechanisms and proceed to the process of step ST403. In the process of step ST402, the index value may not be used. In this case, the asymmetric step values ​​SSa and SSb can be set according to the row of the index value #0 of the step value table 123.

[0269] (2: Specific example of the process of step ST404)

[0270] Fig.28 It means reference Fig.26 This is a flowchart illustrating an example of a detailed procedure of the processing of step ST404.

[0271] When the process of step ST404 starts (start), the Vth tracking processing unit 110b of the memory controller 1 issues a setting request (ST421) of the search read parameter taking into account the asymmetry associated with the current index value to the on-chip Vth tracking processing unit 222. In the search read parameter setting request in the process of step ST421, the step value SSa and the step value SSb are different from each other. In addition, the Vth tracking processing unit 110b uses the switching point of the step values ​​SSa and SSb and the reference value S1 to generate a search read parameter. Fig.26 The optimum read level estimated in the process of step ST402 described above is matched, and the start read level is set. The details of setting the start read level will be described later.

[0272] Next, the on-chip Vth tracking processing unit 222 of the memory device 2 sets the search read parameter based on the setting request (ST422). Thus, in the search read, a plurality of read levels based on a plurality of different step values ​​can be used.

[0273] Next, the Vth tracking processing unit 110b issues a search read request to the on-chip Vth tracking processing unit 222 (ST423). Then, the on-chip Vth tracking processing unit 222 performs a search read based on the search read request (ST424). In the search read in the process of step ST424, a plurality of read levels based on a plurality of different step values ​​can be used. In addition, the on-chip Vth tracking processing unit 222 obtains a detection search number and an adjustment coefficient based on the result of the search read.

[0274] Next, the on-chip Vth tracking processing section 222 outputs the valley position information (detection search number and adjustment coefficient) acquired by the search read to the Vth tracking processing section 110 b ( ST425 ).

[0275] Next, the Vth tracking processing unit 110b estimates the optimum read level based on the valley position information (ST426). When the processing of step ST426 is completed, a series of processing included in step ST404 ends (end).

[0276] (3: Specific example of the process of step ST405)

[0277] Fig.29 It means reference Fig.26 This is a flowchart illustrating an example of a detailed procedure of the processing of step ST405.

[0278] When the process of step ST405 is started (start), the Vth tracking processing unit 110b of the memory controller 1 issues a setting request for parameters of page read using the estimated optimal read level to the shift read processing unit 221 (ST431). The optimal read level is based on the result of the process of the most recently executed step ST426. In the process of step ST431, for example, the optimal read level is set using Fig. 20 The instruction set CS1 is shown.

[0279] Next, the shift read processing unit 221 of the memory device 2 sets the parameter based on the setting request (ST432). Thus, in the page read, the optimum read level based on the result of Vth tracking is used.

[0280] Next, the Vth tracking processing unit 110b issues a page read request to the shift read processing unit 221 (ST433). In the process of step ST433, for example, Fig. 20 The shift read processing unit 221 then executes page read based on the page read request (ST434). In the page read in the process of step ST434, the optimal read level based on the result of Vth tracking is used. The page data obtained by the page read is stored in the data register 28, for example.

[0281] Next, the shift read processing unit 221 outputs the page data obtained by the page read to the Vth tracking processing unit 110b (ST435). In the process of step ST435, for example, Fig. 20 Then, the ECC processing unit 111 of the Vth tracking processing unit 110b performs error correction processing on the page data read out by the processing of step ST435 (ST436). When the processing of step ST436 is completed, the series of processing included in step ST405 ends (end).

[0282] (4: Specific example of instruction sequence)

[0283] Fig.30 : is a table showing an example of a command sequence used by the memory system MS of the fourth embodiment. Fig.30 As shown, for example, the memory system MS in addition to the reference Fig. 20 In addition to the instruction sets CS1 to CS3 described above, instruction sets CS4 to CS8 can also be used. For example, instruction sets CS4 to CS6 are used for Fig. 27 ST411 or Fig.28 The ST421 process searches for a read parameter setting request. For example, instruction set CS7 is used to Fig. 27 ST413 or Fig.28The ST423 process searches for read requests. For example, instruction set CS8 is used to Fig. 27 ST415 or Fig.28 The output request of the valley position information is processed in ST425.

[0284] Instruction set CS4 includes, for example, "cch", "ADD(LUN)", "ADD(BBh)", and "DAT2". "cch" is an instruction requesting a change in the search read parameters. "ADD(BBh)" is the address of a register storing the setting of the start read level used for the search read. "DAT2" includes parameters corresponding to the newly set start read level of the search read. When "cch", "ADD(LUN)", "ADD(BBh)", and "DAT2" are received sequentially from the memory controller 1, the memory device 2 changes to a busy state and sets the parameter "DAT1" to the register specified by "ADD(LUN)" and "ADD(BBh)". When the setting of the parameters is completed, the memory device 2 changes to a ready state. Time tFEAT represents the time for the memory device 2 to execute processing based on the instruction set CS4.

[0285] Instruction set CS5 has a structure in which "ADD(BBh)" is replaced by "ADD(CCh)" and "DAT2" is replaced by "DAT3" relative to instruction set CS4. "ADD(CCh)" is, for example, the address of a register storing the step value SSa of the search read and the number of first-half explorations (for example, the number of shift reads applying the step value SSa). "DAT3" includes, for example, parameters corresponding to the newly set step value SSa of the search read and the number of first-half explorations. When "cch", "ADD(LUN)", "ADD(CCh)", and "DAT3" are received in sequence from the memory controller 1, the memory device 2 sets the parameter "DAT3" to the register specified by "ADD(LUN)" and "ADD(CCh)".

[0286] Instruction set CS6 has a structure in which "ADD(BBh)" is replaced by "ADD(DDh)" and "DAT2" is replaced by "DAT4" with respect to instruction set CS4. "ADD(DDh)" is the address of a register that stores the step value SSb of the search read and the number of second-half explorations (for example, the number of shift reads using the step value SSb). "DAT4" includes parameters corresponding to the newly set step value SSb of the search read and the number of second-half explorations. When "cch", "ADD(LUN)", "ADD(DDh)", and "DAT4" are received sequentially from the memory controller 1, the memory device 2 sets the parameter "DAT4" to the register specified by "ADD(LUN)" and "ADD(DDh)".

[0287] Instruction set CS7 includes, for example, "ddh", "01h / 02h / 03h", "00h", "ADD(CUsel)", and "30h". "ddh" is an instruction requesting a search read. "ADD(CUsel)" is the address of the unit group CU of the object of the search read. "30h" is an instruction indicating the start of the read action. When "ddh", "01h / 02h / 03h", "00h", "ADD(CUsel)", and "30h" are received sequentially from the memory controller 1, the memory device 2 changes to a busy state and performs a search read of the page data specified by "01h / 02h / 03h" for the address specified by "ADD(CUsel)". When the search read is completed, the memory device 2 changes to a ready state. Time tR represents the time when the memory device 2 executes processing based on the instruction set CS7.

[0288] The instruction set CS8 includes, for example, "eeh" and "ADD (EEh)". "eeh" is an instruction requesting output of data stored in a register. "ADD (EEh)" is an instruction requesting output of data stored in a register. Fig. 27 ST414 or Fig.28 The memory device 2 receives the detection search number and the adjustment coefficient of the register specified by the search of ST424. When receiving "eeh" and "ADD (EEh)" from the memory controller 1 in sequence, the memory device 2 outputs the detection search number and the adjustment coefficient stored in the register specified by "ADD (EEh)" to the memory controller 1. Fig. 27 ST414 and Fig.28 In ST424, the detection search number and the adjustment coefficient may be stored in the same register or in different registers.

[0289] According to the type of search reading parameters set, Fig. 27 ST411 or Fig.28 In the process of ST421, only part of the instruction sets CS4 to CS6 may be used. When a read operation targeting a plurality of states is executed, an instruction set CS for setting a shift read parameter may be issued for each state.

[0290] (5: Specific example of search and read operation)

[0291] Fig.31 1 is a diagram showing a specific example of a voltage applied to a word line WL selected as a target of a search read in the search read of the memory system MS according to the fourth embodiment. Fig.31 In the graph shown, the horizontal axis represents time and the vertical axis represents the voltage applied to the selected word line WL. This example shows the case where a search read using 7 read levels is performed for each state. Fig.31As shown, in the search read of this example, the search read targeting the S0-S1 state (S0-S1 state tracking) and the search read targeting the S4-S5 state (S4-S5 state tracking) are successively executed.

[0292] In the S0-S1 state tracking, the read levels RL1(1) to RL1(7) are sequentially applied to the selected word line WL. The read levels RL1(1) to RL1(7) correspond to the seven read levels corresponding to the S0-S1 state tracking. The sequencer 24 asserts the control signal STB in each of the multiple periods in which the read levels RL1(1) to RL1(7) are applied, so that the sense amplifier module 29 determines the data. In the S0-S1 state tracking, the switching point of the step values ​​SSa and SSb is set between the read levels RL1(4) and RL1(5). In addition, the step value set in the S0-S1 state tracking is set to SSb>SSa.

[0293] In the S4-S5 state tracking, the read levels RL5(1) to RL5(7) are sequentially applied to the selected word line WL. The read levels RL5(1) to RL5(7) correspond to the seven read levels corresponding to the S4-S5 state tracking. The sequencer 24 asserts the control signal STB in each of the multiple periods in which the read levels RL5(1) to RL5(7) are applied, so that the sense amplifier module 29 determines the data. The step value of the S4-S5 state tracking is set to SSa=SSb based on the symmetry of the S4-S5 state. That is, in the S4-S5 state tracking, multiple different step values ​​are not applied, but one step value is used.

[0294] (6: Specific example of search and read processing)

[0295] Fig.32 It is a schematic diagram showing a specific example of a process of estimating an optimum read level in Vth tracking of the memory system MS according to the fourth embodiment. Fig.32 The threshold voltage distribution of adjacent states (S(L-1) state and S(L) state) and the search read process are shown. The search number (SN) indicates the number of shift reads in the search read. The search number (0) corresponds to the start point of the search read. In the shift read at the start point of the search read, the start read level is used.

[0296] like Fig.32As shown, in this example, a search read using 8 read levels is performed. And, the switching point of the step values ​​SSa and SSb is set between the search numbers (4) and (5). The parameters used for the search read are the start point offset SPO (Start Point Offset), the step values ​​SSa and SSb, and the number of explorations (Searching Counts) in the first half and the second half. In addition, the information output by the memory device 2 based on the result of the search read is the detected search number (Detected Search Number) and the adjustment coefficient (Adjustment Coefficient). The following is a specific example of the processing of the search read.

[0297] First, based on the preset read level DRL, the read operation is started from the position specified by the start point offset SPO (that is, the start read level). Next, the read operation after the read level is shifted is performed by the number of explorations. Specifically, in the first half of the number of explorations, the read operation is performed to shift the read level by each step value SSa. Then, in the second half of the number of explorations, the read operation is performed to shift the read level by each step value SSb. In addition, here, the preset read level DRL, the start point offset SPO, and the step values ​​SSa and SSb are specified by the DAC value.

[0298] Next, the difference BC of the number of cells turned on in the continuous readout operation is calculated. Next, the search number corresponding to the smallest difference BC(best) is obtained as the detection search number. For example, when the readout operation under the starting point offset SPO corresponds to the search number (0), and the difference between the search number (4) and the search number (5) is BC(best), the detection search number becomes (4). Next, the internal point calculation is performed using the differences BC(prev) and BC(next) before and after the difference BC(best), and the calculation result is obtained as the adjustment coefficient. The adjustment coefficient is calculated, for example, by the following formula (1).

[0299] [Number 1]

[0300]

[0301] The optimal read level (RTRK) obtained by the search read can be estimated based on the following formula (2) or formula (3). In addition, formula (2) is used when the step value corresponding to the difference BC (best) is SSa, and formula (3) is used when it is SSb. Specifically, if it is assumed that the step value between search numbers (3) and (4) is SSa, the step value between search numbers (4) and (5) is SSb, and the step value between search numbers (5) and (6) is SSb, then formula (2) is used when the difference between search numbers (3) and search numbers (4) is BC (best), and formula (3) is used when the difference between search numbers (4) and search numbers (5) is BC (best).

[0302] [Number 2]

[0303] RTRK=(DRL+SPO)+(Detected Search Number*SSa)+(Ad justment Coefficient *SSa) (2)

[0305] [Number 3]

[0306] RTRK=(DRL+SPO)+(Detected Search Number*SSa)+(Adjustment Coefficient*SSb) (3)

[0308] For example, when DRL=30DAC, SPO=-20DAC, SSa=4DAC, adjustment coefficient (AdjustmentCoefficient)=1 / 2, detected search number (Detected Search Number)=2, and the step value corresponding to the difference BC(best) is SSa, RTRK is (30-20)+(2*4)+(1 / 2*4)=20DAC.

[0309] The start point offset SPO used for the search read (e.g. in the reference Fig.26 The starting read level used in the processing of step ST404 described above can be adjusted based on the following formula (4). In addition, RTRK (#0) is the valley position obtained by the search read processing using the search read parameters with the step value SSa and the step value SSb being equal (for example, in reference Fig.26 The optimum read level estimated in the process of step ST402 described above).

[0310] [Number 4]

[0311]

[0312] For example, when RTRK(#0)=20DAC, SSa=4DAC, Searching Counts=10, and DRL=30DAC, SPO becomes 20-(4*10*1 / 2)-30=-30DAC.

[0313] <4-3> Effects of the Fourth Embodiment

[0314] As described above, in the memory system MS of the fourth embodiment, a plurality of combinations of step values ​​SSa and SSb are prepared in advance. Furthermore, in the case where error correction of page data read using the optimal read level estimated based on the search read fails, the memory system MS of the fourth embodiment changes the search read parameters in the order of the index values ​​and retries the shift read. As a result, the memory system MS of the fourth embodiment can improve the accuracy of estimating the optimal read level in Vth tracking. Therefore, the memory system MS of the fourth embodiment can reduce the number of error bits and obtain higher reliability.

[0315] Furthermore, in the memory system MS of the fourth embodiment, after the valley position (that is, the optimal read level) is estimated by the search read using one step value, the switching point of the step values ​​SSa and SSb of the search read is made to coincide with the valley position. Thus, the memory system MS of the fourth embodiment can improve the estimation accuracy of the optimal read level based on Vth tracking, and can improve reliability.

[0316] Furthermore, in the memory system MS of the fourth embodiment, the memory device 2 can perform a read operation using a plurality of read levels based on a search read request received from the memory controller 1. Therefore, in the memory system MS of the fourth embodiment, the exchange of commands and the like between the memory controller 1 and the memory device 2 required for Vth tracking can be reduced compared to the first to third embodiments. Therefore, the memory system MS of the fourth embodiment can improve performance more than the first to third embodiments.

[0317] In addition, in the fourth embodiment, although the case of setting two step values ​​SSa and SSb has been illustrated, three or more step values ​​may be set in the search read. The switching point of the step values ​​SSa and SSb is not limited to the center of the number of explorations, and may be switched outside the center of the number of explorations. The various formulas described in the fourth embodiment are only examples. Coefficients or offsets may also be added in accordance with the characteristics of the memory cell transistor MT. The starting point of the search read can be appropriately changed based on the specified information. A fixed value may also be selected as the starting point of the search read.

[0318] <5>Others

[0319] The functional configuration of the memory controller 1 described in the second to fourth embodiments can be realized by firmware executed by the CPU 12 in the hardware configuration of the memory controller 1 described in the first embodiment. The functional configuration of the memory device 2 described in the second to fourth embodiments can be realized by the function assigned to the sequencer 24 in the hardware configuration of the memory device 2 described in the first embodiment. An MPU (Micro Processing Unit) can also be used instead of the CPU 12. In addition, each process described in the above embodiments can be realized by a dedicated hardware circuit, a processor that executes a program (firmware), or a combination thereof.

[0320] The instruction sequence described in the above embodiment is only an example. The address information (ADD) sent from the memory controller 1 to the memory device 2 may be one cycle or multiple cycles.

[0321] The flowchart used for explanation in the above-mentioned embodiment is only an example. The order of each process described using the flowchart can also be replaced within a possible range. Other processes can be added to the processes shown in the flowchart, and some processes can also be omitted.

[0322] In this specification, "connection" means electrical connection, and does not exclude the presence of another element therebetween. "Electrical connection" may be interposed with an insulator as long as it can operate in the same manner as electrical connection. Word lines WL, select gate lines SGD and SGS, etc. may also be referred to simply as "wiring".

[0323] A high-level voltage is a voltage that turns an N-type transistor into an on state when a voltage of the level is applied to the gate. A low-level voltage is a voltage that turns an N-type transistor into an off state when a voltage of the level is applied to the gate. In this specification, applying a voltage to a word line WL corresponds to the driver circuit 26 applying a voltage to the word line WL via the row decoder module 27. As for applying a voltage to other wirings, it corresponds to the driver circuit 26 applying a voltage via the row decoder module 27, similarly to the word line WL. The voltage of each wiring can also be estimated based on the voltage of the signal line connecting the driver circuit 26 and the row decoder module 27.

[0324] Although several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in many other ways, and can be omitted, replaced, or changed in many ways without departing from the scope of the invention. These embodiments or their variations are included in the scope or spirit of the invention, and are also included in the invention described in the claims and their equivalents.

Claims

1. A memory system comprising: A memory device comprising a plurality of memory cells configured to nonvolatilely store data including at least a first value and a second value, respectively, according to a threshold voltage, wherein the first value corresponds to the threshold voltage included in a first voltage range, and the second value corresponds to the threshold voltage included in a second voltage range different from the first voltage range; and a memory controller configured to write the data of the first value into each of the plurality of first storage cells among the plurality of storage cells; writing the data of the second value into each of the plurality of second storage cells among the plurality of storage cells, determining a first voltage based on information about a gradient of the threshold voltage distribution of each of the plurality of memory cells, The following tracking operation is performed: taking the plurality of memory cells as objects, within a third voltage range including at least a portion of the first voltage range and at least a portion of the second voltage range, causing the memory device to perform a plurality of read operations using a plurality of read levels, and obtaining the number of memory cells that are turned on, that is, the number of turned-on cells, among the plurality of memory cells in each of the plurality of read operations; and The memory controller is further configured to, during the tracking operation, A first voltage difference between two adjacent read levels among the multiple read levels within a fourth voltage range in the third voltage range that is lower than the first voltage, and a second voltage difference between two adjacent read levels among the multiple read levels within a fifth voltage range in the third voltage range that is higher than the first voltage are set to be different from each other.

2. The memory system according to claim 1, wherein The memory controller is further configured as follows: detecting that the gradient of the threshold voltage distribution in the fourth voltage range is steeper than the gradient of the threshold voltage distribution in the fifth voltage range, and Based on the detection, the first voltage difference is set to be smaller than the second voltage difference.

3. The memory system according to claim 1, wherein The memory controller is further configured as follows: In a sixth voltage range including at least a portion of the first voltage range and at least a portion of the second voltage range, the memory device is caused to perform a plurality of read operations using a plurality of read levels, and the number of the turned-on cells is obtained in each of the plurality of read operations. obtaining a difference in the number of the on cells for each group of two reads using two adjacent read levels among the plurality of read levels within the sixth voltage range, and A seventh voltage range in which the difference decreases as the read level increases and an eighth voltage range in which the difference increases as the read level increases are detected, and the first voltage is determined based on a voltage range between the seventh voltage range and the eighth voltage range.

4. The memory system of claim 3, wherein The memory controller is further configured as follows: obtaining a plurality of said differences, obtaining a first difference between a minimum difference among the plurality of differences and a previous difference, and a second difference between the minimum difference and a subsequent difference, When a third difference, which is a difference between the first difference and the second difference, is smaller than a first threshold value, the first voltage difference and the second voltage difference are determined based on the third difference.

5. The memory system of claim 4, wherein The memory controller is further configured as follows: When the third difference is equal to or greater than the first threshold, at least one of the plurality of read levels within the third voltage range is changed, and the tracking operation is performed.

6. The memory system of claim 3, wherein The memory controller is further configured as follows: obtaining a plurality of said differences, calculating a first difference between a minimum difference among the plurality of differences and a previous difference, and a second difference between the minimum difference and a subsequent difference, obtaining a ratio of the first difference to the second difference, and When the ratio is larger than a second threshold value and smaller than a third threshold value, the first voltage difference and the second voltage difference are determined according to the ratio.

7. The memory system of claim 6, wherein The memory controller is further configured as follows: When the ratio is lower than the second threshold value or the ratio is equal to or greater than the third threshold value, at least one of the plurality of read levels within the third voltage range is changed and the tracking operation is performed.

8. The memory system of claim 1, wherein The information is a voltage value belonging to the first voltage range and a voltage value belonging to the second voltage range.

9. The memory system of claim 1, wherein The information is any one of the positions of the plurality of storage cells in the memory device, the number of reads, the time elapsed after data is written, and the number of writes and erases.

10. A memory system comprising: A memory device comprising a plurality of memory cells configured to nonvolatilely store data including at least a first value and a second value, respectively, according to a threshold voltage, wherein the first value corresponds to the threshold voltage included in a first voltage range, and the second value corresponds to the threshold voltage included in a second voltage range different from the first voltage range; and The memory controller is configured to write data of the first value to each of the plurality of first memory cells among the plurality of memory cells, write data of the second value to each of the plurality of second memory cells among the plurality of memory cells, and perform the following tracking operations multiple times: taking the plurality of memory cells as objects, within a third voltage range including at least a portion of the first voltage range and at least a portion of the second voltage range, causing the memory device to perform multiple read operations using multiple read levels, and obtaining the number of memory cells that are turned on, that is, the number of turned-on cells, among the plurality of memory cells in each of the multiple read operations, estimating the gradient of the threshold voltage distribution based on the number of the on cells obtained in a first tracking operation among the plurality of tracking operations, determining a first voltage based on the estimated gradient, and In the second tracking action performed after the first tracking action in the multiple tracking actions, a first voltage difference between two adjacent read levels among the multiple read levels within a fourth voltage range lower than the first voltage in the third voltage range and a second voltage difference between two adjacent read levels among the multiple read levels within a fifth voltage range higher than the first voltage in the third voltage range are set to be different from each other.

11. The memory system of claim 10, wherein The memory controller is further configured as follows: In the first tracking operation, voltage differences between two adjacent read levels among the plurality of read levels within the third voltage range are set equal to each other.

12. The memory system of claim 10, wherein The memory controller is further configured as follows: A voltage difference between two adjacent read levels among the plurality of read levels within the third voltage range of the first tracking operation and a voltage difference between two adjacent read levels among the plurality of read levels within the third voltage range of the second tracking operation are set to be different from each other.

13. The memory system of claim 10, wherein The memory controller is further configured as follows: A plurality of the first voltage differences that can be used for the second tracking operation are managed.

14. The memory system of claim 13, wherein The memory controller is further configured as follows: The first voltage difference used for the second tracking operation is determined from the plurality of managed first voltage differences based on any one of the number of readouts, the elapsed time after data writing, and the number of write and erase times.

15. A memory device comprising: a memory cell configured to nonvolatilely store data including at least a first value and a second value according to threshold voltages, wherein the first value corresponds to the threshold voltage included in a first voltage range, and the second value corresponds to the threshold voltage included in a second voltage range different from the first voltage range; and The peripheral circuit is configured to write the data of the first value into each of the plurality of first storage cells among the plurality of storage cells, write the data of the second value into each of the plurality of second storage cells among the plurality of storage cells, and perform the following search reading: taking the plurality of storage cells as objects, within a third voltage range including at least a part of the first voltage range and at least a part of the second voltage range, perform a plurality of read operations using a plurality of read levels, and in each of the plurality of read operations, obtain the number of storage cells that are turned on, that is, the number of turned-on cells among the plurality of storage cells; and The peripheral circuit is further configured such that, in the search read, A first voltage difference between two adjacent read levels among the multiple read levels within a fourth voltage range that is lower than the first voltage in the third voltage range and a second voltage difference between two adjacent read levels among the multiple read levels within a fifth voltage range that is higher than the first voltage in the third voltage range are set to be different from each other.

16. The memory device of claim 15, wherein The peripheral circuit is further configured as follows: obtaining a difference in the number of the ON cells for each group of two reads using two adjacent read levels among the plurality of read levels within the third voltage range, and The obtained difference is output to the outside.

17. The memory device of claim 16, wherein The peripheral circuit is further configured as follows: obtaining a plurality of said differences, Information on the read level corresponding to the smallest difference among the plurality of differences is output to the outside.

18. The memory device of claim 17, wherein The peripheral circuit is further configured as follows: An internal division point calculation is performed using differences before and after the smallest difference among the plurality of differences, and a result of the internal division point calculation is output to the outside.

19. A memory system comprising: The memory device according to claim 15; and The memory controller is configured to request the memory device to change the setting of the search read parameter and to execute the search read.

20. The memory system of claim 19, wherein The peripheral circuit is further configured as follows: outputting the search read result to the memory controller; and The memory controller is further configured as follows: calculating a first read voltage based on the result of the search reading, instructing the memory device to perform a read operation using the first read voltage, performing error correction of the data read out by the first reading operation, When the error correction fails, the memory device is requested again to execute the search read after changing at least one of the first voltage difference and the second voltage difference.

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