Memory device, memory circuit and operating method thereof

Abstract

The invention discloses a memory device, a memory circuit and an operating method thereof. In one aspect, a memory device includes a memory cell coupled between a first bit line and a second bit line. The memory cell includes a write circuit configured to write data to the memory cell via the first bit line and the second bit line during a write operation. The memory cell includes a voltage equalization device configured to equalize voltages of the first bit line and the second bit line after a write operation and before a second memory operation of the memory cell.

Description

Technical Field

[0001] Embodiments of the present application relate to a memory device, a memory circuit, and an operating method thereof. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In large part, the increase in integration density comes from the repeated reduction in the minimum feature size, which allows more components to be integrated into a given area. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a memory device is provided, including: a memory cell coupled between a first bit line and a second bit line; a write circuit configured to write data to the memory cell via the first bit line and the second bit line during a write operation; and a voltage equalization device configured to equalize the voltages of the first bit line and the second bit line after a write operation and before a read operation of the memory cell.

[0004] According to another aspect of an embodiment of the present application, a memory circuit is provided, comprising: a first bit line and a second bit line, coupled to a memory cell; and a first transistor, connected in parallel with the memory cell, a first source / drain terminal of the first transistor coupled to the first bit line, a second source / drain terminal of the first transistor coupled to the second bit line, and a gate terminal of the first transistor receiving a voltage equalization signal, the voltage equalization signal being configured to equalize the voltages of the first bit line and the second bit line between memory operations.

[0005] According to another aspect of an embodiment of the present application, a method for operating a memory device is provided, including: precharging a first bit line and a second bit line coupled to a memory cell; performing a first memory operation on the memory cell; equalizing the voltages of the first bit line and the second bit line of the memory cell after the first memory operation and before the second memory operation; and after equalizing the voltages of the first bit line and the second bit line, performing a second memory operation on the memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A schematic diagram is shown of an example memory circuit having a device for equalizing bit line voltages during double pumped memory operation in accordance with some embodiments.

[0008] Figure 2 shows that during dual pump storage operation, the Figure 1 Graphs of example waveforms of signals propagated by a memory circuit are shown.

[0009] Figure 3 A diagram showing an example memory circuit with two complementary devices that equalize bit line voltages during double pumped memory operation in accordance with some embodiments.

[0010] Figure 4 A diagram of an example memory circuit having a device to equalize bit line voltages during double pumped memory operation and a voltage clamping device coupled to each bit line in accordance with some embodiments.

[0011] Figure 5 According to some embodiments, Figure 4 The memory circuit shown is similar to a diagram of an example memory circuit having complementary devices that equalize bit line voltages during memory operations.

[0012] Figure 6 According to some embodiments, Figure 4 Schematic diagram of an example memory circuit similar to the memory circuit shown, with a voltage clamping device coupled to each bit line that receives a clamping voltage.

[0013] Figure 7 According to some embodiments, Figure 6 The memory circuit shown is similar to a diagram of an example memory circuit having complementary devices that equalize bit line voltages during memory operations.

[0014] Figure 8 Schematic diagram of an example memory circuit including an alternative arrangement of voltage clamping devices according to some embodiments is shown.

[0015] Fig. 9 A graph showing example waveforms of signals during another double pump memory operation is shown in accordance with some embodiments.

[0016] Fig.10 A flow chart illustrating an example method of operating an example memory circuit to achieve voltage equalization of an intermediate pre-charge during double pumped memory operation in accordance with some embodiments. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0018] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0019] Memory circuits, such as dynamic random access memory (DRAM), can implement "double pumping" operation, in which multiple memory operations are performed in a single clock cycle. For example, a write operation after a read operation or a read operation after a write operation can be performed in a single memory clock cycle instead of two clock cycles. In traditional memory systems, double pumping operation requires precharging the bit lines of the memory circuit between operations. Precharging involves raising the voltage level of the selected bit line to approximately the power supply voltage level. However, this traditional approach results in excessive power consumption. As the density and performance requirements of semiconductor technology increase, double pumping using this approach has become technically impractical.

[0020] The present disclosure provides various techniques for implementing low-power intermediate precharge operations. This technique does not require precharging the voltage level of the selected bit line to about the power supply voltage. Instead, the techniques described herein implement a circuit that skips the precharge of the bit line pair between the first and second memory operations of the dual pump operation. To this end, the various circuits described herein equalize the voltage between the bit line pairs during the intermediate precharge to ensure a stable margin for the operation of the memory cell. These techniques reduce the overall power consumption of the memory circuit, thereby enabling higher density memory circuits to be implemented on smaller process nodes.

[0021] Figure 1A schematic diagram of an example memory circuit 100 with a device for equalizing bit line voltages during dual pump memory operation according to some embodiments is shown. The memory circuit 100 may be included in any type of memory device or integrated circuit (IC) device. In at least one embodiment, the memory device is a separate IC device. In some embodiments, the memory device is included as part of a larger IC device that includes circuits outside of the memory device for other functions.

[0022] Each component shown in the memory circuit 100 can receive power from one or more voltage sources (for example, the power supply voltage shown here is VDD). The memory circuit 100 may include one or more logic gates and subcircuits, each of which may be composed of one or more logic gates. A logic gate is an electronic device that performs a logical operation on one or more input signals to produce a single output signal.

[0023] Various embodiments of the circuits and logic gates implementing the memory circuit 100 may include various transistors. The transistors described herein may be of a certain type (n-type or p-type), but the embodiments are not limited thereto. The transistor may be any suitable type of transistor, including but not limited to a metal oxide semiconductor field effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS) transistor, a p-type metal oxide semiconductor (PMOS), an n-type metal oxide semiconductor (NMOS), a bipolar transistor (BJT), a high voltage transistor, a high frequency transistor, a p-channel and / or n-channel field effect transistor (PFET / NFET), a fin field effect transistor (FinFET), a planar metal oxide semiconductor transistor with a raised source / drain, a nanosheet field effect transistor, a nanowire field effect transistor, etc.

[0024] It should be understood that although Figure 1 The memory circuit 100 shown in the figure can be part of a larger memory circuit, including any number of bit line BL and BLB pairs, which can be addressed by corresponding memory cell selection circuits. Likewise, although not shown here for visual clarity, various additional circuits can be included to address (e.g., select) various portions of memory cells or perform different memory operations, including but not limited to computation in memory (CIM) operations, write operations, or read operations, etc.

[0025] The memory circuit 100 is shown to include at least one memory cell 112 located between a pair of bit lines BL and BLB. The memory cell 112 can be any type of memory device capable of storing at least one bit of memory data, including but not limited to a static random access memory (SRAM) cell or a dynamic random access memory (DRAM) cell, etc. In some implementations, the bit lines BL and BLB and the memory cells 112 therebetween can be included as part of a column of a memory array. In such an implementation, a plurality of memory cells 112 can be arranged in a plurality of rows and coupled to each of the bit lines BL and BLB. The memory array can include a plurality of columns, each column including a set of corresponding bit lines having a plurality of memory cells 112 coupled thereto.

[0026] Individual memory cells 112 of the memory array can be addressed by accessing corresponding bit lines BL and BLB (selected by column) and / or corresponding word lines or source lines (selected by row). The addressed memory cells can be selected for write and / or read operations. The memory array can be implemented for dual pump operation, where multiple memory operations can be performed in a single memory clock cycle. Signals for selecting memory cells and coordinating read / write / dual pump operations can be provided by a memory control circuit. The memory control circuit can include any type of control circuit that provides signals to coordinate read or write operations through the circuits of the memory circuit 100. The memory control circuit can provide any of the signals described herein to control the functions of the memory circuit 100.

[0027] The memory circuit 100 is shown as receiving a write clock (WCLK) signal. The WCLK signal is a timing signal that controls the timing of write operations in the memory circuit 100. During a write operation, the WCLK signal causes data to be written to the memory cell at the correct time and is synchronized with other signals and processes within the memory circuit 100. As shown, the WCLK signal is provided as an input to an inverter 102, which generates a WCLKB signal. As used herein, a signal appended with a "B" is the logical inversion of the same signal without the "B" suffix. In the case where the corresponding signal without the "B" suffix does not exist or is not referenced, the "B" suffix can indicate that the corresponding signal is a low-level active signal (e.g., valid in a logical low, logical zero, or ground state).

[0028] As shown in the memory circuit 100, the circuit 100 includes seven transistors M1, M2, M3, M4, M5, M6 and M7, each of which implements a portion of the circuit to perform low-power dual pump operation. Although each transistor M1-M7 shown is shown as a transistor, the embodiment is not limited thereto. For example, each transistor may include multiple transistors ("sub-transistors") connected in parallel to each other. For example, in one embodiment, each sub-transistor of any transistor described herein may include respective gate, drain and source terminals, each of which may be connected in parallel to each other.

[0029] Circuit 100 includes transistors M1, M2, M3, M4, M5, M6, and M7. In some embodiments, transistors M1, M2, M3, M4, and M5 each include a pMOSFET, and transistors M6 and M7 each include an nMOSFET. It should be understood that each of transistors M1-M7 may include any of various other types of transistors (e.g., bipolar junction transistors, high electron mobility transistors, etc.) while still within the scope of the present disclosure. As shown, the sources of transistors M1, M2, M4, and M5 are electrically coupled to a power supply voltage VDD, and the sources of transistors M6 and M7 are connected to a ground voltage. The drains of transistors M4 and M5 are connected to the drains of transistors M6 and M7, respectively. The drain terminals of transistors M4 and M6 are coupled to a first bit line BL, and the drain terminals of transistors M5 and M7 are coupled to a second bit line BLB. The drain terminals of transistors M1 and M2 are coupled to bit lines BL and BLB, respectively.

[0030] Transistors M1 and M2 can be activated during a precharge operation to set the voltage level of bit lines BL and BLB to about the power supply voltage VDD. As shown, the gate terminals of transistors M1 and M2 are coupled to each other and receive an effective low bit line precharge signal BLPREB. When the BLPREB signal is logic high (e.g., logic 1, a power supply voltage of about VDD, etc.), each of transistors M1 and M2 is turned off and does not conduct. Therefore, in this state, the voltage of bit lines BL and BLB is set according to other circuit elements (e.g., transistors M4 and M6, transistors M5 and M7, etc.).

[0031] When the BLPREB signal is logic low (e.g., logic zero, approximately equal to ground voltage, etc.), each of transistors M1 and M2 is turned on. When transistor M1 is turned on, the voltage at the first bit line BL is set to approximately the power supply voltage VDD. When transistor M2 is turned on, the voltage at the second bit line BLB is set to approximately the power supply voltage VDD. Figure 2As described, the BLPREB signal may be maintained at a logic low state (eg, by memory control circuitry) until the bit lines are sufficiently precharged (eg, after a predetermined amount of time). The precharge operation may be performed prior to a read and / or write operation, including prior to a double pumping operation.

[0032] Prior to a read operation, the bit lines BL and BLB are precharged to a reference voltage. This prepares the bit lines to sense and amplify the voltage changes caused by the memory cell during a read operation. Similarly, prior to a write operation, the bit lines are precharged to a reference voltage level. This ensures that there is a clear starting point for the voltage difference that will be sensed during a subsequent write operation. However, during a double pump operation, transistor M3 may be activated as part of an intermediate precharge, rather than a full precharge, to equalize the voltages of the first and second bit lines.

[0033] The transistor M3 has a first source / drain terminal coupled to the first bit line BL and a second source / drain terminal coupled to the second bit line BLB. In this example, the transistor M3 may have a gate terminal that receives a bit line voltage equalization signal indicated as BLEQB (shown as a low level). Figure 2 As described, the equal voltage of the first bit line BL and the second bit line BLB can be set to be less than the power supply voltage VDD, but greater than the ground voltage of the memory circuit. As shown, the transistor M3 is connected in parallel with the memory cell 112. In this example, the source / drain terminals of the transistor M3 are also coupled to the corresponding source / drain terminals of the transistors M1 and M2, respectively. Although the transistor M3 is shown as a p-type device, it should be understood that any suitable transistor device can be used, including but not limited to an n-type device.

[0034] Each of the first bit line BL and the second bit line BLB is shown as including a write circuit. The first write circuit includes a NAND (NAND) gate 104, a NOR (NOR) gate 108, a transistor M4, and a transistor M6. The gate terminal of transistor M4 is coupled to the output of the NAND gate 104, and the gate terminal of transistor M6 is connected to the output of the NOR gate 108. The NAND gate 104 receives the input data signal DATA as an input and receives the write clock signal WCLK as an input. The NOR gate 108 receives the input data signal DATA as an input and receives the logical inversion WCLKB of the write clock signal as an input. As described herein, the logical inversion WCLKB of the write clock signal can be generated by the inverter 102 as an output.

[0035] The input data signal DATA may be a logic high or logic low signal that indicates the bit to be written to the memory cell 112. For example, in some implementations, the input data signal DATA may be a logic high signal to indicate that a logic binary "1" value is to be written to the memory cell 112, and the input data signal DATA may be a logic low signal to indicate that a logic binary "0" value is to be written to the memory cell 112, and vice versa. In some implementations, the memory circuit 100 may include one or more inverters to generate the logical inversion of the data signal DATAB.

[0036] When the write clock signal WCLK is in a logic low state (e.g., a ground state, a logarithmic zero state, etc.), a read operation on the memory cell 112 is indicated. During the read operation, since the WCLK signal is logic low, the output of the NAND gate 104 is always logic high, regardless of the input data signal DATA. Therefore, during the read operation, the gate terminal of the p-type transistor M4 is provided with a logic high signal, causing the transistor M4 to be turned off and not conducting. Similarly, when the WCLK signal is logic low, the logical inversion WLKB of the write signal is logic high. When the WCLKB signal is logic high (e.g., logic 1 of approximately the power supply voltage VDD), the output of the NOR gate 108 is always logic low regardless of the input data signal DATA. When the output of the NOR gate 108 is provided to the gate terminal of the n-type transistor M6, the transistor M6 is turned off and does not conduct during the read operation.

[0037] The second write circuit for the second complementary bit line BLB includes a NAND gate 106, a NOR gate 110, a transistor M5, and a transistor M7. The gate terminal of the p-type transistor M5 is coupled to the output of the NAND gate 106, and the gate terminal of the n-type transistor M7 is connected to the output of the NOR gate 110. The NAND gate 106 receives the input data signal DATA as an input and receives the write clock signal WCLK as an input. The NOR gate 110 receives the input data signal DATA as an input and receives the logical inversion of the write clock signal WCLKB as an input.

[0038] As described herein, during a read operation, the write clock signal WCLK is in a logic low state (e.g., a ground state, a logarithmic zero state, etc.). When the WCLK signal is logic low, the output of the NAND gate 106 is always logic high, regardless of the input data signal DATA. Therefore, during a read operation, the gate terminal of the p-type transistor M5 is provided with a logic high signal, causing the transistor M5 to be turned off and not conducting. Similarly, when the WCLK signal is logic low, the logical inversion WLKB of the write signal is logic high. When the WCLKB signal is logic high (e.g., logic 1 of approximately the power supply voltage VDD), the output of the NOR gate 110 is always logic low regardless of the input data signal DATA. Since the output of the NOR gate 110 is provided to the gate terminal of the n-type transistor M7, the transistor M7 is turned off and does not conduct during a read operation.

[0039] Therefore, during a read operation, the first and second write circuits effectively do not change the voltages of the bit lines BL and BLB. Instead, the memory cell 112 coupled between the bit lines BL and BLB itself generates a voltage difference between the bit lines BL and BLB depending on its state. For example, if the memory cell 112 stores a charge (e.g., representing a logical 1), the memory cell 112 may discharge one of the bit lines BL or BLB, resulting in a voltage drop between the bit lines BL and BLB. As a further example, if the memory cell 112 does not store a charge (e.g., representing a logical 0), the bit lines BLB and BLB will maintain their precharge voltage levels. The differential sensing circuit may compare the voltages of the bit lines BL and BLB to determine the logic state of the memory cell 112 during a read operation. The difference in voltage levels may be amplified and used to generate an output signal indicating the stored data (e.g., a logical 0 or a logical 1).

[0040] During a write operation, the WCLK signal may be in a logic high state and its logical inversion WCLKB may be in a logic low state. The input data signal DATA may be in a logic low state, indicating that a logic 0 is to be written to the memory cell 112, or may be in a logic high state, indicating that a logic 1 is to be written to the memory cell 112. During a write operation, when the DATA signal is in a logic high state, the NAND gate receives two logic high signals (from WCLK and DATA) and produces a logic low output to the gate terminal of transistor M4. The logic low signal at the gate terminal of the p-type transistor M4 turns on and conducts. Further, the NOR gate 108 receives a logic high signal (DATA) and a logic low signal (WCLKB). Therefore, the output of the NOR gate 108 is a logic low signal, causing the n-type transistor M6 to be turned off and not conducting. When the transistor M4 is turned on, the power supply voltage VDD is then coupled to the bit line BL, causing the voltage of the bit line BL to rise to about the power supply voltage VDD.

[0041] Further illustrating an example where the input data signal DATA is in a logic high state during a write operation, the NAND gate 106 receives a logic high signal (WCLK) and a logic low signal (DATAB, the inverse of DATA). Therefore, the output of the NAND gate 106 provided to the gate terminal of transistor M5 is in a logic high state, causing transistor M5 to be turned off and not conducting. The NOR gate 110 receives two logic low signals (DATAB and WCLKB), causing the NOR gate 110 to generate and provide a logic high output to the gate terminal of transistor M7. The logic high at the gate terminal of transistor M7 causes transistor M7 to turn on and conduct, effectively coupling the second bit line BLB to ground (e.g., setting it to approximately zero). Therefore, during an operation of writing a logic 1 to the memory cell 112, the bit line BL can be set to approximately the power supply voltage and the complementary bit line BLB can be set to approximately the ground voltage.

[0042] When the input data signal DATA to be written to the memory cell 112 is a logic zero, the opposite of the above example can occur. For example, during a write operation, when DATA is in a logic low state, the output of the NAND gate 104 is a logic high, causing the transistor M4 to be turned off and not turned on, and the output of the NOR gate 108 is also a logic high, causing the transistor M6 to be turned on, thereby pulling the voltage of the bit line BL to about the ground voltage. Similarly, when DATA is in a logic low state during a write operation, the output of the NAND gate 106 is a logic low, causing the transistor M4 to be turned on, and the output of the NOR gate 110 is a logic low, causing the transistor M7 to be turned off and turned on, thereby pulling the voltage of the complementary bit line BLB to about the power supply voltage. Therefore, during the operation of writing a logic 0 to the memory cell 112, the bit line BL can be set to about the ground voltage, and the complementary bit line BLB can be set to about the power supply voltage. The voltage difference between BL and BLB causes the memory cell 112 to store the data in the input data signal DATA.

[0043] Figure 2 A diagram 200 is shown showing that during dual pump reservoir operation, the Figure 1 200. The example waveforms shown in the diagram 200 represent a double pumping operation that may occur within a single memory clock cycle in some implementations. The double pumping operation includes a read operation during a time period 202, a voltage equalization during a time period 204, and a write operation during a time period 206 after the voltage equalization.

[0044] In this example, the bit lines (e.g., BL and BLB) of the memory cell are precharged before the operation by setting the effective low precharge signal BLPREB to a logic low before the time period 202, thereby initializing the double pump operation. This makes the bit lines BL and BLB approximately equal to the power supply voltage VDD, as shown. During the read operation, the word line WL selection signal of the corresponding memory cell (e.g., memory cell 112) is a logic high, causing the memory cell to be selected for the read operation. At the same time, the effective low precharge signal BLPREB is converted to a logic high state, disabling the precharge operation. The effective low voltage equalization signal BLEQB is also driven to a logic high state, thereby disabling the voltage equalization between the bit lines BL and BLB.

[0045] Since the first operation is a read operation, the logical inversion of the write clock WCLKB remains in a logic high state, indicating a read operation. During time period 202, as shown, as the memory cell discharges, the voltages of the bit lines BL and BLB deviate slightly, indicating that the memory cell stores a logic 1. As described herein, after the precharge operation, the voltage of the bit line does not change during the read operation, causing any charge stored in the memory cell to change the voltage difference between the bit lines BL and BLB. The voltage difference between the bit lines BL and BLB can be amplified to detect the data stored in the memory cell.

[0046] After the read operation, the word line select signal WL can return to a logic low state, while the active low precharge signal BLPREB and the logical inversion of the write clock WCLKB remain in a logic high state. However, the active low voltage equalization signal BLEQB is pulled to a logic low state instead of performing a second precharge operation. As shown, during the dual pump equalization period 204, the voltage equalization device (e.g., transistor M3) makes the voltage between the bit lines BL and BLB approximately equal, at a voltage level Vequ. As shown, the voltage level Vequ is less than the power supply voltage VDD, but greater than the ground voltage.

[0047] Once the voltage is equalized within time period 204, a write operation is performed as the second operation in the dual pump operation. As shown, during time period 206, the word line WL select signal for the corresponding memory cell (e.g., memory cell 112) is set to a logic high, causing the memory cell to be selected for the write operation. At the same time, the effective low voltage equalization signal BLEQB is changed to a logic high state, disabling voltage equalization. The effective low precharge signal BLPREB remains in a logic high state. During the time period 206 of the write operation, the logic inversion WCLKB of the write clock is changed to a logic low state, indicating a write operation.

[0048] As shown, during the duration 206 of the write operation, the voltages of the bit lines BL and BLB deviate, with one bit line transitioning to approximately the power supply voltage VDD and the other complementary bit line transitioning to approximately the ground voltage. Once the write operation is completed after the time period 206, the precharge for the next operation can be initiated by transitioning the word lines WL, BLEQB, and BLPREB to a logic low state while transitioning the logical inversion of the write clock WCLKB to a logic high state. This results in both bit lines of the memory cell being set to approximately the power supply voltage for the next set of operations, as shown. Fig. 9 , similar waveforms are provided for double pumping operation starting from a write operation.

[0049] Reference Fig. 9 , shows a diagram 900 illustrating example waveforms of signals during another dual pump memory operation according to some embodiments. The example waveforms shown in diagram 900 represent a dual pump operation that may occur during a single memory clock cycle in some implementations. The dual pump operation includes a write operation during time period 902, voltage equalization during time period 904, and a read operation during time period 906 after voltage equalization.

[0050] In this example, the bit lines (e.g., BL and BLB) of the memory cells are precharged before the operation by setting the effective low precharge signal BLPREB to a logic low before the time period 902, thereby initializing the double pump operation. This makes the bit lines BL and BLB approximately equal to the power supply voltage VDD, as shown. During the first write operation, the word line WL selection signal for the corresponding memory cell (e.g., memory cell 112) is set to a logic high, causing the memory cell to be selected for the write operation. At the same time, the effective low precharge signal BLPREB is converted to a logic high state, disabling the precharge operation. The effective low voltage equalization signal BLEQB is also driven to a logic high state, thereby disabling the voltage equalization between the bit lines BL and BLB.

[0051] Since the first operation is a write operation, the logical inversion of the write clock WCLKB is set to a logic low state, indicating a write operation. During time period 902, as shown, the voltage of the bit line deviates to VDD and ground (e.g., based on the state of the input data signal), resulting in the input data being written to the memory cell. As described herein, one of the bit lines BL and BLB is set to a logic high and the other is set to a logic low, resulting in the circuit components (e.g., capacitors) of the memory cell being charged or discharged to store data.

[0052] After the write operation, the word line select signal WL can return to a logic low state, while the effective low precharge signal BLPREB remains in a logic high state, and the logic inversion WCLKB of the write clock is driven to a logic high state. However, the effective low voltage equalization signal BLEQB is pulled to a logic low state instead of performing a second precharge operation. As shown, during the dual pump equalization time period 904, this causes the voltage equalization device (e.g., transistor M3) to set the voltage between the bit lines BL and BLB to an approximately equal voltage level Vequ. As shown, the voltage level Vequ is less than the power supply voltage VDD, but greater than the ground voltage.

[0053] Once the voltages are equalized within time period 904, a read operation is performed as the second operation in the dual pump operation. As shown, during time period 906, the word line WL select signal for the corresponding memory cell (e.g., memory cell 112) is set to a logic high, causing the memory cell to be selected for the read operation. At the same time, the effective low voltage equalization signal BLEQB is transformed into a logic high state, disabling voltage equalization. The effective low precharge signal BLPREB remains in a logic high state. During time period 906 for the read operation, the logical inversion WCLKB of the write clock remains in a logic high state, indicating a write operation.

[0054] As shown, as the memory cell discharges, the bit lines BL and BLB deviate slightly, indicating that the memory cell stores a logic 1. As described herein, after the precharge operation, the voltage of the bit lines does not change during the read operation, causing any charge stored in the memory cell to change the voltage difference between the bit lines BL and BLB. The voltage difference between the bit lines BL and BLB can be amplified to detect the data stored in the memory cell. Once the read operation is completed after time period 906, the precharge for the next operation can be initiated by transitioning the word lines WL, BLEQB, and BLPREB to a logic low state while maintaining the logical inverse of the write clock WCLKB in a logic high state. This results in both bit lines of the memory cell being set to approximately the supply voltage for the next set of operations, as shown. In combination Figure 3-Figure 8 Describes what can be achieved Figure 2 and Fig. 9 Various configurations of memory circuits with the waveforms shown in .

[0055] Figure 3 FIG. 3 is a schematic diagram of an example memory circuit 300 having two complementary devices that equalize bit line voltages during double pump memory operation according to some embodiments. The memory circuit 300 may be similar to Figure 1Memory circuit 300 is shown in Figure 100, but includes an additional complementary transistor C10. As shown, memory circuit 300 includes transistors M8, M9, M10, C10, M11, M12, M13, and M14. Memory circuit 300 includes NAND gates 304 and 306 and NOR gates 308 and 310. In some embodiments, transistors M8, M9, M10, M11, and M12 each include a pMOSFET, and transistors C10, M13, and M14 each include an nMOSFET. It should be understood that each of transistors C10 and M7-M14 can include any of a variety of other types of transistors (e.g., bipolar junction transistors, high electron mobility transistors, etc.) while still within the scope of the present disclosure.

[0056] Various embodiments of the circuits and logic gates implementing the memory circuit 300 may include various transistors. The transistors described herein may be of a certain type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including but not limited to MOSFET, CMOS transistor, PMOS, NMOS, BJT, high voltage transistor, high frequency transistor, PFET / NFET, FinFET, planar MOS transistor with raised source / drain, nanosheet FET, nanowire FET, etc.

[0057] It should be understood that although Figure 3 The memory circuit 300 shown in the figure can be part of a larger memory circuit, including any number of bit line BL and BLB pairs, which can be addressed by corresponding memory cell selection circuits. Likewise, although not shown here for visual clarity, various additional circuits can be included to address (e.g., select) various portions of memory cells or perform different memory operations, including but not limited to CIM operations, write operations, or read operations, etc.

[0058] As shown, each of transistors M8, M9, M10, M11, M12, M13, and M14 may be similar to the combination of Figure 1 306, NAND gate 308, and NOR gate 310 may be similar to and include their respective counterparts ( Figure 1 Any structure and function of memory cell 112, inverter 102, NAND gate 104, NAND gate 106, NOR gate 108 and NOR gate 110).

[0059] For example, the inverter 302, the NAND gates 304 and 306, the NOR gates 308 and 310, and the transistors M11, M12, M13, and M14 may receive the data input signal DATA and the write clocks WCLK and WLKB signals to write data into the memory cell 312 via the bit lines BL and BLB, as shown in combination with Figure 1 Likewise, each of transistors M8 and M9 may receive a bit line precharge signal BLPREB to precharge each bit line before a double pump memory operation (eg, read after write or write after read in a single clock cycle).

[0060] In addition, transistor M10 can be similar to Figure 1 , and can receive an active low bit line voltage equalization signal BLEQB at its gate terminal. In addition, the memory circuit 300 may include a second inverter 303, which can generate a high level corresponding signal of BLEQB, shown here as BLEQ. As shown, the memory circuit 300 includes an additional complementary transistor C10 in parallel with the transistor M10. The complementary transistor C10 is shown as an n-type transistor, whose first source / drain terminal is coupled to the first bit line BL and the second source / drain terminal is coupled to the second bit line BLB. The gate terminal of the complementary transistor C10 receives the active high voltage equalization signal BLEQ. Compared to a single transistor, the use of complementary transistors M10 and C10 provides higher drive strength, allows additional current to flow through the circuit, and reduces voltage stress compared to a single transistor approach.

[0061] Figure 4 1 shows a schematic diagram of an example memory circuit 400 having devices for equalizing bit line voltages during double pump memory operation and voltage clamping devices coupled to each bit line in accordance with some embodiments. The memory circuit 400 may be similar to Figure 1 The memory circuit 100 shown in FIG. 1 includes both voltage clamp circuits 412 and 414. As shown, the memory circuit 400 includes transistors M15, M16, M17, M18, M19, M20, and M21. The first voltage clamp circuit 412 operates as a diode clamp device coupled to the bit line BL, including transistors D1 and D2. The second voltage clamp circuit 414 operates as a diode clamp device coupled to the bit line BLB, including transistors D3 and D4.

[0062] Memory circuit 400 includes NAND gates 404 and 406 and NOR gates 408 and 410. In some implementations, transistors M15, M16, M17, M18, M19, D1, D2, D3, and D4 each include a pMOSFET, and transistors M20 and M21 each include an nMOSFET. It should be understood that each of transistors M15-M21 and D1-D4 may include any of various other types of transistors (e.g., bipolar junction transistors, high electron mobility transistors, etc.) while still within the scope of the present disclosure. Various embodiments of circuits and logic gates implementing memory circuit 400 may include various transistors. The transistors described herein may be of a certain type (n-type or p-type), but embodiments are not limited thereto. The transistor may be any suitable type of transistor, including but not limited to MOSFET, CMOS transistor, PMOS, NMOS, BJT, high voltage transistor, high frequency transistor, PFET / NFET, FinFET, planar MOS transistor with convex source / drain, nanosheet FET, nanowire FET, etc.

[0063] It should be understood that although Figure 4 The memory circuit 400 shown in the figure can be part of a larger memory circuit, including any number of bit line BL and BLB pairs, which can be addressed by corresponding memory cell selection circuits. Likewise, although not shown here for visual clarity, various additional circuits can be included to address (e.g., select) various portions of memory cells or perform different memory operations, including but not limited to CIM operations, write operations, or read operations, etc.

[0064] As shown, each of transistors M15, M16, M17, M18, M19, M20, and M21 may be similar to the combination of Figure 1 4, M4, M5, M6, and M7, and may include any structure and functionality thereof. Similarly, various logic components, such as memory cell 416, inverter 402, NAND gate 404, NAND gate 406, NOR gate 408, and NOR gate 410, may be similar to and include their respective counterparts ( Figure 1 Any structure and function of memory cell 112, inverter 102, NAND gate 104, NAND gate 106, NOR gate 108 and NOR gate 110).

[0065] For example, inverter 402, NAND gates 404 and 406, NOR gates 408 and 410, and transistors M18, M19, M20, and M21 may receive data input signal DATA and write clocks WCLK and WLKB signals to write data into memory cell 416 via bit lines BL and BLB, as in combination with Figure 1Similarly, each of transistors M15 and M16 can receive a bit line precharge signal BLPREB to precharge each bit line before a double pump memory operation (e.g., read after write or write after read in a single clock cycle). Transistor M17 can be similar to Figure 1 The transistor M3 may receive the effective low bit line voltage equalization signal BLEQB at a gate terminal thereof.

[0066] As shown, the memory circuit 400 includes a first voltage clamp circuit 412 and a second voltage clamp circuit 414, which can be activated during a non-write operation when the WCLK signal is in a logic low state. As shown, the first voltage clamp circuit 412 includes a transistor D1 and a transistor D2. A first source / drain terminal of the transistor D1 is coupled to a power supply voltage VDD, and a second source / drain terminal of the transistor D1 is coupled to a first source / drain terminal of the transistor D2. A second source / drain terminal of the transistor D2 is coupled to a bit line BL. A gate terminal of the transistor D1 is coupled to source / drain terminals of the transistors D1 and D2, as shown, in a diode configuration.

[0067] In this configuration, transistor D1 forms a PMOS diode-connected transistor and behaves as a diode-like circuit element. The gate terminal of transistor D2 is connected to the write clock signal WCLK. Therefore, when the memory circuit performs a write operation, the WCLK signal is in a logic high state and transistor D2 is turned off and non-conductive. This prevents the first voltage clamp circuit 412 from being activated or affecting the voltage of the bit line BL.

[0068] The memory circuit 400 includes a second voltage clamp circuit 414, which is shown as including a transistor D3 and a transistor D4. A first source / drain terminal of the transistor D3 is coupled to the power supply voltage VDD, and a second source / drain terminal of the transistor D3 is coupled to a first source / drain terminal of the transistor D4. A second source / drain terminal of the transistor D4 is coupled to the bit line BLB. A gate terminal of the transistor D3 is coupled to source / drain terminals of the transistors D3 and D4, as shown, in a diode configuration.

[0069] In this configuration, transistor D3 forms a PMOS diode-connected transistor and behaves as a diode-like circuit element. The gate terminal of transistor D4 is connected to the write clock signal WCLK. Therefore, when the memory circuit performs a write operation, the WCLK signal is in a logic high state and transistor D4 is turned off and non-conductive. This prevents the second voltage clamp circuit 414 from being activated or affecting the voltage of the bit line BLB.

[0070] During non-write operations, when the WCLK signal is in a logic low state, transistors D2 and D4 are turned on and conduct. This effectively clamps the minimum voltage of the bit lines BL and BLB to the supply voltage minus the threshold voltage of transistors D1 and D3 plus the voltage drop across transistors D2 and D4, respectively. Clamping the voltage drop during read operations can improve the overall read performance of the device and promote proper equalization of the voltage Vequ between the bit lines BL and BLB for double pumped memory operations.

[0071] Figure 5 According to some embodiments, Figure 4 Schematic diagram of an example memory circuit 500 similar to the memory circuit 400 shown in FIG. 4 , having complementary devices that equalize bit line voltages during memory operation. The memory circuit 500 may be similar to Figure 1 The memory circuit 100 shown in FIG. 1 includes a memory circuit 100 similar to the combination of Figure 4 1 and 12. The memory circuit 500 is a block diagram of a memory circuit 500 that is similar to the described voltage clamp circuits 412 and 414. As shown, the memory circuit 500 includes transistors M22, M23, M24, C24, M25, M26, M27, and M28. The first voltage clamp circuit 512 operates as a diode clamp device coupled to the bit line BL and includes transistors D5 and D6. The second voltage clamp circuit 514 operates as a diode clamp device coupled to the bit line BLB and includes transistors D7 and D8.

[0072] The memory circuit 500 includes NAND gates 504 and 506 and NOR gates 508 and 510. In some implementations, transistors M22, M23, M24, M25, M26, D5, D6, D7, and D8 all include pMOSFETs, and transistors C24, M27, and M28 all include nMOSFETs. It should be understood that each of transistors C24 and M22-M28 may include any of various other types of transistors (e.g., bipolar junction transistors, high electron mobility transistors, etc.), while still within the scope of the present disclosure. Various embodiments of the circuits and logic gates implementing the memory circuit 500 may include various transistors. The transistors described herein may be of a certain type (n-type or p-type), but embodiments are not limited thereto. The transistor may be any suitable type of transistor, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high voltage transistors, high frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drains, nanosheet FETs, nanowire FETs, and the like.

[0073] It should be understood that although Figure 5The memory circuit 500 shown in the figure can be part of a larger memory circuit, including any number of bit line BL and BLB pairs, which can be addressed by corresponding memory cell selection circuits. Likewise, although not shown here for visual clarity, various additional circuits can be included to address (e.g., select) various portions of memory cells or perform different memory operations, including but not limited to CIM operations, write operations, or read operations, etc.

[0074] As shown, each of transistors M22, M23, M24, C24, M25, M26, M27, and M28 may be similar to the combination of Figure 3 10, M10, M11, M12, M13, and M14, and may include any structure and function thereof. Similarly, various logic components, such as memory cell 516, inverter 502, second inverter 503, NAND gate 504, NAND gate 506, NOR gate 508, and NOR gate 510, may be similar to those described above. Figure 3 The memory cell 312, inverter 302, second inverter 303, NAND gate 304, NAND gate 306, NOR gate 308 and NOR gate 310 of the present invention include any structure and function of their respective counterparts.

[0075] For example, inverter 502, NAND gates 504 and 506, NOR gates 508 and 510, and transistors M25, M26, M27, and M28 may receive data input signal DATA and write clocks WCLK and WLKB signals to write data into memory cell 516 via bit lines BL and BLB, as in combination with Figure 1 and Figure 3 Similarly, each of transistors M22 and M23 can receive a bit line precharge signal BLPREB to precharge each bit line before a double pump memory operation (e.g., read after write or write after read in a single clock cycle). Transistor M24 can be similar to Figure 1 The transistor M3 may receive the effective low bit line voltage equalization signal BLEQB at a gate terminal thereof.

[0076] Each of the voltage clamping circuits 512 and 514 and the transistors D5, D6, D7, and D8 included therein may be similar to Figure 4The voltage clamp circuits 412 and 414 and transistors D1, D2, D3 and D4 in the embodiment of the present invention include any structure and function thereof. As described herein, the voltage clamp circuits 512 and 514 can respectively turn on and conduct transistors D2 and D4 during non-write operations when the write pulse signal WCLK is in a logic low state. This effectively clamps the minimum voltage of the bit lines BL and BLB to the value of the power supply voltage minus the threshold voltage of transistors D5 and D6, and the voltage drop across transistors D7 and D8 for each of the bit lines BL and BLB. Clamping the voltage drop during the read operation can improve the overall read performance of the device and help provide a suitable equal voltage Vequ between the bit lines BL and BLB for the double pump memory operation.

[0077] As shown, the memory circuit 500 includes an additional complementary transistor C24 in parallel with the transistor M24. The complementary transistor C24 is shown as an n-type transistor having a first source / drain terminal coupled to the first bit line BL and a second source / drain terminal coupled to the second bit line BLB. The gate terminal of the complementary transistor C24 receives the active high voltage equalization signal BLEQ. The use of complementary transistors M24 and C24 provides higher drive strength than a single transistor, allowing additional current to flow through the circuit and reducing voltage stress compared to a single transistor approach.

[0078] Figure 6 According to some embodiments, Figure 4 Schematic diagram of an example memory circuit 600 similar to the memory circuit 400 shown in FIG. 1 , a voltage clamp device is coupled to each bit line that receives a clamp voltage. The memory circuit 600 may be similar to Figure 1 The memory circuit 100 shown in FIG. 1 includes voltage clamp circuits 612 and 614. As shown, the memory circuit 600 includes transistors M29, M30, M31, M32, M33, M34, and M35. The first voltage clamp circuit 612 operates as a configurable clamp device coupled to the bit line BL, including transistors D9 and D10. The second voltage clamp circuit 614 operates as a configurable clamp device coupled to the bit line BLB, including transistors D11 and D12.

[0079] The memory circuit 600 includes NAND gates 604 and 606 and NOR gates 608 and 610. In some implementations, transistors M29, M30, M31, M32, M33, D10, and D12 each include a pMOSFET, and transistors D9, D11, M34, and M35 each include an nMOSFET. It should be understood that each of transistors M29-M35 and D9-D12 may include any of various other types of transistors (e.g., bipolar junction transistors, high electron mobility transistors, etc.) while still within the scope of the present disclosure. Various embodiments of the circuits and logic gates implementing the memory circuit 600 may include various transistors. The transistors described herein may be of a certain type (n-type or p-type), but embodiments are not limited thereto. The transistor may be any suitable type of transistor, including but not limited to MOSFET, CMOS transistor, PMOS, NMOS, BJT, high voltage transistor, high frequency transistor, PFET / NFET, FinFET, planar MOS transistor with convex source / drain, nanosheet FET, nanowire FET, etc.

[0080] It should be understood that although Figure 6 The memory circuit 600 shown in the figure can be part of a larger memory circuit, including any number of bit line BL and BLB pairs, which can be addressed by corresponding memory cell selection circuits. Likewise, although not shown here for visual clarity, various additional circuits can be included to address (e.g., select) various portions of memory cells or perform different memory operations, including but not limited to CIM operations, write operations, or read operations, etc.

[0081] As shown, the memory circuit 600 includes a first voltage clamp circuit 612 and a second voltage clamp circuit 614, which can be activated during a non-write operation when the WCLK signal is in a logic low state. As shown, the first voltage clamp circuit 612 includes a transistor D9 and a transistor D10. A first source / drain terminal of the transistor D9 is connected to a power supply voltage VDD, and a second source / drain terminal of the transistor D9 is connected to a first source / drain terminal of the transistor D10. A second source / drain terminal of the transistor D10 is coupled to a bit line BL. The gate terminal of the transistor D9 receives a voltage clamp control signal Vclamp, as shown.

[0082] In this configuration, transistor D9 forms a configurable resistor or current source, either of which can be operated in the ohmic or linear region by varying the voltage Vclamp. The gate terminal of transistor D10 is connected to the write clock signal WCLK. Therefore, when the memory circuit performs a write operation, the WCLK signal is in a logic high state and transistor D10 is turned off and non-conductive. This prevents the first voltage clamp circuit 612 from being activated or affecting the voltage of the bit line BL. During a write operation, the voltage Vclamp can be set to turn off transistors D9 and D11.

[0083] The memory circuit 600 includes a second voltage clamp circuit 614, which is shown to include a transistor D11 and a transistor D12. A first source / drain terminal of the transistor D11 is coupled to the power supply voltage VDD, and a second source / drain terminal of the transistor D11 is connected to a first source / drain terminal of the transistor D12. A second source / drain terminal of the transistor D12 is connected to the bit line BLB. Similar to the gate terminal of the transistor D9, the gate terminal of the transistor D11 receives a voltage clamp control signal Vclamp, as shown.

[0084] In this configuration, transistor D11 forms a configurable resistor or current source, either of which can be operated in the ohmic or linear region by varying the voltage Vclamp. The gate terminal of transistor D12 is connected to the write clock signal WCLK. Therefore, when the memory circuit performs a write operation, the WCLK signal is in a logic high state and transistor D12 is turned off and non-conductive. This prevents the second voltage clamp circuit 614 from being activated or affecting the voltage of the bit line BLB.

[0085] During non-write operations, when the WCLK signal is in a logic low state, transistors D10 and D12 are turned on and conducted according to their respective electrical characteristics, the voltages at the bit lines BL and BLB, and the configured voltage signal Vclamp. The first clamp circuit 612 and the second clamp circuit 614 effectively clamp the minimum voltage of the bit lines BL and BLB to the voltage drop across transistors D9 and D10 and the voltage drop across transistors D11 and D12, respectively. Clamping the voltage drop during a read operation can improve the overall read performance of the device and promote the appropriate equalization voltage Vequ between the bit lines BL and BLB for dual pump memory operation. The configurable voltage signal Vclamp can be provided by one or more control circuits and can be varied to achieve a desired minimum voltage at each of the bit lines BL and BLB.

[0086] Figure 7 According to some embodiments, Figure 6Schematic diagram of an example memory circuit 700 similar to the memory circuit shown in FIG. 1 , which has complementary devices that equalize bit line voltages during memory operation. The memory circuit 700 may be similar to Figure 1 The memory circuit 100 shown in FIG. 1 includes a memory circuit 100 similar to the combination of Figure 6 1 and 12. The memory circuit 700 is a memory circuit that is similar to the memory circuit 700 of the voltage clamp circuits 612 and 614 described above. As shown, the memory circuit 700 includes transistors M36, M37, M38, C38, M39, M40, M41, and M42. The first voltage clamp circuit 712 operates as a configurable voltage clamp device coupled to the bit line BL and includes transistors D13 and D14. The second voltage clamp circuit 714 operates as a configurable voltage clamp device coupled to the bit line BLB and includes transistors D15 and D16.

[0087] Memory circuit 700 includes NAND gates 704 and 706 and NOR gates 708 and 710. In some implementations, transistors M36, M37, M38, C38, M39, M40, D14, and D16 each include a pMOSFET, and transistors C24, M41, M42, D13, and M15 each include an nMOSFET. It should be understood that each of transistors C38, M36-M42, and D13-D16 may include any of a variety of other types of transistors (e.g., bipolar junction transistors, high electron mobility transistors, etc.) while still within the scope of the present disclosure. Various embodiments of circuits and logic gates implementing memory circuit 700 may include various transistors. The transistors described herein may be of a certain type (n-type or p-type), but embodiments are not limited thereto. The transistor can be any suitable type of transistor, including but not limited to MOSFET, CMOS transistor, PMOS, NMOS, BJT, high voltage transistor, high frequency transistor, PFET / NFET, FinFET, planar MOS transistor with raised source / drain, nanosheet FET, nanowire FET, etc.

[0088] It should be understood that although Figure 7 The memory circuit 700 shown in the figure can be part of a larger memory circuit, including any number of bit line BL and BLB pairs, which can be addressed by corresponding memory cell selection circuits. Likewise, although not shown here for visual clarity, various additional circuits can be included to address (e.g., select) various portions of memory cells or perform different memory operations, including but not limited to CIM operations, write operations, or read operations, etc.

[0089] As shown, each of transistors M36, M37, M38, M38, M39, M40, M41, and M42 can be similar to the combination of Figure 310, M10, M11, M12, M13, and M14, and may include any structure and function thereof. Similarly, various logic components, such as memory cell 716, inverter 702, second inverter 703, NAND gate 704, NAND gate 706, NOR gate 708, and NOR gate 710, may be similar to Figure 3 The memory cell 312, the inverter 302, the second inverter 303, the NAND gate 304, the NAND gate 306, the NOR gate 308 and the NOR gate 310 and any structure and function of their respective counterparts are combined.

[0090] For example, the inverter 702, the NAND gates 704 and 706, the NOR gates 708 and 710, and the transistors M39, M40, M41, and M42 may receive the data input signal DATA and the write clocks WCLK and WLKB signals to write data into the memory cell 716 via the bit lines BL and BLB, as shown in combination with Figure 1 and Figure 3 Likewise, each of transistors M36 and M37 may receive a bit line precharge signal BLPREB to precharge each bit line prior to a double pump memory operation (eg, read after write or write after read in a single clock cycle). Transistor M38 may be similar to Figure 1 The transistor M3 may receive the effective low bit line voltage equalization signal BLEQB at a gate terminal thereof.

[0091] Each of the voltage clamping circuits 712 and 714 and the transistors D13, D14, D15, and D16 included therein may be similar to Figure 6 The voltage clamping loops 612 and 614 and transistors D9, D10, D11 and D12 of the present invention include any structure and function thereof. As described herein, the voltage clamping circuits 712 and 714 can clamp the minimum voltage of the bit lines BL and BLB to a configurable value, respectively, according to the configuration voltage Vclamp applied to the gate terminal of each of the transistors D13 and D15. During a write operation, the voltage Vclamp can be set to turn off the transistors D13 and D15. Clamping the voltage drop during a read operation can improve the overall read performance of the device and help provide a suitable equalization voltage Vequ between the bit lines BL and BLB for a double pump memory operation.

[0092] As shown, the memory circuit 700 includes an additional complementary transistor C38 in parallel with the transistor M38. The complementary transistor C38 is shown as an n-type transistor having a first source / drain terminal coupled to the first bit line BL and a second source / drain terminal coupled to the second bit line BLB. The gate terminal of the complementary transistor C38 receives the active high voltage equalization signal BLEQ. The use of complementary transistors M38 and C38 provides higher drive strength than a single transistor, allowing additional current to flow through the circuit and reducing voltage stress compared to a single transistor approach.

[0093] Figure 8 FIG. 8 is a schematic diagram of an example memory circuit 800 including an alternative arrangement of voltage clamping devices according to some embodiments. The memory circuit 800 may be similar to Figure 1 The memory circuit 100 shown in FIG. 1 includes a memory circuit 100 similar to the combination of Figure 6 8 and 814. As shown, the memory circuit 800 includes transistors M43, M44, M45, M46, M47, M48, and M49. The first voltage clamp circuit 812 operates as a configurable voltage clamp device coupled to the bit line BL, including transistors D17 and D18. The second voltage clamp device 814 operates as a configurable voltage clamp device coupled to the bit line BLB, including transistors D19 and D20.

[0094] The memory circuit 800 includes NAND gates 804 and 806 and NOR gates 808 and 810. In some implementations, transistors M43, M44, M45, M46, M47, D17, and D19 all include pMOSFETs, and transistors M48, M49, D18, and M20 all include nMOSFETs. It should be understood that each of transistors M43-M49 and D17-D20 may include any of various other types of transistors (e.g., bipolar junction transistors, high electron mobility transistors, etc.), while still within the scope of the present disclosure. Various embodiments of circuits and logic gates implementing the memory circuit 800 may include various transistors. The transistors described herein may be of a certain type (n-type or p-type), but embodiments are not limited thereto. The transistor may be any suitable type of transistor, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high voltage transistors, high frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drains, nanosheet FETs, nanowire FETs, and the like.

[0095] It should be understood that although Figure 8The memory circuit 800 shown in the figure can be part of a larger memory circuit, including any number of bit line BL and BLB pairs, which can be addressed by corresponding memory cell selection circuits. Likewise, although not shown here for visual clarity, various additional circuits can be included to address (e.g., select) various portions of memory cells or perform different memory operations, including but not limited to CIM operations, write operations, or read operations, etc.

[0096] As shown, each of transistors M43, M44, M45, M46, M47, M48, and M49 may be similar to the combination of Figure 1 806, NAND gate 808, and NOR gate 810 may be similar to the transistors M1, M2, M3, M4, M5, M6, and M7 described above, and may include any structure and function thereof. Similarly, various logic components, such as memory cell 816, inverter 802, NAND gate 804, NAND gate 806, NOR gate 808, and NOR gate 810, may be similar to Figure 1 Memory cell 112, inverter 102, NAND gate 104, NAND gate 106, NOR gate 108, and NOR gate 110 of and include any structure and functionality of their respective counterparts.

[0097] For example, inverter 802, NAND gates 804 and 806, NOR gates 808 and 810, and transistors M46, M47, M48, and M49 may receive data input signal DATA and write clocks WCLK and WLKB signals to write data into memory cell 816 via bit lines BL and BLB, as in combination with Figure 1 Similarly, each of transistors M43 and M44 can receive a bit line precharge signal BLPREB to precharge each bit line before a double pump memory operation (e.g., read after write or write after read in a single clock cycle). Transistor M45 can be similar to Figure 1 The transistor M3 may receive the effective low bit line voltage equalization signal BLEQB at a gate terminal thereof.

[0098] Each of the voltage clamping circuits 812 and 814 and the transistors D13, D14, D15, and D16 included therein may be similar to Figure 6 The voltage clamp circuits 612 and 614 and transistors D17, D18, D19 and D20 of the present invention include any structure and function thereof. As described herein, the voltage clamp circuits 812 and 814 can clamp the minimum voltage of the bit lines BL and BLB to a configurable value, respectively, according to the configuration voltage Vclamp applied to the gate terminal of each of the transistors D17 and D19. During a write operation, the voltage Vclamp can be set to turn off the transistors D17 and D19.

[0099] exist Figure 8 In the illustrated embodiment, voltage clamps 812 and 814 are located on the “far side” of the BL circuit, for example, above one or more memory cells 816 coupled between bit lines BL and BLB. For example, voltage clamps 812 and 814 can be coupled at opposite ends of bit lines BLB and BLB relative to the write circuit and precharged as described with respect to memory cell 816 in memory circuit 800. In some implementations, memory circuit 800 may include a complementary n-type device in parallel with transistor M45, as described herein in conjunction with Figure 5 and Figure 7 described.

[0100] Fig.10 A flow chart of an example method 1000 for operating an example memory circuit that implements voltage equalization of an intermediate precharge during a double pump memory operation according to some embodiments is shown. The method 1000 may be used to operate a memory circuit (e.g., memory circuits 100, 300, 400, 500, 600, 700, 800, etc.). For example, at least some of the operations described in the method 700 may be used to operate a memory circuit (e.g., memory circuits 100, 300, 400, 500, 600, 700, 800, etc.). Figure 1 and Figure 3-Figure 8 It should be noted that method 1000 is merely an example and is not intended to limit the present disclosure. Therefore, it is understood that in Figure 1 Additional operations may be provided before, during, and after method 1000. And some other operations may only be briefly described here.

[0101] In brief, the method 1000 begins at operation 1002, where a first bit line and a second bit line coupled to a memory cell are precharged. The method 1000 proceeds to operation 1004, where a first operation is performed on the memory cell. The method 1000 continues to operation 1006, where voltages of the first bit line and the second bit line of the memory cell are equalized after the first memory operation and before the second memory operation. The method 1000 proceeds to operation 1008, where a second memory operation is performed on the memory cell after the voltages of the first bit line and the second bit line are equalized.

[0102] Referring to operation 1002, a first bit line (e.g., BL) and a second bit line (e.g., BLB) coupled to a memory cell (e.g., memory cell 112) are precharged. For example, a memory controller may activate one or more precharge devices (e.g., pass transistors M1 and M2) using a control signal (e.g., BLPREB) to set the voltage of the bit lines to approximately a power supply voltage (e.g., VDD). The precharge operation may be performed before a dual pump memory operation, which includes multiple memory operations (e.g., read followed by write, write followed by read, etc.) in a single memory clock cycle. The precharge operation may be performed before the first operation.

[0103] Referring to operation 1004, a first memory operation (e.g., read, write) is performed on the memory cell. The first memory operation may be a write operation or a read operation. In a read operation, the voltage of the precharged bit line is not changed or modified, but the voltage change caused by the voltage difference between the bit lines affected by the memory cell is sensed as a logic value stored in the memory cell. In a write operation, the voltage across the bit line is set so that input data (e.g., a logic high or logic low bit value) is written to the memory cell. Additional circuitry (e.g., a control circuit) may provide a signal to selectively activate the memory cell for a memory operation.

[0104] Referring to operation 1006, in an intermediate precharge operation after a first memory operation and before a second memory operation, the voltages across the bit lines are equalized. As described herein, a double pump memory operation includes multiple memory operations within a single clock cycle. In order to reduce overall dynamic power consumption, rather than precharging the bit lines of the memory cells again before the memory operation, a voltage equalization device (e.g., transistor M3, complementary transistors M10 and C10, etc.) can be used to set the voltages of the bit lines to be equal to each other. A control signal (e.g., BLEQB) can be provided to activate the voltage equalization device. The voltage (e.g., Vequ) to which the bit lines are set can be less than the power supply voltage but greater than the ground voltage.

[0105] Referring to operation 1008, after the voltage between the first bit line and the second bit line is equalized, a second operation can be performed on the memory cell. The second memory operation can be a read operation or a write operation, and can be performed by providing a corresponding control signal (e.g., WCLK) to the memory cell. In some implementations, the second memory operation can be different from the first memory operation. After the intermediate precharge operation, the second memory operation can be performed in the same clock cycle as the first memory operation.

[0106] In one aspect of the present disclosure, a memory device is disclosed. The memory device includes a memory cell coupled between a first bit line and a second bit line. The memory device includes a write circuit configured to write data to the memory cell via the first bit line and the second bit line during a write operation. The memory device includes a voltage equalization device configured to equalize the voltages of the first bit line and the second bit line after a write operation and before a read operation of the memory cell.

[0107] In some embodiments, the voltage equalization device is further configured to set the voltage of the first bit line and the second bit line to a voltage less than a power supply voltage.

[0108] In some embodiments, the voltage equalization device equalizes voltages of the first bit line and the second bit line during a double pumping operation.

[0109] In some embodiments, the write circuit includes at least one NOR gate and at least one NAND gate.

[0110] In some embodiments, the voltage equalization device includes at least one p-type device.

[0111] In some embodiments, the voltage equalization device further includes at least one n-type device coupled in parallel to the at least one p-type device.

[0112] In some embodiments, the memory device further includes at least one precharge device coupled to the first bit line and the second bit line.

[0113] In some embodiments, the at least one pre-charge device is coupled to the voltage equalization device.

[0114] In some embodiments, the memory device further includes at least one voltage clamp device coupled to the first bit line or the second bit line.

[0115] In some embodiments, the at least one voltage clamping device is further configured to clamp a voltage of the first bit line or the second bit line according to a control signal.

[0116] In another aspect of the present disclosure, a memory circuit is disclosed. The memory circuit includes a first bit line and a second bit line coupled to a memory cell. The memory circuit includes a first transistor connected in parallel with the memory cell. A first source / drain terminal of the first transistor is coupled to the first bit line. A second source / drain terminal of the first transistor is coupled to the second bit line. A gate terminal of the first transistor receives a voltage equalization signal. The voltage equalization signal is configured to equalize the voltage of the first bit line and the second bit line between memory operations.

[0117] In some embodiments, the memory circuit further includes a second transistor and a third transistor, the second transistor coupled to a power supply voltage and the first bit line, the third transistor coupled to the power supply voltage and the second bit line, each of the second transistor and the third transistor receiving a precharge signal.

[0118] In some embodiments, the memory circuit further includes a second transistor connected in parallel with the first transistor.

[0119] In some embodiments, the first transistor is a p-type transistor.

[0120] In some embodiments, the memory circuit further includes a second transistor and a third transistor, wherein a first source / drain terminal of the second transistor is coupled to a power supply voltage, a second source / drain terminal of the second transistor is coupled to a first drain / source terminal of the third transistor, and a second source / drain terminal of the third transistor is coupled to the first bit line or the second bit line.

[0121] In some embodiments, the gate terminal of the second transistor is coupled to the second source / drain terminal of the second transistor.

[0122] In some embodiments, a gate terminal of the second transistor receives a voltage clamp control signal.

[0123] In another aspect of the present disclosure, a method of operating a memory device is disclosed. The method includes precharging a first bit line and a second bit line coupled to a memory cell. The method includes performing a first memory operation on the memory cell. The method includes equalizing the voltages of the first bit line and the second bit line of the memory cell after the first memory operation and before a second memory operation. The method includes performing the second memory operation on the memory cell after equalizing the voltages of the first bit line and the second bit line.

[0124] In some embodiments, voltages of the first bit line and the second bit line are both made equal to a voltage less than a power supply voltage.

[0125] In some embodiments, the first memory operation is a read operation and the second memory operation is a write operation.

[0126] As used herein, the terms "about" and "approximately" generally refer to plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0127] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, comprising: a memory cell coupled between the first bit line and the second bit line; a write circuit configured to write data to the memory cell via the first bit line and the second bit line during a write operation; as well as A voltage equalizing device is configured to equalize the voltages of the first bit line and the second bit line after a write operation and before a read operation of the memory cell.

2. The memory device according to claim 1, wherein: The voltage equalization device is further configured to set the voltages of the first bit line and the second bit line to a voltage less than a power supply voltage.

3. The memory device according to claim 1, wherein: The voltage equalizing device equalizes voltages of the first bit line and the second bit line during a double pumping operation.

4. The memory device according to claim 1, wherein: The write circuit includes at least one NOR gate and at least one NAND gate. 5 . The memory device of claim 1 , further comprising at least one precharge device coupled to the first bit line and the second bit line. 6 . The memory device of claim 1 , further comprising at least one voltage clamp device coupled to the first bit line or the second bit line.

7. A memory circuit comprising: A first bit line and a second bit line coupled to the memory cell; as well as A first transistor is connected in parallel with the memory cell, a first source / drain terminal of the first transistor is coupled to the first bit line, a second source / drain terminal of the first transistor is coupled to the second bit line, and a gate terminal of the first transistor receives a voltage equalization signal configured to equalize voltages of the first bit line and the second bit line between memory operations.

8. The memory circuit of claim 7 , further comprising a second transistor and a third transistor, the second transistor being coupled to a power supply voltage and the first bit line, the third transistor being coupled to the power supply voltage and the second bit line, each of the second transistor and the third transistor receiving a precharge signal.

9. The memory circuit of claim 7 , further comprising a second transistor and a third transistor, a first source / drain terminal of the second transistor being coupled to a power supply voltage, a second source / drain terminal of the second transistor being coupled to a first drain / source terminal of the third transistor, and a second source / drain terminal of the third transistor being coupled to the first bit line or the second bit line.

10. A method of operating a memory device, comprising: precharging a first bit line and a second bit line coupled to the memory cell; performing a first memory operation on the memory cell; equalizing voltages of the first bit line and the second bit line of the memory cell after the first memory operation and before the second memory operation; as well as After equalizing the voltages of the first bit line and the second bit line, the second memory operation is performed on the memory cell.

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