Semiconductor device, method for manufacturing semiconductor device, electronic device, and vehicle

Abstract

The invention discloses a semiconductor device, a method for preparing the semiconductor device, electronic equipment and a vehicle, and the semiconductor device comprises a substrate of a first conduction type, a metal electrode and a first electric leakage protection layer, and the metal electrode is located on the upper surface of the substrate; the first leakage protection layer is located on the substrate surface between the metal electrode and the side surface of the substrate. According to the device, effective isolation between the metal electrode and the side face of the substrate is achieved, the potential risk of electric leakage is reduced, and the stability and reliability of the device are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device, a method for preparing the semiconductor device, an electronic device and a vehicle. Background Art

[0002] In the actual application of semiconductor device packaging, the metal electrodes of the device are usually connected to the substrate through conductive adhesives or welding wires to realize circuit functions and protect other components. However, since the metal electrodes are close to the edge of the table of the semiconductor device and the side of the substrate is exposed to the air, this can easily cause the metal electrode material to overflow to the side of the substrate during the process of solid crystal or wire bonding during the manufacturing and packaging process, forming a conductive path, which in turn causes leakage problems. In addition, the conductive adhesive on the back of the substrate may migrate to the upper surface of the device through the side of the substrate, which may also cause similar leakage risks. This leakage problem not only reduces the service life of the semiconductor device, but may also affect its stability and electrical performance, thereby negatively affecting the reliability of the entire electronic system. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a semiconductor device, which realizes effective isolation between a metal electrode and a side surface of a substrate, reduces the potential risk of leakage, and improves the stability and reliability of the device.

[0004] A second object of the present invention is to provide a method for manufacturing a semiconductor device.

[0005] A third objective of the present invention is to provide an electronic device.

[0006] A fourth object of the present invention is to provide a vehicle.

[0007] In order to achieve the above-mentioned purpose, a semiconductor device according to an embodiment of the first aspect of the present invention includes: a substrate of a first conductive type; a metal electrode, the metal electrode being located on the upper surface of the substrate; and a first leakage protection layer, the first leakage protection layer being located on the surface of the substrate between the metal electrode and the side surface of the substrate.

[0008] According to the semiconductor device of the embodiment of the present invention, a first leakage protection layer is provided between the metal electrode and the side of the substrate. The first leakage protection layer has excellent insulation performance and can form effective isolation protection, thereby preventing the metal electrode from overflowing to the side of the substrate during the solid crystal or wire bonding process. This can avoid the formation of a conductive path between the metal electrode and the side of the substrate, reducing the potential risk of leakage. In addition, the presence of the first leakage protection layer can also prevent the conductive adhesive on the back of the substrate from migrating upward, further reducing the occurrence of leakage problems. This design ensures the insulation between the metal electrode and the side of the substrate, effectively improving the overall stability and reliability of the device.

[0009] In some embodiments, the first leakage protection layer is configured as at least one step.

[0010] In some embodiments, the first leakage protection layer is configured as a plurality of steps, and the plurality of steps are continuously arranged along a side surface from the metal electrode to the substrate.

[0011] In some embodiments, the first leakage protection layer includes: a first passivation layer, wherein the first passivation layer is located on the surface of the substrate between the metal electrode and the side surface of the substrate.

[0012] In some embodiments, the thickness H1 of the first passivation layer satisfies: 0.5um≤H1≤1.5um.

[0013] In some embodiments, the first leakage protection layer further includes: a second passivation layer, wherein the second passivation layer is located on the first passivation layer.

[0014] In some embodiments, the thickness H2 of the second passivation layer satisfies: 0.5um≤H2≤1.5um.

[0015] In some embodiments, the first leakage protection layer is arranged in a slope from the metal electrode to the side of the substrate, and the first leakage protection layer forms a preset angle with the upper surface of the substrate.

[0016] In some embodiments, the thickness H3 of the first leakage protection layer satisfies: 0.5um≤H3≤1.5um.

[0017] In some embodiments, the first leakage protection layer also covers a portion of the upper surface of the substrate.

[0018] In some embodiments, a thickness H4 of the first leakage protection layer located on the upper surface of the substrate satisfies: 1um≤H4≤3um.

[0019] In some embodiments, the semiconductor device further includes: at least one doped region of the second conductivity type, the doped region being located within the substrate and close to an upper surface of the substrate.

[0020] In some embodiments, the semiconductor device also includes: a metal dielectric layer, the metal dielectric layer is located in an area on the upper surface of the substrate corresponding to the doped region; the metal electrode is connected to the metal dielectric layer through a contact hole, and the contact hole is constructed by the first leakage protection layer located on the upper surface of the substrate.

[0021] In some embodiments, the semiconductor device further includes: a second leakage protection layer, one end of the second leakage protection layer is connected to the first leakage protection layer, and a second end of the second leakage protection layer extends along the side of the substrate and at least extends to a position close to the lower surface of the substrate.

[0022] In some embodiments, the second leakage protection layer surrounds a lower surface of the substrate.

[0023] In order to achieve the above-mentioned purpose, the method for preparing a semiconductor device according to the second aspect of an embodiment of the present invention includes: providing a substrate of a first conductive type; preparing a first leakage protection layer and a metal electrode on the substrate, wherein the metal electrode is located on the upper surface of the substrate, and the first leakage protection layer is located on the surface of the substrate between the metal electrode and the side of the substrate.

[0024] According to the method for preparing a semiconductor device according to an embodiment of the present invention, a first leakage protection layer is prepared between the metal electrode and the side of the substrate. The first leakage protection layer has excellent insulation properties and can form an effective isolation protection, thereby preventing the metal electrode from overflowing to the side of the substrate during the solid crystal or wire bonding process. This can avoid the formation of a conductive path between the metal electrode and the side of the substrate, reducing the potential risk of leakage. In addition, the presence of the first leakage protection layer can also prevent the conductive adhesive on the back of the substrate from migrating upward, further reducing the occurrence of leakage problems. This design ensures the insulation between the metal electrode and the side of the substrate, effectively improving the overall stability and reliability of the device.

[0025] In some embodiments, preparing a first leakage protection layer on the substrate includes: preparing at least one step structure on the surface of the substrate between the metal electrode and the side of the substrate; forming the first leakage protection layer on the surface of the at least one step structure, wherein the first leakage protection layer is constructed as at least one step.

[0026] In some embodiments, forming the first leakage protection layer on the surface of the at least one step structure includes: forming a first passivation layer on the surface of the at least one step structure; forming a second passivation layer on the first passivation layer, the first passivation layer and the second passivation layer constitute the first leakage protection layer.

[0027] In some embodiments, preparing a first leakage protection layer on the substrate includes: forming a sloped first leakage protection layer on the surface of the substrate between the metal electrode and the side of the substrate, wherein the first leakage protection layer is at a preset angle to the upper surface of the substrate.

[0028] In some embodiments, the first leakage protection layer also covers a portion of the upper surface of the substrate, and the method further includes: preparing at least one doped region of a second conductivity type within the substrate and close to the upper surface of the substrate; preparing a metal dielectric layer in an area corresponding to the doped region on the upper surface of the substrate, wherein the metal electrode is connected to the metal dielectric layer through a contact hole, and the contact hole is constructed by the first leakage protection layer located on the upper surface of the substrate.

[0029] In some embodiments, the method further includes: preparing a second leakage protection layer on the side of the substrate, one end of the second leakage protection layer is connected to the first leakage protection layer, and the second end of the second leakage protection layer extends along the side of the substrate at least to a position close to the lower surface of the substrate.

[0030] In some embodiments, the second leakage protection layer surrounds a lower surface of the substrate.

[0031] In order to achieve the above object, an electronic device according to an embodiment of a third aspect of the present invention comprises the semiconductor device described in the above embodiment.

[0032] The electronic device according to the embodiment of the present invention, by adopting the semiconductor device described in the above embodiment, realizes effective isolation between the metal electrode and the side of the substrate, reduces the potential risk of leakage, and thus improves the stability and reliability of the device.

[0033] In some embodiments, the electronic device includes a light emitting diode light source.

[0034] In some embodiments, the semiconductor device includes a transient suppression diode (TVS diode); the LED light source further includes a LED and a substrate, the LED is located on the substrate, and the TVS diode is flip-chip connected to the substrate to be connected in parallel with the LED.

[0035] In order to achieve the above-mentioned purpose, the vehicle according to the fourth aspect of the embodiment of the present invention includes the semiconductor device described in the above embodiment, or includes the electronic device described in the above embodiment.

[0036] According to the vehicle of the embodiment of the present invention, by adopting the semiconductor device or electronic device described in the above embodiment, the first leakage protection layer inside has excellent insulation performance, which can form an effective isolation protection, thereby preventing the metal electrode from overflowing to the side of the substrate during the solid crystal or wire bonding process, thereby avoiding the formation of a conductive path between the metal electrode and the side of the substrate, reducing the potential risk of leakage. In addition, the presence of the first leakage protection layer can also prevent the conductive adhesive on the back of the substrate from migrating upward, further reducing the occurrence of leakage problems. This design ensures the insulation between the metal electrode and the side of the substrate, thereby improving the overall performance of the vehicle.

[0037] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 is a structural cross-sectional view of a semiconductor device according to an embodiment of the present invention; Figure 2 is a structural cross-sectional view of a semiconductor device according to yet another embodiment of the present invention; Figure 3 is a top view of the structure of a semiconductor device according to an embodiment of the present invention; Figure 4 is a flow chart of a method for preparing a semiconductor device according to one embodiment of the present invention; Figure 5 is a block diagram of an electronic device according to an embodiment of the present invention; Figure 6 is a block diagram of a vehicle according to one embodiment of the present invention; Figure 7 is a block diagram of a vehicle according to yet another embodiment of the present invention.

[0039] Reference numerals: Vehicle 100; Electronic device 110; Semiconductor device 1; Light emitting diode light source 2; Substrate 10; metal electrode 20; first leakage protection layer 30; doped region 40; metal dielectric layer 50; second leakage protection layer 60; contact hole 70; A first passivation layer 31 ; and a second passivation layer 32 . DETAILED DESCRIPTION

[0040] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0041] Reference below Figure 1 A semiconductor device according to an embodiment of the present invention is described.

[0042] Figure 1 is a structural cross-sectional view of a semiconductor device according to an embodiment of the present invention, Figure 1 As shown, the semiconductor device 1 includes a substrate 10 of a first conductivity type, a metal electrode 20 and a first leakage protection layer 30 .

[0043] In some embodiments, the substrate 10 is the basic material of the semiconductor device 1, carrying and supporting all subsequent layer structures. The selection of the material of the substrate 10 is very important for the performance of the semiconductor device 1. The material of the substrate 10 may include silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs) and other materials.

[0044] Among them, silicon (Si) is one of the most commonly used semiconductor materials with low cost and is suitable for most electronic devices, such as diodes, triodes, CMOS, etc. Silicon (Si) has good conductivity, mechanical strength and mature processing technology, so it is widely used in large-scale integrated circuits, power semiconductor devices1 and other fields. Silicon carbide (SiC) has high breakdown field strength, high thermal conductivity and wide bandgap characteristics, and is suitable for harsh environments such as high temperature, high pressure and high frequency. The excellent properties of silicon carbide (SiC) make it suitable for the manufacture of high-power electronic devices such as power MOSFET, IGBT, Schottky diode, etc. Gallium arsenide (GaAs) has high electron mobility and low parasitic capacitance, and is suitable for high-frequency applications (such as wireless communications, microwave circuits, optoelectronic devices, etc.).

[0045] In some embodiments, the first conductivity type refers to the doping type of the substrate 10, which can be N-type or P-type. The doping type is achieved by introducing specific impurity elements into pure semiconductor materials, and different doping types determine the type of carriers and the current conduction mode in the semiconductor device 1. For example, the N-type conductivity type is obtained by doping impurities of pentavalent elements such as phosphorus (P) and arsenic (As) to generate additional free electrons in the material as majority carriers, thereby obtaining an N-type conductivity type substrate 10. The P-type conductivity type is obtained by doping impurities of trivalent elements such as boron (B) to generate holes in the material as majority carriers, thereby obtaining a P-type conductivity type substrate 10.

[0046] Therefore, the conductivity type of the substrate 10 affects the overall electrical performance of the device, and it provides physical and electrical support for other layers and structures of the device. The conductivity type determines factors such as the electric field distribution and the carrier conduction mechanism, and therefore can affect the response speed, on-off characteristics of the device in practical applications.

[0047] In some embodiments, the metal electrode 20 may be a conductive structure for providing electrical connection. It is located on the upper surface of the substrate 10 and is used to implement input and output of current or signals. The metal electrode 20 may be a conductive layer formed by a deposition process, which is directly connected to an external circuit or device to provide electrical contact.

[0048] In some embodiments, the metal electrode 20 can be made of metal materials such as gold-tin solder (AuSn). Among them, the melting point of gold-tin solder (AuSn) is about 280°C, which is suitable for use in high temperature environments. In addition, gold-tin solder (AuSn) has good conductivity and high mechanical strength, can effectively transmit electrical signals, make the device more stable, and suitable for long-term use. Therefore, gold-tin solder (AuSn) is often used in electronic devices that require high reliability and durability.

[0049] In addition to gold-tin solder (AuSn), other metal materials can also be selected to prepare the metal electrode 20. The specific selection depends on factors such as application requirements, working environment and cost. For example, aluminum (Al), copper (Cu), silver (Ag), etc. Among them, aluminum is widely used in most integrated circuits, has low cost and mature process, but its performance may not be as good as gold-tin solder in high temperature or high power applications. Copper has good conductivity and heat dissipation, and is often used in power devices or applications that require higher current carrying capacity. Copper electrodes are suitable for high-power electronic components, but they are easily oxidized and require proper packaging protection. Silver has excellent conductivity and is suitable for high-frequency and radio frequency applications. However, silver is easily oxidized in the air and also requires surface protection to ensure long-term stability.

[0050] In some embodiments, the first leakage protection layer 30 may be an insulating material layer in the semiconductor device 1, which is located on the surface of the substrate 10 between the metal electrode 20 and the side of the substrate 10. The main function of the first leakage protection layer 30 is to form electrical isolation, prevent the metal electrode 20 material from overflowing to the side of the substrate 10 during the process of die bonding or wire bonding, and avoid unnecessary conductive paths between the metal electrode 20 and the side of the substrate 10, thereby effectively avoiding leakage.

[0051] In some embodiments, the material of the first leakage protection layer 30 can be selected according to the specific application scenario and device requirements. Common materials may include silicon dioxide (SiO2), silicon nitride (Si3N4) or other dielectric materials with excellent insulation. Among them, silicon dioxide (SiO2) has excellent insulation properties and can also withstand high temperatures, so it is widely used in integrated circuits and power devices. Silicon nitride (Si3N4) has high dielectric strength and mechanical strength, and has better chemical stability in a humid environment. Therefore, it is suitable for semiconductor devices 1 working in harsh environments, especially in high voltage, high humidity or high frequency applications. In addition, in some high-performance devices, organic insulating materials such as polyimide can be used as the first leakage protection layer 30. This type of material has good flexibility, high temperature resistance and insulation properties, and is suitable for some application scenarios with extremely high electrical performance requirements and complex environments.

[0052] According to the semiconductor device 1 of the embodiment of the present invention, a first leakage protection layer 30 is provided between the metal electrode 20 and the side of the substrate 10. The first leakage protection layer 30 has excellent insulation performance and can form an effective isolation protection, thereby preventing the metal electrode 20 from overflowing to the side of the substrate 10 during the solid crystal or wire bonding process. This can avoid the formation of a conductive path between the metal electrode 20 and the side of the substrate 10, reducing the potential risk of leakage. In addition, the presence of the first leakage protection layer 30 can also prevent the conductive adhesive on the back of the substrate 10 from migrating upward, further reducing the occurrence of leakage problems. This design ensures the insulation between the metal electrode 20 and the side of the substrate 10, effectively improving the overall stability and reliability of the device.

[0053] In some embodiments, the first leakage protection layer 30 is constructed as at least one step, which means that the protection layer is not just a flat insulating material in design, but has a certain step-like structure. This step structure can indicate that a level difference is introduced in the first leakage protection layer 30, that is, different areas of the first leakage protection layer 30 have different heights or thicknesses. This structural design can be formed by deposition, photolithography and etching processes of insulating materials. The height of the step can be designed according to the thickness of the metal electrode 20 and the device operating voltage. Higher voltage devices may require thicker insulating layers to provide stronger electrical isolation capabilities.

[0054] In some embodiments, designing the first leakage protection layer 30 as a step structure can increase the length of the leakage path, thereby effectively improving the insulation performance. The step structure helps to form a stronger electric field shielding effect, thereby preventing leakage between the metal electrode 20 and the side of the substrate 10, especially when the metal electrode 20 is close to the edge. If it is only a planar insulating layer, it may not provide sufficient protection at the edge of the device, and the step structure can further enhance the leakage protection effect of the edge area.

[0055] In addition, the step structure design can not only prevent the overflow of the metal electrode 20 material, but also play a better buffering and supporting role in the process operation of the electrode, thereby improving the overall reliability. In high-voltage or high-temperature applications, the step structure can also help disperse stress and reduce the impact of material deformation on electrical performance.

[0056] In some embodiments, the first leakage protection layer 30 is constructed as a plurality of steps, and the plurality of steps are continuously arranged along the side of the metal electrode 20 to the substrate 10. The continuous arrangement design of the plurality of steps means that they are geometrically continuously distributed, extending from the metal electrode 20 to the side of the substrate 10. This continuity ensures that the first leakage protection layer 30 maintains consistency throughout the structure without interruptions or irregular areas. By further increasing the length of the leakage path, the insulation effect is enhanced and the risk of leakage current is reduced. The key purpose of this design is to create a more complex geometric path between the electrode and the substrate 10, making it difficult for the leakage current to conduct through the path.

[0057] In addition, the continuous multiple step design can also help disperse the electric field distribution. Especially in high-voltage devices, the electric field is often concentrated in the edge area of ​​the metal electrode 20 and the substrate 10, which can easily lead to breakdown or leakage. By designing multiple steps, the electric field can be dispersed and weakened layer by layer, reducing the risk of excessive concentration of the electric field in the side edge area, thereby improving the breakdown voltage and reliability of the device.

[0058] like Figure 1 As shown, the first leakage protection layer 30 includes a first passivation layer 31, and the first passivation layer 31 is located on the surface of the substrate 10 between the metal electrode 20 and the side of the substrate 10. The main function of the first passivation layer 31 is to provide electrical isolation to prevent the metal electrode 20 from overflowing during the die bonding or wire bonding process or the adhesive on the back of the substrate 10 from migrating to the upper surface through the side wall to cause leakage. In addition to the electrical isolation function, the passivation layer can also protect the edge area of ​​the substrate 10 from corrosion by the external environment such as moisture, oxidation and chemicals, thereby increasing the reliability and life of the device. In some embodiments, the material of the first passivation layer 31 may include silicon dioxide (SiO2), silicon nitride (Si3N4), etc. These materials have good insulation properties and can maintain chemical stability in harsh environments such as high temperature and high humidity. For specific application scenarios, organic materials such as polyimide (PI) or other high insulation and high temperature resistance materials can also be selected to form the first passivation layer 31.

[0059] In some embodiments, the thickness H1 of the first passivation layer 31 satisfies: 0.5um≤H1≤1.5um. The setting of this range is not only closely related to the electrical isolation effect required by the device, but also takes into account factors such as the feasibility of the manufacturing process, cost and application environment.

[0060] Among them, 0.5um is selected as the lower limit to ensure that the first passivation layer 31 has sufficient thickness to provide effective electrical isolation. If the first passivation layer 31 is too thin, it may not be able to effectively prevent leakage current between the metal electrode 20 and the side of the substrate 10, especially under high voltage environment. In addition, a too thin passivation layer is easily damaged during the process of die bonding or wire bonding, affecting the overall performance of the device.

[0061] The upper limit of 1.5um takes into account the balance between process and cost. If the first passivation layer 31 is too thick, although the electrical isolation capability is increased, it may also introduce mechanical stress or affect the packaging reliability of the device. In addition, if the thickness of the first passivation layer 31 is too large, it may increase the difficulty of the manufacturing process. For example, it is more difficult to control the accuracy during the photolithography and etching process, affecting the dimensional consistency and yield of the device.

[0062] Therefore, the appropriate thickness of the first passivation layer 31 can ensure the effectiveness of electrical insulation performance, prevent leakage current and electric field concentration, and provide necessary support and buffering in mechanical performance to reduce the risk of stress concentration. The thickness range (0.5um≤H1≤1.5um) fully considers the requirements of different application scenarios for insulation performance, mechanical strength, thermal stability, etc.

[0063] like Figure 1 As shown, the first leakage protection layer 30 also includes a second passivation layer 32, which is another layer of insulating material located on the first passivation layer 31. This layer of insulating material can be the same or different from the first passivation layer 31, and its main function is also to provide additional electrical isolation, thereby effectively reducing the leakage current between the metal electrode 20 and the side of the substrate 10. In addition, the second passivation layer 32 provides additional protection for the first passivation layer 31, especially under harsh environmental conditions (such as high humidity, corrosive gases, etc.). It can effectively prevent the external environment from corroding the first passivation layer 31, thereby improving the long-term reliability of the device.

[0064] In some embodiments, the material selection of the second passivation layer 32 can be adjusted according to the requirements of specific applications, and commonly used materials include silicon dioxide (SiO2), silicon nitride (Si3N4) or other insulating materials. The manufacturing process of the second passivation layer 32 can be achieved through a variety of technologies, including vapor deposition, photolithography, etching and other processes.

[0065] In some embodiments, the thickness value H2 of the second passivation layer 32 satisfies: 0.5um≤H2≤1.5um. The thickness of the second passivation layer 32 directly affects its electrical insulation performance. 0.5um is selected as the lower limit to ensure that it has a certain effectiveness in electrical isolation. If the second passivation layer 32 is too thin, it may not be able to effectively isolate the current between the metal electrode 20 and the substrate 10, especially under high voltage operating conditions, which may lead to an increase in leakage current. Under high voltage conditions, a thinner passivation layer may cause the electric field to concentrate in certain areas, thereby increasing the risk of electrical breakdown. Therefore, an appropriate thickness can effectively prevent this from happening.

[0066] Furthermore, the second passivation layer 32 provides additional protection under harsh environmental conditions (such as humidity, chemical corrosion, etc.). If its thickness is insufficient, its protective function may be affected, causing the first passivation layer 31 to be corroded by the external environment. An appropriate thickness can also help disperse the stress generated during the process and reduce the risk of damage caused by thermal expansion or mechanical stress.

[0067] In addition, the setting of the thickness range also takes into account the feasibility of lithography and etching during the manufacturing process. A passivation layer that is too thick may cause difficulties in process control, affecting the dimensional consistency and production yield of the device. A reasonable thickness range can help achieve better process control and improve production efficiency. Choosing a suitable thickness range also takes cost factors into consideration. A thicker passivation layer will increase material and processing costs, while a layer that is too thin may cause device failure, ultimately leading to higher repair and replacement costs.

[0068] Therefore, the design of the thickness H2 of the second passivation layer 32 within the range of 0.5 um≤H2≤1.5 um fully considers various factors such as electrical performance, mechanical strength, manufacturing feasibility and cost, and ensures the stability and reliability of the device.

[0069] Figure 2 is a structural cross-sectional view of a semiconductor device 1 according to yet another embodiment of the present invention, Figure 2 As shown, in addition to designing the first leakage protection layer 30 as a plurality of steps, the first leakage protection layer 30 can also be arranged in a slope from the metal electrode 20 to the side of the substrate 10, and the first leakage protection layer 30 forms a preset angle with the upper surface of the substrate 10. This design increases the separation space between the metal electrode 20 and the side of the substrate 10, ensuring that an effective physical barrier is formed between the metal electrode 20 and the side of the substrate 10, preventing the metal electrode 20 material from overflowing to the substrate 10, thereby generating a leakage risk.

[0070] In some embodiments, the slope design can be implemented through a variety of manufacturing processes, including physical vapor deposition (PVD), chemical vapor deposition (CVD), photolithography, and etching. By adjusting the process parameters, the angle and height of the slope can be precisely controlled to meet the design requirements of different applications. The slope design also helps to simplify the processing of subsequent devices, such as improving the alignment accuracy with other layers and reducing the requirements for the photolithography process, thereby improving production yield and manufacturing efficiency.

[0071] In some embodiments, the thickness value H3 of the first leakage protection layer 30 satisfies: 0.5um≤H3≤1.5um. Among them, the thickness range of 0.5um to 1.5um takes into account a variety of factors, including electrical insulation capability, mechanical stability, stress management, and reliability of the manufacturing process. For the thickness range of the first leakage protection layer 30, different manufacturing processes can accurately control its thickness by adjusting parameters such as deposition time, etching time, and process temperature. Through process optimization, it can be ensured that the thickness of the first leakage protection layer 30 is within the range of 0.5um to 1.5um, while meeting the electrical isolation and mechanical requirements of the device design.

[0072] In some embodiments, the first leakage protection layer 30 also covers part of the upper surface of the substrate 10, which can better isolate the potential leakage path between the metal electrode 20 and the substrate 10, and prevent the metal electrode 20 material from diffusing to the substrate 10 under high pressure or high temperature conditions. Specifically, in the semiconductor device 1, there is a potential difference between the metal electrode 20 and the substrate 10. If there is no effective isolation layer, the current may leak to the substrate 10 through the sidewall or tiny defects on the surface of the substrate 10, resulting in device performance degradation or failure. By covering the upper surface portion of the substrate 10 with the first leakage protection layer 30, the protection layer can not only prevent the current from leaking from the metal electrode 20 to the side of the substrate 10, but also prevent the current from flowing directly along the upper surface of the substrate 10, thereby effectively isolating the current path and reducing the risk of leakage.

[0073] In addition, the design of covering part of the surface of the substrate 10 helps to enhance the mechanical protection of the device, especially during the die bonding or welding process, the first leakage protection layer 30 can prevent mechanical stress from damaging the substrate 10. At the same time, it can also effectively prevent the substrate 10 from being exposed to the external environment, such as moisture, oxygen, corrosive chemicals, etc., thereby improving the durability and life of the device.

[0074] In some embodiments, the thickness value H4 of the first leakage protection layer 30 located on the upper surface of the substrate 10 satisfies: 1um≤H4≤3um. The thickness range is obtained by comprehensively considering the requirements of the semiconductor device 1 for leakage protection, electrical insulation, mechanical protection, process feasibility and other factors. Specifically, in the semiconductor device 1, effective electrical isolation is required between the metal electrode 20 and the substrate 10. The setting of H4 ensures that the first leakage protection layer 30 is thick enough to prevent leakage of current through the upper surface of the substrate 10. Especially in power devices, thicker protection layers can cope with higher operating voltages and effectively reduce the risk of current leakage.

[0075] In addition, the first leakage protection layer 30 within the thickness range not only provides electrical isolation, but also effectively enhances the mechanical strength of the upper surface of the substrate 10, especially in processes such as solid crystal and welding, and can resist damage to the device by external forces. Especially in large-size and high-power devices, the thicker protection layer can better resist the thermal stress and mechanical stress caused by temperature changes. The thicker first leakage protection layer 30 can also provide better protection against external environmental factors such as moisture, oxygen, and chemicals, and extend the service life of the device. In harsh working environments, such as high temperature, high humidity or chemical corrosion environments, a thickness of 1um to 3um can provide sufficient protection to avoid damage to the substrate 10 by the external environment.

[0076] like Figure 1 and Figure 2 As shown, the semiconductor device 1 further includes: at least one doping region 40 of a second conductivity type. The conductivity type of the doping region 40 is opposite to the conductivity type of the substrate 10. For example, if the conductivity type of the substrate 10 is P-type, the conductivity type of the doping region 40 is N-type. Conversely, if the conductivity type of the substrate 10 is N-type, the conductivity type of the doping region 40 is P-type.

[0077] In some embodiments, the doped region 40 is located in the substrate 10 and close to the upper surface of the substrate 10. The purpose of such a setting is to form a PN junction inside the device, thereby adjusting the electric field distribution and effectively alleviating the concentration of the electric field. Therefore, by introducing doped regions 40 of different conductivity types into the substrate 10, an electric field shielding layer can be formed, thereby reducing the electric field gradient inside the device. This is particularly important under high voltage conditions and helps prevent local breakdown caused by electric field concentration.

[0078] In some embodiments, the doped region 40 may be formed by ion implantation or diffusion processes. During the manufacturing process, the depth and concentration of doping may be precisely controlled to ensure that the region has the desired electrical properties.

[0079] like Figure 1 and Figure 2As shown, the semiconductor device 1 further includes: a metal dielectric layer 50. The metal dielectric layer 50 is located on the upper surface of the substrate 10 in an area corresponding to the doped region 40. The function of the metal dielectric layer 50 is to ensure that a stable ohmic contact is formed between the metal electrode 20 and the doped region 40 of the second conductivity type. This contact can form a low-impedance electrical connection between the metal electrode 20 and the doped region 40, allowing current to flow smoothly between the two. Good ohmic contact is an important condition for ensuring the normal operation and high efficiency of the device.

[0080] In some embodiments, the metal dielectric layer 50 can use a variety of metal materials, including but not limited to: titanium (Ti), nickel (Ni), platinum (Pt). Among them, titanium (Ti) has good electrical conductivity, corrosion resistance and good adhesion. Titanium (Ti) is usually used for the bottom metal dielectric layer 50 as a good interface material with the silicon substrate, especially maintaining good electrical properties under high temperature conditions. Nickel (Ni) has good electrical conductivity and corrosion resistance, and has good compatibility with many metals. Nickel can also form metal silicide (NiSi) with silicon to improve the stability of ohmic contact. Platinum has excellent electrical conductivity, high temperature resistance and corrosion resistance. Its chemical stability enables it to maintain good performance under many extreme conditions.

[0081] In some embodiments, the metal electrode 20 is connected to the metal dielectric layer 50 through a contact hole 70, and the contact hole 70 is formed by the first leakage protection layer 30 located on the upper surface of the substrate 10. Among them, the contact hole 70 is a channel connecting the metal electrode 20 and the metal dielectric layer 50, which can be formed by etching or other micromachining techniques. Such a hole allows the metal electrode 20 to effectively contact the metal dielectric layer 50, ensuring the reliability of the electrical connection. The size and shape of the contact hole 70 can be optimized according to the specific electrical characteristics.

[0082] like Figure 1-Figure 3 As shown, the semiconductor device 1 further includes: a second leakage protection layer 60, one end of the second leakage protection layer 60 is connected to the first leakage protection layer 30, and the second end of the second leakage protection layer 60 extends along the side of the substrate 10 and at least extends to a position close to the lower surface of the substrate 10. The main function of the second leakage protection layer 60 is to effectively isolate the gold-tin solder (AuSn) compound that is squeezed out during the eutectic process, prevent it from leaking to the substrate 10, and thus reduce the risk of leakage.

[0083] In some embodiments, the material of the second leakage protection layer 60 can be a passivation material with a high dielectric constant, such as silicon nitride (Si3N4) or silicon dioxide (SiO2), and the specific selection depends on the manufacturing process and performance requirements. These materials not only have excellent insulation properties, but also can effectively shield the electric field and improve the overall reliability of the device.

[0084] In addition, the thickness of the second leakage protection layer 60 should be designed according to the operating voltage of the device. In high voltage applications, a thicker protection layer can provide a stronger electric field shielding effect. For low voltage applications, appropriately thinning the thickness of the protection layer helps to reduce manufacturing costs while still maintaining sufficient electric field control effects.

[0085] In some embodiments, the second leakage protection layer 60 surrounds the lower surface of the substrate 10 to form an all-round isolation barrier, thereby enhancing the overall electrical insulation performance, making the electric field distribution between the substrate 10 and the external environment more uniform, and avoiding electrical breakdown caused by local electric field concentration. The surrounding design of the second leakage protection layer 60 can also provide additional physical protection for the substrate 10 to prevent external mechanical impact or chemical corrosion.

[0086] Figure 4 is a flow chart of a method for preparing a semiconductor device according to an embodiment of the present invention. Figure 4 As shown, the method for preparing a semiconductor device includes at least steps S1-S2, which are specifically as follows: S1, providing a substrate of a first conductivity type.

[0087] In some embodiments, the conductivity type of the substrate may be P-type or N-type, wherein the N-type conductivity type is obtained by doping impurities of pentavalent elements such as phosphorus (P) and arsenic (As) to generate additional free electrons in the material as majority carriers, thereby obtaining an N-type conductivity type substrate. The P-type conductivity type is obtained by doping impurities of trivalent elements such as boron (B) to generate holes in the material as majority carriers, thereby obtaining a P-type conductivity type substrate.

[0088] In some embodiments, the substrate may be made of silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs) and other materials, each of which has different electrical and thermal properties and can meet the application requirements of specific devices.

[0089] In some embodiments, the substrate should be strictly cleaned before preparation to remove surface impurities and oxide layers. Chemical solvents (such as acetone, isopropyl alcohol) and ultrasonic cleaning techniques can be used. To ensure adhesion in subsequent processes, surface roughening or flattening can also be performed to enhance the bonding strength of the material.

[0090] S2, preparing a first leakage protection layer and a metal electrode on the substrate, wherein the metal electrode is located on the upper surface of the substrate, and the first leakage protection layer is located on the surface of the substrate between the metal electrode and the side surface of the substrate.

[0091] In some embodiments, the main function of the first leakage protection layer is to form electrical isolation to prevent the metal electrode material from overflowing to the side of the substrate during the crystal bonding or wire bonding process, and to avoid the generation of unnecessary conductive paths between the metal electrode and the side of the substrate, thereby effectively avoiding leakage.

[0092] In some embodiments, the first leakage protection layer can be made of an insulating material with a high dielectric constant, such as silicon nitride (Si3N4) or silicon dioxide (SiO2). The selection of the material should take into account its electrical insulation performance, mechanical strength, and environmental stability to ensure its reliability under various working conditions.

[0093] In some embodiments, the first leakage protection layer can be prepared by thermal oxidation or chemical vapor deposition (CVD). The thermal oxidation method can form a uniform oxide layer on the substrate surface, while the CVD method can achieve high-quality thin film deposition and is suitable for surfaces with complex shapes.

[0094] In some embodiments, the metal electrode can be made of metal materials such as gold-tin solder (AuSn). Among them, the melting point of gold-tin solder (AuSn) is about 280°C, which is suitable for use in high temperature environments. In addition, gold-tin solder (AuSn) has good conductivity and high mechanical strength, can effectively transmit electrical signals, make the device more stable, and suitable for long-term use. Therefore, gold-tin solder (AuSn) is often used in electronic devices that require high reliability and durability.

[0095] In some embodiments, the metal electrode can be prepared by using sputtering deposition or evaporation technology to uniformly deposit the metal material on the substrate, form the desired electrode shape on the metal film by photolithography, and remove the excess metal by development and etching technology to leave the desired electrode structure.

[0096] According to the method for preparing a semiconductor device according to an embodiment of the present invention, a first leakage protection layer is prepared between the metal electrode and the side of the substrate. The first leakage protection layer has excellent insulation properties and can form an effective isolation protection, thereby preventing the metal electrode from overflowing to the side of the substrate during the solid crystal or wire bonding process. This can avoid the formation of a conductive path between the metal electrode and the side of the substrate, reducing the potential risk of leakage. In addition, the presence of the first leakage protection layer can also prevent the conductive adhesive on the back of the substrate from migrating upward, further reducing the occurrence of leakage problems. This design ensures the insulation between the metal electrode and the side of the substrate, effectively improving the overall stability and reliability of the device.

[0097] In some embodiments, preparing a first leakage protection layer on a substrate includes: preparing at least one step structure on the surface of the substrate between the metal electrode and the side of the substrate. Forming the first leakage protection layer on the surface of the at least one step structure, the first leakage protection layer is constructed as at least one step.

[0098] Among them, constructing the first leakage protection layer as at least one step can increase the length of the leakage path, thereby effectively improving the insulation performance. The step structure helps to form a stronger electric field shielding effect, thereby preventing leakage between the metal electrode and the side of the substrate, especially when the metal electrode is close to the edge.

[0099] In some embodiments, the step structure can be formed by photolithography and etching processes. Specifically, first, a layer of photoresist is applied to the surface of the substrate. Then, a photolithography machine is used to project the designed pattern onto the photoresist. After exposure, the photoresist undergoes a chemical reaction in a specific area. The exposed substrate is placed in a developer, and the unexposed photoresist is removed to form the desired pattern. Then, a wet or dry etching process is used to remove the portion of the substrate surface that is not protected by the photoresist. This process can form a step shape on the substrate. After the etching is completed, the residual photoresist is removed, leaving a substrate with a step structure.

[0100] In some embodiments, forming a first leakage protection layer on the surface of at least one step structure includes: forming a first passivation layer on the surface of at least one step structure, forming a second passivation layer on the first passivation layer, and the first passivation layer and the second passivation layer constitute the first leakage protection layer.

[0101] In some embodiments, the first passivation layer and the second passivation layer can be made by thermal oxidation or chemical vapor deposition (CVD) and other methods. By superimposing the two passivation layers, the first leakage protection layer has good electrical isolation capability, which can effectively prevent the metal electrode from overflowing to the side of the substrate during the process of solid crystal or wire bonding, thereby reducing the risk of leakage.

[0102] In some embodiments, preparing the first leakage protection layer on the substrate further includes: forming a sloped first leakage protection layer on the surface of the substrate between the metal electrode and the side of the substrate, the first leakage protection layer forming a preset angle with the upper surface of the substrate.

[0103] Among them, the sloped design increases the separation space between the metal electrode and the side of the substrate, ensuring that an effective physical barrier is formed between the metal electrode and the side of the substrate to prevent the metal electrode material from overflowing into the substrate, thereby causing the risk of leakage.

[0104] In some embodiments, the slope design can be realized by a variety of manufacturing processes, including photolithography, etching, thermal oxidation, chemical vapor deposition (CVD), etc. During the etching process, the etching time and rate need to be precisely controlled to ensure that the angle and shape of the slope meet the design requirements.

[0105] In some embodiments, the first leakage protection layer also covers a portion of the upper surface of the substrate, and the method further includes: preparing at least one doped region of the second conductivity type in the substrate and near the upper surface of the substrate. Preparing a metal dielectric layer in an area corresponding to the doped region on the upper surface of the substrate, wherein the metal electrode is connected to the metal dielectric layer through a contact hole, and the contact hole is constructed by the first leakage protection layer located on the upper surface of the substrate.

[0106] In some embodiments, the second conductivity type may be P type or N type. If the first conductivity type is P type, the second conductivity type is N type; conversely, if the first conductivity type is N type, the second conductivity type is P type. The doped region may be formed by ion implantation or diffusion processes, which can effectively control the depth and concentration of doping, thereby ensuring that the region has the desired electrical properties.

[0107] In some embodiments, the material of the metal dielectric layer can be selected from metals with good electrical conductivity and chemical stability, such as titanium (Ti), nickel (Ni), platinum (Pt), etc. The metal dielectric layer can be formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD) and other techniques, which ensure uniform deposition of the metal dielectric layer and avoid the problem of poor local electrical conductivity.

[0108] In some embodiments, the contact hole may be formed by processes such as photolithography and etching to ensure good connection between the metal electrode and the metal dielectric layer, thereby ensuring smooth flow of current.

[0109] In some embodiments, the method for preparing a semiconductor device also includes: preparing a second leakage protection layer on the side of the substrate, one end of the second leakage protection layer is connected to the first leakage protection layer, and the second end of the second leakage protection layer extends along the side of the substrate at least to a position close to the lower surface of the substrate.

[0110] In some embodiments, the material of the second leakage protection layer can be selected from materials with good insulation properties, high temperature resistance and chemical corrosion resistance, such as silicon dioxide (SiO2), silicon nitride (Si3N4), etc.

[0111] In some embodiments, the second leakage protection layer may be formed by a process similar to that of the first leakage protection layer, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD), etc. These techniques can ensure uniform coverage of the insulating layer on the side of the substrate.

[0112] In some embodiments, the second leakage protection layer surrounds the lower surface of the substrate. This means that the entire lower surface of the substrate is covered by the second leakage protection layer, so that the entire device has a more complete leakage protection structure. Especially for the edge and back of the semiconductor device, this fully covered leakage protection design can effectively prevent leakage caused by electric field concentration. In addition, during the preparation process, the thickness and uniformity of the second leakage protection layer can be optimized by adjusting the etching and deposition process parameters.

[0113] As Figure 1 Taking the semiconductor device shown in FIG. 1 as an example, the preparation process of the semiconductor device may include the following steps: First, provide a silicon substrate of a first conductivity type. The substrate may be an N-type or P-type silicon substrate. The N-type silicon substrate is obtained by doping with phosphorus impurities, and the P-type silicon substrate is obtained by doping with boron impurities. The thickness of the substrate is 150 um.

[0114] Second, photoresist is coated on the surface of the substrate, and then the required pattern is produced through exposure and development methods so that it can be subsequently etched in the appropriate area to form a specific shape.

[0115] Third, chemical substances are used to etch the substrate surface according to the pattern produced in the above-mentioned photolithography step, so as to form at least one step structure on the substrate surface between the metal electrode and the side of the substrate. This structure provides support for the subsequent generation of the first passivation layer, and extends the path from the metal electrode to the side of the substrate, thereby forming a barrier between the metal electrode and the side of the substrate, and preventing it from overflowing to the side of the substrate to cause leakage.

[0116] Fourth, use chemical cleaning solution to clean the substrate to remove organic and inorganic impurities on the surface.

[0117] Fifth, a first passivation layer is formed on the side of the substrate by thermal oxidation or chemical vapor deposition. The first passivation layer can be silicon dioxide (SiO2), silicon nitride (Si3N4) or other insulating materials. Its main function is to provide moisture and leakage protection. The thickness of the first passivation layer is 0.5um to 1.5um.

[0118] Sixth, a photoresist is coated on the surface of the first passivation layer, and then a desired pattern is produced through exposure and development methods, so that contact holes can be subsequently opened in appropriate areas.

[0119] Seventh, chemical gases (such as trifluoromethyl (CF3), sulfur hexafluoride (SF6) and oxygen (O2)) are used to etch holes on the surface of the first passivation layer under the guidance of the photolithography pattern in the above step to form contact holes.

[0120] Eighth, at high temperature, doping the contact hole with impurities of the second conductivity type to form two symmetrically distributed doping regions of the second conductivity type. If the conductivity type of the substrate is N-type, the doping region is doped with boron impurities to form a P-type doping region. If the conductivity type of the substrate is P-type, the doping region is doped with arsenic or phosphorus impurities to form an N-type doping region. The thickness of the doping region is 3um to 6um.

[0121] Ninth, a photoresist is coated on the surface of the oxide layer (first passivation layer) of the second conductive type doping area, and then a desired pattern is produced through exposure and development methods so that contact holes can be subsequently opened in appropriate areas.

[0122] Tenth, the oxide layer (first passivation layer) of the doped area is etched and opened by chemical gases (such as trifluoromethyl (CF3), sulfur hexafluoride (SF6) and oxygen (O2)) under the guidance of the photolithography pattern in the above step to form contact holes again.

[0123] Eleventh, metal is deposited in the contact hole to form a metal dielectric layer. The metal dielectric layer can be made of materials such as titanium (Ti), nickel (Ni) or platinum (Pt), which have good conductivity, corrosion resistance and good adhesion.

[0124] 12. A second passivation layer is formed on the surface of the substrate by thermal oxidation or chemical vapor deposition (CVD). The second passivation layer can be silicon dioxide (SiO2) or silicon nitride (Si3N4) or other insulating materials, used for moisture and leakage protection. The thickness of the second passivation layer is set between 0.5um and 1.5um to ensure sufficient insulation effect while taking into account the feasibility of the process.

[0125] Thirteenth, a photoresist is coated on the surface of the newly formed passivation layer, and then the required pattern is produced through exposure and development methods, so that contact holes can be opened in appropriate areas later.

[0126] Fourteenth, according to the photolithography pattern, a hole is opened on the surface of the second passivation layer through an etching process to form a contact hole again for the subsequent deposition of a metal electrode.

[0127] 15. Metal deposition is performed in the contact hole and on the surface of the second passivation layer to form a metal electrode. The material of the metal electrode can use gold-tin solder (AuSn), and the thickness of the metal electrode is 2um to 5um. In practical applications, the conductive connection with the substrate is achieved through the eutectic process.

[0128] 16. Through laser cutting technology, the entire silicon wafer is cut into individual independent devices. This process ensures that each device can be subsequently tested and packaged separately.

[0129] 17. Through the method of evaporation coating, silicon dioxide (SiO2) or silicon nitride (Si3N4) material is deposited on the side of the substrate to form a second leakage protection layer. In practical applications, it effectively isolates the gold-tin solder (AuSn) compound that is squeezed out during the eutectic process to prevent it from overflowing to the substrate and causing leakage.

[0130] As Figure 2 Taking the semiconductor device shown in FIG. 1 as an example, the preparation process of the semiconductor device may include the following steps: First, provide a silicon substrate of a first conductivity type. The substrate may be an N-type or P-type silicon substrate. The N-type silicon substrate is obtained by doping with phosphorus impurities, and the P-type silicon substrate is obtained by doping with boron impurities. The thickness of the substrate is 150 um.

[0131] Second, photoresist is coated on the surface of the substrate, and then the required pattern is produced through exposure and development methods so that it can be subsequently etched in the appropriate area to form a specific shape.

[0132] Third, a chemical substance is used to etch the substrate surface according to the pattern produced in the above-mentioned photolithography step, and a sloped first leakage protection layer is formed on the substrate surface between the metal electrode and the side of the substrate, and the first leakage protection layer is at a preset angle with the upper surface of the substrate. The partition space from the metal electrode to the side of the substrate is increased, and in practical applications, a barrier is formed between the metal electrode and the side of the substrate to prevent it from overflowing to the substrate and causing leakage.

[0133] Fourth, use chemical cleaning solution to clean the substrate to remove organic and inorganic impurities on the surface.

[0134] Fifth, a first leakage protection layer is formed on the side of the substrate by thermal oxidation or chemical vapor deposition. The first leakage protection layer can be silicon dioxide (SiO2), silicon nitride (Si3N4) or other insulating materials. Its main function is to provide moisture and leakage protection. The thickness of the first leakage protection layer is 0.5um to 1.5um.

[0135] Sixth, a photoresist is coated on the surface of the first leakage protection layer, and then a desired pattern is produced through exposure and development methods, so that contact holes can be subsequently opened in appropriate areas.

[0136] Seventh, chemical gases (such as trifluoromethyl (CF3), sulfur hexafluoride (SF6) and oxygen (O2)) are used to etch holes on the surface of the first leakage protection layer under the guidance of the photolithography pattern in the above steps to form contact holes.

[0137] Eighth, at high temperature, doping the contact hole with impurities of the second conductivity type to form two symmetrically distributed doping regions of the second conductivity type. If the conductivity type of the substrate is N-type, the doping region is doped with boron impurities to form a P-type doping region. If the conductivity type of the substrate is P-type, the doping region is doped with arsenic or phosphorus impurities to form an N-type doping region. The thickness of the doping region is 3um to 6um.

[0138] Ninth, a photoresist is coated on the surface of the oxide layer (first leakage protection layer) of the second conductive type doping area, and then a desired pattern is produced through exposure and development methods so that contact holes can be subsequently opened in appropriate areas.

[0139] Tenth, the oxide layer (first leakage protection layer) of the doped area is etched and opened by chemical gases (such as trifluoromethyl (CF3), sulfur hexafluoride (SF6) and oxygen (O2)) under the guidance of the photolithography pattern in the above step to form contact holes again.

[0140] Eleventh, metal is deposited in the contact hole to form a metal dielectric layer. The metal dielectric layer can be made of materials such as titanium (Ti), nickel (Ni) or platinum (Pt), which have good conductivity, corrosion resistance and good adhesion.

[0141] Twelfth, a first leakage protection layer is continuously generated on the surface of the substrate by thermal oxidation or chemical vapor deposition (CVD) method, with a thickness of 0.5um to 1.5um.

[0142] Thirteenth, a photoresist is coated on the surface of the first leakage protection layer, and then a desired pattern is produced through exposure and development methods, so that contact holes can be subsequently opened in appropriate areas.

[0143] Fourteenth, according to the photolithography pattern, a hole is opened on the surface of the first leakage protection layer through an etching process to form a contact hole again for the subsequent deposition of a metal electrode.

[0144] 15. Metal deposition is performed in the contact hole and on the surface of the first leakage protection layer to form a metal electrode. The material of the metal electrode can be gold-tin solder (AuSn), and the thickness of the metal electrode is 2um to 5um. In practical applications, the conductive connection with the substrate is achieved through the eutectic process.

[0145] 16. Through laser cutting technology, the entire silicon wafer is cut into individual independent devices. This process ensures that each device can be tested and packaged separately. 17. Through the method of evaporation coating, silicon dioxide (SiO2) or silicon nitride (Si3N4) material is deposited on the side of the substrate to form a second leakage protection layer. In practical applications, it effectively isolates the gold-tin solder (AuSn) compound that is squeezed out during the eutectic process to prevent it from overflowing to the substrate and causing leakage.

[0146] In general, the embodiments of the present invention can be realized through multiple photolithography, etching, deposition, evaporation and coating process steps. Figure 1 and Figure 2 Preparation of semiconductor devices.

[0147] Reference below Figure 5 An electronic device according to an embodiment of the present invention is described.

[0148] Figure 5 is a block diagram of an electronic device according to an embodiment of the present invention, such as Figure 5 As shown, the electronic device 110 includes the semiconductor device 1 described in the above embodiment.

[0149] In some embodiments, the electronic device 110 may include but is not limited to smart electronic products (such as smart phones, tablets, smart watches, laptops, etc.), automotive electronic systems, communication equipment (such as base stations, switches, routers, etc.), industrial equipment (such as automation equipment, robots, controllers, etc.), and medical equipment (such as CT scanners, ultrasound equipment, and heart rate monitors, etc.).

[0150] The electronic device 110 according to the embodiment of the present invention, by adopting the semiconductor device 1 described in the above embodiment, realizes effective isolation between the metal electrode 20 and the side of the substrate 10, reduces the potential risk of leakage, and thus improves the stability and reliability of the device.

[0151] like Figure 5 As shown, the electronic device 110 includes a light emitting diode light source 2. The light emitting diode light source 2 is a highly efficient and long-life light source and is widely used in various electronic devices 110, such as display screens, lighting equipment, communication equipment, etc. The high brightness and low power consumption characteristics of the light emitting diode light source 2 make it a common choice in modern electronic devices 110.

[0152] In some embodiments, the semiconductor device 1 includes a transient voltage suppression diode (TVS). A transient voltage suppression diode is a device specifically used to protect electronic circuits from transient high voltages (such as electrostatic discharge, surge current, or lightning strikes). When a transient overvoltage occurs in a circuit, the TVS diode can quickly turn on and absorb energy to prevent the voltage from rising to a level that damages the device. The design feature of the TVS diode is that it has a very fast response speed and is suitable for occasions where sensitive components (such as light-emitting diodes) need to be protected.

[0153] In some embodiments, the LED light source 2 further includes a LED and a substrate, the LED is located on the substrate, and the transient suppression diode is flip-chip connected to the substrate to be connected in parallel with the LED. Specifically, under normal conditions, the transient suppression diode is high impedance and can be regarded as an open circuit (ideal state), which does not affect the operation of the LED. When subjected to transient high voltage impact, the transient suppression diode immediately uses the avalanche breakdown effect of the PN junction to change the impedance from high impedance to low impedance, and the surge generated by the high voltage is shunted by the transient suppression diode, so that the LED is effectively protected.

[0154] In some embodiments, the TVS diode is flip-chip connected to the substrate, which means that the TVS diode is directly in contact with the pads on the substrate through flip-chip welding technology, achieving a more compact, low-inductance connection, further improving the circuit's response speed and electrical performance. Specifically, flip-chip technology is an advanced packaging technology that shortens the electrical path and reduces the package volume by inverting the chip and connecting it directly to the substrate. The main advantage of this technology is that it reduces parasitic inductance and resistance, and improves the device's response speed and heat dissipation performance. The TVS diode uses flip-chip technology, which helps to increase its reaction speed in the circuit, thereby more effectively protecting the light-emitting diode.

[0155] In some embodiments, the substrate is used to support the light-emitting diode and the transient suppression diode, and the substrate material can be selected from materials with good thermal conductivity, such as ceramics, metals, or composite materials. The design of the substrate should ensure stable connection between the light-emitting diode and the transient suppression diode, and provide good heat dissipation and electrical performance.

[0156] Reference below Figure 6-Figure 7 A vehicle according to an embodiment of the present invention will be described.

[0157] Figure 6 is a block diagram of a vehicle according to an embodiment of the present invention, Figure 6As shown, the vehicle 100 includes the semiconductor device 1 described in the above embodiment. Among them, the semiconductor device 1 may involve an electronic control unit (ECU), a sensor, a power management module, etc. These devices are widely used in various subsystems of the vehicle 100, such as a power system, a braking system, a body control system, an infotainment system, etc. The design of the semiconductor device 1 can achieve more precise current control, reduce power consumption, leakage protection and other functions in the vehicle 100. These technical advantages can make the electronic system of the vehicle 100 more reliable and more efficient.

[0158] Figure 7 is a block diagram of a vehicle according to yet another embodiment of the present invention, Figure 7 As shown, the vehicle 100 includes the electronic device 110 described in the above embodiment. Among them, the electronic device 110 includes a light emitting diode light source 2 and a transient suppression diode, and is widely used in the vehicle 100, especially in parts related to the lighting system, signal system, display system, etc. of the vehicle 100. For example, the light emitting diode light source 2 is widely used in the headlights, taillights, turn signals and interior lighting of the vehicle 100, while the transient suppression diode can prevent the light emitting diode from being damaged due to voltage spikes or transient currents. This design not only improves the electrical stability of the vehicle 100, but also extends the service life of the light emitting diode light source 2.

[0159] According to the vehicle 100 of the embodiment of the present invention, by adopting the semiconductor device 1 or the electronic device 110 described in the above embodiment, the first leakage protection layer 30 inside has excellent insulation performance, which can form an effective isolation protection, thereby preventing the metal electrode 20 from overflowing to the side of the substrate 10 during the solid crystal or wire bonding process, thereby avoiding the formation of a conductive path between the metal electrode 20 and the side of the substrate 10, reducing the potential risk of leakage. In addition, the presence of the first leakage protection layer 30 can also prevent the conductive adhesive on the back of the substrate 10 from migrating upward, further reducing the occurrence of leakage problems. This design ensures the insulation between the metal electrode 20 and the side of the substrate 10, thereby improving the overall performance of the vehicle 100.

[0160] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0161] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: include: a substrate of a first conductivity type; a metal electrode, the metal electrode being located on the upper surface of the substrate; A first leakage protection layer is located on the surface of the substrate between the metal electrode and the side surface of the substrate.

2. The semiconductor device according to claim 1, wherein: The first leakage protection layer is configured as at least one step.

3. The semiconductor device according to claim 2, characterized in that The first leakage protection layer is constructed as a plurality of steps, and the plurality of steps are continuously arranged along the side from the metal electrode to the substrate.

4. The semiconductor device according to claim 2, characterized in that The first leakage protection layer comprises: A first passivation layer is located on the surface of the substrate between the metal electrode and the side of the substrate.

5. The semiconductor device according to claim 4, characterized in that The thickness H1 of the first passivation layer satisfies: 0.5um≤H1≤1.5um.

6. The semiconductor device according to claim 4, characterized in that The first leakage protection layer also includes: A second passivation layer is located on the first passivation layer.

7. The semiconductor device according to claim 6, characterized in that The thickness H2 of the second passivation layer satisfies: 0.5um≤H2≤1.5um.

8. The semiconductor device according to claim 1, wherein: The first leakage protection layer is arranged in a slope from the metal electrode to the side surface of the substrate, and the first leakage protection layer forms a preset angle with the upper surface of the substrate.

9. The semiconductor device according to claim 8, characterized in that The thickness value H3 of the first leakage protection layer satisfies: 0.5um≤H3≤1.5um.

10. The semiconductor device according to claim 1, wherein: The first leakage protection layer also covers a portion of the upper surface of the substrate.

11. The semiconductor device according to claim 10, characterized in that The thickness value H4 of the first leakage protection layer located on the upper surface of the substrate satisfies: 1um≤H4≤3um.

12. The semiconductor device according to claim 10, characterized in that The semiconductor device further comprises: At least one doped region of the second conductivity type is located in the substrate and close to the upper surface of the substrate.

13. The semiconductor device according to claim 12, characterized in that The semiconductor device further comprises: A metal dielectric layer, the metal dielectric layer being located on the upper surface of the substrate in a region corresponding to the doped region; The metal electrode is connected to the metal dielectric layer through a contact hole, and the contact hole is formed by the first leakage protection layer located on the upper surface of the substrate.

14. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: A second leakage protection layer, one end of the second leakage protection layer is connected to the first leakage protection layer, and a second end of the second leakage protection layer extends along the side surface of the substrate and at least extends to a position close to the lower surface of the substrate.

15. The semiconductor device according to claim 14, characterized in that The second leakage protection layer surrounds the lower surface of the substrate.

16. A method for preparing a semiconductor device, characterized in that: include: providing a substrate of a first conductivity type; A first leakage protection layer and a metal electrode are prepared on the substrate, wherein the metal electrode is located on the upper surface of the substrate, and the first leakage protection layer is located on the surface of the substrate between the metal electrode and the side surface of the substrate.

17. The method according to claim 16, characterized in that Preparing a first leakage protection layer on the substrate, comprising: preparing at least one step structure on the surface of the substrate between the metal electrode and the side of the substrate; The first leakage protection layer is formed on the surface of the at least one step structure, and the first leakage protection layer is configured as at least one step.

18. The method according to claim 17, characterized in that The first leakage protection layer is formed on the surface of the at least one step structure, comprising: forming a first passivation layer on a surface of the at least one step structure; A second passivation layer is formed on the first passivation layer, and the first passivation layer and the second passivation layer constitute the first leakage protection layer.

19. The method according to claim 16, characterized in that Preparing a first leakage protection layer on the substrate, comprising: The first leakage protection layer is formed in a sloped manner on the surface of the substrate between the metal electrode and the side surface of the substrate, and the first leakage protection layer forms a preset angle with the upper surface of the substrate.

20. The method according to claim 16, characterized in that The first leakage protection layer also covers a portion of the upper surface of the substrate, and the method further includes: Preparing at least one doped region of a second conductivity type in the substrate and close to an upper surface of the substrate; A metal dielectric layer is prepared in an area corresponding to the doped region on the upper surface of the substrate, wherein the metal electrode is connected to the metal dielectric layer through a contact hole, and the contact hole is constructed by the first leakage protection layer located on the upper surface of the substrate.

21. The method according to any one of claims 16 to 20, characterized in that: The method further comprises: A second leakage protection layer is prepared on the side of the substrate, one end of the second leakage protection layer is connected to the first leakage protection layer, and the second end of the second leakage protection layer extends along the side of the substrate at least to a position close to the lower surface of the substrate.

22. The method according to claim 21, characterized in that The second leakage protection layer surrounds the lower surface of the substrate.

23. An electronic device, characterized in that: The electronic device comprises the semiconductor device according to any one of claims 1 to 15.

24. The electronic device according to claim 23, characterized in that: The electronic device includes a light emitting diode light source.

25. The electronic device according to claim 24, characterized in that: The semiconductor device includes a transient suppression diode; The LED light source further includes a LED and a substrate. The LED is located on the substrate. The transient suppression diode is flip-chip connected to the substrate to be connected in parallel with the LED.

26. A vehicle, characterized in that: A semiconductor device comprising any one of claims 1 to 15, or an electronic device comprising any one of claims 23 to 25.

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