Cooling system, thermal management system and method of thermal management

Abstract

The liquid cooling system includes a thermoelectric cooler (TEC) located between the heat sink plate and the heat sink, and a thermoelectric generator (TEG) located at a location where the TEG is driven by heat from the chip package. The chip package is cooled by a cold plate of the liquid cooling system, and the TEC is controlled by the TEG. The TEG may be located between the chip package and the cold plate, or may be located within the chip package or other locations adjacent to the chip package. The TEG can control the TEC through the relay. When the chip package is at a peak load, the TEG automatically activates the TEC. The embodiment of the invention further provides a thermal management system and a thermal management method.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to cooling systems, thermal management systems, and methods of thermal management. Background Art

[0002] As semiconductor technology continues to advance, the demand for high-performance devices with smaller form factors continues to increase. As part of the solution to meet these demands, multiple substrates can be stacked vertically within a chip package. Higher performance, smaller form factors, and vertical stacking all make thermal management more difficult. If heat is not managed properly, heat can deteriorate the performance of integrated circuit (IC) devices, reduce their lifespan, and even cause catastrophic failure. Existing thermal management techniques include the use of heat sinks, fans, and thermal interface materials (TIMs). Some of the highest performance cooling systems are liquid cooling systems. Summary of the invention

[0003] Some embodiments of the present disclosure provide a thermal management system, which includes: a chip package; a cooling system, including a cold plate, a heat sink plate, a fluid and a pump, the pump being configured to circulate the fluid between the cold plate and the heat sink plate, wherein the cold plate is arranged to cool the chip package; a thermoelectric generator having a hot side and a cold side, wherein the thermoelectric generator is arranged so that the hot side receives heat from the chip package; and a relay configured to be controlled by the thermoelectric generator so as to provide a selective connection between the cooling system and a power supply device.

[0004] Other embodiments of the present disclosure provide a cooling system comprising: a radiator plate; a cold plate; a pump configured to circulate a fluid between the cold plate and the radiator plate; a radiator; a thermoelectric cooler configured to move heat from the radiator plate to the radiator; a thermoelectric generator mounted to the cold plate; and a relay, wherein the relay provides power to the thermoelectric cooler and is turned on by the thermoelectric generator.

[0005] Another embodiment of the present disclosure provides a method of thermal management, the method comprising: providing a liquid cooling system, the liquid cooling system comprising a thermoelectric cooler, a heat sink, a cold plate, a heat sink plate, a fluid and a pump, wherein the pump is configured to circulate the fluid between the cold plate and the heat sink plate, and the thermoelectric cooler is located between the heat sink and the heat sink plate; placing the cold plate against a chip package; operating the chip package; and selectively operating the thermoelectric cooler based on a temperature difference, wherein the temperature difference is driven by heat from the chip package. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. Moreover, in addition, the sizes of the various components in the individual figures may be arbitrarily increased or decreased relative to each other for ease of illustration or to provide emphasis.

[0007] Figure 1 A cross-sectional view of a system with a cooled chip package according to an embodiment of the present disclosure is shown.

[0008] Figure 2A and Figure 2B A relay is shown that may be used in some embodiments of the present disclosure.

[0009] Figure 3 A cross-sectional view of a thermoelectric module according to an embodiment of the present disclosure is shown.

[0010] Figure 4 is a perspective view of a thermoelectric module according to an embodiment of the present disclosure.

[0011] Figure 5 A thermoelectric module connected as a thermoelectric cooler (TEC) is shown.

[0012] Figure 6 A thermoelectric module connected as a thermoelectric generator (TEG) is shown.

[0013] Figures 7 to 10 Arrangements of thermoelectric modules according to various embodiments of the present disclosure are shown.

[0014] Fig.11 A cross-sectional view of a system with a cooled chip package according to another embodiment of the present disclosure is shown.

[0015] Figure 12 to Figure 13 Arrangements of thermoelectric modules according to various embodiments of the present disclosure are shown.

[0016] Figure 14 to Figure 15 A cross-sectional view of a system with a cooled chip package according to some other embodiments of the present disclosure is shown.

[0017] Fig.16A A cross-sectional view of a system with a cooled chip package according to another embodiment of the present disclosure is shown.

[0018] Fig. 16B Shows Fig.16A Cross-sectional view of the chip in the system.

[0019] Figure 17 to Figure 18 A cross-sectional view of a system with a cooled chip package according to some other embodiments of the present disclosure is shown.

[0020] Figure 19 to Figure 20 Flowcharts of processes according to various embodiments of the present disclosure are provided. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for implementing the different components of the present application. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact.

[0022] For ease of description, spatially relative terms such as "below," "under," "lower," "above," "upper," etc. may be used herein to describe the relationship of an element or component to another element or component as shown in the figure. In addition to the orientation shown in the figure, these spatially relative terms are intended to include different orientations of the device or apparatus in use or operation. The device or apparatus may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used in this article may be interpreted accordingly. The terms "first," "second," "third," "fourth," etc. are merely general identifiers and, therefore, may be interchangeable in various embodiments. For example, while in some embodiments a certain element (e.g., an opening) may be referred to as a "first" element, in other embodiments, the element may be referred to as a "second" element.

[0023] The present disclosure relates to a liquid cooling system, which includes a cold plate, a radiator and a pump. The radiator and the cold plate have internal channels and can be connected to each other by a fluid conduit, which can be a hose or the like. The pump passes the fluid through the radiator and the cold plate and circulates between the radiator and the cold plate, thereby transferring heat from the cold plate to the radiator. The cold plate is placed in thermal contact with the chip package to cool the chip package. The radiator absorbs heat from the fluid and releases the heat to the surrounding environment. A fan can be aimed at the radiator to improve the efficiency of the radiator in releasing heat.

[0024] Although this type of liquid cooling system is one of the most efficient systems, during peak loads, the liquid cooling system may not provide adequate heat removal from the chip package. This may especially occur if the liquid circulation rate within the liquid cooling system is curtailed due to age-related degradation or other factors.

[0025] One aspect of the present disclosure is an enhanced liquid cooling system comprising a thermoelectric cooler (TEC) located between a heat sink plate and a radiator. A coolant circulates in the heat sink plate. When powered on, the TEC drives the heat sink plate temperature below the radiator temperature, thereby making it possible to drive the temperature of the cooling fluid below the ambient temperature. The TEC enhances the liquid cooling system without significantly increasing the amount of space occupied by the liquid cooling system. In some embodiments, the TEC extends to about 70% to about 100% of the interface area between the heat sink plate and the radiator. Higher coverage provides more efficient cooling. Most of the benefits can be achieved if the area coverage is 70% or greater.

[0026] Another aspect of the present disclosure is a method of operation in which a TEC or some other liquid cooling system enhancement device is selectively operated during peak load periods. Peak load periods may be periods when the chip package generates heat above a threshold rate. Peak load periods may only account for a small portion of the chip package's duty cycle. Limiting the operation of the TEC to peak demand periods can significantly reduce the power consumption of the liquid cooling system.

[0027] One method of limiting the operation of the TEC to peak load periods is to measure the temperature of the chip package and selectively operate the TEC based on whether the measured temperature exceeds a threshold. The difficulty with this method is that there is a range of temperatures within the chip package, especially if the chip package is of a type that includes multiple device layers. The peak temperature occurs at a hot spot inside the package. The temperature can be measured at a location closer to the outside of the chip package than the hot spot, and therefore the measured temperature may have a value between the hot spot temperature and the cold plate temperature. The cold plate temperature is variable, so the measured temperature may not accurately track the hot spot temperature.

[0028] According to another aspect of the present disclosure, a TEC or another liquid cooling system enhancement device is selectively activated in response to a temperature differential exceeding a threshold. The temperature differential can be any temperature differential driven by heat from the chip package. The temperature differential more accurately tracks the need for enhanced cooling than the measured temperature mentioned in the previous paragraph. If the heat generation rate within the chip package doubles, all temperature gradients within and around the chip package will approximately double. If the coolant circulation rate decreases and the chip package begins to heat up, the temperature gradients within and around the chip package will increase, allowing the enhanced cooling system to be reliably triggered.

[0029] In some embodiments, the temperature difference is not measured. In some embodiments, the enhancement of the liquid cooling system is activated by a thermoelectric generator (TEG). The TEG can be installed in any position where the TEG is driven by heat from the chip package. In some embodiments, the TEG is installed between the cold plate and the chip package. The path from the chip package to the cold plate is the path of most of the heat released by the chip package. Placing the TEG along this path helps ensure that the TEG receives enough heat to generate a strong signal.

[0030] In some embodiments, the TEG extends across the area between the chip package and the cold plate. The TEG can act as an insulating barrier to some extent. Accordingly, in some other embodiments, the TEG extends across only a small area between the chip package and the cold plate. The remaining area can be filled by a thermally conductive structure that is transverse to the TEG. Specifically, the thermally conductive structure that is transverse to the TEG can be placed between the hot spot in the chip package and the cold plate. The thermally conductive structure can be designed so that the heat transferred from the cold plate to the chip package through the thermally conductive structure is more than the heat transferred through the TEG.

[0031] In some embodiments, the TEG extends 100% of the interface area between the chip package and the cold plate. In some embodiments, the TEG extends only a fraction of that area, for example, from about 10% to about 90% of that area. In some embodiments, the TEG extends 30% or less of that area. Larger TEG area coverage helps ensure that the output current is sufficient to close the relay. Smaller TEG area allows for more efficient cooling. If the TEG area fraction is 30% or less, the insulating effect of the TEG is generally small enough not to significantly degrade overall thermal performance.

[0032] The coolant temperature increases as it passes through the cold plate. Therefore, the coolant temperature can vary across the cold plate between the coolant inlet and the coolant outlet. In embodiments where the TEG extends across only a small area between the chip package and the cold plate, the TEG can be positioned so that it is located at the coldest location of the cold plate between the chip package and the cold plate, which is the area adjacent to the coolant inlet. Placing the TEG in this location helps ensure that the TEG experiences a large enough temperature gradient to generate a strong signal.

[0033] In some embodiments, the output of the TEG controls a relay. In some of these embodiments, the TEG is connected to the coil of the relay so that the relay closes in response to the TEG output reaching a threshold level. A cooling enhancement device such as a TEC can be powered through the relay. This provides a reliable structure for selectively engaging the cooling enhancement device according to the requirements of the chip package.

[0034] The TEG can be configured relative to the relay so as to provide a suitable voltage and sufficient current to close the relay when a predetermined temperature difference is reached. To this end, it is useful to provide the TEG as a plurality of thermoelectric modules. The voltage of the thermoelectric module will vary in proportion to the temperature difference. A group of thermoelectric modules can be connected in series so that the voltage output matches the coil voltage specification of the relay when the temperature difference is reached. Additional thermoelectric modules can be connected in parallel to provide sufficient current to switch the relay. The thermoelectric modules can be arranged on a cold plate.

[0035] In some embodiments, the predetermined temperature difference at which the TEG closes the relay is in the range of about 10°C to about 100°C. In some embodiments, the predetermined temperature difference is at least about 30°C. In some embodiments, the predetermined temperature difference is at least about 60°C. A lower threshold keeps the chip package temperature within a narrower range. A higher threshold saves power.

[0036] In some embodiments, the coil voltage specification of the relay is in the range of about 1V to about 10V. In some embodiments, the coil voltage specification of the relay is about 5V or less. In some embodiments, the coil voltage specification of the relay is about 1.5V. In some embodiments, the coil voltage specification of the relay is about 3V. Lower voltage specifications allow for the use of smaller TEGs. Specifying a standard voltage such as 1.5V or 3V allows for the use of less expensive relays.

[0037] In some embodiments, the TEC is provided by a plurality of thermoelectric modules. A group of thermoelectric modules are connected in series to provide a predetermined temperature difference at a voltage level of a power source, which may be a power source connected and disconnected by a relay. Additional thermoelectric modules may be connected in parallel to increase the overall cooling capacity. The thermoelectric modules may be arranged across the surface of a heat sink plate. In some embodiments, the thermoelectric modules are disposed on two opposing surfaces of the heat sink plate to increase the overall cooling capacity. A second heat sink and / or a second fan may be placed above the second surface. It should be noted that the thermoelectric module may be configured as a TEC or a TEG, the difference being that for a TEG, the thermoelectric module is coupled to a load, while for a TEC, the thermoelectric module is coupled to a power source.

[0038] In some embodiments, the TEG is adjacent to a metal cover above the chip package. The metal cover helps dissipate heat. In some embodiments, the TEG is integrated into the cover. In some embodiments, the TEG is located inside the cover. In some embodiments, the TEG is installed between the motherboard and the chip package. In some embodiments, the TEG is installed inside the chip package.

[0039] The TEG can be set in an intermediate position between the hot spot and the cold plate within the chip package, but typically does not span the entire distance between the hot spot and the cold plate. Accordingly, the temperature difference between the hot side and the cold side of the TEG may be less than the temperature difference between the hot spot and the cold plate within the chip package. In some embodiments, the temperature difference between the hot side and the cold side is in the range of about 10% to about 90% of the temperature difference between the hot spot and the cold plate within the chip package. In some embodiments, the temperature difference between the hot side and the cold side is at least about 30% of the temperature difference between the hot spot and the cold plate within the chip package. If the temperature difference is too small, the TEG may not be able to provide enough power to control the relay without an amplifier. In some embodiments, the temperature difference between the hot side and the cold side is about 50% or less of the temperature difference between the hot spot and the cold plate within the chip package. The reason for the smaller temperature difference is that the TEG adopts a practical location and helps to characterize the difference between TEGs designed for energy harvesting and TEGs designed for control according to the present disclosure.

[0040] Figure 1 A cross-sectional view of a system 100 according to some embodiments is shown. The system 100 includes a chip package 127 and a liquid cooling system 101. The chip package 127 is covered by a cover 117 and can be mounted on a motherboard 125. The liquid cooling system 101 includes a fan 103, a heat sink 105, a TEC 133, a heat sink plate 113, a pipe 111, a pump 131, a cold plate 115, a TEG 129, and a relay 109. The heat sink plate 113 and the cold plate 115 have internal fluid channels (not shown) connected by pipes 111 and containing a fluid 112. The pump 131 circulates the fluid 112 between the heat sink plate 113 and the cold plate 115. The TEG 129 is located between the cold plate 115 and the cover 117 and is adjacent to both the cold plate 115 and the cover 117. The TEC 133 is located between and adjacent to the radiator plate 113 and the radiator 105. The fan 103 is positioned to drive the gas flow through the radiator 105.

[0041] The fan 103 and the pump 131 may be powered by a first power source (not shown). The TEC 133 is selectively connected to the auxiliary power supply 107 through the relay 109. The auxiliary power supply 107 may be the same as or different from the first power source. The TEG 129 is connected to the relay 109 so that when the temperature difference between the lid 117 and the cold plate 115 reaches a predetermined threshold, the TEG 129 closes the relay 109. The threshold is predetermined by the structure of the TEG 129.

[0042] Figure 2A and Figure 2B Cross-sectional views of the relay 200 in the open and closed positions are provided, respectively. The relay 200 can be used as Figure 1The relay 109 in the system 100. The relay 200 has a coil 205. When the coil 205 is energized, it pulls the spring arm 201 downward so that the first contact 209A and the second contact 209B are adjacent. When the coil 205 is deenergized, the spring arm 201 deflects upward so that the first contact 209A and the second contact 209B are separated. The first contact 209A and the second contact 209B form a selective connection between the first terminal 203 and the second terminal 207. One of the first terminal 203 and the second terminal 207 can be connected to the auxiliary power supply device 107, and the other of the first terminal 203 and the second terminal 207 can be connected to the TEC 133 (see Figure 1 ). Coil 205 may be powered by TEG 129 (see Figure 1 ).

[0043] Figure 3 A cross-sectional view of a thermoelectric module 300 is shown. The thermoelectric module 300 may provide Figure 1 The thermoelectric module 300 includes a hot side plate 319, a first wire 315 in a first wiring layer 313, an N-type via 305, a P-type via 307, a dielectric 317, a second wire 308 in a second wiring layer 311, and a cold side plate 303. The N-type via 305 and the P-type via 307 are semiconductors with P-type doping and N-type doping, respectively.

[0044] Figure 4 A perspective view of a thermoelectric module 300 is shown with the dielectric 317 removed and the cold side plate 303 shown in outline. Figure 4 As can be seen in FIG, the first wire 315 and the second wire 308 connect the group of N-type vias 305 and P-type vias 307 in series between the first lead 301 and the second lead 309. When current flows from the first lead 301 to the second lead 309, current flows from the N-type vias 305 to the P-type vias 307 on the cold side 302. The charge carriers passing between the N-type vias 305 and the P-type vias 307 on the cold side 302 absorb heat to produce a cooling effect. The charge carriers passing between the P-type vias 307 and the N-type vias 305 on the hot side 320 release the absorbed heat. In the N-type vias 305, heat is transported from the cold side 302 to the hot side 320 by the flow of electrons 321. In the P-type vias 307, heat is transported from the cold side 302 to the hot side 320 by the flow of holes 323.

[0045] Figure 5A cross-sectional view 500 of a thermoelectric module 300 configured as a TEC is provided. The thermoelectric module 300 is configured as a TEC by connecting the first lead 301 and the second lead 309 of the thermoelectric module 300 to a DC power source 501. The DC power source 501 may be an auxiliary power supply 107 (see Figure 1 ). The DC power supply 501 drives the temperature difference between the hot side 320 and the cold side 302.

[0046] Figure 6 A cross-sectional view 600 of a thermoelectric module 300 configured as a TEG is provided. The thermoelectric module 300 is configured as a TEG by connecting the first lead 301 and the second lead 309 to a load 601. The load 601 may be the coil 205 of the relay 200 (see Figure 2A and Figure 2B ). The temperature difference between the hot side 320 and the cold side 302 drives the load 601.

[0047] refer to Figure 4 , the thermoelectric module 300 may include series connections and parallel connections between groups of N-type through holes 305 and P-type through holes 307. In the case of TEG, the series connection increases the voltage output for a given temperature difference between the hot side 320 and the cold side 302. The parallel connection increases the output current. In the case of TEC, the series connection increases the temperature difference between the hot side 320 and the cold side 302 generated by a given power supply voltage, and the parallel connection increases the overall cooling capacity. Accordingly, the thermoelectric module 300 can be constructed to meet the design specifications of either TEC 133 or TEG 129. However, in practice, it may be more economical to construct TEC 133 and / or TEG 129 using multiple thermoelectric modules 300 manufactured in batches according to specifications set independently of the present application. Then, multiple thermoelectric modules 300 can be connected in any combination or in series and parallel as long as the specification requirements of TEC 133 or TEG129 are met.

[0048] Figure 7 A top layout view of a thermoelectric device 700 is provided, which can provide either a TEC 133 or a TEG 129. The thermoelectric device 700 includes four thermoelectric modules 300 connected in series. If the first lead 301 and the second lead 309 are connected to a load, the voltage output will be four times that of a single thermoelectric module 300. This arrangement is suitable for operating the coil 205 at a voltage four times the voltage generated by each thermoelectric module 300 at a threshold temperature difference (see Figure 1 ). If the first lead 301 and the second lead 309 are connected to a power source, the resulting temperature difference will be the temperature difference provided by each thermoelectric module 300 at one quarter of the applied voltage.

[0049] Figure 8A top view of a thermoelectric device 800 is provided, which can also be used as either a TEC 133 or a TEG 129. The thermoelectric device 800 includes nine thermoelectric modules 300 connected in series. If the first lead 301 and the second lead 309 are connected to a load, the voltage output will be nine times that of a single thermoelectric module 300. This arrangement provides nine times the voltage that each thermoelectric module 300 produces at any given temperature difference. If the first lead 301 and the second lead 309 are connected to a power supply, the temperature difference produced will be the temperature difference that each thermoelectric module 300 provides at one-ninth the applied voltage.

[0050] For TEG 129, the target voltage may be the rated voltage of coil 205. A group of thermoelectric modules 300 connected in series, each group providing an output that satisfies the rated voltage at a threshold temperature difference, may be combined so that the current provided at the threshold temperature difference is sufficient to close relay 200 (see FIG. 2A to FIG. 2B ). For TEC 133, groups of thermoelectric modules 300 can be connected in series to meet a target temperature difference. Multiple such series groups can be provided to meet the overall cooling requirements. In selecting a target temperature difference, a lower temperature difference provides a more efficient use of the power provided for cooling, but the overall cooling capacity is lower. A larger temperature difference provides a less efficient use of power, but allows for more intense cooling. The target temperature difference can be selected to provide a balance between these two effects. The target temperature difference can also be limited to avoid freezing the fluid 112. Although refrigerants with various freezing points can be used, in some embodiments, the fluid is water (H2O). Water is easy to handle and has a larger specific heat capacity than most refrigerants.

[0051] Fig. 9 A top layout diagram of a thermoelectric device 900 is provided, which may provide either a TEC 133 or a TEG 129. The thermoelectric device 900 includes four thermoelectric modules 300 in two groups 901. In each group 901, two thermoelectric modules 300 are connected in series. The two groups 901 are connected in parallel.

[0052] Fig.10 A top view of a thermoelectric device 1000 is provided, which may also be used as either a TEC 133 or a TEG 129. The thermoelectric device 1000 includes nine thermoelectric modules 300 in three groups 1001. In each group 1001, three thermoelectric modules 300 are connected in series. The three groups 1001 are connected in parallel.

[0053] For TEC 133, adding more thermoelectric modules 300 is desirable in terms of increasing potential cooling capacity. The number of thermoelectric modules 300 that can be added may be limited by the area of ​​​​the heat sink plate 113 (see Figure 1 ).

[0054] Fig.11 FIG. 1 shows a cross-sectional view of a system 1100 in which a chip package 127 is paired with a liquid cooling system 1101. Figure 1 The liquid cooling system 1101 is similar to the liquid cooling system 101 of 1102, except that the liquid cooling system 1101 has two TECs 133, two heat sinks 105, and two fans 103, and the two TECs 133, two heat sinks 105, and two fans 103 are arranged on opposite sides of the heat sink plate 113. The cooling power of the liquid cooling system 1101 may be approximately twice that of the liquid cooling system 101. Both TECs 133 may be controlled by the TEG 129 via the relay 109.

[0055] For TEG 129, adding more thermoelectric modules 300 is not necessarily desirable. Once the output of TEG 129 is sufficient to close relay 109 (see Figure 1 ), there is no benefit in adding more thermoelectric modules 300. In addition, TEG 129 can act as an insulating layer.

[0056] Fig.12 A top view of a thermoelectric device 1200 that can provide a TEG 129 is provided. The thermoelectric device 1200 includes eight thermoelectric modules 300. In the center region (which can be located above the hot spot 114 in the chip package 127) (see Figure 1 ), there is a heat conductive block 1201. The heat conductive block 1201 can have the same thickness as the thermoelectric module 300 and is composed of a material with high thermal conductivity. The material can be a metal, a high thermal conductivity dielectric, a very high thermal conductivity dielectric, or an extremely high thermal conductivity dielectric.

[0057] In the present disclosure, a high thermal conductivity dielectric has a thermal conductivity of at least about 10 Watts / meter-Kelvin (W / mK). In contrast, silicon dioxide (SiO2) has a thermal conductivity in the range of about 1.1 W / mK to about 1.4 W / mK. Crystalline silicon nitride (Si3N4) is an example of a high thermal conductivity dielectric and can have a thermal conductivity as high as 29 W / mK. Silicon nitride (Si3N4) commonly found in semiconductor devices is amorphous and has a thermal conductivity in the range of about 2 W / mK to about 5 W / mK. Amorphous forms are typically produced because they allow for a higher deposition rate than crystalline forms. Likewise, when forming dielectrics for semiconductor devices, a lower dielectric constant for the amorphous form is typically sought. Thermal conductivity may vary continuously with the degree of crystallinity between the pure amorphous form and the pure crystalline form.

[0058] Very high thermal conductivity dielectrics have a thermal conductivity higher than pure crystalline silicon nitride (Si3N4), in other words, higher than 29W / mK. In some embodiments, very high thermal conductivity dielectrics have a thermal conductivity of at least about 100W / mK. Examples of dielectrics having a thermal conductivity of about 100W / mK or more include, but are not limited to, aluminum nitride (AlN), crystalline boron nitride (BN), crystalline boron phosphide (BP), crystalline boron arsenide (BAs), hexagonal boron nitride (hBN), graphene, diamond, and the like. In these examples, aluminum nitride (AlN), boron nitride (BN), boron phosphide (BP), and boron arsenide (BAs) have an amorphous form, a crystalline form, and a medium crystallinity form. The form with sufficient crystallinity is an extremely high thermal conductivity dielectric. For hexagonal compounds, including hexagonal boron nitride (hBN) and graphene, the thermal conductivity depends on the shape. The lateral shape (thin sheet) generally provides the highest thermal conductivity. Very high thermal conductivity dielectrics have a thermal conductivity of at least about 1000 W / mK or higher. This can be achieved, for example, by using boron arsenide (BA), one of the above-mentioned carbon-based dielectrics, or the like.

[0059] Another consideration for the placement of the thermoelectric modules 300 is that the fluid 112 heats up as it passes through the cold plate 115, so that when the thermoelectric modules 300 are located near the inlet side 130 of the cold plate 115, they experience a greater temperature gradient and produce more power (see Figure 1 ). Fig.13 A top view of a thermoelectric device 1300 that can provide a TEG 129 is provided. The thermoelectric device 1300 includes three thermoelectric modules 300 that are located near the inlet side 130 (see Figure 1 ). The area above the cold plate 115 and transverse to the thermoelectric module 300 is occupied by the heat conductive block 1301. In addition to the difference in size and position, the heat conductive block 1301 can be Fig.12 The heat conductive block 1201 is similar.

[0060] Back to Figure 3 , the N-type via 305 is a semiconductor material having a high thermoelectric performance coefficient and N-type doping. The high thermoelectric performance coefficient is 1.0 or greater. The greater the thermoelectric performance coefficient, the higher the efficiency of the resulting thermoelectric cooler. Examples of semiconductor materials having a high thermoelectric performance coefficient include bismuth telluride-based compounds (BiTe-), antimony telluride-based compounds (SbTe-), antimony telluride-based compounds (Bi 2-y Sb y Te-), lead telluride (PbTe), silicon germanium (SiGe), skutterudite compounds, zinc antimonide (Zn3Sb3), germanium telluride (GeTe), half-Heusler compounds, and other semiconductor materials. Examples of bismuth telluride-based compounds include Bi2(Te xSe 1-x )3, etc. Examples of antimony telluride-based compounds include Sb2(Te x Se 1-x )3, etc. Examples of antimony bismuth telluride-based compounds include Bi 2-y Sb y (Te x Se 1-x )3, etc. In these molecular formulas, x and y may independently have any value from 0 to 1. Examples of skutterudite compounds include cobalt antimonide (CoSb3), etc. Examples of half-Heusler compounds include hafnium nickel tin (HfNiSn), zirconium nickel tin (ZrNiSn), etc. N-type dopants may be, for example, phosphorus (P), arsenic (As), antimony (Sb), etc.

[0061] In some embodiments, the semiconductor material includes nanostructures that increase the thermoelectric coefficient of performance. Using nanostructures, the thermoelectric coefficient of performance can be increased to 2.0 or higher. Examples of nanostructures include quantum dots and superlattices. Quantum dots can be nanoparticles of semiconductors such as cadmium selenide (CdSe), cadmium telluride (CdTe), lead sulfide (PbS), indium arsenide (InAs), etc. These more expensive structures are particularly suitable for thermoelectric modules 300 for TEG 129 and other TEGs described herein, especially in those embodiments where small size or functionality with small temperature gradients is particularly advantageous.

[0062] The P-type via 307 is a semiconductor material with a high thermoelectric performance coefficient and P-type doping. The P-type dopant can be, for example, boron (B), aluminum (Al), gallium (Ga), indium (In), etc. In addition to being semiconductors with different doping types, the P-type via 307 and the N-type via 305 can also be different semiconductor materials.

[0063] The dielectric 317 is disposed between the P-type via 307 and the N-type via 305. The dielectric 317 may be silicon dioxide (SiO2), a low-k dielectric, or an ultra-low-k dielectric. The first wire 315 and the second wire 308 may be metals or other conductive materials. The metal may be, for example, copper (Cu), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), zirconium (Zi), titanium (Ti), tantalum (Ta), aluminum (Al), conductive carbides, oxides, alloys, etc. of these metals.

[0064] The hot side plate 319 and the cold side plate 303 are composed of a material selected to have a high thermal conductivity and can include one or more layers of any suitable material. For the hot side plate 319, at least the layer closest to the first wire 315 is a dielectric layer. For the cold side plate 303, at least the layer closest to the second wire 308 is a dielectric layer. The layers can be metals, high thermal conductivity dielectrics, very high thermal conductivity dielectrics, or extremely high thermal conductivity dielectrics. In some embodiments, the hot side plate 319 and / or the cold side plate 303 include very high thermal conductivity dielectrics. In some embodiments, the hot side plate 319 and / or the cold side plate 303 include extremely high thermal conductivity dielectrics. In some embodiments, the hot side plate 319 and / or the cold side plate 303 include graphite. In addition to having an extremely high thermal conductivity dielectric, graphite also has the advantage of being soft, thereby promoting good thermal contact with adjacent structures.

[0065] Back to Figure 1 , the chip package 127 includes a semiconductor substrate 121, and may also include additional substrate layers (such as a carrier substrate 119) and a redistribution layer 123. The semiconductor substrate may be a bulk semiconductor substrate or a semiconductor on insulator (SOI) substrate. At least the upper portion of the semiconductor substrate is a semiconductor. The semiconductor may be silicon (Si), a III-V semiconductor (e.g., GaAs) or other binary semiconductors, a ternary semiconductor (e.g., AlGaAs), a higher order semiconductor, etc., or any other suitable semiconductor. The carrier substrate 119 may also be a semiconductor substrate. Various semiconductor devices are formed on or in the semiconductor substrate 121. These semiconductor devices may include transistors (such as complementary metal oxide field effect transistors (MOSFETs), fin field effect transistors (finFETS), etc.), diodes, capacitors, memory cells, thyristors, resistors, etc., or any combination thereof.

[0066] The redistribution layer 123 and the motherboard 125 may include a dielectric substrate. The dielectric substrate may be, for example, an organic polymer substrate or some other suitable dielectric material. Examples of organic polymer substrate materials include, but are not limited to, polyimide, polytetrafluoroethylene, epoxy resin, etc. The epoxy resin may be formed of bismaleimide-triazine resin (BT resin), some other epoxy resins, etc. The dielectric substrate may be a laminate and may be reinforced with glass cloth, glass fiber, etc.

[0067] The chip package 127 may be attached to the motherboard 125 by an array of solder balls 124, which form a ball grid array (BGA). The solder balls 124 may be surrounded by a thermally conductive paste 126 to improve heat transfer between the chip package 127 and the motherboard 125. The thermally conductive paste 116 may also be disposed between the lid 117 and the chip package 127. The thermally conductive paste may also be used between the lid 117 and the TEG 129, between the TEG 129 and the cold plate 115, between the heat sink plate 113 and the TEC 133, and between the TEC 133 and the heat sink 105.

[0068] Fig.14 1 shows a system 1400 according to another embodiment. The system 1400 includes a chip package 127 having a liquid cooling system 101. The liquid cooling system 101 and Figure 1 The liquid cooling system 101 is similar to the liquid cooling system 101, except that in the liquid cooling system 101, the TEG 129 is incorporated into the cover 1403, which replaces the Figure 1 14. The cover 1403 is used in the system 100. The TEG 129 can be incorporated into the cover 1403 so as to be located within the cover 1403. In the position shown, the TEG 129 can experience a large temperature gradient, and the cover 1403 dissipates heat in such a way as to ensure adequate cooling of the chip package 127. Contact pads 1401 can be formed on the cover 1403 to facilitate connecting the TEG 129 to the relay 109.

[0069] Fig.15 A system 1500 according to another embodiment is shown. The system 1500 includes a chip package 1501, a liquid cooling system 101, and a motherboard 125. The chip package 1501 includes a plurality of device layers, including a first wiring layer 1519, a first chip 1515, a second wiring layer 1511, a second chip 1507, and a third chip 1503. Each of these device layers includes a substrate. The first wiring layer 1519 includes a first packaging substrate 1521. The first chip 1515 includes a first semiconductor substrate 1517. The second wiring layer 1511 includes a second packaging substrate 1513. The second chip 1507 includes a second semiconductor substrate 1509. The third chip 1503 includes a third semiconductor substrate 1505. A high thermal conductivity bottom filler 1516 may fill the space between the second wiring layer 1511 and the first chip 1515. The TEG 129 may be in direct contact with the uppermost device layer (i.e., the third chip 1503).

[0070] Fig.16A 1 shows a system 1600 according to another embodiment. The system 1600 includes a chip package 1501, a liquid cooling system 1601, and a motherboard 125. The liquid cooling system 1601 is similar to the liquid cooling system 101 (see Fig.15 ), except that the liquid cooling system 1601 uses a TEG 1604 incorporated into the chip package 1501. In this example, the TEG 1604 is incorporated into the third chip 1503, located directly below the cold plate 115, and the cold plate 115 can be in direct contact with the third chip 1503. The TEG 1604 can be connected to the relay 109 through a conductive wire 1605, which is attached to a contact pad 1607 on the third chip 1503.

[0071] Fig. 16B A cross-sectional view 1650 showing a portion of a third chip 1503 including a TEG 1604 is provided. Fig. 16B As shown, the third chip 1503 includes a metal interconnect structure 1633 located above the third semiconductor substrate 1505. Semiconductor devices such as transistors 1643 can be formed on the third semiconductor substrate 1505 or in the third semiconductor substrate 1505. The metal interconnect structure 1633 includes a plurality of metallization layers 1645, including an uppermost metallization layer 1645u, and a plurality of via layers 1647. The metallization layer 1645 includes a conductive line 1637, and the via layer 1647 includes a via 1639. The TEG 1604 is disposed in a passivation stack 1646 above the uppermost metallization layer 1645u.

[0072] The first contact pad 1619 and the second contact pad 1621 can be disposed in a pad layer 1651 above the passivation stack 1646. The dielectric 1620 of the bonding layer 1623 surrounds and isolates the first contact pad 1619 and the second contact pad 1621. In some embodiments, the dielectric 1620 is a high thermal conductivity dielectric. In some embodiments, the dielectric 1620 is a very high thermal conductivity dielectric. In some embodiments, the dielectric 1620 is an extremely high thermal conductivity dielectric. There is a high thermal conductivity layer between the TEG 1604 and the cold plate 115 (see Fig. 16B ) helps provide effective cooling while maintaining a large temperature gradient across the TEG 1604.

[0073] The TEG 1604 includes a first electrode 1648 and a second electrode 1630. A first via 1649 passes through the first electrode 1648 and the passivation stack 1646. The first via 1649 can couple the first electrode 1648 to either or both of the first contact pad 1619 and the first conductive line 1637A in the uppermost metallization layer 1645u. The second via 1627 passes through the passivation stack 1646 and the second electrode 1630. The second via 1627 can couple the second electrode 1630 to either or both of the second contact pad 1621 and the second conductive line 1637B in the uppermost metallization layer 1645u. In this manner, the TEG 1604 can be connected to the contact pad 1607 through the pad layer 1651 or through the metal interconnect structure 1633 (see Fig.16A ). In some embodiments, TEG 1604 is coupled to transistor 1643 or to some other structure that can be used to amplify the signal from TEG 1604 before routing the signal to relay 109 (see Fig. 16B ).

[0074] The passivation stack 1646 is a dielectric structure that may include various layers, such as an etch stop layer 1636, a dielectric layer 1631, and a barrier layer 1629. The etch stop layer 1636 may be a material such as silicon nitride (SiN), silicon carbide (SiC), silicon carbon nitride (SiCN), silicon oxycarbide (SIOC), silicon oxycarbonitride (SiOCN), a combination thereof, or the like. The dielectric layer 1631 may be a dielectric layer that provides electrical insulation between the N-type via 305 and the P-type via 307 of the TEG 1604 and between the third chip 1503 and the external environment. In some embodiments, the dielectric layer 1631 is silicon dioxide (SiO2). In some embodiments, the dielectric layer 1631 is a low-k dielectric, such as an interlayer dielectric 1638 that may be used as a metal interconnect structure 1633. The low-k dielectric may be, for example, an organic silicate glass (OSG), such as carbon-doped silicon dioxide, fluorinated silicon glass (FSG), porous silicate glass, or the like.

[0075] In some embodiments, barrier layer 1629 is a high thermal conductivity dielectric. In some embodiments, barrier layer 1629 is silicon nitride (Si3N4) or the like. Silicon nitride (Si3N4) provides superior moisture resistance and has greater mechanical strength than silicon dioxide (SiO2). In some embodiments, barrier layer 1629 is a very high thermal conductivity dielectric. In some embodiments, barrier layer 1629 is an extremely high thermal conductivity dielectric.

[0076] Fig.171 shows a system 1700 according to another embodiment. The system 1700 includes a chip package 1501, a liquid cooling system 1701, and a motherboard 125. The liquid cooling system 1701 is different from the liquid cooling system 1601 (see Fig.16A ), except that the liquid cooling system 1701 uses one or more TEGs 1709 disposed between the chip package 1501 and the motherboard 125 instead of incorporating TEGs 1604 into the chip package 1501. The TEGs 1709 may be disposed in a connection layer 1706 between the solder balls 124. Signals from the TEGs 1709 may be routed through the motherboard 125 and coupled to the relays 109 through conductive wires 1705 connected to contact pads 1707 on the motherboard 125. The liquid cooling system 1701 may be used without changing the design of the chip package 1501, and without placing any barrier that impedes heat flow between the chip package 1501 and the cold plate 115.

[0077] Fig.18 1 shows a system 1800 according to another embodiment. The system 1800 includes a chip package 127, a liquid cooling system 1801, and a motherboard 125. The liquid cooling system 1801 is similar to the liquid cooling system 101 (see Figure 1 ), except that the liquid cooling system 1801 has a TEG 1803 incorporated into the chip package 127 instead of the TEG 129. The TEG 1803 can be located between two device layers in the chip package 127, and in particular can be located in the controlled collapse chip connection (C4) layer 1805 between the solder bumps 1804. The TEG 1803 can be located near the hot spot 114, between the hot spot 114 and the motherboard 125, or between the hot spot 114 and the cold plate 115. The cold plate 115 can be adjacent to the lid 117. Direct signals from the TEG 1803 or amplified signals from the TEG 1803 can be routed through the chip package 127 to the motherboard 125, and from the motherboard 125 to the relay 109.

[0078] Fig.19 A flow chart of method 1900 of forming a system for cooling a chip package according to some embodiments of the present disclosure is provided. Although method 1900 is shown and described below as a series of actions or events, it should be understood that the order in which these actions or events are shown should not be interpreted as limiting. For example, some actions may occur in a different order and / or occur simultaneously with other actions or events other than those shown and / or described herein. In addition, not all of the actions shown may be necessary to implement one or more aspects or embodiments described herein. Furthermore, one or more of the actions described herein may be performed in one or more separate actions and / or stages. Method 1900 may be used to form a system for cooling a chip package. Figure 1 System 100, Fig.11 System 1100, Fig.15 System 1500, etc.

[0079] Method 1900 may begin with act 1901, where a TEC is mounted between a heat sink plate and a heat sink. A thermal paste may be used to improve contact with the heat sink plate and / or the heat sink. A fan may be placed to move air over the heat sink.

[0080] Action 1903 attaches the TEG to the cold plate. Action 1905 connects the cold plate and the radiator plate through a fluid delivery conduit (such as a tube). Action 1907 attaches the TEG and the cold plate to the chip package so that the TEG is located between the cold plate and the chip package. Thermally conductive paste can be used to improve the contact between the TEG and the cold plate or between the TEG and the chip package. In some embodiments, the TEG is clamped to the chip package. In some embodiments, the TEG is soldered to the chip package.

[0081] Action 1909 is to connect the TEG to control a relay or some other switch through which the TEC is activated. In some embodiments, the TEG output is directly coupled to the coil of the relay. In some embodiments, the TEG is coupled to an amplifier and the amplified output of the TEG is sent to the relay.

[0082] Action 1911 connects the pump and fan of the liquid cooling system to the power supply. Action 1913 connects the relay to the power supply. The relay can be connected to the same power supply as the pump and fan or to a different power supply. Action 1911 and action 1913 can be combined into a single action. Action 1915 connects the output of the relay to the TEC, so that the TEC is controlled by the TEG through the relay.

[0083] Fig. 20 A flowchart of method 2000 is provided, which is a variation of method 1900 and can be used to form Fig.14 System 1400, Fig.16A System 1600, Fig.17 System 1700, Fig.18 The system 1800 and the method 2000 differ in two aspects: one involves installing the TEG, and the other involves connecting the TEG to the relay.

[0084] Method 1900 includes an act 1903 of attaching the TEG to a cold plate, while method 2000 includes an act 2003 of mounting the TEG on or within a chip package. The TEG may be mounted on a chip package, such as Fig.14As shown in the system 1400, it is located between the cover and the chip package, and can also be installed at a certain position inside the chip package, such as Fig.16A and Fig. 16B System 1600 or Fig.18 As shown in the system 1800, it can also be installed in a chip in a chip package, such as Fig.16A and Fig. 16B As shown in system 1600, or can be mounted on the side of the chip package opposite the cold plate, such as Fig.17 As shown in system 1700.

[0085] Fig. 20 Method 2000 can also be used in conjunction with the method of performing action 1915 (connecting the TEG to the relay). Fig.19 In method 2000, the TEG may be connected to the relay via contact pads on the cover, such as Fig.14 As shown in the system 1400, the chip package is connected to the relay through the contact pads on the chip package, such as Fig.15 System 1500 or Fig.16A As shown in the system 1600, the chip package is connected to the relay, such as Fig.16A and Fig. 16B System 1600 or Fig.18 as shown in system 1800, or connected to the relay via a motherboard, such as Fig.17 System 1700 or Fig.18 As shown in system 1800.

[0086] Some embodiments of the present disclosure provide a thermal management system, which includes: a chip package; a cooling system including a cold plate, a heat sink plate, a fluid and a pump, the pump being configured to circulate the fluid between the cold plate and the heat sink plate, wherein the cold plate is arranged to cool the chip package; a thermoelectric generator having a hot side and a cold side, wherein the thermoelectric generator is arranged so that the hot side receives heat from the chip package; and a relay configured to be controlled by the thermoelectric generator to provide a selective connection between the cooling system and the power supply. In some embodiments, the cooling system also includes a first thermoelectric cooler and a first heat sink; the first thermoelectric cooler is located between the heat sink plate and the first heat sink; and the first thermoelectric cooler is powered by the relay. In some embodiments, the cooling system also includes a second thermoelectric cooler and a second heat sink; the second thermoelectric cooler is located between the heat sink plate and the second heat sink; the first thermoelectric cooler and the second thermoelectric cooler are located on opposite surfaces of the heat sink plate; and the second thermoelectric cooler is powered by the relay. In some embodiments, the first thermoelectric cooler includes a plurality of thermoelectric modules located on one surface of the heat sink plate. In some embodiments, the first thermoelectric cooler covers 70% or more of a surface of the heat sink plate. In some embodiments, the thermoelectric generator includes a plurality of thermoelectric modules connected in series to provide a switching voltage for the relay. In some embodiments, the thermoelectric generator is located between the chip package and the cold plate. In some embodiments, the thermal management system further includes a heat conductive block located between the chip package and the cold plate and transverse to the thermoelectric generator, wherein the heat conductive block provides more heat transfer between the chip package and the cold plate than the heat transfer provided by the thermoelectric generator. In some embodiments, the thermoelectric generator occupies 30% or less of the interface area between the chip package and the cold plate. In some embodiments, at least a portion of the thermoelectric generator is located within the chip package. In some embodiments, the chip package is operable to generate heat that raises the internal temperature of the chip package so as to generate a first temperature difference between the internal temperature and the hot side, and a second temperature difference between the hot side and the cold side, wherein the first temperature difference is greater than the second temperature difference.

[0087] Other embodiments of the present disclosure provide a cooling system, including: a radiator plate; a cold plate; a pump configured to circulate a fluid between the cold plate and the radiator plate; a radiator; a thermoelectric cooler configured to move heat from the radiator plate to the radiator; a thermoelectric generator mounted to the cold plate; and a relay, wherein the relay provides power to the thermoelectric cooler and is switched on by the thermoelectric generator. In some embodiments, the thermoelectric cooler includes two thermoelectric modules located on opposite surfaces of the radiator plate. In some embodiments, the thermoelectric cooler includes a plurality of thermoelectric modules connected in series.

[0088] Still other embodiments of the present disclosure provide a method of thermal management, the method comprising: providing a liquid cooling system, the liquid cooling system comprising a thermoelectric cooler, a heat sink, a cold plate, a heat sink plate, a fluid and a pump, wherein the pump is configured to circulate a fluid between the cold plate and the heat sink plate, and the thermoelectric cooler is located between the heat sink and the heat sink plate; placing the cold plate against a chip package; operating the chip package; and selectively operating the thermoelectric cooler according to a temperature difference, wherein the temperature difference is driven by heat from the chip package. In some embodiments, selectively operating the thermoelectric cooler according to the temperature difference comprises generating a current from the temperature difference using a thermoelectric generator, and using a current control to couple the thermoelectric cooler to a relay of a power supply. In some embodiments, generating a current from a temperature difference using a thermoelectric generator comprises connecting a plurality of thermoelectric modules in series, such that when a predetermined temperature difference is reached, the thermoelectric generator turns off a relay. In some embodiments, generating a current from a temperature difference using a thermoelectric generator also comprises connecting additional thermoelectric modules in parallel, such that when a predetermined temperature difference is reached, the thermoelectric generator provides sufficient current to switch the relay. In some embodiments, generating current from a temperature difference using a thermoelectric generator includes positioning the thermoelectric generator between the chip package and a cold plate. In some embodiments, the method of thermal management also includes providing thermal coupling between a hot spot of the chip package and a cold plate, the cold plate bypassing the thermoelectric generator.

[0089] Some aspects of the present disclosure relate to a system including a chip package, a cooling system, a thermoelectric generator, and a relay. The cooling system includes a cold plate, a radiator plate, a fluid, and a pump, the pump being configured to circulate the fluid between the cold plate and the radiator plate. The cold plate is arranged to cool the chip package. The thermoelectric generator has a hot side and a cold side, and the thermoelectric generator is arranged so that the hot side receives heat from the chip package. The relay is configured to be controlled by the thermoelectric generator to provide a selective connection between the cooling system and the power supply. In some embodiments, the cooling system also includes a thermoelectric cooler and a radiator. The thermoelectric cooler is located between the radiator plate and the radiator. The thermoelectric cooler is a portion of the cooling system powered by the relay. In some embodiments, there is a second thermoelectric cooler and a second radiator. The second thermoelectric cooler is located between the radiator plate and the second radiator. The first thermoelectric cooler and the second thermoelectric cooler are located on opposite surfaces of the radiator plate. The second thermoelectric cooler is also powered by the relay.

[0090] In some embodiments, the thermoelectric cooler includes a plurality of thermoelectric modules located on one surface of a heat sink plate. In some embodiments, the thermoelectric generator includes a plurality of thermoelectric modules connected in series to provide a switching voltage to the relay. In some embodiments, the thermoelectric generator is located between the chip package and the cold plate. In some embodiments, in addition to the thermoelectric generator, there is a thermally conductive block between the chip package and the cold plate. The thermally conductive block is transverse to the thermoelectric generator. In some embodiments, the thermally conductive block provides more heat transfer between the chip package and the cold plate than the thermoelectric generator.

[0091] In some embodiments, at least a portion of the thermoelectric generator is located within the chip package. In some embodiments, the chip package is operable to generate heat that raises an internal temperature of the chip package so as to generate a first temperature difference between the internal temperature and the hot side and a second temperature difference between the hot side and the cold side, and the first temperature difference is greater than the second temperature difference. In some embodiments, the chip package includes a plurality of device layers in a vertical stack.

[0092] Some aspects of the present disclosure relate to a system including a chip package, a cooling system and a relay. The cooling system includes a thermoelectric cooler, a radiator, a cold plate, a radiator plate, a fluid and a pump. The pump is configured to circulate the fluid between the cold plate and the radiator plate. The thermoelectric cooler is configured to move heat from the radiator plate to the radiator. The cold plate is arranged to cool the chip package. The relay provides power to the thermoelectric cooler and is turned on by heat from the chip package. In some embodiments, the system also includes a thermoelectric generator. The thermoelectric generator is configured to receive heat from the chip package, generate current from the heat, and turn on the relay using the current. In some embodiments, the thermoelectric cooler includes two thermoelectric modules located on opposite surfaces of the radiator plate. In some embodiments, the thermoelectric cooler includes a plurality of thermoelectric modules connected in series.

[0093] Some aspects of the present disclosure relate to a cooling system, the cooling system comprising a radiator plate, a cold plate, a pump configured to circulate a fluid between the cold plate and the radiator plate, a radiator, a thermoelectric cooler configured to move heat from the radiator plate to the radiator, a thermoelectric generator attached to the cold plate, and a relay. The relay provides power to the thermoelectric cooler and is connected through the thermoelectric generator. In some embodiments, the thermally conductive block is attached to the cold plate and is transverse to the thermoelectric generator. In some embodiments, the thermally conductive block has the same thickness as the thermoelectric generator. In some embodiments, the thermoelectric cooler includes two thermoelectric modules located on opposite sides of the radiator plate. In some embodiments, the thermoelectric cooler includes a plurality of thermoelectric modules connected in series.

[0094] Some aspects of the present disclosure relate to methods of thermal management. The method includes providing a liquid cooling system, wherein the liquid cooling system includes a thermoelectric cooler, a radiator, a cold plate, a radiator plate, a fluid, and a pump. The pump is configured to circulate the fluid between the cold plate and the radiator plate. The thermoelectric cooler is located between the radiator and the radiator plate. The method also includes placing the cold plate against a chip package, operating the chip package, and selectively operating the thermoelectric cooler based on a temperature difference driven by heat from the chip package. In some embodiments, selectively operating the thermoelectric cooler based on the temperature difference includes using a thermoelectric generator to generate an electric current from the temperature difference, and using the electric current to control a relay that couples the thermoelectric cooler to a power source.

[0095] In some embodiments, generating current from a temperature difference using a thermoelectric generator includes connecting a plurality of thermoelectric modules in series so that when a predetermined temperature difference is reached, the thermoelectric generator closes a relay. In some embodiments, generating current from a temperature difference using a thermoelectric generator also includes connecting additional thermoelectric modules in parallel so that when a predetermined temperature difference is reached, the thermoelectric generator provides sufficient current to switch the relay. In some embodiments, generating current from a temperature difference using a thermoelectric generator includes positioning the thermoelectric generator between a chip package and a cold plate. In some embodiments, the method also includes providing a thermal coupling between a hot spot of the chip package and the cold plate, wherein the thermal coupling bypasses the thermoelectric generator.

[0096] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A thermal management system, comprising: Chip packaging; a cooling system comprising a cold plate, a heat sink plate, a fluid, and a pump, the pump being configured to circulate the fluid between the cold plate and the heat sink plate, wherein the cold plate is positioned to cool the chip package; a thermoelectric generator having a hot side and a cold side, wherein the thermoelectric generator is positioned so that the hot side receives heat from the chip package; and A relay is configured to be controlled by the thermoelectric generator to provide a selective connection between the cooling system and a power supply.

2. The thermal management system according to claim 1, wherein: The cooling system also includes a first thermoelectric cooler and a first heat sink; the first thermoelectric cooler is located between the heat sink plate and the first heat sink; and The first thermoelectric cooler is powered through the relay.

3. The thermal management system according to claim 2, wherein: The cooling system also includes a second thermoelectric cooler and a second heat sink; the second thermoelectric cooler being located between the heat sink plate and the second heat sink; The first thermoelectric cooler and the second thermoelectric cooler are located on opposite surfaces of the heat sink plate; and The second thermoelectric cooler is powered through the relay.

4. The thermal management system according to claim 2, wherein: The first thermoelectric cooler includes a plurality of thermoelectric modules located on one surface of the heat sink plate.

5. The thermal management system according to claim 2, wherein: The first thermoelectric cooler covers 70% or more of a surface of the heat sink plate.

6. The thermal management system according to claim 1, wherein: The thermoelectric generator includes a plurality of thermoelectric modules connected in series to provide a switching voltage for the relay.

7. The thermal management system according to claim 1, wherein: The thermoelectric generator is located between the chip package and the cold plate.

8. The thermal management system of claim 7, further comprising a thermally conductive block located between the chip package and the cold plate and transverse to the thermoelectric generator, wherein: The thermally conductive block provides more heat transfer between the chip package and the cold plate than the thermoelectric generator provides.

9. A cooling system comprising: Radiator panels; Cold plate; a pump configured to circulate a fluid between the cold plate and the heat sink plate; heat sink; a thermoelectric cooler configured to move heat from the heat sink plate to the heat sink; a thermoelectric generator mounted on the cold plate; as well as A relay, wherein the relay provides power to the thermoelectric cooler and is switched on by the thermoelectric generator.

10. A method of thermal management, the method comprising: Providing a liquid cooling system, the liquid cooling system comprising a thermoelectric cooler, a heat sink, a cold plate, a heat sink plate, a fluid, and a pump, wherein the pump is configured to circulate the fluid between the cold plate and the heat sink plate, and the thermoelectric cooler is located between the heat sink and the heat sink plate; placing the cold plate against the chip package; operating the chip package; and The thermoelectric cooler is selectively operated based on a temperature differential, wherein the temperature differential is driven by heat from the chip package.

Images