Coordination module and associated method for collision avoidance

Abstract

A coordination module for a node of a multipoint bus network, the node comprising a MAC module and a PHY module, the coordination module comprising circuitry configured to: assert a listening signal until each transmission opportunity of the node begins; de-asserting the listening signal at the time to cause the MAC module to send available data to the coordination module to begin to transmit the data over the multipoint bus network via the PHY module at a corresponding transmission opportunity; and re-asserting the listening signal upon receipt of the data from the MAC module or upon timeout of the respective transmission opportunity.

Description

Technical Field

[0001] The present disclosure relates to multi-drop bus networks, and in particular, to an apparatus and associated method for collision avoidance of nodes of a multi-drop bus network. Background Art

[0002] Conflicts on the bus of a multi-drop bus network may result in reduced bus efficiency and throughput. The devices and associated methods described herein can address this problem. Summary of the invention

[0003] According to a first aspect of the present disclosure, there is provided a coordination module for a node of a multi-point bus network, the node comprising a MAC module and a PHY module, the coordination module comprising a circuit system, the circuit system being configured to:

[0004] asserting a listening signal until each transmission opportunity of the node begins;

[0005] De-asserting the listening signal at the time to enable the MAC module to send available data to the coordination module to start transmitting the data on the multi-point bus network via the PHY module at a corresponding transmission opportunity; and

[0006] The listening signal is re-asserted when the data is received from the MAC module or the corresponding transmission opportunity times out.

[0007] The MAC module may be configured to delay the transmission of the data by a waiting time after the de-assertion of the listening signal, and the coordination module may be configured to pass the data received from the MAC module to the PHY module during the waiting time of the MAC module for transmission on the multi-point bus network without transmitting a padding sequence.

[0008] In one or more embodiments, each transmission opportunity may have a duration equal to or greater than the waiting time of the MAC module.

[0009] In one or more embodiments, the waiting time of the MAC module may be equal to a packet gap length.

[0010] In one or more embodiments, in the case where the MAC module sends data that cannot be transmitted on the multi-point bus network starting from a transmission opportunity to the coordination module, the coordination module may be configured to:

[0011] asserting a conflict signal when receiving the data from the MAC module to cause the MAC module to stop sending the data; and

[0012] The sensing signal is controlled to cause the MAC module to resend the data for transmission starting from a next transmission opportunity.

[0013] In one or more embodiments, the data sent by the MAC module may include multiple data frames within the same sequence for transmission starting from a transmission opportunity, and the coordination module may be configured to insert an active-idle sequence between adjacent data frames to prevent the multi-point bus network from becoming idle before the multiple data frames have been transmitted.

[0014] In one or more embodiments, the coordination module may be unbuffered.

[0015] According to a second aspect of the present disclosure, a node of a multi-point bus network is provided, the node comprising the coordination module, MAC module and PHY module of the first aspect.

[0016] In one or more embodiments, the multi-drop bus network may be an Ethernet network, the MAC module may be an Ethernet CSMA / CD MAC layer, and the PHY module may be a 10BASE-T1S PHY layer.

[0017] According to a third aspect of the present disclosure, a multi-point bus network is provided, comprising a plurality of nodes of the second aspect.

[0018] According to a fourth aspect of the present disclosure, a method for conflict avoidance of a node in a multi-point bus network is provided, wherein the node includes a coordination module, a MAC module and a PHY module, and the method includes:

[0019] asserting, by the coordination module, a listening signal until each transmission opportunity of the node begins;

[0020] deasserting the listening signal by the coordination module at the time so that the MAC module sends available data to the coordination module to start transmitting the data on the multi-point bus network via the PHY module at a corresponding transmission opportunity; and

[0021] The coordination module re-asserts the listening signal when the data is received from the MAC module or the corresponding transmission opportunity times out.

[0022] According to a fifth aspect of the present disclosure, a computer program is provided, comprising computer code, wherein the computer code is configured to control the coordination module of the first aspect, control the node of the second aspect, control the multi-point bus network of the third aspect, or execute the method of the fourth aspect.

[0023] Although the present disclosure allows various modifications and alternative forms, the details of the present disclosure have been shown in the drawings by way of example and will be described in detail. However, it should be understood that other embodiments outside the specific embodiments described are also possible. All modifications, equivalents and alternative embodiments falling within the spirit and scope of the appended claims are also encompassed.

[0024] The above discussion is not intended to represent every example embodiment or every implementation within the scope of the current or future claim sets. The following figures and detailed descriptions also illustrate various example embodiments. The various example embodiments can be more fully understood by considering the following detailed descriptions in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0026] Figure 1 Shows the IEEE standard medium independent interface (MII) between the MAC module and the PHY module;

[0027] Figure 2 A coordination module between a MAC module and a PHY module is shown to avoid bus conflicts, wherein both the MAC module and the PHY module communicate with the coordination module using MII;

[0028] Figure 3 A coordination module having a data buffer between a MAC module and a PHY module is shown;

[0029] Figure 4 Shown by Figure 3 The MAC module of the node attempts to transmit on a fully loaded bus;

[0030] Figure 5 Shown by Figure 3 A transmission attempt by a MAC module of a node where the transmission opportunity has timed out;

[0031] Figure 6 Shown by Figure 3 A transmission attempt made by the MAC module of the node, in which the consecutive transmission opportunities have timed out;

[0032] Figure 7 A coordination module is shown without a data buffer between the MAC module and the PHY module;

[0033] Figure 8 Shown by Figure 7 The MAC module of the node attempts to transmit on a fully loaded bus;

[0034] Fig. 9 Shown by Figure 7A transmission attempt by a MAC module of a node where the transmission opportunity has timed out;

[0035] Fig.10 Shown by Figure 7 A transmission attempt made by the MAC module of the node, in which the consecutive transmission opportunities have timed out;

[0036] Fig.11 A method of conflict avoidance for nodes of a multi-point bus network is shown; and

[0037] Fig.12 is shown to include being configured to control, execute or enable Fig.11 A computer readable medium containing a computer program for the method. DETAILED DESCRIPTION

[0038] Ethernet Standards

[0039] Although the recent focus of Ethernet development has been on high data rates, not every application requires speeds of up to 400Gbps. For some applications, including the Internet of Things (IoT), industrial and automotive, 10Mps is sufficient for certain functions. For these use cases, factors such as cost, weight, distance and space required for cables are more important.

[0040] Recognizing these evolving requirements, the IEEE began defining IEEE 802.3cg, a single-pair Ethernet standard supporting 10Mbps, in early 2017. The goal of IEEE 802.3cg is to define short-range standards for point-to-point and multipoint with a maximum length of 25 meters, as well as a long-range point-to-point standard supporting distances up to 1,000 meters. The resulting IEEE 802.3cg specification includes two link layer standards: 10BASE-T1S and 10BASE-T1L.

[0041] The 10BASE-T1S short-range standard is primarily targeted at automotive and industrial applications. Multiple nodes on the network can share the cable in half-duplex shared media mode (multipoint mode) using the standard Ethernet Carrier Sense Multiple Access and Collision Detection (CSMA / CD) access method, or operate using PHY-level collision avoidance (PLCA). The cable can be an unshielded twisted pair (UTP) that can have multiple nodes with a media dependent interface (MDI) attached to them. Therefore, 10BASE-T1S can also be referred to as multi-point single-pair Ethernet.

[0042] The 10BASE-T1L long-range option is designed for IoT and industrial control applications. The 1,000-meter range is sufficient for use in large factories or warehouses, and 10Mbps is sufficient to collect data from sensors and monitor and control many types of industrial machinery. It shares the advantages of the short network variant: MAC-level compatibility with multi-pair Ethernet, as well as lower cost, weight, and required space.

[0043] The following description refers to the 10BASE-T1S standard, but may also be applicable to other (including future) networking standards, and thus is not necessarily limited to Ethernet or 10BASE-T1S.

[0044] Technical issues

[0045] Figure 1 The carrier sense multiple access and collision detection (CSMA / CD) medium access control (MAC) protocol is shown. CSMA / CD uses carrier sense (CRS) to delay transmission until no other nodes on the network are transmitting. When the PHY module / layer of a node detects a collision (CRS=1), the PHY module / layer stops transmitting the frame, asserts a collision signal (COL=1) to the MAC module / layer of the node, and waits until the bus is silent before deasserting the sense signal (CRS=0). The MAC module keeps transmitting for a predefined (jamming) time to ensure that all nodes on the bus will observe the collision, then pauses for a predefined time interval and then attempts to resend the frame to the PHY module for retransmission on the bus. The first retransmission attempt occurs one IPG time after the sense signal (CRS) is deasserted. However, if this will result in another collision, the MAC module introduces a random variable backoff time starting from the second retransmission attempt to avoid infinitely repeated collisions.

[0046] The problem with CSMA / CD is that when the bus is quiet, multiple nodes may attempt to transmit data on the bus simultaneously. This results in collisions, corrupted data, timeouts, and loss of bus capacity, which in turn may cause the effective bus throughput to drop significantly or even completely collapse as the total bus load approaches the maximum bus capacity (e.g., becomes approximately 70% of the maximum bus capacity).

[0047] Figure 2An example of a collision avoidance mechanism developed to increase bus capacity is shown. This mechanism is called physical layer collision avoidance (PLCA) and uses a coordination module / layer connected between the MAC module and the PHY module using the corresponding IEEE standard media independent interface (MII). Each MII may include the same set of pins: transmit data (TXD[3:0]), transmit enable (TXEN), transmit error (TXER), receive data (RXD[3:0]), received data valid (RXDV), receive error (RXER), collision detection (COL) and carrier sense (CRS), and in addition two clock signals (TXCLK and RXCLK, not shown), as defined in IEEE802.3 Clause 22.

[0048] PLCA uses a round-robin scheme in which nodes are numbered and have the opportunity to transmit one at a time starting from a dedicated time slot (or transmission opportunity TO) in a round-robin manner based on their number. One node is assigned as the head node (or PLCA coordinator) and starts each cycle with a beacon. If a node does not transmit data at its transmission opportunity, the transmission opportunity is passed to the next node. The coordination module knows when its node's transmission opportunity occurs based on the node number, and manages the MAC module using conflict (COL-M) and listen (CRS-M) signal manipulation to prevent the MAC module from sending data that cannot be transmitted by the PHY module. In this way, the coordination module passes data to the PHY module only when there is a transmission opportunity. Therefore, the combination of the round-robin scheme and the coordination module avoids conflicts on the bus. Since there should be no conflict events for the PHY module to report, the COL-P pin becomes functionally redundant (and therefore in Figure 3 grayed out in the display), but can still be used to detect real bus problems.

[0049] Figure 3 An example of a PLCA mechanism involving a coordination module having a data buffer (e.g., a first-in, first-out buffer) is shown. The data buffer addresses a scenario where the coordination module begins receiving data from the MAC module shortly before a node's transmission opportunity. In this scenario, the data has been sent from the MAC module too early to be transmitted immediately, but too late for the coordination module to signal a conflict and retransmit the data in time for the upcoming transmission opportunity. Therefore, the data buffer enables the coordination module to temporarily store data sent from the MAC module so that the data can be passed to the PHY module for transmission at the upcoming transmission opportunity.

[0050] Figure 4 Shows the use of the MAC module by the node Figure 31. Transmission attempts (MAC-TXDATA) on a fully loaded bus with a collision avoidance mechanism, where frames are available in the MAC modules of the respective nodes in time to take advantage of each transmission opportunity. In this figure, four nodes are transmitting data on the bus, where each node transmits a single data frame at each of its respective transmission opportunities. The numbering of the nodes is provided for illustrative purposes and is non-limiting (e.g., in practice, the head node may be numbered "0"). The first transmission attempt of node 2 for data frames 1-3 is denoted F1-F3, respectively, and the second (re)transmission attempt is denoted F1'-F3', respectively.

[0051] The coordination module receives a detection signal (CRS-P) from the PHY module indicating transmission activity detected on the bus. The detection signal substantially follows the bus schedule, but with a slight delay, depending on the responsiveness of the PHY module to detect and report bus activity. The coordination module is configured to de-assert the listening signal (CRS-M) whenever the detection signal (CRS-P) is de-asserted, unless the MAC module has made an earlier transmission attempt for the same frame, as described below.

[0052] The MAC module is configured to send data to the coordination module whenever the MAC module has a pending frame for transmission and the listening signal (CRS-M) has been de-asserted by the coordination module. However, in order to ensure the minimum gap between frames of most Ethernet PHY types, the MAC module will delay the waiting time by sending data to the coordination module after the de-assertion of the listening signal (CRS-M). In this example shown, the waiting time of the MAC module is equal to the packet gap (IPG) length (e.g., 12 bytes). Then, the coordination module re-asserts the listening signal (CRS-M) again when receiving data from the MAC module or when detecting the activity on the bus via the detection signal (CRS-P). In the example shown in this article, the de-assertion of the listening signal (CRS-M) is directly related to the de-assertion of the detection signal (CRS-P), but the re-assertion of the listening signal (CRS-M) is slightly delayed relative to the re-assertion of the detection signal (CRS-P). This is intended to help ensure that the MAC module sends pending data after the waiting time, even if the transmission opportunity is shorter than 1 IPG (but this may not be necessary). Therefore, the re-assertion of the listening signal (CRS-M) may also be directly related to the re-assertion of the detection signal (CRS-P).

[0053] When the listening signal (CRS-M) is deasserted, data from the MAC module is buffered in the coordination module, provided that the buffer does not overflow. If the transmission attempt made by the MAC module cannot be fully aligned with the transmission opportunity of the node using the buffer, the coordination module is configured to assert the conflict signal (COL-M) to stop the MAC module from sending data. This occurs by default when another node starts transmitting on the bus and the detection signal (CRS-P) is asserted. The coordination module then deasserts the conflict signal (COL-M). The conflict signal (COL-M) only needs to be asserted long enough to be recognized by the MAC module, and ideally should be as short as possible (e.g., one clock cycle) to avoid any time loss before recovery.

[0054] After the conflict signal (COL-M) is asserted by the coordination module, the listening signal (CRS-M) is not immediately de-asserted. This is for two reasons. First, the MAC module requires a recovery time (CR) after the assertion of the conflict signal (COL-M), and then the MAC module can resend the data as part of the upcoming transmission attempt. Secondly, it is more efficient for the bus to try and ensure that the retransmission attempt is synchronized with the upcoming transmission opportunity to avoid any additional delays in transmitting the data frame. To achieve this, the listening signal (CRS-M) remains asserted until the data can be transmitted directly at the upcoming transmission opportunity without buffering, and then is de-asserted after the recovery time of the MAC module to enable the transmission.

[0055] The data frame is then passed by the coordination module to the PHY module for transmission (PHY-TXDATA) starting from the upcoming transmission opportunity. It should be mentioned that the transmission opportunity can be relatively short (e.g., shorter than the IPG length) and generally does not provide enough time for a node to transmit a complete frame. Instead, they provide a time slot or window for a node to claim the bus before the opportunity times out and the next node has a chance. A node can claim the bus during a transmission opportunity by starting to transmit a data frame or a fill sequence (SYNC symbol). For example, the coordination module can be configured to transmit a SYNC symbol on the bus via the PHY layer module during the waiting time of the MAC module. Once the bus has been claimed by a node, the node can continue to transmit any frame size or even multiple data frames (if configured to allow this).

[0056] exist Figure 4In the example of FIG. 1 , the upcoming transmission opportunity of frame 1 of node 2 is the next transmission opportunity on the bus schedule after the (virtual) collision. On the other hand, for frames 2 and 3 of node 2, there are intervening transmission opportunities of other nodes on the bus schedule. Since the coordination module keeps the listening signal (CRS-M) asserted until the frame can be retransmitted at the corresponding upcoming transmission opportunity, the de-assertion of the listening signal (CRS-M) that would otherwise follow the detection signal (CRS-P) from the PHY module is skipped.

[0057] Figure 5 Shows the use of the MAC module by the node Figure 3 The conflict avoidance mechanism of the bus is used to avoid additional transmission attempts. Figure 4 Unlike the example of , one of the transmission opportunities of node 2 has timed out. This is because frame 3 of node 2 only becomes available in the MAC module at some time during the transmission of frame 3 of node 1. Since the MAC module will delay the waiting time of one IPG to send data to the coordination module after the de-assertion of the listening signal (CRS-M), if the transmission opportunity ends within about 1 IPG length after the de-assertion of the listening signal (CRS-M), there is not enough time for the node to start transmitting frame 3 in the upcoming transmission opportunity. Therefore, the coordination module asserts the collision signal (COL-M) and the listening signal (CRS-M), and keeps the listening signal (CRS-M) asserted until the next transmission opportunity of the node is detected, at which time the listening signal is de-asserted to enable the transmission of the frame on the bus. It is worth noting here that although the coordination module can temporarily store a limited amount of data in the buffer, if any other node transmits data between the transmission opportunities of this node, the buffer is refreshed (otherwise, a large buffer will be required in the coordination module to store the complete frame). For this reason, Frame 3 cannot be stored in the buffer in preparation for the next transmission opportunity of Node 2 (hence, the collision signal (COL-M) is asserted and the first transmission attempt is aborted).

[0058] Figure 6 Shows the use of the MAC module by the node Figure 3 In this example, the consecutive transmission opportunities of nodes 3, 4, and 1 have each timed out, leaving node 2 the only node transmitting on the bus for the duration. This is referred to herein as a "boomerang transmit opportunity" for node 2, where the transmission opportunity of this node returns without any intervening transmissions from other nodes.

[0059] As shown, the MAC module attempts to transmit frame 1 one IPG length after the listening signal (CRS-M) is deasserted after node 1 transmits the first frame. Since this is too late for transmission at the upcoming transmission opportunity of node 2, the coordination module temporarily stores frame 1 in a buffer until the next transmission opportunity arrives, at which time frame 1 is transmitted on the bus by the PHY module. This is only possible because there are no intervening transmissions from other nodes, otherwise the buffer would have been flushed and the collision signal (COL-M) would have been asserted (according to Figure 5 ). The result is that the transmission of frames 1-3 by node 2 is delayed by the buffer until the corresponding transmission opportunity of the node, without any retransmission attempt by the MAC module. In contrast, the collision signal (COL-M) is asserted for frames 4 and 5, because frames 4 and 5 are received from the MAC module in the presence of intervening transmissions by other nodes. Therefore, similar to the previous example, these frames are retransmitted at the next transmission opportunity.

[0060] Although the PLCA mechanism successfully avoids conflicts on the bus by preventing nodes from transmitting outside of their scheduled transmission opportunities, the use of data buffers in the coordination module complicates the system and the benefits of using data buffers in the coordination module are lost when the MAC module attempts to send more data than the buffer can temporarily store before the data can be transmitted on the bus. In addition, the period of time during which data is transmitted too early from the MAC module but too late to retransmit after a virtual conflict is relatively short relative to the total bus cycle time. In addition, as previously mentioned, the head node may transmit a beacon at the beginning of each bus cycle. In this scenario, unless the head node is the only transmitting node, or the head node sends a short fixed-length beacon but no data frames, the buffer may potentially be flushed due to the transmission of the beacon, thereby preventing Figure 6 The boomerang transmission opportunity shown in . In view of the above, it may be difficult to justify the additional cost and complexity associated with a data buffer.

[0061] Embodiments of the present disclosure

[0062] Figure 7 An example of a conflict avoidance mechanism involving a coordination module (or layer) is shown, which avoids conflicts on the bus without the need for a data buffer. As in the previous example, the coordination module is configured to receive data sent from the MAC module (or layer) for transmission on the multi-point bus network via the PHY module (or layer) at the node's transmission opportunity. The MAC module is configured to send data to the coordination module whenever the MAC module has a frame pending for transmission, the listening signal (CRS-M) has been de-asserted by the coordination module, and the waiting time has passed after the de-assertion of the listening signal (CRS-M).

[0063] Moreover, in the event that data is received from the MAC module but cannot be transmitted via the PHY module, the coordination module is configured to assert a conflict signal (COL-M), keep the listening signal (CRS-M) asserted until data can be transmitted at an upcoming transmission opportunity, and then de-assert the listening signal (CRS-M) at the upcoming transmission opportunity to enable the transmission.

[0064] However, unlike the early conflict avoidance mechanism, the coordination module does not de-assert the listening signal (CRS-M) whenever the detection signal (CRS-P) is de-asserted. Instead, the coordination module is configured to de-assert the listening signal (CRS-M) only at the beginning of each transmission opportunity of the node. Specifically, the listening signal (CRS-M) is de-asserted at the said moment to enable the MAC module to send available data to the coordination module to start transmitting data at the corresponding transmission opportunity, and then the listening signal is re-asserted when data is received from the MAC module.

[0065] This method ensures that data already pending in the MAC module is passed to the coordination module only at the right time so that the data can be transmitted at the node's upcoming transmission opportunity as the first transmission attempt. In addition, this eliminates the need for the coordination module to buffer data and also eliminates the need to assert conflict signals for those data frames that are available (pending) before the upcoming transmission opportunity. In order for this scheme to work, the frame interval on the bus should be equal to or greater than 1 IPG. The benefit is simplicity, but the disadvantage is the extra quiet time between frames on the bus.

[0066] Figure 8 Show the use Figure 7 The collision avoidance mechanism of FIG. 10A is used to avoid the transmission attempt (MAC-TXDATA) made by the MAC module of a node (in this example, Node 2) and the associated data transmission (PHY-TXDATA) made by the PHY module of the node on a fully loaded bus to Figure 4 For comparison. Although the bus schedule is shown as having a fixed bus cycle time and a fixed frame length for a node, this is only an example and is not required. In this figure, the latency of each MAC module is equal to one IPG length.

[0067] The duration of a transmission opportunity is a variable set by the system integrator and depends on several parameters. Figure 3 The duration will most likely be about 0.5 IPG length. Figure 7In the case of a collision avoidance mechanism, each transmission opportunity must have a duration equal to or greater than the waiting time of the MAC module, which is typically one IPG length. This increases the probability that the frame will be received in sufficient time for transmission on the first attempt. In addition, this keeps the minimum distance between frames on the bus equal to or greater than 1 IPG length, as for many other Ethernet PHY modules / layers. For the first transmission attempt, the coordination module has no knowledge of the pending frames. Therefore, the coordination module cannot claim the bus by sending a SYNC symbol (i.e., a padding sequence) to the PHY module during the waiting time, because the coordination module may make a retransmission attempt when it is sure that it knows that the frame is from the MAC module. In addition, the longer transmission opportunities eliminate the need for the coordination module to claim the bus in any way before the frame is transmitted by the MAC, because the MAC waiting time before receiving the frame from the MAC can be adapted.

[0068] like Figure 8 As shown in , frames 1-3 of node 2 are available in the MAC module at the beginning of the corresponding transmission opportunity. Therefore, once the waiting time has expired, the frames are passed to the coordination module and transmitted on the first attempt. Moreover, even if the transmission opportunities and the silent intervals between the transmissions of different nodes may be longer than Figure 4 example, but the efficiency of the bus (PHY-TXDATA) is also not affected because no padding sequence is required to assert the bus.

[0069] Fig. 9 The MAC module of node 2 uses Figure 7 The transmission attempt of the collision avoidance mechanism is to Figure 5 For comparison. Similar to Figure 5 In the example of , the transmission opportunity of frame 3 of node 2 times out because this frame arrives too late to be transmitted at the transmission opportunity (i.e., frame 3 is not pending / available in the MAC module until sufficiently into the transmission opportunity period). Therefore, upon receiving data from the MAC module, the coordination module is forced to assert the collision signal (COL-M) to cause the coordination module to stop sending data, and then the coordination module controls the listening signal (CRS-M) to cause the MAC module to resend the data for transmission at the next transmission opportunity (similar to before). This shows that even with longer transmission opportunities, there may still be a situation where a data frame is received from the MAC module too late to be transmitted at the first transmission opportunity and needs to be delayed until the next (second) transmission opportunity. Similarly, relative to Figure 5 , has no impact on bus efficiency.

[0070] Fig.10 The MAC module of node 2 uses Figure 7 The additional transmission attempts by the collision avoidance mechanism are Figure 6. Again, the consecutive transmission opportunities of nodes 3, 4, and 1 have each timed out, leaving node 2 as the only node transmitting on the bus for the duration (i.e., the boomerang transmission opportunity). However, this time, instead of the coordination module buffering frames 1-3 that were received from the MAC module too early for immediate transmission, the asserted listen signal (CRS-M) prevents the MAC module from sending frames until a transmission opportunity arrives. In this way, the coordination module receives these frames immediately after the MAC module's wait time, and these frames are then passed to the PHY module for transmission on the first attempt at their corresponding transmission opportunities.

[0071] Regarding frames 4 and 5, the assertion of the keep listening signal (CRS-M) between consecutive transmissions of the same node means that the MAC module cannot pass these frames to the coordination module when other nodes are transmitting. For this reason, avoid Figure 6 Assertion of the collision signal in and retransmission of frames 4 and 5.

[0072] As shown in the above example, Figure 7 The collision avoidance mechanism of the present invention provides a simpler method of preventing conflicts on the bus than existing systems by eliminating the need for the coordination module to buffer data or transmit SYNC symbols. In addition, increasing the length of a node's transmission opportunity increases the number of frames transmitted at the first transmission opportunity, thereby reducing the number of interrupt frames (using COL-M) and retransmission attempts.

[0073] Although the illustrated example shows each transmission opportunity being limited to the transmission of a single data frame, a node may also transmit multiple data frames within a single sequence starting from a single transmission opportunity. To allow this, the coordination module may be configured to insert an active-idle sequence between adjacent data frames of the sequence to prevent the bus from becoming idle before multiple data frames have been transmitted.

[0074] Each node of the multi-point bus network described herein may include a MAC module, a PHY module, and a coordination module. The multi-point bus network may be an Ethernet network, the MAC module may be an Ethernet CSMA / CD MAC layer, and the PHY module may be a 10BASE-T1S PHY layer. Figure 7 The described coordination module does not require a data buffer, and the coordination module can be unbuffered. Even in the "unbuffered" example where there is no data buffer for storing frames until the next transmission opportunity, the coordination module can still include a small buffer of a few bits in size to help parse data between layers / modules of the Ethernet protocol.

[0075] Although the coordination module (or layer) has been described herein with reference to the MAC and PHY modules (or layers), the coordination module may be formed independently of the other modules and incorporated into the node during a subsequent modular assembly process. In some cases, the coordination module may even be retrofitted to an existing node. Alternatively, the coordination module may be integrated with other modules of the node at the time of manufacture (e.g., as a different part / portion of the same chip). One or more (or each) modules may include a circuit system including at least one processor and at least one memory including computer program code. The at least one memory and computer program code may be configured to, together with the at least one processor, cause the module to perform the associated functionality described herein.

[0076] Fig.11 The main steps of the method for conflict avoidance of a node of a multi-point bus network are schematically shown, and the node includes a coordination module, a MAC module and a PHY module. As shown in the figure, the method includes:

[0077] asserting, by the coordination module, a listening signal until each transmission opportunity of the node begins;

[0078] deasserting the listening signal by the coordination module at the time so that the MAC module sends available data to the coordination module to start transmitting the data on the multi-point bus network via the PHY module at a corresponding transmission opportunity; and

[0079] The coordination module re-asserts the listening signal when the data is received from the MAC module or the corresponding transmission opportunity times out.

[0080] Fig.12 Schematically illustrates a computer / processor readable medium providing a computer program according to an example. The computer program may include computer code configured to execute, control or enable the use of the coordination module described herein. Fig.11 In this example, the computer / processor readable medium is an optical disc, such as a digital versatile disc (DVD) or a compact disc (CD). In other embodiments, the computer / processor readable medium can be any medium that has been programmed in a manner to perform the functions of the present invention. The computer / processor readable medium can be a removable storage device, such as a memory stick or memory card (SD, mini SD, micro SD or nano SD) or an embedded or external non-volatile memory (e.g., flash memory or MRAM).

[0081] Unless a specific order is explicitly stated, the instructions and / or flow chart steps in the above figure may be executed in any order. Moreover, those skilled in the art will recognize that although an example instruction set / method has been discussed, the materials in this specification may be combined in a variety of ways to produce other examples and should be understood within the context provided in this specific embodiment.

[0082] In some example embodiments, the instruction set / method steps described above are implemented as functions and software instructions embodied as an executable instruction set, which is implemented on a computer or a machine programmed and controlled with the executable instructions. Such instructions are loaded for execution on a processor (e.g., one or more CPUs). The term processor includes a microprocessor, a microcontroller, a processor module or subsystem (including one or more microprocessors or microcontrollers), or other control or computing devices. A processor may refer to a single component or multiple components.

[0083] In other examples, the instruction sets / methods shown herein and the data and instructions associated therewith are stored in corresponding storage devices, which are implemented as one or more non-transitory machine or computer readable or computer usable storage media. Such computer readable or computer usable storage media are considered to be part of an article (or product). An article or product may refer to any manufactured single component or multiple components. One or more non-transitory machine or computer usable media as defined herein do not include signals, but such one or more media are capable of receiving and processing information from signals and / or other temporary media.

[0084] Example embodiments of the materials discussed in this specification may be implemented in whole or in part via network, computer or data-based devices and / or services. These may include the cloud, the Internet, an intranet, a mobile device, a desktop computer, a processor, a lookup table, a microcontroller, a consumer device, an infrastructure, or other enabling devices and services.

[0085] In one example, one or more instructions or steps discussed herein are automatic. The term automation or automatic (and similar variations thereof) means the use of computers and / or mechanical / electrical devices to control the operation of equipment, systems and / or processes without human intervention, observation, effort and / or decision making.

[0086] It should be understood that any components that are said to be coupled may be coupled or connected directly or indirectly. In the case of indirect coupling, additional components may be placed between the two components that are said to be coupled.

[0087] In this specification, example embodiments have been presented based on a selected set of details. However, one of ordinary skill in the art will appreciate that many other example embodiments may be practiced that include different selected sets of these details. It is intended that the appended claims cover all possible example embodiments.

Claims

1. A coordination module for a node of a multipoint bus network, characterized in that: The node comprises a MAC module and a PHY module, and the coordination module comprises a circuit system, wherein the circuit system is configured to: asserting a listening signal until each transmission opportunity of the node begins; deasserting the listening signal at the time to enable the MAC module to send available data to the coordination module to start transmitting the data on the multi-point bus network via the PHY module at a corresponding transmission opportunity; as well as The listening signal is re-asserted when the data is received from the MAC module or the corresponding transmission opportunity times out.

2. The coordination module according to claim 1, characterized in that: The MAC module is configured to delay the transmission of the data for a waiting time after the de-assertion of the listening signal, and wherein the coordination module is configured to pass the data received from the MAC module to the PHY module during the waiting time of the MAC module for transmission on the multi-point bus network without transmitting a padding sequence.

3. The coordination module according to claim 2, characterized in that: Each transmission opportunity has a duration equal to or greater than the waiting time of the MAC module.

4. The coordination module according to claim 2 or 3, characterized in that: The waiting time of the MAC module is equal to the packet gap length.

5. A coordination module according to any of the preceding claims, characterized in that In the case where the MAC module sends data that cannot be transmitted on the multi-point bus network starting from a transmission opportunity to the coordination module, the coordination module is configured to: asserting a conflict signal when receiving the data from the MAC module to cause the MAC module to stop sending the data; and The sensing signal is controlled to cause the MAC module to resend the data for transmission starting from a next transmission opportunity.

6. A coordination module according to any of the preceding claims, characterised in that The data sent by the MAC module includes multiple data frames in the same sequence for transmission starting from a transmission opportunity, and wherein the coordination module is configured to insert an active-idle sequence between adjacent data frames to prevent the multi-point bus network from becoming idle before the multiple data frames have been transmitted.

7. A node of a multipoint bus network, characterized in that: The node comprises the coordination module according to any of the preceding claims, the MAC module and the PHY module.

8. A multi-point bus network, characterized in that: Comprising a plurality of nodes according to claim 7.

9. A method for avoiding conflicts among nodes in a multipoint bus network, characterized in that: The node includes a coordination module, a MAC module and a PHY module, and the method includes: asserting, by the coordination module, a listening signal until each transmission opportunity of the node begins; deasserting the listening signal by the coordination module at the time so that the MAC module sends available data to the coordination module to start transmitting the data on the multi-point bus network via the PHY module at a corresponding transmission opportunity; and The coordination module re-asserts the listening signal when the data is received from the MAC module or the corresponding transmission opportunity times out.

10. A computer program, characterized in that comprising computer code configured to perform the method according to claim 9.

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