Direct access of data plane of switch to storage device

Abstract

Various implementations of the present disclosure relate to direct access of a data plane of a switch to a storage device. Determining, at a data plane of the switch, whether an acknowledgement signal for a predetermined number of data packets is not received from the storage device after the data packet for which the acknowledgement signal is recently received; in response to the fact that the response signal for the preset number of data packets is not received after the data packet of the response signal is received recently, updating the first state serial number of the switch to be a second state serial number, wherein the first state serial number represents the serial number of the data packet to be sent by the switch; the second state serial number represents the serial number of the data packet which receives the acknowledgement signal recently; packaging the first state serial number and data to be sent by the switch into a data packet; and sending the packaged data packet to a storage device.

Description

Related Applications

[0001] This application is a divisional application of the invention patent application with application number 202110901026.3 and invention name “Direct access of the data plane of the switch to the storage device”. Background Art

[0002] With the development of computer technology and network technology, many analytical applications based on big data have played an important role in today's production environment. Generally, the workflow of analytical applications includes two stages: data collection stage and data analysis stage. Since the data collection stage does not generate any new information, ideally, it is hoped that as few computing resources as possible are spent in the collection stage and as many available computing resources as possible are spent in the analysis stage, thereby minimizing costs. However, in actual situations, the data collection stage may consume a lot of computing resources. Summary of the invention

[0003] According to multiple implementations of the present disclosure, a scheme for accessing a storage device through a data plane of a switch is provided. At the data plane of the switch, a response signal for a first data packet sent by the switch to the storage device is received from the storage device, the first data packet encapsulates a data packet sequence number and first data to be sent by the switch, and the response signal includes the data packet sequence number. In response to determining that the response signal is a negative response signal, the first state sequence number of the switch is updated to the data packet sequence number included in the response signal, the first state sequence number indicating the sequence number of the data packet to be sent by the switch. The first state sequence number and the second data to be sent by the switch are encapsulated into a second data packet, and the second data packet is sent to the storage device.

[0004] This Summary is provided to introduce a selection of concepts in a simplified form that are further described in the Detailed Description below. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 A block diagram of a data collection system capable of implementing various implementations of the present disclosure is shown;

[0006] Figure 2 A block diagram of a switch according to some implementations of the present disclosure is shown;

[0007] Figure 3 A flowchart of a method for establishing a connection according to some implementations of the present disclosure is shown;

[0008] Figure 4 A flow chart of a data packet encapsulation method according to some implementations of the present disclosure is shown;

[0009] Figure 5 A schematic diagram showing a "black hole" state;

[0010] Figure 6 A flow chart showing a method of control plane implementation according to some implementations of the present disclosure;

[0011] Figure 7 A flow chart showing a method for processing a reply signal according to some implementations of the present disclosure is shown;

[0012] Figure 8 A flow chart of a retransmission method according to the prior art is shown;

[0013] Fig. 9 A flow chart of a retransmission method according to some implementations of the present disclosure is shown;

[0014] Fig.10 A flow chart showing a transmission completion processing method according to some implementations of the present disclosure is shown;

[0015] Fig.11 A flow chart showing a method of control plane implementation according to some implementations of the present disclosure;

[0016] Fig.12 A mapping table between logical addresses and physical addresses according to some implementations of the present disclosure is shown;

[0017] Fig.13 A schematic diagram showing an append operation according to some implementations of the present disclosure; and

[0018] Fig.14 A flow chart illustrating a method according to some implementations of the present disclosure is shown.

[0019] In these drawings, the same or similar reference symbols are used to designate the same or similar elements. DETAILED DESCRIPTION

[0020] The present disclosure will now be discussed with reference to several example implementations. It should be understood that these implementations are discussed only to enable those skilled in the art to better understand and thus implement the present disclosure, and do not imply any limitation on the scope of the present subject matter.

[0021] As used herein, the term "including" and variations thereof are to be interpreted as open-ended terms meaning "including, but not limited to." The term "based on" is to be interpreted as "based at least in part on." The terms "an implementation" and "an implementation" are to be interpreted as "at least one implementation." The term "another implementation" is to be interpreted as "at least one other implementation." The terms "first," "second," etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0022] A fault-tolerant application is an application that is insensitive to the loss of data to be processed. For example, some data analysis applications focus on extracting useful semantics from data statistics and are therefore insensitive to data loss. Examples of these applications include telemetry systems based on packet mirroring (e.g., EverFlow, NetSight, etc.) and log analysis systems (e.g., audit logs of search engines). According to multiple implementations of the present disclosure, in a fault-tolerant application, direct access to a storage device through the data plane of a switch, when a transmission error occurs in a data packet, the sequence number in the data packet can be used to encapsulate the next data packet to be sent to meet the requirements of reliable transmission. In this way, there is no need to consider the problem of data loss, computing resources can be saved, and thus the requirements for computing resources in the data collection phase are reduced. Multiple implementations of the present disclosure will be described below in conjunction with the accompanying drawings.

[0023] Figure 1 Schematic diagram of a data collection system 100 according to some implementations of the present disclosure is shown. Figure 1 As shown, the data collection system 100 includes a switch 102 and a server 104 that is communicatively connected to the switch 102. The server 104 includes a storage device 112, which may be any suitable storage device such as a flash memory, a hard disk, etc. The switch 102 may be a programmable switch and include a control plane 108 and a data plane 110. The switch 102 may receive data packets 106 from various data sources and send the data packets 106 to the server 104 for processing by the server 104. For example, these data sources may be logs from a search engine, etc. For example, the server 104 may include a remote direct memory access (RDMA) network interface card (RNIC) so that the storage device 112 communicates with the data plane 110 of the switch 102. The switch 102 may be a programmable switch, such as a P4 programmable switch.

[0024] Non-Volatile Memory Express (NVMe) transport is a non-volatile memory-based transport specification designed to provide reliable storage access and data transmission through transport methods such as the PCIe bus. Based on transport methods such as the PCIe bus, network storage in data centers can be supported through NVMe (NVMe over Fabric, NVMe-oF) extensions on the network structure. Options for network structures that support RDMA include InfiniBand (IB), RDMA Converged Ethernet (RoCE), Internet Wide Area RDMA (iWARP), etc. The multiple implementations of the present disclosure are mainly described for these scenarios, however, it should be understood that these implementations can also be applied to other suitable standards or protocols.

[0025] Figure 21 shows a block diagram of a switch 102 according to some implementations of the present disclosure. Figure 2 As shown, the control plane 108 of the switch 102 includes a control unit 220, which can be used to perform various operations of the control plane 108. The data plane 110 of the switch 102 includes a parser 202, which is used to parse the received data packet 106. In some implementations, the data plane 110 is implemented in hardware, such as a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc. In a programmable switch, the data plane 110 can be programmed to implement various different functions.

[0026] like Figure 2 As shown, the parser 202 sends the parsed data packet 106 to the pipeline selector 204, and the pipeline selector 204 forwards the data packet 106 to different pipelines according to the type of the data packet 106, for example, the metadata transmission pipeline 206, the NVMe-oF encapsulation pipeline 208, the RMDA ACK / NACK pipeline 210, and the NVMe-oF completion response processing pipeline 212. For example, if the pipeline selector 204 determines that the data packet 106 is metadata, the data packet 106 can be sent to the metadata transmission pipeline 206. These pipelines can process the data packet 106 accordingly and send the processed data packet to the pipeline demultiplexer 214. The pipeline demultiplexer 214 sends the data packet to the forwarding engine 216, and depending on the destination address in the data packet, the forwarding engine 216 can send the data packet to the control unit 220 in the control plane 108, or send the data packet to the assembler 218. The assembler 218 assembles the data packet into a predetermined format for sending to the server 104. The following will specifically combine Figure 3-Figure 12 The operation of pipelines 206-212 is described.

[0027] Figure 3 A flow chart of a method 300 for establishing a connection between a switch and a storage device according to some implementations of the present disclosure is shown. For example, the method 300 may be implemented in a Figure 1 and Figure 2 The method 300 is executed at the control plane 108 of the switch 102 shown to establish an NVMe-oF connection between the switch 102 and the storage device 112. For example, the method 300 can be implemented by software in the control plane 108 of the switch 102.

[0028] At block 302, an NVMe-oF connection is established between the switch 102 and the storage device 112. For example, an NVMe connection and an RDMA reliable connection (RC) may be established between the switch 102 and the storage device 112, respectively, to establish an NVMe-oF connection between the switch 102 and the storage device 112. For example, metadata may be exchanged between the switch 102 and the storage device 112 when the NVMe connection and the RDMA RC connection are established.

[0029] At block 304, after the NVMe-oF connection is established between the switch 102 and the storage device 112, the control plane 108 of the switch 102 offloads or provides the metadata to the data plane 110 of the switch 102. For example, the control plane 108 may provide the metadata to the data plane 110 via an application programming interface (API) of the data plane 110. After receiving the metadata, the data plane 110 may implement functions such as encapsulating data packets according to the received metadata.

[0030] Figure 4 A flow chart of a method 400 for encapsulating a data packet according to some implementations of the present disclosure is shown. For example, the method 400 may be implemented as follows: Figure 2 The NVMe-oF encapsulation pipeline shown is implemented at 208.

[0031] For example, the switch 102 may receive data 106, such as an EverFlow data packet, from one or more data sources. In box 402, based on the first state sequence number of the switch 102, the data 106 received by the switch 102 from the data source is encapsulated into a data packet, such as an NVMe-oF data packet. The RDMA RC type uses the packet sequence number (PSN) field in the IB basic transmission header to achieve reliable transmission. Therefore, in order to achieve reliable transmission, the switch 102 needs to maintain a state sequence number, which indicates the sequence number of the data packet to be sent (also called the packet sequence number, PSN). Otherwise, the data packet sent by the switch 102 may be rejected by the RNIC at the server 104.

[0032] In some implementations, the first state sequence number may be maintained by the data plane 110 of the switch 102 and represent the sequence number of the data packet to be sent. For example, the data 106 and the first state sequence number may be encapsulated as part of the NVMe-oF data packet. In some implementations, the data plane 110 of the switch 102 may include multiple virtual interfaces, such as queue pairs (QPs). For example, a first state sequence number may be maintained for each virtual interface. For ease of discussion, this will be described for one QP, and it should be understood that the methods described herein may also be applied to other QPs.

[0033] In some implementations, according to the RDMA Converged Ethernet Version 2 (RoCEv2) and NVMe-oF specifications, a valid data packet includes multiple headers, such as an Ethernet header, an Internet Protocol (IP) header, a User Datagram Protocol (UDP) header, an IB basic transport header, and an NVMe command capsule. The metadata used to construct these headers can be obtained through Figure 3 The metadata may be obtained by the metadata offloading process shown in block 304 of FIG. For example, the metadata may include metadata of each queue pair (QP), such as a QP number (QPN), a packet sequence number (PSN), etc. Although the metadata specified in the RoCEv2 specification is provided as an example here, the corresponding metadata may also be provided according to other suitable specifications.

[0034] In block 404, the first state sequence number is incremented by 1. In this way, when a data packet is encapsulated next time, the updated first state sequence number can be used to encapsulate the data packet.

[0035] In block 406, it is determined whether a predetermined number of packets have not received an acknowledgment signal after the most recent packet that received the acknowledgment signal. For convenience, G is used to represent the predetermined number, also known as a threshold. Here, the acknowledgment signal includes a positive acknowledgment signal (ACK) and a negative acknowledgment signal (NACK).

[0036] If it is determined in block 406 that no response signal has been received for G data packets after the data packet that most recently received the response signal, it can be determined that the current Figure 5 In the "black hole" state, the receiver discards all packets without sending any feedback to the sender. Figure 5 As shown, the transmitter sends three data packets P1, P2 and P3 in sequence, where data packet P1 is lost during transmission. When the receiver receives data packet P2, the receiver determines that data packet P1 is lost through the sequence number in data packet P2. Then, the receiver discards data packet P2 and sends a NACK for data packet P1 to the transmitter. When data packet P3 arrives at the receiver, since the receiver has already sent a NACK, the receiver will discard data packet P3 without sending feedback. When the transmitter receives the NACK, the transmitter will retransmit three data packets P1', P2' and P3'. If the receiver successfully receives data packet P1', the receiver will be ready to receive subsequent data packets, including data packets P2' and P3'. However, if the NACK or P1' is lost, the receiver will fall into a "black hole" state until the receiver receives data packet P1.

[0037] When it is determined at block 406 that a predetermined number of packets have not received an acknowledgement signal (i.e., a "black hole" state) after the packet that most recently received an acknowledgement signal, the method 400 proceeds to block 408. At block 408, the first state sequence number is updated based on the second state sequence number, wherein the second state sequence number represents the sequence number of the packet that most recently received a positive acknowledgement signal. The second state sequence number may be maintained by the data plane 110 of the switch 102. For example, the packet encapsulated at block 402 may be considered the first packet since the packet that most recently received a positive acknowledgement signal, and therefore, the first state sequence number may be reset to the second state sequence number + 1. Then, the method 400 proceeds to block 410, and the switch 102 sends the encapsulated packet to the storage device 112.

[0038] If it is determined in block 406 that there is no situation where no response signal is received for the predetermined number of packets, the method 400 proceeds to block 410. In block 410, the switch 102 sends the encapsulated packet to the storage device 112. In this way, in the data plane 110 of the switch 102, the problem of the "black hole" state can be solved.

[0039] In some implementations, a counter may be used to determine whether a predetermined number of data packets have not received an acknowledgement signal after the most recent data packet that received an acknowledgement signal, thereby determining whether a "black hole" state has been entered. In order to count the number of data packets that have been sent, the counter may be increased by 1 each time a data packet is sent. In addition, when an acknowledgement signal (ACK or NACK) is received, the counter is reset to 0. Therefore, when the counter reaches a predetermined number or a predetermined threshold (G), it may be determined that a predetermined number of data packets have not received an acknowledgement signal after the most recent data packet that received an acknowledgement signal. Otherwise, when the counter does not reach a predetermined number or a predetermined threshold (G), it may be determined that a predetermined number of data packets have not received an acknowledgement signal after the most recent data packet that received an acknowledgement signal.

[0040] In box 412, when necessary, the data plane 110 of the switch 102 can notify the control plane 108 of the switch 102. In some implementations, the control plane 108 of the switch 102 can be notified through a notification mechanism based on the amount of data. For example, the data plane 110 of the switch 102 can maintain a counter that represents the number of packets sent, and if the counter reaches a threshold, the control plane 108 of the switch 102 is notified. The server 104 cannot know the amount of data received by the storage device 112. Therefore, after receiving the notification from the data plane 110, the control plane 108 of the switch 102 can send a message to the server 104 to notify the server 104 that the amount of data it has received has reached the threshold. At this point, the server 104 has obtained enough data and can perform subsequent processing on the data. The following will be combined with Figure 6 This section describes the follow-up processing of the corresponding notification.

[0041] Figure 6 A flow chart of a method 500 implemented by the control plane 108 of the switch 102 according to some implementations of the present disclosure is shown. For example, the method 500 can be implemented in the control plane 108 of the switch 102.

[0042] At block 502, the control plane 108 of the switch 102 receives a notification sent from the data plane 108 of the switch 102. Figure 4 As described in block 412 of the embodiment, the notification may be that the data transmission from the switch 102 to the storage device 112 reaches a predetermined number. Alternatively or additionally, the notification may also be that the data transmission from the switch 102 to the storage device 112 reaches a predetermined time.

[0043] In block 504, the control plane 108 of the switch 102 sends a notification to the server 104. After receiving the notification, the server 104 can process the data received by the storage device 112. Since the storage device 112 directly participates in the data transmission process and the processor of the server 104 does not participate in the data transmission process, the server 104 cannot know when the data transmission ends, when to start processing the data, etc. With the help of the method 500, the server 104 can obtain the above information and perform subsequent data processing.

[0044] Figure 7 FIG. 6 is a flow chart of a method 600 for processing a response signal according to some implementations of the present disclosure. For example, the method 600 may be performed as follows: Figure 2 The RDMA ACK / NACK processing pipeline 210 is shown to implement this.

[0045] At block 602, the data plane 110 of the switch 102 receives an acknowledgement signal from the storage device 112. At block 604, the data plane 110 of the switch 102 determines whether the acknowledgement signal is a positive acknowledgement signal (ACK) or a negative acknowledgement signal (NACK). If the acknowledgement signal is determined to be a NACK at block 604, then at block 606, the data plane 110 of the switch 102 updates or resets the first state sequence number of the switch 102 by the sequence number included or specified in the NACK. Figure 8 and Fig. 9 Block 606 is further described.

[0046] Generally speaking, RDMA uses the Priority Flow Control (PFC) mechanism to achieve reliable data transmission. However, in some cases, the RDMA network interface card (RNIC) may still lose some data packets due to invalid checksums caused by bit errors. In addition, the RDMA receiver may reject some data packets due to insufficient resources. Therefore, the RDMA receiver will send a NACK to the RDMA sender, and the NACK contains the expected PSN of the next data packet to be sent by RDMA. Then, the RDMA sender needs to perform a back-off N-step retransmission mechanism to retransmit.

[0047] Figure 8 FIG. 4 shows a back-off N-step retransmission mechanism according to the prior art. Figure 8 As shown, when the receiver receives data packet P2, it finds that data packet P1 has not been received, and thus determines that data packet P1 has failed to be received. In this case, the receiver returns a NACK response of data packet P1 to the transmitter. At this time, the transmitter needs to resend data packet P1 and data packet P2 in sequence. However, due to the limitation of the hardware resources of the switch 102, it is usually difficult for the switch 102 to store the data in the data packet for retransmission.

[0048] Fig. 9 A schematic diagram of a retransmission method according to some implementations of the present disclosure is shown to meet the requirements of RDMA reliable transmission. Fig. 9 As shown, the data in the data packet P1 and the data packet P2 are data 1 and data 2, respectively. When the sender receives the NACK response of the data packet P1, the sender still sends the data packets P1 and P2, however, the data in the data packets P1 and P2 are updated to data 3 and data 4, respectively. Since data loss is acceptable in fault-tolerant applications, the implementation of the present disclosure allows the loss of data 1 and data 2 during the transmission process, and the switch 102 does not need to store the data in the data packet for retransmission, and can support the implementation of RDMA reliable transmission.

[0049] For example, in Fig. 9In the example of FIG. 1 , the response signal to the data packet P1 is NACK, which includes the sequence number of the data packet P1, which is also the expected sequence number of the next data packet to be sent. The first state sequence number is reset to the sequence number included or specified in the NACK, thereby retransmitting the data packet P1, wherein the data packet P1 has the same sequence number as the original data packet P1, but includes different data from the original data packet P1.

[0050] return Figure 7 , at block 608, the second state sequence number is updated based on the first state sequence number. The data packet that has recently received a positive acknowledgment signal is the previous data packet of the data packet responded to by NACK, and thus the second state sequence number representing the sequence number of the data packet that has recently received a positive acknowledgment signal can be updated to the first state sequence number minus one.

[0051] If it is determined at block 604 that the acknowledgement signal is an ACK, then at block 610, the second state signal is updated based on the sequence number included or specified in the ACK. For example, the second state sequence number may be updated to the sequence number included or specified in the ACK.

[0052] Fig.10 FIG. 7 is a flow chart of a transmission completion processing method 700 according to some implementations of the present disclosure. For example, the method 700 may be performed as follows: Figure 2 The NVMe-oF completion response processing pipeline 212 shown is implemented.

[0053] After completing the execution of the NVMe command, the storage device 112 will send an NVMe-oF completion packet to the switch 102. Since the NVMe-oF data transmission supporting RDMA is built on the RDMA RC, from the perspective of RDMA, the NVMe-oF completion packet is only a payload and needs to be responded by the switch 102. Therefore, the switch 102, as the receiving end of the RDMAQP of the storage device 112, needs to maintain the expected sequence number of the RDMAQP of the storage device 112, which can be expressed as an ePSN.

[0054] In block 702, when the switch 102 receives an NVMe-oF completion packet, a source QP number (QPN) and a sequence number (PSN) of a packet corresponding to the QP are obtained from the received NVMe-oF completion packet.

[0055] At block 704, it is determined whether the PSN is greater than, equal to, or less than the ePSN. If it is determined at block 704 that the PSN is equal to the ePSN, then at block 706, the switch 102 sends a positive acknowledgment signal to the storage device 112 and updates the ePSN, for example, the ePSN may be increased by 1. For example, the ACK packet may be constructed by adding an appropriate header and removing the received payload.

[0056] If it is determined at block 704 that the PSN is less than the ePSN, then at block 708, the switch 102 sends a positive acknowledgement to the storage device 112, but does not update the ePSN. If it is determined at block 704 that the PSN is greater than the ePSN, then at block 710, the switch 102 sends a negative acknowledgement signal to the storage device 112, but does not update the ePSN. For example, a NACK packet may be constructed by adding an appropriate header and removing the received payload.

[0057] The NVMe-oF completion packet carries the status of the storage device 112. If necessary, the data plane 110 of the switch 102 can send a notification about the status of the storage device 112 to the control plane 108. For example, the data plane 110 can examine the NVMe-oF completion packet to determine the status of the storage device 112. If the data plane 110 of the switch 102 determines that the status of the storage device 112 is abnormal (e.g., disconnected, etc.), the data plane 110 of the switch 102 can notify the control plane 108 of the switch 102.

[0058] Fig.11 A flow chart of a method 800 for maintaining a connection between a switch 102 and a storage device 112 according to some implementations of the present disclosure is shown. For example, the method 800 can be implemented in the control plane 108 of the switch 102.

[0059] In some implementations, a Keep Alive command may be sent periodically based on a timer to ensure that the RDMA connection between the switch 102 and the storage device 112 is in a normal state. For example, the NVMe-oF specification that supports RDMA may require support for the Keep Alive command. The Keep Alive command is sent less frequently (e.g., once every few seconds), so it does not occupy too many resources of the control plane.

[0060] In response to the expiration of a timer, the switch 102 determines to send a keep-alive command at block 802. The timer may be triggered periodically, for example, the period may be several seconds.

[0061] In block 804, the switch 102 constructs a keep-alive command. For example, the keep-alive command can be constructed through a queue pair in the system queue (Admin Queue) of the NVMe protocol.

[0062] In block 806, the packet sequence number (PSN) of the system queue is increased by 1. In block 808, a packet of a keep-alive command is sent to the server 104 to tell the server 104 that the connection between the two is valid, to prevent the server 104 from disconnecting, and to release resources.

[0063] According to multiple implementations of the present disclosure, the switch receives data from the data source and stores the data in a remote storage device. The channel from the data source to the remote storage device can be abstracted as a logical stream. The data source appends data to the logical stream, and the data has a corresponding logical address in the logical stream. In addition, when encapsulating the data from the data source into a data packet, the switch can dynamically assign a physical address to the data. For example, the physical address can be a physical address of the NVMe protocol. The switch can maintain a register in the data plane to index the physical address where the next data received from the data source is to be stored, and encapsulate the data and its physical address into a data packet and send it to the remote storage device. After receiving the data packet, the remote storage device can store the data in the data packet to the corresponding location in the remote storage device. For example, the remote storage device can parse the physical address of the data according to the NVMe protocol and store the data in the corresponding location. Fig.12 A schematic diagram of the mapping between logical addresses and physical addresses according to some implementations of the present disclosure is shown. The mapping between logical addresses and physical addresses can be implemented through a multi-level page table. Fig.12 In the example of , a two-level page table is used as an example to introduce the mapping between logical addresses and physical addresses. It should be understood that other levels of multi-level page tables can also be used to implement the mapping between logical addresses and physical addresses. Through the mapping between logical addresses and physical addresses, continuous logical addresses and scattered physical addresses can be accessed, thereby more efficiently utilizing physical storage space.

[0064] Fig.12 An example of writing data D in a storage device based on a logical stream logical address 0x0203 is shown. Fig.12 In the example shown, the logical address includes three offsets, where the first-level offset is 0, the second-level offset is 2, and the third-level offset is 03. Through the three offsets of the logical address and the base address (0x00F0), the corresponding physical address can be determined to be 0xA303. Specifically, through the base address (0x00F0) and the first-level offset (0) of the logical stream, the location of the first-level page table entry can be determined, and the address stored therein, that is, 0xB0D0, can be read from the location. Then, using the address 0xB0D0 in the first-level page table entry as the base address, based on the second-level offset (2), the location of the second-level page table entry can be determined, and the address stored therein, that is, 0xA300, can be read from the location. Then, based on the address 0xA300 and the third-level offset (03), the final physical address is determined to be 0xA303, and the data "D" is stored in the physical address.

[0065] In some implementations, the data append operation can be implemented based on the offset of the multi-level page table. The data plane of the switch 102 can include multiple registers to store the offset of the multi-level page table to record the current storage state. For example, for the secondary page table, the data plane of the switch 102 can include three registers to store three offsets respectively. In addition, the multi-level page table can be stored in the storage device 112 of the server 104 to reduce the storage capacity requirements of the data plane of the switch 102.

[0066] When the primary offset or the secondary offset is moved, a new page table entry may be written to the storage device 112. The processing of metadata such as page table entries may be performed by, for example, Figure 2 The metadata transmission pipeline 206 shown is implemented. Fig.13 FIG. 2 shows a schematic diagram of a data append operation according to some implementations of the present disclosure. Fig.13 As shown, it is assumed that the page table entries corresponding to the tail of the current logical flow logical address are the first-level page table entry 1308 and the second-level page table entry 1310. When the switch receives the next data and finds that the second-level page table 1304 has been used up, a new second-level page table 1306 can be allocated, and a new first-level page table entry 1312 can be allocated in the first-level page table 1302 to store the base address of the second-level page table 1306. Then, the physical address assigned to the data is stored in the first second-level page table entry 1314 of the second-level page table 1306. At this time, the page table entries corresponding to the tail of the logical flow logical address are the first-level page table entry 1312 and the second-level page table entry 1314. In this way, an append operation can be implemented. In this example, the new metadata entry can be written to the storage device 112, and the data plane of the switch 102 can only update the offset.

[0067] In some implementations, the mirroring function in the switch 102 can be applied to a data packet to obtain a mirrored data packet. The data packet is sent to the storage device 112 through an encapsulation operation. In addition, the mirrored data packet is processed to determine metadata of the mirrored data packet (e.g., an entry of a multi-level page table), and the metadata of the mirrored data packet is sent to the storage device 112.

[0068] The higher the level of metadata, the lower the generation frequency and the greater the impact of the loss; the lower the level of metadata, the higher the generation frequency and the smaller the impact of damage. For example, data corruption of entries in a level one page table (high level) in a multi-level page table may cause all entries in the entire level two page table to be unavailable, which has a very serious impact. In some implementations, different transmission strategies can be used for metadata of different levels. For example, for high-level metadata (e.g., level one page table entries), reliable transmission can be performed via the control plane, for example, through a retransmission mechanism. For low-level metadata (e.g., level two page table entries), reliability can be improved through redundant transmission. For example, R entries can be transmitted at each transmission, where the R entries include 1 new entry and R-1 old entries. Assuming the damage ratio is l, the redundant transmission scheme can reduce the damage ratio to l. R In addition, no special processing is required for the data itself.

[0069] Fig.14 1400 according to some implementations of the present disclosure. Figure 1 or Figure 2 The switch 102 is shown as being implemented.

[0070] In block 1402, a data plane of a switch receives a response signal from a storage device for a first data packet sent by the switch to the storage device. The first data packet encapsulates a data packet sequence number and first data received by the switch from a data source. The response signal includes the data packet sequence number.

[0071] At block 1404, the data plane of the switch determines whether the acknowledgment signal is a positive acknowledgment signal or a negative acknowledgment signal.

[0072] If the acknowledgement signal is determined to be a negative acknowledgement signal in block 1404, method 1400 proceeds to block 1406, where the data plane of the switch updates the first state sequence number of the switch to the sequence number of the data packet included or specified in the acknowledgement signal. The first state sequence number indicates the sequence number of the data packet to be sent by the switch.

[0073] At block 1408, the data plane of the switch encapsulates the first state sequence number and second data received by the switch from the data source into a second data packet. For example, the switch may receive the first data from a first data source and the second data from a second data source, and the first data source may be the same as or different from the second data source.

[0074] At block 1410 , the data plane of the switch sends a second data packet to the storage device.

[0075] In some implementations, the method 1400 further includes: determining the physical address of the second data in the storage device through a multi-level page table based on the logical address of the second data. Fig.12 As shown, the logical address may be 0x0203 and the physical address may be 0xA303.

[0076] In some implementations, the logical address includes multiple offsets associated with a multi-level page table, and the multiple offsets are stored in the data plane. Fig.12 In the implementation of , the logical address includes three offsets, which can be stored in three registers.

[0077] In some implementations, the multi-level page table is stored in a storage device.

[0078] In some implementations, high-level page table entries in the multi-level page table are sent through a control plane of the switch.

[0079] In some implementations, low-level page table entries in a multi-level page table are sent via redundant transmission.

[0080] In some implementations, method 1400 further includes: determining whether a response signal for a predetermined number of packets has not been received after the packet for which the response signal was most recently received; and in response to determining that a response signal for the predetermined number of packets has not been received after the packet for which the response signal was most recently received, updating the first state sequence number based on a second state sequence number of the switch, the second state sequence number representing a sequence number of a packet for which a positive response signal was most recently received. For example, the first state sequence number may be updated by: Figure 4 Blocks 406 and 408 are shown to update the first state sequence number.

[0081] In some implementations, method 1400 further includes: in response to determining that the acknowledgement signal is a negative acknowledgement signal including the first sequence number, updating the second state sequence number to the first state sequence number minus one. Figure 7 The second state sequence number is updated using the method shown in box 608 in the example.

[0082] In some implementations, if it is determined at block 1404 that the acknowledgment signal is a positive acknowledgment signal, method 1400 proceeds to block 1412 to update the second state sequence number to the data packet sequence number included in or specified in the acknowledgment signal. Figure 7 The second state sequence number is updated using the method shown in box 610 in FIG.

[0083] Some example implementations of the present disclosure are listed below.

[0084] In a first aspect, the present disclosure provides a method implemented at a switch. The method includes: at a data plane of the switch: receiving a response signal from a storage device for a first data packet sent by the switch to the storage device, the first data packet encapsulating a data packet sequence number and first data to be sent by the switch, and the response signal including the data packet sequence number; in response to determining that the response signal is a negative response signal, updating a first state sequence number of the switch to the data packet sequence number included in the response signal, the first state sequence number indicating the sequence number of the data packet to be sent by the switch; encapsulating the first state sequence number and second data to be sent by the switch into a second data packet; and sending the second data packet to the storage device.

[0085] In some implementations, the method further includes: determining a physical address of the second data in the storage device through a multi-level page table based on a logical address of the second data.

[0086] In some implementations, the logical address includes a plurality of offsets associated with the multi-level page table, the plurality of offsets being stored in the data plane.

[0087] In some implementations, the multi-level page table is stored in the storage device.

[0088] In some implementations, a high-level page table entry in the multi-level page table is sent via a control plane of the switch.

[0089] In some implementations, lower level page table entries in the multi-level page table are sent via redundant transmission.

[0090] In some implementations, the method further includes: determining whether a response signal for a predetermined number of data packets has not been received after a data packet for which a response signal has been most recently received; and in response to determining that a response signal for a predetermined number of data packets has not been received after a data packet for which a response signal has been most recently received, updating the first state sequence number based on a second state sequence number of the switch, wherein the second state sequence number represents a sequence number of a data packet for which a positive response signal has been most recently received.

[0091] In some implementations, the method further includes: in response to determining that the response signal is a negative response signal, updating a second state sequence number of the switch to the first state sequence number minus one, the second state sequence number representing the sequence number of the data packet that most recently received the positive response signal.

[0092] In some implementations, the method further includes: in response to determining that the response signal is an affirmative response signal, updating the second state sequence number of the switch to the data packet sequence number included in the response signal, wherein the second state sequence number represents the sequence number of the data packet for which the affirmative response signal has been most recently received.

[0093] In a second aspect, the present disclosure provides a switch. The switch includes: a data plane, the data plane being configured to: receive a response signal from a storage device for a first data packet sent by the switch to the storage device, the first data packet encapsulating a data packet sequence number and first data received by the switch from a data source, and the response signal including the data packet sequence number; in response to determining that the response signal is a negative response signal, update a first state sequence number of the switch to the data packet sequence number included in the response signal, the first state sequence number indicating the sequence number of the data packet to be sent; encapsulate the first state sequence number and second data received by the switch from the data source into a second data packet; and send the second data packet to the storage device.

[0094] In some implementations, the data plane is further configured to determine, based on the logical address of the second data, a physical address of the second data in the storage device through a multi-level page table.

[0095] In some implementations, the logical address includes a plurality of offsets associated with the multi-level page table, the plurality of offsets being stored in the data plane.

[0096] In some implementations, the multi-level page table is stored in the storage device.

[0097] In some implementations, a high-level page table entry in the multi-level page table is sent via a control plane of the switch.

[0098] In some implementations, lower level page table entries in the multi-level page table are sent via redundant transmission.

[0099] In some implementations, the data plane is further configured to: determine whether a response signal for a predetermined number of data packets has not been received after a data packet for which a response signal has been most recently received; and in response to determining that a response signal for a predetermined number of data packets has not been received after a data packet for which a response signal has been most recently received, update the first state sequence number based on a second state sequence number of the switch, wherein the second state sequence number represents a sequence number of a data packet for which a positive response signal has been most recently received.

[0100] In some implementations, the data plane is further configured to: in response to determining that the response signal is a negative response signal, update the second state sequence number of the switch to the first state sequence number minus one, the second state sequence number representing the sequence number of the data packet that most recently received the positive response signal.

[0101] In some implementations, the data plane is further configured to: in response to determining that the response signal is a positive response signal, update the second state sequence number of the switch to the data packet sequence number contained in the response signal, wherein the second state sequence number represents the sequence number of the data packet for which the positive response signal was most recently received.

[0102] In a third aspect, the present disclosure provides a device, comprising: a processing unit; and a memory coupled to the processing unit and containing instructions stored thereon, wherein when the instructions are executed by the processing unit, the device executes the method in the first aspect of the present disclosure.

[0103] In a fourth aspect, the present disclosure provides a computer program product, which is tangibly stored in a computer storage medium and includes computer executable instructions, which when executed by a device cause the device to perform the method in the first aspect of the present disclosure.

[0104] In a fifth aspect, the present disclosure provides a computer-readable storage medium having computer-executable instructions stored thereon, which, when executed by a device, cause the device to perform the method in the first aspect of the present disclosure.

[0105] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), and the like.

[0106] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0107] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0108] In addition, although each operation is described in a specific order, this should be understood as requiring such operation to be performed in the specific order shown or in a sequential order, or requiring that all illustrated operations should be performed to obtain the desired result. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Certain features described in the context of a separate implementation can also be implemented in a single implementation in combination. On the contrary, the various features described in the context of a single implementation can also be implemented in multiple implementations individually or in any suitable sub-combination.

[0109] Although the subject matter has been described in language specific to structural features and / or methodological logical actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims.

Claims

1. A method implemented at a switch, comprising: At the data plane of the switch: determining whether an acknowledgement signal for a predetermined number of packets has not been received from the storage device after the packet for which the acknowledgement signal was most recently received; In response to determining that an acknowledgement signal has not been received for a predetermined number of packets after the packet for which the acknowledgement signal was most recently received, updating a first state sequence number of the switch to a second state sequence number, the first state sequence number indicating a sequence number of a packet to be transmitted by the switch, the second state sequence number indicating a sequence number of a packet for which a positive acknowledgement signal was most recently received; Encapsulating the first state sequence number and the data to be sent by the switch into a data packet; as well as The encapsulated data packet is sent to the storage device.

2. A switch, comprising: A data plane, the data plane being configured as: determining whether an acknowledgement signal for a predetermined number of packets has not been received from the storage device after the packet for which the acknowledgement signal was most recently received; In response to determining that an acknowledgement signal has not been received for a predetermined number of packets after the packet for which the acknowledgement signal was most recently received, updating a first state sequence number of the switch to a second state sequence number, the first state sequence number indicating a sequence number of a packet to be transmitted by the switch, the second state sequence number indicating a sequence number of a packet for which a positive acknowledgement signal was most recently received; Encapsulating the first state sequence number and the data to be sent by the switch into a data packet; as well as The encapsulated data packet is sent to the storage device.

3. A computer program product, the computer program product being stored in a computer storage medium and comprising computer executable instructions, the computer executable instructions, when executed by a data plane of a switch, causing the data plane of the switch to perform actions, the actions comprising: determining whether an acknowledgement signal for a predetermined number of packets has not been received from the storage device after the packet for which the acknowledgement signal was most recently received; In response to determining that an acknowledgement signal has not been received for a predetermined number of packets after the packet for which the acknowledgement signal was most recently received, updating a first state sequence number of the switch to a second state sequence number, the first state sequence number indicating a sequence number of a packet to be transmitted by the switch, the second state sequence number indicating a sequence number of a packet for which a positive acknowledgement signal was most recently received; Encapsulating the first state sequence number and the data to be sent by the switch into a data packet; as well as The encapsulated data packet is sent to the storage device.

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