Image sensor, image signal conversion method, image pickup device, and vehicle

Abstract

The invention provides an image sensor, an image signal conversion method, a camera device and a vehicle. The image sensor comprises a pixel circuit and a logic circuit. The pixel circuit comprises a pixel array, and the pixel array comprises pixel units which are arranged in multiple rows and multiple columns. The logic circuit comprises at least two groups of analog-to-digital converters, and the pixel units in the pixel array are connected to the at least two groups of analog-to-digital converters. According to the image sensor provided by the invention, the two rows of pixel units are selected at the same time and the image signals acquired by the pixel units are output to the two groups of analog-to-digital converters respectively, so that the problem of low efficiency caused by the fact that only one row of image signals can be output at one time in the prior art is solved at least.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to an image sensor, an image signal conversion method, a camera device and a vehicle. Background Art

[0002] When reading an image, the existing CIS generally converts and reads one line at a time for a frame of image, resulting in low efficiency in image conversion and reading. Summary of the invention

[0003] The embodiments of the present application provide an image sensor, an image signal conversion method, a camera device and a vehicle, which can simultaneously convert at least two lines of image signals to at least partially solve the above-mentioned technical problems.

[0004] In order to achieve the above-mentioned purpose, according to the first aspect of the present application, there is provided an image sensor, comprising a pixel circuit and a logic circuit; the pixel circuit comprises a pixel array, the pixel array comprises pixel units arranged in multiple rows and columns; the logic circuit comprises at least two groups of analog-to-digital converters, the pixel units in the pixel array are connected to at least two groups of the analog-to-digital converters; wherein the pixel units in the same row but different columns of the pixel array are connected to at least two groups of the analog-to-digital converters, and / or the pixel units in the same column but different rows of the pixel array are connected to at least two groups of the analog-to-digital converters.

[0005] Optionally, the logic circuit further includes: at least two groups of row switching switches, which are arranged corresponding to the at least two groups of analog-to-digital converters.

[0006] Optionally, the logic circuit includes: a first group of row switching switches, a second group of row switching switches, a first group of analog-to-digital converters and a second group of analog-to-digital converters; wherein, the pixel array is electrically connected to the first group of analog-to-digital converters via the first group of row switching switches, and the pixel array is electrically connected to the second group of analog-to-digital converters via the second group of row switching switches, the first group of row switching switches is arranged on the first row side of the pixel array, and the second group of row switching switches is arranged on the last row side of the pixel array.

[0007] Optionally, the pixel array includes M rows×N columns of pixel units, and each column of the pixel units is respectively connected to the first group of row switching switches and the second group of row switching switches through two column buses.

[0008] Optionally, the first group of row switching switches includes 2N first switches, the second group of row switching switches includes 2N second switches, and each of the column buses corresponds to a first switch and a second switch.

[0009] Optionally, the pixel units in the odd rows of the nth column are all connected to the 2n-1th column bus, and are connected to the 2n-1th first switch through the 2n-1th column bus, and the pixel units in the even rows of the nth column are all connected to the 2nth column bus, and are connected to the 2nth second switch through the 2nth column bus, 1≤n≤N.

[0010] Optionally, the pixel units in the even rows of the nth column are all connected to the 2n-1th column bus, and are connected to the 2n-1th first switch through the 2n-1th column bus, and the pixel units in the odd rows of the nth column are all connected to the 2nth column bus, and are connected to the 2nth second switch through the 2nth column bus, 1≤n≤N.

[0011] Optionally, the nth second switch and the n+1th first switch are both controlled to be turned on or off by the first pulse signal, and the n+1th second switch and the nth first switch are both controlled to be turned on or off by the second pulse signal; wherein the first pulse signal and the second pulse signal have opposite phases.

[0012] Optionally, the n+2th second switch and the n+3th first switch are both controlled to be turned on or off by the third pulse signal, and the n+3th second switch and the n+2th first switch are both controlled to be turned on or off by the fourth pulse signal; wherein, the third pulse signal and the fourth pulse signal have opposite phases, the first pulse signal and the fourth pulse signal have the same phase, and the second pulse signal and the third pulse signal have the same phase.

[0013] According to a second aspect of the present application, a method for converting an image signal is provided, comprising: determining image signals in at least two rows of pixel units to be converted according to a control signal; outputting the image signals in at least two rows of pixel units to at least two groups of analog-to-digital converters at the same time; converting the image signals in at least two rows of pixel units by at least two groups of analog-to-digital converters; wherein the image signals in pixel units in different columns of the same row are output to at least two groups of analog-to-digital converters respectively; and / or the image signals in pixel units in different rows of the same column are output to at least two groups of analog-to-digital converters respectively.

[0014] Optionally, outputting the image signals in at least two rows of pixel units to at least two groups of analog-to-digital converters at the same time respectively includes: outputting the image signals in pixel units in different columns of the same row respectively to at least two groups of analog-to-digital converters; and / or outputting the image signals in pixel units in different rows of the same column respectively to at least two groups of analog-to-digital converters.

[0015] Optionally, the image signals in the pixel units in the same column but different rows are respectively output to at least two groups of the analog-to-digital converters, including: outputting the image signals of the pixel units in all odd rows in the nth column to the first group of analog-to-digital converters, and outputting the image signals of the pixel units in all even rows in the nth column to the second group of analog-to-digital converters.

[0016] Optionally, the image signals in the pixel units in the same column but different rows are output to at least two groups of the analog-to-digital converters respectively, including: outputting the image signals of the pixel units in all odd rows in the nth column to the second group of analog-to-digital converters, and outputting the image signals of the pixel units in all even rows in the nth column to the first group of analog-to-digital converters.

[0017] Optionally, the image signals in the pixel units in the same column but different rows are respectively output to at least two groups of the analog-to-digital converters, including: outputting the image signals of the pixel units in all odd rows in the n+1th column to the second group of analog-to-digital converters; and outputting the image signals of the pixel units in all even rows in the n+1th column to the first group of analog-to-digital converters.

[0018] Optionally, the image signals in the pixel units in the same column but different rows are respectively output to at least two groups of the analog-to-digital converters, including: outputting the image signals of the pixel units in all even rows in the n+1th column to the second group of analog-to-digital converters; and outputting the image signals of the pixel units in all odd rows in the n+1th column to the first group of analog-to-digital converters.

[0019] Optionally, the image signals in the pixel units in the same row but different columns are respectively output to at least two groups of the analog-to-digital converters, including: outputting the image signals of the pixel units in all odd columns in the mth row to the first group of analog-to-digital converters, and outputting the image signals of the pixel units in all even columns in the mth row to the second group of analog-to-digital converters.

[0020] Optionally, the image signals in the pixel units in the same row but different columns are respectively output to at least two groups of the analog-to-digital converters, including: outputting the image signals of the pixel units in all odd columns in the m+1th row to the second group of analog-to-digital converters; and outputting the image signals of the pixel units in all even columns in the m+1th row to the first group of analog-to-digital converters.

[0021] Optionally, the image signals in the pixel units in the same row but different columns are respectively output to at least two groups of the analog-to-digital converters, including: outputting the image signals of the pixel units in all odd columns in the m+2th row to the second group of analog-to-digital converters; and outputting the image signals of the pixel units in all even columns in the m+2th row to the first group of analog-to-digital converters.

[0022] Optionally, outputting the image signals in the two rows of pixel units to the first group of analog-to-digital converters and the second group of analog-to-digital converters at the same time respectively includes: outputting the image signals of the pixel units in all odd columns in the m+3th row to the first group of analog-to-digital converters; outputting the image signals of the pixel units in all even columns in the m+3th row to the second group of analog-to-digital converters.

[0023] Optionally, the image signals in the pixel units in the same row but different columns are respectively output to at least two groups of the analog-to-digital converters, including: outputting the image signals of the pixel units in all odd columns in the mth row to the second group of analog-to-digital converters; and outputting the image signals of the pixel units in all even columns in the mth row to the first group of analog-to-digital converters.

[0024] Optionally, the image signals in the pixel units in the same row but different columns are respectively output to at least two groups of the analog-to-digital converters, including: outputting the image signals of the pixel units in all odd columns in the m+1th row to the first group of analog-to-digital converters; and outputting the image signals of the pixel units in all even columns in the m+1th row to the second group of analog-to-digital converters.

[0025] Optionally, the image signals in the pixel units in the same row but different columns are respectively output to at least two groups of the analog-to-digital converters, including: outputting the image signals of the pixel units in all odd columns in the m+2th row to the first group of analog-to-digital converters; and outputting the image signals of the pixel units in all even columns in the m+2th row to the second group of analog-to-digital converters.

[0026] Optionally, the image signals in the pixel units in the same row but different columns are respectively output to at least two groups of the analog-to-digital converters, including: outputting the image signals of the pixel units in all odd columns in the m+3th row to the second group of analog-to-digital converters; outputting the image signals of the pixel units in all even columns in the m+3th row to the first group of analog-to-digital converters.

[0027] According to a third aspect of the present application, there is also provided a camera device, comprising the above-mentioned image sensor.

[0028] According to a fourth aspect of the present application, a vehicle is also provided, comprising the above-mentioned camera device.

[0029] The image sensor of the embodiment of the present application includes a pixel circuit and a logic circuit; the pixel circuit includes a pixel array, and the pixel array includes pixel units arranged in multiple rows and columns; the logic circuit includes at least two groups of analog-to-digital converters, and the pixel units in the pixel array are connected to at least two groups of the analog-to-digital converters; wherein the pixel units in the same row but different columns of the pixel array are connected to at least two groups of the analog-to-digital converters, and / or the pixel units in the same column but different rows of the pixel array are connected to at least two groups of the analog-to-digital converters.

[0030] The image sensor provided by the present application can simultaneously select two rows of pixel units and output the collected image signals to two groups of analog-to-digital converters respectively, thereby solving the problem of low efficiency caused by only being able to output one row of image signals at a time in the prior art, improving the conversion quantization speed of the image signal, and at the same time improving the frame rate of image refresh.

[0031] Other features and advantages of the present application will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0033] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0034] Figure 1 is a schematic structural diagram of an image sensor provided in an exemplary embodiment of the present application;

[0035] Figure 2 is a schematic diagram of a pixel readout scheme provided in an exemplary embodiment of the present application;

[0036] Figure 3 is a schematic diagram of a system architecture of an image sensor provided in an exemplary embodiment of the present application;

[0037] Figure 4 is a schematic structural diagram of a row switching circuit provided in an exemplary embodiment of the present application;

[0038] Figure 5 is a schematic diagram of a row exchange switch control signal provided in an exemplary embodiment of the present application;

[0039] Figure 6 is Figure 5 A schematic diagram of a row-switching pixel readout scheme under the control signal shown;

[0040] Figure 7 is another row exchange switch control signal schematic diagram provided in an exemplary embodiment of the present application;

[0041] Figure 8 is Figure 7 A schematic diagram of a row-switching pixel readout scheme under the control signal shown;

[0042] Fig. 9 is a flowchart of an image signal conversion method provided in an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0044] Reference Figure 1 As shown, according to an embodiment of the present application, an image sensor 10 is provided, comprising a pixel circuit 20 and a logic circuit 30 which are arranged opposite to each other.

[0045] The pixel circuit 20 includes: a pixel array 21 located in the central area of ​​the pixel circuit 20 and a first peripheral circuit 22 located on at least one side of the pixel array 21. The first peripheral circuit 22 can be arranged around the pixel array 21. Pixel is the smallest photosensitive unit of the image sensor, and the pixel array is arranged together to form the photosensitive area of ​​the image sensor. The pixel array described in the embodiment of the present application can be understood as effective pixels (Number of effective pixels), that is, pixels in the CIS that can perform effective photoelectric conversion and output image signals, which is an important technical indicator for measuring the CIS.

[0046] The pixel circuit 20 includes a pixel array 21, and the pixel array 21 includes pixel units arranged in multiple rows and columns; the logic circuit 30 includes at least two groups of analog-to-digital converters, and the pixel units in the pixel array 21 are connected to the at least two groups of analog-to-digital converters; wherein, the pixel units in the same row but different columns of the pixel array 21 are connected to the at least two groups of analog-to-digital converters, and / or, the pixel units in the same column but different rows of the pixel array are connected to the at least two groups of analog-to-digital converters.

[0047] In the embodiment of the present application, two groups of analog-to-digital converters can be set to simultaneously convert the image data corresponding to two rows of pixel units, three groups of analog-to-digital converters can be set to simultaneously convert the image data corresponding to three rows of pixel units, four groups of analog-to-digital converters can be set to simultaneously convert the image data corresponding to four rows of pixel units, or even more analog-to-digital converters can be set, which is not limited in the embodiment of the present application. It should be noted that each group of analog-to-digital converters corresponds to a group of row switching switches.

[0048] Reference Figures 1 to 3 As shown, in the embodiment of the present application, the logic circuit includes two groups of analog-to-digital converters as an example for illustrative description. The logic circuit 30 includes: a first group of analog-to-digital converters 31 and a second group of analog-to-digital converters 32 arranged in parallel, a row decoder (Row Decoder, RDEC) 33 located on one side of the first group of analog-to-digital converters 31, and a second peripheral circuit 34 located on at least one side of the first group of analog-to-digital converters, a first group of row exchange switches 35, and a second group of row exchange switches 36.

[0049] Among them, the row decoder 33 is electrically connected to the pixel array 21, the pixel array 21 is electrically connected to the first group of analog-to-digital converters 31 via the first group of row switching switches 35, and the pixel array 21 is electrically connected to the second group of analog-to-digital converters 32 via the second group of row switching switches 36, so that the image signal in the pixel array 21 is output to two rows at the same time to the first group of analog-to-digital converters 31 and the second group of analog-to-digital converters 32.

[0050] The pixel circuit 20 and the logic circuit 30 are electrically connected to each other through the first peripheral circuit 22 and the second peripheral circuit 34 .

[0051] The first group of analog-to-digital converters 31 described in the embodiment of the present application can be composed of a group of column-parallel ADCs. Similarly, the second group of analog-to-digital converters 32 can also be composed of a group of column-parallel ADCs, and each ADC corresponds to a column of pixel units.

[0052] In the embodiment of the present application, in the effective pixel array of the pixel chip (Pixel Wafer), the photoelectric conversion element and the pixel circuit will be designed into a two-dimensional matrix structure. The logic circuit including the analog-to-digital converter ADC is placed in the logic area of ​​the logic chip (Logic Wafer). The vertical contacts for connecting the two chips can be arranged in the peripheral area to electrically connect the Pixel Wafer and the Logic Wafer to each other.

[0053] The image sensor provided by the present application can simultaneously select two rows of pixel units and output the collected image signals to two groups of analog-to-digital converters respectively, thereby at least solving the problem of low efficiency caused by only being able to output one row of image signals at a time in the prior art, improving the conversion quantization speed of the image signal, and at the same time improving the frame rate of image refresh.

[0054] refer to Figure 2 As shown, the effective pixel array is read out to the column parallel ADC (the first group of analog-to-digital converters 31 and the second group of analog-to-digital converters 32) according to odd and even rows respectively. A simple row-by-row readout scheme is as follows: Figure 2 As shown. Each column of pixels relies on two column buses to input image signals into the column parallel ADC. One column bus inputs the image signals output by the odd-numbered rows of pixels into the second group of analog-to-digital converters 32 circuits, and the other column bus inputs the image signals output by the even-numbered rows into the first group of analog-to-digital converters 31 circuits. Taking a 6-row 5-column pixel array as an example, the image signals output by the pixel rows Row[0], Row[2], and Row[4] are converted and quantized by the first group of analog-to-digital converters 31 circuits, and the image signals output by the pixel rows Row[1], Row[3], and Row[5] are converted and quantized by the second group of analog-to-digital converters 32 circuits.

[0055] The delay from the 0th row of pixels Row[0] column bus output to the first column readout circuit (ADC1) is t0, and the delay from the 1st row of pixels Row[1] column bus output to the second column readout circuit (ADC2) is t1. In large-array image sensors, due to the asymmetric routing of image signals of the 0th row of pixels and the 1st row of pixels, t1>t0 when the image sensor is working, which leads to the introduction of unequal thermal noise, flicker noise and other noises in the signal transmission process, resulting in obvious row stripes on the image screen.

[0056] refer to Figure 3 As shown, in an optional embodiment, the logic circuit 30 further includes: a first group of row switching switches 35 provided corresponding to the first group of analog-to-digital converters 31 and a second group of row switching switches 36 provided corresponding to the second group of analog-to-digital converters 32. The first group of row switching switches 35 are electrically connected to the pixel array 21 and the first group of analog-to-digital converters 31, respectively, and the second group of row switching switches 36 are electrically connected to the pixel array 21 and the second group of analog-to-digital converters 32, respectively.

[0057] The row decoder 33 outputs a control signal, and the pixel array receives the control signal to find the corresponding pixel unit, and performs reset, exposure and readout processes according to the control signal. The image signal generated in the pixel unit circuit passes through the row exchange switch, and the row exchange switch processes the image signals of two rows of pixels read out at the same time and inputs them into two different column parallel ADC circuits for conversion and quantization.

[0058] In this way, the image signal can be selectively input into different column parallel ADCs through the row exchange switch, thereby effectively alleviating the row fixed pattern noise (row FPN).

[0059] In an optional embodiment, the pixel array 21 includes M rows and N columns of pixel units, each column of pixel units is connected to two column buses, the first group of row switching switches includes 2N first switches, the second group of row switching switches includes 2N second switches, and each column bus corresponds to a first switch and a second switch.

[0060] The pixel units in the odd rows of the nth column are all connected to the 2n-1th column bus and connected to the 2n-1th first switch through the 2n-1th column bus. The pixel units in the even rows of the nth column are all connected to the 2nth column bus and connected to the 2nth second switch through the 2nth column bus, 1≤n≤N.

[0061] Alternatively, the pixel units in the even rows of the nth column are all connected to the 2n-1th column bus and connected to the 2n-1th first switch through the 2n-1th column bus, and the pixel units in the odd rows of the nth column are all connected to the 2nth column bus and connected to the 2nth second switch through the 2nth column bus, 1≤n≤N.

[0062] Reference Figure 4 As shown, taking a 6-row 5-column pixel array as an example, each pixel in the pixel matrix is ​​numbered according to its position, for example, pixel A is located at row 5 and column 4. The image signal generated by the photosensitive pixel unit passes through the row exchange switch circuit module (35 or 36) and is selectively input to the designated column parallel ADC circuit.

[0063] The image signal of each column of pixel units is output to two column parallel ADC circuits through a column bus, and a pair of switches are connected to both ends of the column bus. The closing or opening of each pair of switches is controlled by signals with opposite phases.

[0064] In an optional embodiment, the nth second switch and the n+1th first switch are both controlled to be turned on or off by the first pulse signal, and the n+1th second switch and the nth first switch are both controlled to be turned on or off by the second pulse signal; wherein the first pulse signal and the second pulse signal have opposite phases.

[0065] In an optional embodiment, the n+2th second switch and the n+3th first switch are both controlled to be turned on or off by the third pulse signal, and the n+3th second switch and the n+2th first switch are both controlled to be turned on or off by the fourth pulse signal; wherein the third pulse signal and the fourth pulse signal have opposite phases, the first pulse signal and the fourth pulse signal have the same phase, and the second pulse signal and the third pulse signal have the same phase.

[0066] Reference Figure 5As shown, switches s1 and s2 are controlled by a pair of signals Switch_S1 (corresponding to the first pulse signal in the above text) and Switch_S2 (corresponding to the second pulse signal in the above text) with opposite phases; switches s3 and s4 are controlled by a pair of signals Switch_S3 (corresponding to the third pulse signal in the above text) and Switch_S4 (corresponding to the fourth pulse signal in the above text) with opposite phases, and the control signals Switch_S1 and Switch_S4 of switches s1 and s4 have the same phase.

[0067] The first switch control scheme is as follows Figure 5 As shown, the row exchange switches of the odd columns are controlled by the same signal when reading out the image signals of the pixel units, and the row exchange switches of the even columns are controlled by the same signal when reading out the image signals of the pixel units. The image signals output by all the odd-numbered row pixel units in the same column are converted and quantized in the same column parallel ADC, and the image signals output by all the even-numbered row pixel units in the same column are converted and quantized in another column parallel ADC.

[0068] In an optional embodiment, a specific readout situation is as follows Figure 6 As shown, when switch s1 is turned on, switch s2 is turned off, switch s3 is turned off, and switch s4 is turned on, the odd columns (corresponding to Figure 6 The image signals output by the second group of analog-to-digital converters 32 are converted and quantized, and the even columns (corresponding to the 1st and 3rd columns of the pixel rows Row[0], Row[2], and Row[4]) are converted and quantized by the second group of analog-to-digital converters 32. Figure 6 The image signals output by the first group of analog-to-digital converters 31 are converted and quantized, and the odd columns (corresponding to the 0, 2, and 4 columns in the pixel rows Row[1], Row[3], and Row[5]) are converted and quantized by the first group of analog-to-digital converters 31. Figure 6 The image signals output by the first group of analog-to-digital converters 31 are converted and quantized, and the even columns (corresponding to the 1st and 3rd columns of the pixel rows Row[1], Row[3], and Row[5]) are converted and quantized by the first group of analog-to-digital converters 31. Figure 6 The image signal output by the second group of analog-to-digital converters 32 is converted and quantized.

[0069] The even columns of pixel rows Row[0], Row[2], and Row[4] (corresponding to Figure 6 The image signals output by the pixel units of columns 0, 2, and 4 in the upper column parallel ADC circuit are input to the first group of analog-to-digital converters 31 through the first group of row exchange switches 35, and the odd columns (corresponding to Figure 6 The image signals output by the pixel units of columns 1 and 3 in the figure are input to the second group of analog-to-digital converters 32 of the column parallel ADC circuit below through the second group of row exchange switches 36; the even columns (corresponding to the even columns) output by the pixel rows Row[1], Row[3], and Row[5] Figure 6The image signals output by the pixel units of columns 0, 2, and 4 in the figure are input to the second group of analog-to-digital converters 32 of the column parallel ADC circuit below through the second group of row exchange switches 36, and the odd columns (corresponding to Figure 6 The image signals output by the pixel units (columns 1 and 3 in the figure) are input to the first group of analog-to-digital converters 31 of the upper column parallel ADC circuit through the first group of row exchange switches 35.

[0070] The first switch control scheme groups image signals generated by adjacent row pixels into different column-parallel analog-to-digital conversion circuits with two rows in a group, averaging the noise difference between rows within the group and reducing the row fixed pattern noise (row FPN) in the pixel array.

[0071] Taking the 0th row and the 1st row as an example, due to the existence of two column-parallel ADC circuits, the image signal of the pixel in the 0th row is converted and quantized by the first group of analog-to-digital converters 31 of the column-parallel ADC circuit, and the image signal of the pixel in the 1st row is converted and quantized by the second group of analog-to-digital converters 32 of the column-parallel ADC circuit. Switch control scheme 1 performs row exchange between adjacent columns of pixels in the same row, and selects whether the even columns or the odd columns are exchanged in the adjacent columns. For example, the paths of the image signals output by the even columns of the pixels in the 0th row and the 1st row remain unchanged, and the paths of the image signals output by the odd columns of the pixels are exchanged. The image signals output by the odd columns of the pixels in the 0th row are converted and quantized by the second group of analog-to-digital converters 32 of the column-parallel ADC circuit, and the image signals output by the odd columns of the pixels in the 1st row are converted and quantized by the first group of analog-to-digital converters 31 of the column-parallel ADC circuit.

[0072] The second switch control scheme is as follows Figure 7 As shown, after the image signals of every two rows of pixels are read out, the switch control signal phase rotates 180 degrees, the high level becomes the low level, and the low level becomes the high level. For the image signals output by the selected row, the first group of column parallel analog-to-digital converters 31 or the second group of column parallel analog-to-digital converters 32 read out the signals at intervals; the image signals of two adjacent odd rows (e.g., Row[1] and Row[3]) are read out to different column parallel analog-to-digital converters, and the image signals of two adjacent even rows (e.g., Row[0] and Row[2]) are read out to different column analog-to-digital converters.

[0073] The image signals of the upper and lower pixels in the same column of two rows are read out simultaneously as one unit, such as Figure 6 and Figure 8 As shown in the figure, the noise in the non-ideal image signal may come from the slight mismatch between the two column-parallel ADCs during the manufacturing process, the thermal noise and flicker noise introduced during the transmission of the image signal, etc. Therefore, due to the different signal transmission directions of each unit, the noise of different units may vary greatly. Figure 6 and Figure 8 Indicated by different colors.

[0074] The image signal generated by the upper pixel in the yellow shading unit is read out in the first group of analog-to-digital converters 31 of the analog-to-digital converter, and the image signal generated by the lower pixel is read out in the second group of analog-to-digital converters 32 of the analog-to-digital converter; the image signal generated by the upper pixel in the blue shading unit is read out in the second group of analog-to-digital converters 32 of the analog-to-digital converter, and the image signal generated by the lower pixel is read out in the first group of analog-to-digital converters 31 of the analog-to-digital converter.

[0075] The second switch control scheme mentioned above refers to Figure 8 As shown, for the image signal output by the selected row, the first group of column parallel analog-to-digital converters 31 or the second group of analog-to-digital converters 32 read out the image signal at intervals. Specifically, two adjacent rows are grouped together, for example, Row[0] and Row[1] are the first group, and Row[2] and Row[3] are the second group. In the first group, the even columns (corresponding to Figure 8 The data of the columns 0, 2, and 4 shown in FIG. 1 are converted and quantized by the first group of analog-to-digital converters 31 of the column parallel ADC circuit. The odd columns of Row[0] (corresponding to Figure 8 The data of the columns 1 and 3 shown in FIG. 1 are converted and quantized by the second group of analog-to-digital converters 32 of the column parallel ADC circuit; the even columns of Row[1] (corresponding to Figure 8 The data of columns 0, 2, and 4 shown in FIG. 1 are converted and quantized by the second group of analog-to-digital converters 32 of the column parallel ADC circuit. The odd columns of Row[1] (corresponding to Figure 8 The data of the columns 1 and 3 shown in FIG. 1 are converted and quantized by the first group of analog-to-digital converters 31 of the column parallel ADC circuit. In the second group, the control signal switches, and the even columns of Row[2] (corresponding to Figure 8 The data of columns 0, 2, and 4 shown in FIG. 1 are converted and quantized by the second group of analog-to-digital converters 32 of the column parallel ADC circuit. The odd columns of Row[2] (corresponding to Figure 8 The data of the columns 1 and 3 shown in FIG. 1 are converted and quantized by the first group of analog-to-digital converters 31 of the column parallel ADC circuit; the even columns of Row[3] (corresponding to Figure 8 The data of columns 0, 2, and 4 shown in FIG. 1 are converted and quantized by the first group of analog-to-digital converters 31 of the column parallel ADC circuit. The odd columns of Row[3] (corresponding to Figure 8 The data (columns 1 and 3) are converted and quantized by a second group of analog-to-digital converters 32 of a column-parallel ADC circuit.

[0076] The second switch control scheme is a further improvement on the first switch control scheme, shortening the obvious noise gap between two adjacent columns of pixels, and further improving the imaging level.

[0077] Reference Fig. 9As shown, according to another embodiment of the present application, a method for converting an image signal is also provided, which is applied to the image sensor described in any of the above embodiments, and the contents already stated are not repeated here. Specifically, the method for converting an image signal includes:

[0078] Step S901, determining image signals in at least two rows of pixel units to be converted according to a control signal;

[0079] Step S902, outputting image signals in at least two rows of pixel units to at least two groups of analog-to-digital converters at the same time;

[0080] Step S903, converting image signals in at least two rows of pixel units by using at least two groups of analog-to-digital converters;

[0081] Wherein, image signals in pixel units in the same row but different columns are respectively output to at least two groups of analog-to-digital converters; and / or

[0082] Image signals in pixel units in the same column but different rows are output to at least two groups of analog-to-digital converters respectively.

[0083] The image signal conversion method provided in the present application can simultaneously select two rows of pixel units and output the collected image signals to two groups of analog-to-digital converters respectively, thereby at least solving the problem of low efficiency caused by only being able to output one row of image signals at a time in the prior art, improving the conversion quantization speed of the image signal, and at the same time improving the frame rate of the image refresh.

[0084] refer to Figure 2 As shown, the effective pixel array is read out to the column parallel ADC (the first group of analog-to-digital converters 31 and the second group of analog-to-digital converters 32) according to odd and even rows respectively. A simple row-by-row readout scheme is as follows: Figure 2 As shown. Each column of pixels relies on two column buses to input image signals into the column parallel ADC. One column bus inputs the image signals output by the odd-numbered rows of pixels into the second group of analog-to-digital converters 32 circuits, and the other column bus inputs the image signals output by the even-numbered rows into the first group of analog-to-digital converters 31 circuits. Taking a 6-row 5-column pixel array as an example, the image signals output by the pixel rows Row[0], Row[2], and Row[4] are converted and quantized by the first group of analog-to-digital converters 31 circuits, and the image signals output by the pixel rows Row[1], Row[3], and Row[5] are converted and quantized by the second group of analog-to-digital converters 32 circuits.

[0085] The delay from the 0th row of pixels Row[0] column bus output to the first column readout circuit (ADC1) is t0, and the delay from the 1st row of pixels Row[1] column bus output to the second column readout circuit (ADC2) is t1. In large-array image sensors, due to the asymmetric routing of image signals of the 0th row of pixels and the 1st row of pixels, t1>t0 when the image sensor is working, which leads to the introduction of unequal thermal noise, flicker noise and other noises in the signal transmission process, resulting in obvious row stripes on the image screen.

[0086] In order to solve this problem, a row decoder 33 is also introduced in the embodiment of the present application. The row decoder 33 outputs a control signal, and the pixel array receives the control signal to find the corresponding pixel unit, and performs reset, exposure and readout processes according to the control signal. The image signal generated in the pixel unit circuit passes through the row exchange switch, and the row exchange switch processes the image signals of two rows of pixels read out at the same time and inputs them into two different column parallel ADC circuits for conversion and quantization.

[0087] In this way, the image signal can be selectively input into different column parallel ADCs through the row exchange switch, thereby effectively alleviating the row fixed pattern noise (row FPN).

[0088] Specifically, there are two control schemes.

[0089] The first control scheme, in an optional embodiment, the above 902 can be implemented by the following steps: outputting the image signals of the pixel units in all odd rows in the nth column to the first group of analog-to-digital converters; outputting the image signals of the pixel units in all even rows in the nth column to the second group of analog-to-digital converters.

[0090] In an optional embodiment, the above 902 can be implemented by the following steps: outputting the image signals of the pixel units in all odd rows in the nth column to the second group of analog-to-digital converters; outputting the image signals of the pixel units in all even rows in the nth column to the first group of analog-to-digital converters.

[0091] In an optional embodiment, the above 902 can also be implemented by the following steps: outputting the image signals of the pixel units of all odd rows in the n+1th column to the second group of analog-to-digital converters; outputting the image signals of the pixel units of all even rows in the n+1th column to the first group of analog-to-digital converters.

[0092] In an optional embodiment, the above 902 can also be implemented by the following steps: outputting the image signals of the pixel units of all odd rows in the n+1th column to the first group of analog-to-digital converters; outputting the image signals of the pixel units of all even rows in the n+1th column to the second group of analog-to-digital converters.

[0093] The first switch control scheme groups every two rows and inputs the image signals generated by the adjacent columns of pixels in the same row into different column parallel analog-to-digital conversion circuits, averaging the noise difference between rows in the group and reducing the row fixed pattern noise (row FPN) in the pixel array.

[0094] Taking row 0 and row 1 as an example, due to the existence of two column-parallel ADC circuits, the conventional means is generally that the image signal of the pixel of row 0 (Row[0]) is converted and quantized by the first group of analog-to-digital converters 31 of the column-parallel ADC circuit, and the image signal of the pixel of row 1 (Row[1]) is converted and quantized by the second group of analog-to-digital converters 32 of the column-parallel ADC circuit. The first switch control scheme provided in the embodiment of the present application performs row exchange between adjacent columns of pixels in the same row, and it can be selected whether the even columns or the odd columns are to be exchanged in the adjacent columns. For example, referring to Figure 6 As shown, the path of the output image signal of the even columns of the 0th and 1st rows of pixels remains unchanged, and the even columns of the 0th row ( Figure 6 The even columns (0, 2, 4) of the first row of pixels are still converted and quantized by the first group of analog-to-digital converters 31 of the column parallel ADC circuit. Figure 6 The 0, 2, and 4 columns (shown in FIG. 1 ) are still converted and quantized by the second group of analog-to-digital converters 32 of the column parallel ADC circuit. However, the paths of the image signal output by the odd-numbered columns of the 0th row and the 1st row are interchanged. That is, the odd-numbered columns ( Figure 6 The image signal output by the second group of analog-to-digital converters 32 of the column parallel ADC circuit is converted and quantized. The odd columns of the first row of pixels ( Figure 6 The image signals outputted by columns 1 and 3 as shown are converted and quantized by the first group of analog-to-digital converters 31 of the column-parallel ADC circuit.

[0095] The embodiment of the present application also provides a second switch control scheme. In an optional embodiment, the above 902 can also be implemented by the following steps: outputting the image signals of the pixel units in all odd columns in the mth row to the first group of analog-to-digital converters; outputting the image signals of the pixel units in all even columns in the mth row to the second group of analog-to-digital converters.

[0096] In an optional embodiment, the above 902 can also be implemented by the following steps: outputting the image signals of the pixel units in all odd columns in the mth row to the second group of analog-to-digital converters; outputting the image signals of the pixel units in all even columns in the mth row to the first group of analog-to-digital converters.

[0097] In an optional embodiment, the above 902 can also be implemented by the following steps: outputting the image signals of the pixel units of all odd columns in the m+1th row to the second group of analog-to-digital converters; outputting the image signals of the pixel units of all even columns in the m+1th row to the first group of analog-to-digital converters.

[0098] In an optional embodiment, the above 902 can also be implemented by the following steps: outputting the image signals of the pixel units of all odd columns in the m+1th row to the first group of analog-to-digital converters; outputting the image signals of the pixel units of all even columns in the m+1th row to the second group of analog-to-digital converters.

[0099] In an optional embodiment, the above 902 can also be implemented by the following steps: outputting the image signals of the pixel units of all odd columns in the m+2th row to the second group of analog-to-digital converters; outputting the image signals of the pixel units of all even columns in the m+2th row to the first group of analog-to-digital converters.

[0100] In an optional embodiment, the above 902 can also be implemented by the following steps: outputting the image signals of the pixel units of all odd columns in the m+2th row to the first group of analog-to-digital converters; outputting the image signals of the pixel units of all even columns in the m+2th row to the second group of analog-to-digital converters.

[0101] In an optional embodiment, the above 902 can also be implemented by the following steps: outputting the image signals of the pixel units of all odd columns in the m+3th row to the first group of analog-to-digital converters; outputting the image signals of the pixel units of all even columns in the m+3th row to the second group of analog-to-digital converters.

[0102] In an optional embodiment, the above 902 can also be implemented by the following steps: outputting the image signals of the pixel units of all odd columns in the m+3th row to the second group of analog-to-digital converters; outputting the image signals of the pixel units of all even columns in the m+3th row to the first group of analog-to-digital converters.

[0103] The second switch control scheme is as follows Figure 7 As shown in the figure, after the image signals of every two rows of pixels are read out, the switch control signal phase rotates 180 degrees, the high level becomes the low level, and the low level becomes the high level. Figure 8As shown, for the image signal output by the selected row, the first group of column parallel analog-to-digital converters 31 or the second group of column parallel analog-to-digital converters 32 read out the image signal at intervals. The image signal of the same column of two adjacent odd rows (e.g., Row[1] and Row[3]) is read out to different column parallel analog-to-digital converters, and the image signal of the same column of two adjacent even rows (e.g., Row[0] and Row[2]) is read out to different column analog-to-digital converters. Specifically, two adjacent rows are grouped together, for example, Row[0] and Row[1] are the first group, and Row[2] and Row[3] are the second group. In the first group, the even columns (corresponding to Row[0]) Figure 8 The data of the columns 0, 2, and 4 shown in FIG. 1 are converted and quantized by the first group of analog-to-digital converters 31 of the column parallel ADC circuit. The odd columns of Row[0] (corresponding to Figure 8 The data of the columns 1 and 3 shown in FIG. 1 are converted and quantized by the second group of analog-to-digital converters 32 of the column parallel ADC circuit; the even columns of Row[1] (corresponding to Figure 8 The data of columns 0, 2, and 4 shown in FIG. 1 are converted and quantized by the second group of analog-to-digital converters 32 of the column parallel ADC circuit. The odd columns of Row[1] (corresponding to Figure 8 The data of the columns 1 and 3 shown in FIG. 1 are converted and quantized by the first group of analog-to-digital converters 31 of the column parallel ADC circuit. In the second group, the control signal switches, and the even columns of Row[2] (corresponding to Figure 8 The data of columns 0, 2, and 4 shown in FIG. 1 are converted and quantized by the second group of analog-to-digital converters 32 of the column parallel ADC circuit. The odd columns of Row[2] (corresponding to Figure 8 The data of the columns 1 and 3 shown in FIG. 1 are converted and quantized by the first group of analog-to-digital converters 31 of the column parallel ADC circuit; the even columns of Row[3] (corresponding to Figure 8 The data of columns 0, 2, and 4 shown in FIG. 1 are converted and quantized by the first group of analog-to-digital converters 31 of the column parallel ADC circuit. The odd columns of Row[3] (corresponding to Figure 8 The data (columns 1 and 3) are converted and quantized by a second group of analog-to-digital converters 32 of a column-parallel ADC circuit.

[0104] According to another embodiment of the present application, a camera device is also provided, including the above-mentioned image sensor, which can realize all the functions of the above-mentioned image sensor, and the contents that have been described will not be repeated here.

[0105] The image sensor provided in the embodiment of the present application can also be used in smart phones, the Internet of Things, wearable devices, smart vehicle driving records, front and reverse images, 360° surround images, collision avoidance systems, etc., and can also be used in security monitoring fields or medical equipment.

[0106] According to another embodiment of the present application, a vehicle is also provided, comprising the above-mentioned camera device. All functions of the above-mentioned camera device can be realized, and the contents already described are not repeated here. The vehicle can be a fuel vehicle, a plug-in hybrid vehicle or a new energy vehicle, etc., and the present application does not make specific limitations on this.

[0107] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0108] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0109] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0110] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. An image sensor, characterized in that: including pixel circuit and logic circuit; The pixel circuit includes a pixel array, and the pixel array includes pixel units arranged in multiple rows and columns; The logic circuit comprises at least two groups of analog-to-digital converters, and the pixel units in the pixel array are connected to the at least two groups of the analog-to-digital converters; The pixel units in the same row but different columns of the pixel array are connected to at least two groups of analog-to-digital converters, and / or the pixel units in the same column but different rows of the pixel array are connected to at least two groups of analog-to-digital converters.

2. An image sensor according to claim 1, characterized in that: The logic circuit further comprises: At least two groups of row switching switches are arranged corresponding to at least two groups of analog-to-digital converters.

3. An image sensor according to claim 2, characterized in that: The logic circuit comprises: A first group of row switching switches, a second group of row switching switches, a first group of analog-to-digital converters, and a second group of analog-to-digital converters; Among them, the pixel array is electrically connected to the first group of analog-to-digital converters via the first group of row switching switches, and the pixel array is electrically connected to the second group of analog-to-digital converters via the second group of row switching switches. The first group of row switching switches is arranged on the first row side of the pixel array, and the second group of row switching switches is arranged on the last row side of the pixel array.

4. The image sensor according to claim 3, characterized in that: The pixel array includes M rows×N columns of pixel units, and each column of the pixel units is respectively connected to the first group of row switching switches and the second group of row switching switches through two column buses.

5. The image sensor according to claim 4, characterized in that: The first group of row switching switches includes 2N first switches, the second group of row switching switches includes 2N second switches, and each of the column buses corresponds to a first switch and a second switch.

6. The image sensor according to claim 5, characterized in that The pixel units in the odd-numbered rows of the nth column are all connected to the 2n-1th column bus, and are connected to the 2n-1th first switch through the 2n-1th column bus. The pixel units in the even-numbered rows of the nth column are all connected to the 2nth column bus, and are connected to the 2nth second switch through the 2nth column bus, 1≤n≤N.

7. The image sensor according to claim 5, characterized in that: The pixel units in the even rows of the nth column are all connected to the 2n-1th column bus, and are connected to the 2n-1th first switch through the 2n-1th column bus. The pixel units in the odd rows of the nth column are all connected to the 2nth column bus, and are connected to the 2nth second switch through the 2nth column bus, 1≤n≤N.

8. The image sensor according to claim 5, characterized in that: The nth second switch and the n+1th first switch are both controlled to be turned on or off by the first pulse signal, and the n+1th second switch and the nth first switch are both controlled to be turned on or off by the second pulse signal; wherein the first pulse signal and the second pulse signal have opposite phases.

9. The image sensor according to claim 8, characterized in that: The n+2th second switch and the n+3th first switch are both controlled to be turned on or off by the third pulse signal, and the n+3th second switch and the n+2th first switch are both controlled to be turned on or off by the fourth pulse signal; wherein, the third pulse signal and the fourth pulse signal have opposite phases, the first pulse signal and the fourth pulse signal have the same phase, and the second pulse signal and the third pulse signal have the same phase.

10. A method for converting an image signal, characterized in that: include: Determining image signals in at least two rows of pixel units to be converted according to the control signal; Outputting the image signals in at least two rows of pixel units to at least two groups of analog-to-digital converters at the same time; Converting the image signals in at least two rows of the pixel units by at least two groups of the analog-to-digital converters; Wherein, the image signals in the pixel units in the same row but different columns are respectively output to at least two groups of the analog-to-digital converters; and / or The image signals in the pixel units in the same column but different rows are respectively output to at least two groups of the analog-to-digital converters.

11. The method according to claim 10, characterized in that Outputting the image signals in at least two rows of pixel units to at least two groups of analog-to-digital converters at the same time comprises: The image signals in the pixel units in the same row but different columns are respectively output to at least two groups of analog-to-digital converters; and / or The image signals in the pixel units in the same column but different rows are respectively output to at least two groups of the analog-to-digital converters.

12. The method according to claim 11, characterized in that The image signals in the pixel units in the same column but different rows are respectively output to at least two groups of analog-to-digital converters, including: Outputting the image signals of the pixel units of all odd-numbered rows in the nth column to a first group of analog-to-digital converters; The image signals of the pixel units in all even-numbered rows in the nth column are output to a second group of analog-to-digital converters.

13. The method according to claim 12, characterized in that The image signals in the pixel units in the same column but different rows are respectively output to at least two groups of analog-to-digital converters, including: Outputting the image signals of the pixel units of all odd-numbered rows in the n+1th column to the second group of analog-to-digital converters; The image signals of the pixel units in all even-numbered rows in the (n+1)th column are output to the first group of analog-to-digital converters.

14. The method according to claim 11, characterized in that The image signals in the pixel units in the same column but different rows are respectively output to at least two groups of analog-to-digital converters, including: Outputting the image signals of the pixel units of all even-numbered rows in the nth column to a first group of analog-to-digital converters; The image signals of the pixel units in all odd-numbered rows in the nth column are output to a second group of analog-to-digital converters.

15. The method according to claim 14, characterized in that The image signals in the pixel units in the same column but different rows are respectively output to at least two groups of analog-to-digital converters, including: Outputting the image signals of the pixel units of all even-numbered rows in the n+1th column to the second group of analog-to-digital converters; The image signals of the pixel units in all odd rows in the (n+1)th column are output to the first group of analog-to-digital converters.

16. The method according to claim 11, characterized in that The image signals in the pixel units in the same row but different columns are respectively output to at least two groups of analog-to-digital converters, including: Outputting the image signals of the pixel units of all odd columns in the mth row to a first group of analog-to-digital converters; The image signals of the pixel units in all even-numbered columns in the m-th row are output to a second group of analog-to-digital converters.

17. The method according to claim 16, characterized in that The image signals in the pixel units in the same row but different columns are respectively output to at least two groups of analog-to-digital converters, including: Outputting the image signals of the pixel units of all odd columns in the m+1th row to the second group of analog-to-digital converters; The image signals of the pixel units in all even columns in the (m+1)th row are output to the first group of analog-to-digital converters.

18. The method according to claim 17, characterized in that The image signals in the pixel units in the same row but different columns are respectively output to at least two groups of analog-to-digital converters, including: Outputting the image signals of the pixel units of all odd columns in the m+2th row to the second group of analog-to-digital converters; The image signals of the pixel units in all even columns in the (m+2)th row are output to the first group of analog-to-digital converters.

19. The method according to claim 18, characterized in that The image signals in the pixel units in the same row but different columns are respectively output to at least two groups of analog-to-digital converters, including: Outputting the image signals of the pixel units of all odd columns in the m+3th row to the first group of analog-to-digital converters; The image signals of the pixel units in all even columns in the (m+3)th row are output to the second group of analog-to-digital converters.

20. The method according to claim 11, characterized in that The image signals in the pixel units in the same row but different columns are respectively output to at least two groups of analog-to-digital converters, including: Outputting the image signals of the pixel units of all odd columns in the mth row to a second group of analog-to-digital converters; The image signals of the pixel units in all even-numbered columns in the m-th row are output to a first group of analog-to-digital converters.

21. The method according to claim 20, characterized in that The image signals in the pixel units in the same row but different columns are respectively output to at least two groups of analog-to-digital converters, including: Outputting the image signals of the pixel units of all odd columns in the m+1th row to the first group of analog-to-digital converters; The image signals of the pixel units in all even columns in the (m+1)th row are output to the second group of analog-to-digital converters.

22. The method according to claim 21, characterized in that The image signals in the pixel units in the same row but different columns are respectively output to at least two groups of analog-to-digital converters, including: Outputting the image signals of the pixel units of all odd columns in the m+2th row to the first group of analog-to-digital converters; The image signals of the pixel units in all even columns in the (m+2)th row are output to the second group of analog-to-digital converters.

23. The method according to claim 22, characterized in that The image signals in the pixel units in the same row but different columns are respectively output to at least two groups of analog-to-digital converters, including: Outputting the image signals of the pixel units of all odd columns in the m+3th row to the second group of analog-to-digital converters; The image signals of the pixel units in all even columns in the (m+3)th row are output to the first group of analog-to-digital converters.

24. A camera device, characterized in that: The image sensor comprises the image sensor according to any one of claims 1 to 9.

25. A vehicle, characterized in that: Includes the camera device described in claim 24.

Images