Memory device and method of making the same, electronic device

Abstract

Embodiments of the present application provide a memory device, a manufacturing method thereof and an electronic device. The manufacturing method of the memory device comprises: providing a substrate having a storage area and a stepped area; then, alternately forming a first insulating layer and a sacrificial layer in sequence, an etching rate of a sacrificial layer located away from the substrate among two adjacent sacrificial layers is greater than an etching rate of a sacrificial layer located close to the substrate among the two adjacent sacrificial layers, and each sacrificial layer comprises a first sacrificial part; then, making a plurality of first sacrificial parts form a step, and forming a first empty slot between two adjacent first insulating layers; and forming a second insulating layer in the first empty slot; then, removing all the sacrificial layers to form a plurality of second empty slots; then, forming a plurality of conductive layers corresponding to the plurality of second empty slots, making each conductive layer fill a corresponding second empty slot, and a part of the plurality of conductive layers corresponding to the stepped area forms a step. Embodiments of the present application can manufacture a stepped structure through a simpler process, and the process difficulty and manufacturing cost are low.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a storage device and its manufacturing method, and an electronic device. Background Technology

[0002] Memory is the main medium for storing data in computers. With the development and progress of storage technology, storage devices are constantly moving towards miniaturization, high device density, and high integration. At the same time, they also face problems and challenges from manufacturing and other aspects. Summary of the Invention

[0003] This application proposes a storage device and its manufacturing method, as well as an electronic device. By using the manufacturing method of the storage device provided in the embodiments of this application, a stepped structure can be manufactured through a simpler process, reducing the process difficulty and manufacturing cost.

[0004] In a first aspect, embodiments of this application provide a method for manufacturing a storage device, comprising:

[0005] A substrate is provided, the substrate having a storage region and a stepped region located on at least one side of the storage region;

[0006] A first insulating layer and a sacrificial layer are alternately formed on one side of the substrate. In two adjacent sacrificial layers, the etching rate of the sacrificial layer located away from the substrate is greater than that of the sacrificial layer located closer to the substrate. Each sacrificial layer includes a first sacrificial portion corresponding to the step region.

[0007] Multiple first sacrificial portions are etched along a first direction to form a step in the multiple first sacrificial portions, and a first trench is formed between two adjacent first insulating layers. The first direction is parallel to the substrate.

[0008] A second insulating layer is formed within the first empty slot;

[0009] Remove all sacrificial layers to form a plurality of second voids arranged sequentially at intervals along a direction perpendicular to the substrate;

[0010] Multiple conductive layers are formed, each corresponding to a multiple second empty slot, and each conductive layer fills the corresponding second empty slot. The portions of the multiple conductive layers corresponding to the stepped area form a step.

[0011] In some optional embodiments of this application, a first insulating layer and a sacrificial layer are sequentially and alternately formed on one side of the substrate, including:

[0012] A first oxide layer and a silicon-germanium compound layer are alternately formed on one side of the substrate. In two adjacent silicon-germanium compound layers, the silicon-germanium compound layer located away from the substrate has a higher germanium content than the silicon-germanium compound layer located closer to the substrate.

[0013] The process involves patterning to form a first partition trench and a second partition trench. Both the first partition trench and the second partition trench penetrate the first oxide layer and the silicon-germanium compound layer and expose the substrate at the bottom. The first partition trench and the second partition trench are arranged alternately along a first direction to divide the silicon-germanium compound layer into a first sacrificial portion corresponding to the stepped region, a second sacrificial portion corresponding to the storage region, and a connecting portion for connecting the first sacrificial portion and the second sacrificial portion. The connecting portion is located between the first partition trench and the second partition trench. The first sacrificial portion, the connecting portion, and the second sacrificial portion form a sacrificial layer. The first oxide layer after patterning forms a first insulating layer.

[0014] In some optional embodiments of this application, after forming the first insulating layer and the sacrificial layer and before etching the plurality of first sacrificial portions, the method for fabricating the memory device further includes:

[0015] A third insulating layer is formed on one side of the substrate, and the third insulating layer fills the first and second partition grooves;

[0016] The first sacrificial portion and the first insulating layer are etched to form an etching trench extending in a direction perpendicular to the substrate, and the etching trench is located at one end of the first sacrificial portion along a first direction, with a portion of the sidewall of the etching trench exposing all the first sacrificial portion and another portion of the sidewall exposing the third insulating layer.

[0017] In some optional embodiments of this application, etching is performed on a plurality of first sacrificial portions along a first direction, including:

[0018] Etching is performed on all exposed first sacrificial portions in the etching groove along the first direction to form a step between multiple first sacrificial portions and to form a first empty groove between two adjacent first insulating layers.

[0019] A second insulating layer is formed within the first cavity, comprising:

[0020] A second oxide layer is formed on one side of the substrate, such that the second oxide layer covers the end face of the first sacrificial portion along the first direction and fills the first empty groove and the etching groove, and the second oxide layer serves as a second insulating layer.

[0021] In some optional embodiments of this application, after forming the second insulating layer and before removing all sacrificial layers, the method for fabricating the storage device further includes:

[0022] Remove the third insulating layer filling the first and second partition grooves so that the sidewalls of the first and second partition grooves are exposed to expose the multiple sacrificial layers after etching the multiple first sacrificial portions along the first direction.

[0023] Remove all sacrifice layers, including:

[0024] All sacrificial layers are wet-etched to remove them and form multiple second empty slots.

[0025] In some optional embodiments of this application, the method of fabricating the storage device further includes, before removing all sacrificial layers:

[0026] A support layer is formed on one side of the substrate, such that the support layer is in contact with at least a portion of the sidewall of the first insulating layer.

[0027] In some optional embodiments of this application, a plurality of conductive layers are formed, each corresponding to one of the plurality of second slots, including:

[0028] A metal material is deposited on one side of the substrate, and the metal material fills a plurality of second empty trenches, first partition trenches and second partition trenches;

[0029] The metal material filling the first and second partition grooves is removed, and the remaining metal material forms multiple conductive layers corresponding to multiple second empty grooves. Multiple conductive layers are exposed on the sidewalls of the first and second partition grooves.

[0030] In some optional embodiments of this application, after forming multiple conductive layers, the method for fabricating the storage device further includes:

[0031] A fourth insulating layer is formed on one side of the substrate. The fourth insulating layer fills the first and second partition grooves. The fourth insulating layer, the first insulating layer, and the second insulating layer form an insulating structure for the memory device.

[0032] Multiple through holes are formed to penetrate the insulating structure, and the multiple through holes are arranged sequentially at intervals along the first direction. The multiple through holes correspond one-to-one with the stepped ends of multiple conductive layers, and the bottom of each through hole exposes the stepped end of the corresponding conductive layer.

[0033] Metal material is filled into multiple through holes so that the metal material in each through hole is in contact with the stepped end of the corresponding conductive layer. The metal material filled into the multiple through holes forms multiple contact structures that are connected one-to-one with the stepped ends of the multiple conductive layers.

[0034] Secondly, embodiments of this application provide a storage device manufactured using the aforementioned method for manufacturing storage devices;

[0035] Storage devices include:

[0036] The substrate has a storage region and a stepped region located on at least one side of the storage region;

[0037] The storage structure is disposed on one side of the substrate, and its orthographic projection on the substrate is located in the storage area. The storage structure includes multiple storage array layers stacked sequentially along a direction perpendicular to the substrate, and each storage array layer includes multiple storage cells arranged in an array.

[0038] A stepped structure is disposed on one side of the substrate, and its orthogonal projection on the substrate is located in the stepped region. The stepped structure includes multiple stepped portions, and each conductive layer corresponding to the stepped region forms a stepped portion. Multiple stepped portions form a step.

[0039] Multiple stepped sections correspond one-to-one with multiple storage array layers, and each stepped section is connected to at least one column of storage cells in the corresponding storage array layer.

[0040] Thirdly, embodiments of this application provide an electronic device including the aforementioned storage device.

[0041] The beneficial technical effects of the technical solutions provided in this application include:

[0042] In this embodiment, a first insulating layer and a sacrificial layer are alternately formed on one side of a substrate. Each sacrificial layer includes a first sacrificial portion corresponding to a stepped region. Then, the formed first sacrificial portions are etched along a first direction parallel to the substrate. Since the etching rate of the sacrificial layer located away from the substrate is greater than that of the sacrificial layer located close to the substrate in two adjacent sacrificial layers, the size of the multiple first sacrificial portions along the first direction will decrease, and the size of the multiple first sacrificial portions along the first direction will decrease along the direction away from the substrate, thereby forming a stepped structure with the multiple first sacrificial portions. The etched portion of the first sacrificial portion forms a first slot, and each first slot is located between two adjacent first insulating layers. The position and shape of each first slot are the same as the etched portion of the corresponding first sacrificial portion.

[0043] Then a second insulating layer is formed in the first cavity. The second insulating layer covers the end face of the remaining first sacrificial part along the first direction and fills the first cavity. At the position where the second insulating layer contacts the end face of the multiple first sacrificial parts, a stepped shape is formed that complements the step formed by the multiple first sacrificial parts.

[0044] Then, all sacrificial layers are removed, and a second slot is formed at the position corresponding to each removed sacrificial layer. Multiple second slots are arranged sequentially at intervals along the direction perpendicular to the substrate. Then, multiple conductive layers are formed, each corresponding to one of the multiple second slots. Each conductive layer fills the corresponding second slot. The portion of the conductive layer corresponding to the stepped region is in contact with the second insulating layer. Since the second insulating layer has a stepped shape, the portions of the multiple conductive layers corresponding to the stepped region will form a step.

[0045] In this embodiment, among two adjacent sacrificial layers, the etching rate of the sacrificial layer located away from the substrate is greater than that of the sacrificial layer located closer to the substrate. That is, along the direction away from the substrate, the etching rate of each sacrificial layer gradually increases. Thus, when etching multiple first sacrificial portions along the first direction, within the same etching time, the etching amount of each sacrificial layer gradually increases along the direction away from the substrate, thereby enabling multiple first sacrificial portions to form a step. After forming the step, all sacrificial layers are removed, and multiple conductive layers are formed accordingly. The conductive layers replace the sacrificial layers, thereby enabling the portions of the multiple conductive layers corresponding to the step region to form a step. Using the storage device fabrication method provided in this embodiment, a stepped structure can be fabricated through a simpler process, reducing the process difficulty and fabrication cost.

[0046] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0047] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0048] Figure 1 A schematic flowchart illustrating a method for manufacturing a storage device according to an embodiment of this application;

[0049] Figures 2 to 20 A schematic diagram of the structure at different stages in a method for manufacturing a storage device according to an embodiment of this application;

[0050] Figure 21 This is a schematic diagram of the structure of a storage device provided in an embodiment of this application.

[0051] Figure label:

[0052] 100 - Memory device; 10 - Substrate; 20 - First insulating layer; 21 - First oxide layer; 22 - Support layer; 30 - Sacrificial layer; 31 - First sacrificial portion; 32 - Second empty slot; 33 - Silicon-germanium compound layer; 34 - Second sacrificial portion; 35 - Connector; 40 - Second insulating layer; 41 - First empty slot; 42 - Etching trench; 50 - Conductive layer; 51 - Step; 52 - Step end; 53 - Metal structure; 61 - First partition trench; 62 - Second partition trench; 63 - Third insulating layer; 64 - Fourth insulating layer; 70 - Contact structure; 80 - Memory structure; 81 - Memory array layer; 82 - Memory cell; 83 - Channel; 84 - Bit line; 90 - Step structure; 91 - Step portion; 110 - Insulating structure. Detailed Implementation

[0053] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0054] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this application means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude implementations of other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by this art. It should be understood that when we say an element is “connected” or “coupled” to another element, the element may be directly connected or coupled to the other element, or it may mean that the element and the other element are connected through an intermediate element. Furthermore, “connected” or “coupled” as used herein may include wireless connection or wireless coupling. The term “and / or” as used herein means at least one of the items defined by the term; for example, “A and / or B” may be implemented as “A,” or as “B,” or as “A and B.”

[0055] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0056] The relevant technologies are explained below:

[0057] With the development of advanced technologies such as the Internet of Things and autonomous driving, the market demand for memory devices is increasing daily. Advanced technologies require advanced chips to implement them, which leads to the continuous miniaturization of integrated circuits. Faced with this situation, the development of memory devices also faces challenges. At this juncture, 3D (3-Dimensional) memory devices have emerged. 3D memory devices can significantly increase storage density while reducing area, and are expected to solve the process challenges brought about by size miniaturization.

[0058] 3D DRAM (Dynamic Random Access Memory) devices require a staircase structure to connect each layer of memory cells to external devices.

[0059] Currently, the main method for fabricating staircase structures is to form each step of the staircase structure through multiple photolithography steps. This manufacturing process is complex and difficult.

[0060] The storage devices, manufacturing methods, and electronic devices provided in this application are intended to solve the above-mentioned technical problems of the prior art.

[0061] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0062] This application provides a method for manufacturing a storage device, the flowchart of which is shown below. Figure 1 As shown, it includes:

[0063] S101. A substrate 10 is provided, the substrate 10 having a storage region and a stepped region located on at least one side of the storage region; optionally, the substrate 10 is a silicon substrate.

[0064] S102. A first insulating layer 20 and a sacrificial layer 30 are alternately formed on one side of the substrate 10. Among two adjacent sacrificial layers 30, the etching rate of the sacrificial layer 30 located on the side away from the substrate 10 is greater than the etching rate of the sacrificial layer 30 located on the side closer to the substrate 10. Each sacrificial layer 30 includes a first sacrificial portion 31 corresponding to the stepped region.

[0065] S103. Etch a plurality of first sacrificial portions 31 along a first direction to form a step between the plurality of first sacrificial portions 31, and form a first trench 41 between two adjacent first insulating layers 20, with the first direction parallel to the substrate 10.

[0066] S104. A second insulating layer 40 is formed in the first empty slot 41.

[0067] S105. Remove all sacrificial layers 30 to form a plurality of second voids 32 arranged sequentially at intervals along a direction perpendicular to the substrate 10.

[0068] S106. Form a plurality of conductive layers 50 corresponding one-to-one with the plurality of second empty slots 32, such that each conductive layer 50 fills the corresponding second empty slot 32, and the portion of the plurality of conductive layers 50 corresponding to the stepped area forms a step 51.

[0069] In this embodiment, the storage device can be manufactured using the storage device manufacturing method of this embodiment.

[0070] In this embodiment, the substrate 10 provides support for the first insulating layer 20, the sacrificial layer 30, the second insulating layer 40, and the conductive layer 50.

[0071] In this embodiment, a first insulating layer 20 and a sacrificial layer 30 are alternately formed on one side of a substrate 10. Each sacrificial layer 30 includes a first sacrificial portion 31 corresponding to a stepped region. Then, the formed first sacrificial portions 31 are etched along a first direction parallel to the substrate 10. Since the etching rate of the sacrificial layer 30 located away from the substrate 10 is greater than that of the sacrificial layer 30 located close to the substrate 10, the size of the multiple first sacrificial portions 31 along the first direction will decrease, and the size of the multiple first sacrificial portions 31 along the first direction will decrease along the direction away from the substrate 10, thereby forming a stepped structure with the multiple first sacrificial portions 31. The etched portion of the first sacrificial portion 31 forms a first empty groove 41. Each first empty groove 41 is located between two adjacent first insulating layers 20, and each first empty groove 41 has the same position and shape as the etched portion of the corresponding first sacrificial portion 31.

[0072] Then a second insulating layer 40 is formed in the first slot 41. The second insulating layer 40 covers the end face of the remaining first sacrificial part 31 along the first direction and fills the first slot 41. At the position where the second insulating layer 40 contacts the end face of the plurality of first sacrificial parts 31, a stepped shape is formed that complements the step formed by the plurality of first sacrificial parts 31.

[0073] Then all sacrificial layers 30 are removed, and a second slot 32 is formed at the position corresponding to each of the removed sacrificial layers 30. The multiple second slots 32 are arranged sequentially at intervals along the direction perpendicular to the substrate 10. Then multiple conductive layers 50 are formed corresponding to the multiple second slots 32. Each conductive layer 50 fills the corresponding second slot 32. The part of the conductive layer 50 corresponding to the stepped region is in contact with the second insulating layer 40. Since the second insulating layer 40 has a stepped shape that complements the stepped region, the parts of the multiple conductive layers 50 corresponding to the stepped region will form a step 51.

[0074] In this embodiment, among two adjacent sacrificial layers 30, the etching rate of the sacrificial layer 30 located away from the substrate 10 is greater than the etching rate of the sacrificial layer 30 located closer to the substrate 10. That is, along the direction away from the substrate 10, the etching rate of each sacrificial layer 30 gradually increases. Thus, when etching multiple first sacrificial portions 31 along the first direction, within the same etching time, the etching amount of each sacrificial layer 30 gradually increases along the direction away from the substrate 10, thereby enabling the multiple first sacrificial portions 31 to form a step. After forming the step, all sacrificial layers 30 are removed, and multiple conductive layers 50 are formed accordingly. The conductive layers 50 replace the sacrificial layers 30, thereby enabling the portions of the multiple conductive layers 50 corresponding to the step region to form a step 51. Using the fabrication method of the memory device provided in this embodiment, a stepped structure can be fabricated through a simpler process, reducing the process difficulty and fabrication cost.

[0075] In some optional embodiments of this application, such as Figures 2 to 4 As shown, a first insulating layer 20 and a sacrificial layer 30 are alternately formed sequentially on one side of the substrate 10, including:

[0076] like Figure 2 As shown, a first oxide layer 21 and a silicon-germanium compound layer 33 are alternately formed sequentially on one side of the substrate 10. In two adjacent silicon-germanium compound layers 33, the germanium content in the material of the silicon-germanium compound layer 33 located away from the substrate 10 is greater than the germanium content in the material of the silicon-germanium compound layer 33 located closer to the substrate 10. That is, along the direction away from the substrate 10, the germanium content in the material of the multiple silicon-germanium compound layers 33 increases sequentially (e.g., ...). Figure 2 The compositions of the three silicon-germanium compound layers 33 are as follows: the composition of the first silicon-germanium compound layer 33 closest to the substrate 10 is Si. 0.9 Ge 0.1 The middle silicon-germanium compound layer 33 is composed of Si. 0.7 Ge 0.3 The last silicon-germanium compound layer 33, furthest from the substrate 10, is composed of Si. 0.5 Ge 0.5 Optionally, the silicon-germanium compound layer 33 is made of polycrystalline silicon-germanium (poly-SiGe). Optionally, the orthogonal projections of the first oxide layer 21 and the silicon-germanium compound layer 33 onto the substrate 10 both cover the storage region and the step region. Optionally, the first oxide layer 21 can be made of an oxide that can provide insulation (such as silicon oxide).

[0077] In this embodiment, the principle that different germanium contents in the silicon-germanium compound layer 33 lead to different etching rates is used to manufacture a staircase structure. Compared with the current methods and technologies for manufacturing staircase structures step by step by photolithography, this can reduce the process difficulty and production cost.

[0078] Next, as Figure 3 and Figure 4 As shown ( Figure 4 for Figure 3The top view of the silicon germanium compound layer 33 is patterned to form a first partition groove 61 and a second partition groove 62. Both the first partition groove 61 and the second partition groove 62 penetrate the first oxide layer 21 and the silicon germanium compound layer 33 and expose the substrate 10 at the bottom. The first partition groove 61 and the second partition groove 62 are arranged sequentially at intervals along the first direction, dividing the silicon germanium compound layer 33 into a first sacrificial portion 31 corresponding to the stepped area, a second sacrificial portion 34 corresponding to the storage area, and a connecting portion 35 for connecting the first sacrificial portion 31 and the second sacrificial portion 34. The first sacrificial portion 31 extends along the first direction, and the connecting portion 35 is located between the first partition groove 61 and the second partition groove 62. The first sacrificial portion 31, the connecting portion 35 and the second sacrificial portion 34 form a sacrificial layer 30. The first oxide layer 21 after patterning forms a first insulating layer 20.

[0079] Optionally, the first partition trench 61 and the second partition trench 62 are formed by etching the first oxide layer 21 and the silicon-germanium compound layer 33 until the substrate 10 is exposed at the bottom. Optionally, the first partition trench 61 and the second partition trench 62 can be formed using a dry etching process.

[0080] In this embodiment, the substrate 10 further has a connection region located between the storage region and the step region, and the connection portion 35 corresponds to the connection region.

[0081] In this embodiment, the first partition trench 61 and the second partition trench 62 divide the silicon-germanium compound layer 33 into a first sacrificial portion 31, a second sacrificial portion 34, and a connecting portion 35. The first sacrificial portion 31, the connecting portion 35, and the second sacrificial portion 34 are arranged sequentially along a second direction parallel to the substrate 10. The first partition trench 61, the connecting portion 35, and the second partition trench 62 are arranged sequentially along a first direction. The first partition trench 61 and the second partition trench 62 can separate the first sacrificial portion 31 and the second sacrificial portion 34, so that the first sacrificial portion 31 and the second sacrificial portion 34 are connected only through the connecting portion 35. In this way, on the one hand, the removal efficiency when removing all sacrificial layers 30 is improved, and on the other hand, after the conductive layer 50 is formed, the portion of the conductive layer 50 corresponding to the memory region and the portion corresponding to the step region can be isolated, thereby isolating the memory structure located in the memory region and the step structure located in the step region, so that the memory structure is connected to the step structure (e.g., a bit line) only through a connecting line (e.g., a bit line).

[0082] In some optional embodiments of this application, such as Figure 5 As shown, after forming the first insulating layer 20 and the sacrificial layer 30, and before etching the plurality of first sacrificial portions 31, the method for fabricating the memory device further includes:

[0083] A support layer 22 is formed on one side of the substrate 10, such that the support layer 22 is in contact with at least a portion of the sidewall of the first insulating layer 20.

[0084] Optionally, the material of the support layer 22 includes, but is not limited to, polysilicon. Specifically, polysilicon layers can be formed at both ends of the substrate 10 along the first direction by a deposition process. The polysilicon layers are located on the side of the substrate 10 where the first insulating layer 20 and the sacrificial layer 30 are formed. The polysilicon layers are in contact with the sidewalls of the first insulating layer 20 and the sacrificial layer 30, respectively, and the polysilicon layers serve as the support layer 22.

[0085] In this embodiment, the support layer 22 is used to support the spaced-apart multilayer first insulating layers 20 after all sacrificial layers 30 have been removed.

[0086] It should be noted that in this embodiment, the support layer 22 is fabricated before the third insulating layer 63 is formed. Of course, the support layer 22 can also be fabricated after the third insulating layer 63 is formed, as long as it can be ensured that the support layer 22 is fabricated before all sacrificial layers 30 are removed.

[0087] In some optional embodiments of this application, such as Figure 5 As shown, after forming the first insulating layer 20 and the sacrificial layer 30, and before etching the plurality of first sacrificial portions 31, the method for fabricating the memory device further includes:

[0088] A third insulating layer 63 is formed on one side of the substrate 10, and the third insulating layer 63 fills the first partition groove 61 and the second partition groove 62.

[0089] Optionally, forming the third insulating layer 63 includes: forming a third oxide layer on one side of the substrate 10, the third oxide layer filling the first separating trench 61 and the second separating trench 62; and planarizing the third oxide layer so that the surface of the third oxide layer away from the substrate 10 is flush with the surface of the last first insulating layer 20 away from the substrate 10. Optionally, planarization can be performed by a chemical mechanical polishing (CMP) process. Optionally, the material of the third oxide layer can be an oxide that can perform insulating functions (such as silicon oxide), and the materials of the third oxide layer and the first oxide layer 21 can be the same or different, depending on actual needs.

[0090] Next, as Figure 6 and Figure 7 As shown ( Figure 7 for Figure 6(Top view) The first sacrificial portion 31 and the first insulating layer 20 are etched to form an etching trench 42 extending in a direction perpendicular to the substrate 10, and the etching trench 42 is located at one end of the first sacrificial portion 31 along the first direction, and a portion of the sidewall of the etching trench 42 exposes all the first sacrificial portions 31, so as to facilitate subsequent etching of all the exposed first sacrificial portions 31 along the first direction, and the other portion of the sidewall exposes the third insulating layer 63.

[0091] In the embodiments of this application, such as Figures 5 to 7 As shown, support layers 22 are formed at both ends of the substrate 10 along the first direction, and the two support layers 22 can stably support the first insulating layer 20. At this time, it is necessary to form an etching trench 42 extending perpendicular to the substrate 10 to expose all the first sacrificial portions 31, thereby facilitating subsequent etching of the first sacrificial portions 31 along the first direction. A portion of the sidewall of the etching trench 42 exposes the support layer 22.

[0092] Optionally, such as Figure 6 and Figure 7 As shown in this embodiment, the etching groove 42 is located at the right end of the first sacrificial portion 31 along the first direction. In other alternative embodiments, the etching groove 42 may also be formed at the left end of the first sacrificial portion 31 along the first direction.

[0093] In some optional embodiments of this application, such as Figure 8 and Figure 9 As shown ( Figure 9 for Figure 8 (The front view), etching is performed on a plurality of first sacrificial portions 31 along a first direction, including:

[0094] Etching is performed on all exposed first sacrificial portions 31 in the first direction within the etching groove 42, so that the multiple first sacrificial portions 31 form a step and a first empty groove 41 is formed between two adjacent first insulating layers 20.

[0095] Optionally, a wet etching process is used to etch all the first sacrificial parts 31 exposed in the etching tank 42 along the first direction.

[0096] In this embodiment, along the direction away from the substrate 10, the etching rate of each first sacrificial portion 31 gradually increases, and at the same time, each first sacrificial portion 31 is etched. Within the same etching time, the etching amount of multiple first sacrificial portions 31 along the direction away from the substrate 10 can gradually increase, thereby forming a step between multiple first sacrificial portions 31. The portion of the first sacrificial portion 31 that is etched away corresponds to the formation of a first empty groove 41.

[0097] In this embodiment of the application, the length difference between two adjacent first sacrificial portions 31 along the first direction after etching is the product of the etching rate difference between the two adjacent first sacrificial portions 31 and the etching time.

[0098] In this embodiment, a staircase structure is fabricated by utilizing the principle that different germanium contents in the materials of each silicon-germanium compound layer 33 lead to different etching rates (the higher the germanium content, the faster the etching rate).

[0099] The embodiments of this application can simultaneously etch multiple first sacrificial portions 31 along a first direction, thereby improving etching efficiency and reducing process difficulty and production costs.

[0100] In this embodiment, a portion of the sidewall of the etching tank 42 exposes the third insulating layer 63. When the first sacrificial portion 31 is etched in the etching tank 42, the third insulating layer 63 can prevent the etchant from etching the second sacrificial portion 34.

[0101] In some optional embodiments of this application, such as Figure 10 and Figure 11 As shown ( Figure 11 for Figure 10 (Front view), a second insulating layer 40 is formed within the first slot 41, including:

[0102] A second oxide layer is formed on one side of the substrate 10, such that the second oxide layer covers the end face of the first sacrificial portion 31 along the first direction and fills the first void 41 and the etching trench 42; the second oxide layer is planarized so that the surface of the second oxide layer away from the substrate 10 is flush with the surface of the last first insulating layer 20 away from the substrate 10. The planarized second oxide layer serves as the second insulating layer 40. This allows the second insulating layer 40 to have a stepped shape that complements the steps formed by the plurality of first sacrificial portions 31, so that the portions of the plurality of conductive layers 50 corresponding to the stepped regions will subsequently form steps 51.

[0103] Alternatively, planarization can be achieved through a chemical mechanical polishing (CMP) process.

[0104] Optionally, the material of the second oxide layer can be an oxide that can play an insulating role (such as silicon oxide). The materials of the second oxide layer and the first oxide layer 21 can be the same or different, and can be selected according to actual needs.

[0105] In some optional embodiments of this application, such as Figure 12 and Figure 13 As shown ( Figure 13 for Figure 12 (Top view), after the formation of the second insulating layer 40 and before the removal of all sacrificial layers 30, the method for manufacturing the storage device further includes:

[0106] The third insulating layer 63 filled in the first partition groove 61 and the second partition groove 62 is removed so that the sidewalls of the first partition groove 61 and the sidewalls of the second partition groove 62 expose the multiple sacrificial layers 30 after etching the multiple first sacrificial portions 31 along the first direction. This facilitates the subsequent removal of the sacrificial layers 30 and improves the removal efficiency.

[0107] Optionally, the third insulating layer 63 filled in the first partition groove 61 and the second partition groove 62 can be removed by an etching process.

[0108] In some optional embodiments of this application, such as Figure 14 and Figure 15 As shown ( Figure 15 for Figure 14 (Main view), remove all sacrifice layers 30, including:

[0109] All sacrificial layers 30 are wet-etched to remove them and form multiple second empty trenches 32. This removes all silicon-germanium compound layers corresponding to the memory region, interconnect region, and step region, facilitating the subsequent formation of the conductive layer 50.

[0110] In some optional embodiments of this application, such as Figure 16 and Figure 17 As shown, a plurality of conductive layers 50 are formed, each corresponding to one of the plurality of second empty slots 32, including:

[0111] like Figure 16 As shown, a metal structure 53 is formed by depositing metal material on one side of the substrate 10. The metal structure 53 fills a plurality of second empty trenches 32, first partition trenches 61, and second partition trenches 62, thereby replacing the sacrificial layer 30 etched along the first direction with the metal material. Optionally, the metal material includes, but is not limited to, tungsten.

[0112] Next, as Figure 17 As shown, the metal material filling the first partition trench 61 and the second partition trench 62 is removed, and the remaining metal material forms a plurality of conductive layers 50 corresponding one-to-one with the plurality of second empty trenches 32. The sidewalls of the first partition trench 61 and the sidewalls of the second partition trench 62 expose the plurality of conductive layers 50. Optionally, the first partition trench 61 and the second partition trench 62 are defined by photolithography, and the metal material filling the first partition trench 61 and the second partition trench 62 is removed by etching (e.g., dry etching).

[0113] In some optional embodiments of this application, such as Figure 18 As shown, after forming multiple conductive layers 50, the fabrication method of the memory device further includes:

[0114] A fourth insulating layer 64 is formed on one side of the substrate 10, filling the first partition trench 61 and the second partition trench 62. The fourth insulating layer 64 is planarized so that the surface of the fourth insulating layer 64 away from the substrate 10 is flush with the surface of the last first insulating layer 20 away from the substrate 10. The planarized fourth insulating layer 64, the first insulating layer 20, and the second insulating layer 40 form the insulating structure 110 of the memory device 100. The fourth insulating layer 64 can isolate the storage structure and the stepped structure of the formed memory device.

[0115] Alternatively, planarization can be achieved through a chemical mechanical polishing (CMP) process.

[0116] Optionally, the material of the fourth insulating layer 64 can be an oxide (such as silicon oxide) that can play an insulating role. The material of the fourth insulating layer 64 and the first oxide layer 21 can be the same or different, and can be selected according to actual needs.

[0117] In some optional embodiments of this application, such as Figure 19 and Figure 20 As shown ( Figure 20 for Figure 19 (Partial structural schematic diagram), after forming the fourth insulating layer 64, the fabrication method of the storage device further includes:

[0118] Multiple through holes are formed through the insulating structure 110, and the multiple through holes are arranged sequentially at intervals along the first direction. The multiple through holes correspond one-to-one with the stepped ends 52 of the multiple conductive layers 50, and the bottom of each through hole exposes the stepped end 52 of the corresponding conductive layer 50.

[0119] Metal material is filled into multiple through holes so that the metal material in each through hole is in contact with the stepped end 52 of the corresponding conductive layer 50. The metal material filled into the multiple through holes forms multiple contact structures 70 that are connected one-to-one with the stepped end 52 of the multiple conductive layers 50.

[0120] In this embodiment, each conductive layer 50 forms a stepped portion 91 corresponding to the stepped area, and multiple stepped portions 91 form a step 51. The portion of each stepped portion 91 used to form the first step of the step 51 is the stepped end 52 (see...). Figure 20 (as shown in the dashed box).

[0121] In this embodiment, the portions of the multiple conductive layers 50 located in the stepped region are connected one-to-one with the multiple contact structures 70 to form a stepped structure. Optionally, the portion of each conductive layer 50 located in the stepped region can form a common bit line, and the portions of the multiple conductive layers 50 located in the stepped region form multiple common bit lines arranged at intervals along a direction perpendicular to the substrate 10.

[0122] In this embodiment, one end of each contact structure 70 is connected to the stepped end 52 of a corresponding conductive layer 50, and the other end extends through the insulating structure 110 and is connected to an external device. This facilitates the connection of the stepped ends 52 of different conductive layers 50 to external devices through the corresponding contact structures 70, thereby achieving the purpose of connecting the storage structure to external devices through the stepped structure.

[0123] It should be noted that the method for manufacturing the storage device in this application mainly involves process improvements to the staircase structure of the storage device. The storage device also includes a storage structure corresponding to the storage area. The manufacturing process of the storage structure in this application can be similar to or the same as the manufacturing process of the conventional storage structure, and will not be described in detail here.

[0124] Optionally, the fabrication process of the storage structure can be carried out simultaneously with the fabrication method of the storage device in the embodiments of this application, or after the fabrication method of the storage device in the embodiments of this application is completed.

[0125] The method for fabricating a memory device provided in this application belongs to the field of semiconductor memory device fabrication. It can be used to fabricate a staircase structure for memory devices and can be applied to 3D DRAM devices. Specifically, it can be applied to Vertical Oxide Channel (VOC) 3D DRAM devices.

[0126] It should be noted that, in the embodiments of this application, the structure of each film layer of the storage device can be patterned by a patterning process to produce each corresponding film layer.

[0127] It should be noted that the "patterning process" mentioned in the embodiments of this application includes processes such as depositing film layers, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography process" mentioned in the embodiments of this application includes processes such as coating film layers, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods; no specific limitations are made here.

[0128] Based on the same inventive concept, this application provides a storage device 100, which is manufactured using the above-described storage device manufacturing method.

[0129] A schematic diagram of the storage device 100 is shown below. Figure 21 As shown, it includes: substrate 10, memory structure 80 and stepped structure 90.

[0130] The substrate 10 has a storage region and a stepped region located on at least one side of the storage region. A storage structure 80 is disposed on one side of the substrate 10, and its orthogonal projection onto the substrate 10 is located in the storage region. The storage structure 80 includes a plurality of storage array layers 81 stacked sequentially along a direction perpendicular to the substrate 10. Each storage array layer 81 includes a plurality of storage cells 82 arranged in an array. A stepped structure 90 is disposed on one side of the substrate 10, and its orthogonal projection onto the substrate 10 is located in the stepped region. The stepped structure 90 includes a plurality of stepped portions 91. Each conductive layer 50 corresponding to a portion of the stepped region forms a stepped portion 91, and the plurality of stepped portions 91 form a step 51. The plurality of stepped portions 91 correspond one-to-one with the plurality of storage array layers 81, and each stepped portion 91 is connected to at least one column of storage cells 82 of the corresponding storage array layer 81.

[0131] This configuration allows for the formation of a 3D stacked structure, which can improve the storage capacity of storage devices, reduce storage costs, increase integration and storage density, and facilitate miniaturization.

[0132] It should be noted that since the storage device in this application embodiment is manufactured using the manufacturing method of the storage device in this application embodiment, the storage device in this application embodiment also has the above-mentioned beneficial effects of the manufacturing method of the storage device in this application embodiment, which will not be repeated here.

[0133] In some optional embodiments of this application, the storage device can be random access memory, specifically static random access memory or dynamic random access memory, and of course, it can also be flash memory, etc.

[0134] In one specific implementation, such as Figure 21 As shown, the memory device 100 is a vertical oxide channel 3D DRAM device. The channel 83 of the memory cell 82 is a vertical channel. The first electrode of the memory cell 82 is connected to a capacitor, and the second electrode is connected to a bit line 84. The second electrodes of two adjacent columns of memory cells 82 in the same memory array layer 81 can share the same bit line 84. The bit line 84 is connected to the corresponding step portion 91, and the step portion 91 is a common bit line. That is, the multiple common bit lines in the vertical oxide channel 3D DRAM device are made into a staircase structure to realize the connection between each layer of memory cells and external devices.

[0135] Optionally, the channel material includes, but is not limited to, metal-oxide-semiconductor (MODS) materials. The MODS material can be indium gallium zinc oxide (IGZO). When the MODS material is IGZO, the transistor's leakage current is relatively small (leakage current less than or equal to 10 Ω). -15 A), thus ensuring a low refresh rate for the dynamic memory. It should be noted that the metal oxide semiconductor material can also be ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), IWO, or ZnO. x InO x In₂O₃, InWO₂, SnO₂, TiO₂ x InSnO x Zn x O y N z Mg x Zn y O z In x Zn y O z In x Ga y Zn z O a Zr x In y Zn z O a Hf x In y Zn z O a Sn x In y Zn z O a Al x Sn y In z Zn a O d Si x In y Zn z O a Zn x Sn y O z Al x Zn y Sn z O a Ga x Zn y Sn z O a Zr xZn y Sn z O a Materials such as InGaSiO and IAZO can be used as long as the leakage current of the transistor meets the requirements; adjustments can be made based on the actual situation.

[0136] Based on the same inventive concept, this application provides an electronic device including the aforementioned storage device 100.

[0137] It should be noted that since the electronic device in the embodiments of this application includes the storage device in the embodiments of this application, the electronic device in the embodiments of this application also has the above-mentioned beneficial effects of the storage device in the embodiments of this application, which will not be repeated here.

[0138] In some optional embodiments of this application, the electronic device includes a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include, for example, memory in a computer, and is not limited thereto.

[0139] By applying the embodiments of this application, at least the following beneficial effects can be achieved:

[0140] In this embodiment, a first insulating layer and a sacrificial layer are alternately formed on one side of a substrate. Each sacrificial layer includes a first sacrificial portion corresponding to a stepped region. Then, the formed first sacrificial portions are etched along a first direction parallel to the substrate. Since the etching rate of the sacrificial layer located away from the substrate is greater than that of the sacrificial layer located close to the substrate in two adjacent sacrificial layers, the size of the multiple first sacrificial portions along the first direction will decrease, and the size of the multiple first sacrificial portions along the first direction will decrease along the direction away from the substrate, thereby forming a stepped structure with the multiple first sacrificial portions. The etched portion of the first sacrificial portion forms a first slot, and each first slot is located between two adjacent first insulating layers. The position and shape of each first slot are the same as the etched portion of the corresponding first sacrificial portion.

[0141] Then a second insulating layer is formed in the first cavity. The second insulating layer covers the end face of the remaining first sacrificial part along the first direction and fills the first cavity. At the position where the second insulating layer contacts the end face of the multiple first sacrificial parts, a stepped shape is formed that complements the step formed by the multiple first sacrificial parts.

[0142] Then, all sacrificial layers are removed, and a second slot is formed at the position corresponding to each removed sacrificial layer. Multiple second slots are arranged sequentially at intervals along the direction perpendicular to the substrate. Then, multiple conductive layers are formed, each corresponding to one of the multiple second slots. Each conductive layer fills the corresponding second slot. The portion of the conductive layer corresponding to the stepped region is in contact with the second insulating layer. Since the second insulating layer has a stepped shape, the portions of the multiple conductive layers corresponding to the stepped region will form a step.

[0143] In this embodiment, among two adjacent sacrificial layers, the etching rate of the sacrificial layer located away from the substrate is greater than that of the sacrificial layer located closer to the substrate. That is, along the direction away from the substrate, the etching rate of each sacrificial layer gradually increases. Thus, when etching multiple first sacrificial portions along the first direction, within the same etching time, the etching amount of each sacrificial layer gradually increases along the direction away from the substrate, thereby enabling multiple first sacrificial portions to form a step. After forming the step, all sacrificial layers are removed, and multiple conductive layers are formed accordingly. The conductive layers replace the sacrificial layers, thereby enabling the portions of the multiple conductive layers corresponding to the step region to form a step. Using the storage device fabrication method provided in this embodiment, a stepped structure can be fabricated through a simpler process, reducing the process difficulty and fabrication cost.

[0144] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and solutions in the prior art that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.

[0145] In the description of this application, the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate directions or positional relationships based on the exemplary directions or positional relationships shown in the accompanying drawings. They are used to facilitate the description or simplification of the embodiments of this application and are not intended to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0146] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0147] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0148] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0149] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown sequentially according to the arrows, the order in which these steps are implemented is not limited to the order indicated by the arrows. Unless explicitly stated herein, in some implementation scenarios of this application, the steps in each process can be executed in other orders as required. Moreover, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on the actual implementation scenario. Some or all of these sub-steps or stages may be executed at the same time or at different times. In scenarios where the execution times are different, the execution order of these sub-steps or stages can be flexibly configured according to requirements, and this application does not limit this.

[0150] The above description is only a partial implementation of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.

Claims

1. A method of fabricating a memory device, comprising: include: A substrate is provided, the substrate having a storage region and a stepped region located on at least one side of the storage region; A first insulating layer and a sacrificial layer are alternately formed on one side of the substrate. In two adjacent sacrificial layers, the etching rate of the sacrificial layer located away from the substrate is greater than the etching rate of the sacrificial layer located closer to the substrate. Each sacrificial layer includes a first sacrificial portion corresponding to the stepped region. Multiple first sacrificial portions are simultaneously etched along a first direction to form a step between the multiple first sacrificial portions, and a first trench is formed between two adjacent first insulating layers, wherein the first direction is parallel to the substrate. A second insulating layer is formed within the first empty slot; Remove all of the sacrificial layers to form a plurality of second voids arranged sequentially at intervals along a direction perpendicular to the substrate; Multiple conductive layers are formed, each corresponding to one of the multiple second empty slots, such that each conductive layer fills the corresponding second empty slot, and the portion of the multiple conductive layers corresponding to the stepped area forms a step.

2. The method of producing a memory device according to claim 1, wherein A first insulating layer and a sacrificial layer are alternately formed sequentially on one side of the substrate, including: A first oxide layer and a silicon-germanium compound layer are alternately formed on one side of the substrate. In two adjacent silicon-germanium compound layers, the silicon-germanium compound layer located away from the substrate has a higher germanium content than the silicon-germanium compound layer located closer to the substrate. The process involves patterning to form a first partition trench and a second partition trench. Both the first partition trench and the second partition trench penetrate the first oxide layer and the silicon-germanium compound layer and expose the substrate at the bottom. The first partition trench and the second partition trench are arranged sequentially at intervals along the first direction, dividing the silicon-germanium compound layer into a first sacrificial portion corresponding to the stepped region, a second sacrificial portion corresponding to the storage region, and a connecting portion for connecting the first sacrificial portion and the second sacrificial portion. The connecting portion is located between the first partition trench and the second partition trench. The first sacrificial portion, the connecting portion, and the second sacrificial portion form a sacrificial layer. The patterned first oxide layer forms a first insulating layer.

3. The method for manufacturing a storage device according to claim 2, characterized in that, After forming the first insulating layer and the sacrificial layer, and before etching the plurality of first sacrificial portions, the method for fabricating the memory device further includes: A third insulating layer is formed on one side of the substrate, the third insulating layer filling the first partition groove and the second partition groove; The first sacrificial portion and the first insulating layer are etched to form an etch trench extending in a direction perpendicular to the substrate, and the etch trench is located at one end of the first sacrificial portion along a first direction, with a portion of the sidewall of the etch trench exposing all of the first sacrificial portion and another portion of the sidewall exposing the third insulating layer.

4. The method for manufacturing a storage device according to claim 3, characterized in that, The etching of the plurality of first sacrificial portions along the first direction includes: In the etching groove, all the exposed first sacrificial portions are etched along the first direction to form a staircase of the plurality of first sacrificial portions and to form a first cavity between two adjacent first insulating layers. A second insulating layer is formed within the first empty slot, comprising: A second oxide layer is formed on one side of the substrate, such that the second oxide layer covers the end face of the first sacrificial portion along the first direction and fills the first empty groove and the etching groove, and the second oxide layer serves as a second insulating layer.

5. The method for manufacturing a storage device according to claim 4, characterized in that, The method for fabricating the storage device after forming the second insulating layer and before removing all of the sacrificial layers further includes: Remove the third insulating layer filling the first and second partition grooves so that the sidewalls of the first and second partition grooves expose the multiple sacrificial layers after etching the multiple first sacrificial portions along the first direction. Remove all of the aforementioned sacrificial layers, including: All of the sacrificial layers are wet-etched to remove them and form a plurality of second empty slots.

6. The method for manufacturing a storage device according to claim 5, characterized in that, Before removing all of the sacrificial layers, the method of fabricating the storage device further includes: A support layer is formed on one side of the substrate, such that the support layer is in contact with at least a portion of the sidewall of the first insulating layer.

7. The method for manufacturing a storage device according to claim 5, characterized in that, The formation of multiple conductive layers corresponding one-to-one with the multiple second empty slots includes: A metal material is deposited on one side of the substrate, the metal material filling a plurality of second empty trenches, first partition trenches and second partition trenches; Remove the metal material filling the first and second partition grooves, and the remaining metal material forms multiple conductive layers corresponding one-to-one with the multiple second empty grooves. The sidewalls of the first and second partition grooves expose the multiple conductive layers.

8. The method for manufacturing a storage device according to claim 7, characterized in that, After forming multiple conductive layers, the method for fabricating the storage device further includes: A fourth insulating layer is formed on one side of the substrate, the fourth insulating layer fills the first partition trench and the second partition trench, and the fourth insulating layer, the first insulating layer and the second insulating layer form an insulating structure for the storage device; Multiple through holes are formed through the insulating structure, and the multiple through holes are arranged sequentially at intervals along the first direction. Each of the multiple through holes corresponds to a step end of a multiple conductive layer, and the bottom of each through hole exposes the step end of the corresponding conductive layer. Metal material is filled into the multiple through holes, such that the metal material in each through hole is in contact with the stepped end of the corresponding conductive layer, and the metal material filled into the multiple through holes respectively forms multiple contact structures that are connected one-to-one with the stepped ends of the multiple conductive layers.

9. A storage device, characterized in that, It is manufactured using the method of any one of claims 1 to 8; The storage device includes: The substrate has a storage region and a stepped region located on at least one side of the storage region; A storage structure is disposed on one side of the substrate, and its orthographic projection on the substrate is located in the storage area. The storage structure includes a plurality of storage array layers stacked sequentially along a direction perpendicular to the substrate, and each storage array layer includes a plurality of storage cells arranged in an array. A stepped structure is disposed on one side of the substrate, and its orthogonal projection on the substrate is located in the stepped region. The stepped structure includes multiple stepped portions, and each conductive layer corresponding to the portion of the stepped region forms a stepped portion. The multiple stepped portions form a step. Each of the multiple stepped sections corresponds one-to-one with a multiple of the storage array layers, and each of the stepped sections is connected to at least one column of storage cells of the corresponding storage array layer; The stepped portion extends along a first direction; The stepped section and the storage array layer are arranged along the second direction; The second electrode of the memory cell is connected to a bit line, the bit line extends along a second direction, and the bit line is connected to the corresponding step portion, the step portion being a common bit line.

10. An electronic device, characterized in that, Includes the storage device as described in claim 9.

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