Semiconductor device and manufacturing method thereof

Abstract

The semiconductor device includes a bit line, a source, a body, a channel, a drain, a word line, and a first body contact. The source electrode is located on the bit line. The body is on the source. The channel is located on the body. The drain electrode is located on the channel. A word line surrounds and is spaced apart from the channel. The first body contact is located on the body, wherein the first body contact and the source are separated by the body. The first body contact and its position may be used to reduce off-state leakage current of the device.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The carriers stored in the floating body cell (FBC) are mainly generated by impact ionization operations such as channel hot electron injection near the drain side. Impact ionization generates electron-hole pairs, where the electrons are attracted by the drain and the holes are swept to the floating body as transient storage for n-channel devices. Due to the parasitic bipolar junction transistor (BJT) operation in the accumulated holes of the body, the off-state leakage current is quite high. Summary of the invention

[0003] Some embodiments of the present disclosure provide a semiconductor device including a bit line, a source, a body, a channel, a drain, a word line, and a first body contact. The source is located on the bit line. The body is located on the source. The channel is located on the body. The drain is located on the channel. The word line surrounds the channel and is spaced apart from the channel. The first body contact is located on the body, wherein the first body contact and the source are separated by the body.

[0004] In some embodiments, the first body contact is adjacent to the first side of the channel.

[0005] In some embodiments, the semiconductor device further includes a second body contact adjacent to a second side of the channel, wherein the second side is opposite to the first side.

[0006] In some embodiments, a top surface of the first body contact is flush with a top surface of the drain.

[0007] In some embodiments, the semiconductor device further includes a dielectric layer extending from a sidewall of the drain, through a sidewall of the channel and a top surface of the body, to the first body contact.

[0008] In some embodiments, the semiconductor device further includes an isolation structure surrounding the first body contact and contacting the dielectric layer.

[0009] In some embodiments, a top surface of the first body contact is flush with a top surface of the isolation structure.

[0010] In some embodiments, a bottom surface of the first body contact is flush with a bottom surface of the channel.

[0011] In some embodiments, the semiconductor device further includes a capacitor located on the drain.

[0012] In some embodiments, the semiconductor device further includes a terminal on the first body contact.

[0013] In some embodiments, the first body contact extends from the body to the terminal.

[0014] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device, including sequentially forming a bit line, a source, a body, a channel material layer, and a drain material layer, wherein the source is located on the bit line, the body is located on the source, the channel material layer is located on the body, and the drain material layer is located on the channel material layer. A first trench is formed in the channel material layer and the drain material layer to expose the body, wherein the remaining portions of the channel material layer and the drain material layer form a channel and a drain. A dielectric layer is formed along the first trench. A word line is formed around the channel, wherein the word line and the channel are separated by the dielectric layer. An isolation structure is formed in the first trench. A body contact is formed in the isolation structure, wherein the body contact contacts the body.

[0015] In some embodiments, the manufacturing method further includes forming a second trench in the source, body, channel material layer, and drain material layer to expose the bit line after forming the first trench.

[0016] In some embodiments, the manufacturing method further includes forming a capacitor on the drain.

[0017] In some embodiments, the manufacturing method further includes forming a terminal on the body contact.

[0018] In some embodiments, forming the body contact includes forming a third trench in the isolation structure and the dielectric layer and exposing the body, and filling the third trench with a heavily p-type doped material to form the body contact.

[0019] In some embodiments, the body contact contacts the isolation structure and the dielectric layer.

[0020] In some embodiments, the bottom of the third trench is flush with the bottom surface of the channel, so that the bottom surface of the body contact is flush with the bottom surface of the channel.

[0021] In some embodiments, a top surface of the body contact is flush with a top surface of the drain.

[0022] In some embodiments, a top surface of the body contact is flush with a top surface of the isolation structure.

[0023] In some embodiments of the present disclosure, a semiconductor device having a body contact is provided. The body contact and its location are used to reduce the off-state leakage current of the device.

[0024] It is to be understood that both the foregoing summary and the following detailed description are exemplary, and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The present disclosure may be more fully understood by reading the following detailed description of the embodiments with reference to the following accompanying drawings:

[0026] Figure 1 FIG. 1 is a top view of a semiconductor device in some embodiments of the present disclosure.

[0027] Figure 2 The diagram shows some embodiments of the present disclosure along Figure 1 A cross-sectional view of a semiconductor device taken along line AA in FIG.

[0028] Figures 3 to 10 FIG. 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device in some embodiments of the present disclosure.

[0029] Fig.11 FIG. 1 is a top view of a semiconductor device in some other embodiments of the present disclosure.

[0030] Fig.12 Some other embodiments of the present disclosure are shown in FIG. Fig.11 A cross-sectional view of a semiconductor device taken along line BB in FIG.

[0031] Fig.13 FIG. 1 is a top view of a semiconductor device in some other embodiments of the present disclosure.

[0032] Fig.14 Some other embodiments of the present disclosure are shown in FIG. Fig.13 A cross-sectional view of a semiconductor device taken along line CC in FIG. DETAILED DESCRIPTION

[0033] In some embodiments of the present disclosure, a semiconductor device having a body contact is provided. In some embodiments, the semiconductor device may be a vertical dynamic random-access memory (DRAM). The body contact and its location may be used to reduce the off-state leakage current of the device.

[0034] Figure 1 FIG. 1 is a top view of a semiconductor device in some embodiments of the present disclosure. Figure 2 The diagram shows some embodiments of the present disclosure along Figure 1 A cross-sectional view of a semiconductor device cut along line AA in FIG. It should be noted that for simplicity, Figure 1 Only the bit line 110, the word line 130, the capacitor 170 and the body contact 150 are shown, and the detailed structure of the semiconductor device is as shown in FIG. Figure 2 shown.

[0035] The semiconductor device includes a bit line 110, a source 122 located on the bit line 110, a body 124 located on the source 122, a channel 126 located on the body 124, a drain 128 located on the channel 126, a word line 130 surrounding and spaced apart from the corresponding channel 126, and a body contact 150 located on the body 124. The body contact 150 and the source 122 are separated from each other by the body 124. The top surface of the body contact 150 is substantially flush with the top surface of the drain 128. The bit line 110 and the word line 130 are arranged along a vertical direction, such as Figure 1 shown.

[0036] The semiconductor device further includes a dielectric layer 142 and an isolation structure 144. The dielectric layer 142 surrounds the corresponding channel 126 and can be used as a gate dielectric layer of the transistor. The dielectric layer 142 is located between the channel 126 and the word line 130. In some embodiments, the dielectric layer 142 includes a portion 142A in contact with the top surface of the body 124 and a portion 142B in contact with the top surface of the bit line 110. The isolation structure 144 surrounds the body contact 150 and contacts the dielectric layer 142. The isolation structure 144 also covers the word line 130. The semiconductor device further includes a dielectric layer 160, a capacitor 170, and a terminal 180. The capacitor 170 is located on the drain 128, and the terminal 180 is located on the body contact 150. The capacitor 170 and the terminal 180 are separated by the dielectric layer 160. In some embodiments, the terminal 180 can be connected to VBB (i.e., the base supply voltage in the transistor circuit).

[0037] The semiconductor device further includes a capacitor 170 disposed on and electrically connected to the corresponding drain 128. In some embodiments where the semiconductor device is a memory device (e.g., a DRAM), the memory may include a plurality of memory cells. A typical DRAM cell includes a capacitor and a transistor, wherein the capacitor temporarily stores data based on a charge state of the capacitor. The bit line is electrically connected to a source region of the transistor, and the bit line is electrically connected to a gate region of the transistor. In some embodiments, the transistor of each memory cell may include a source 122, a body 124, a channel 126, a drain 128, and a dielectric layer 142 (e.g., a gate dielectric layer). The word line 130 may also serve as a gate of the transistor. Assuming that the pitch of each of the word line 130 and the bit line 110 is 2F, the horizontal dimension of the DRAM cell may be 4F2, which means that the DRAM cell may have an area of ​​approximately 4F2 or less, where F is the minimum lithographic feature size.

[0038] The body contact 150 extends from the body 124 to the terminal 180 and is used to reduce the off-state leakage current in the semiconductor device by leading the accumulated holes out of the body 124 to the terminal 180, so that the off-state leakage current may be reduced. In some embodiments, the body contact 150 includes a first body contact 150A and a second body contact 150B. The first body contact 150A is adjacent to the first side 126S1 of the channel 126, the second body contact 150B is adjacent to the second side 126S2 of the channel 126, and the second side 126S2 is opposite to the first side 126S1. The first body contact 150A and the second body contact 150B are both spaced apart from the channel 126. That is, the channel 126 is located between the first body contact 150A and the second body contact 150B. In some embodiments, the body contact 150 is made of a P-type heavily doped material, the body 124 is made of a P-type lightly doped material, and the source 122 is made of an N-type heavily doped material. Therefore, the body contact 150 does not contact the source 122 , and there is no interface between the P-type heavily doped region and the N-type heavily doped region, and the off-state leakage current is further reduced.

[0039] Figures 3 to 10 FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor device in some embodiments of the present disclosure. Figure 3 , a bit line 110, a source 122, a body 124, a channel material layer 126', and a drain material layer 128' are sequentially formed. That is, the source 122 is located on the bit line 110, the body 124 is located on the source 122, the channel material layer 126' is located on the body 124, and the drain material layer 128' is located on the channel material layer 126'. In some embodiments, the bit line 110 is made of metal, such as tungsten (W), copper (Cu) or molybdenum (Mo), but is not limited thereto. The source 122, the body 124, the channel material layer 126', and the drain material layer 128' may be made of a semiconductor material. For example, the source 122 and the drain material layer 128' may be made of an N-type heavily doped silicon layer, the body 124 may be made of a P-type lightly doped silicon layer, and the channel material layer 126' may be made of a P-type moderately doped silicon layer.

[0040] Reference Figure 4, a first trench T1 is formed in the channel material layer 126' and the drain material layer 128' to expose the body 124 and form the channel 126 and the drain 128. After forming the first trench T1, a second trench T2 is formed in the source 122, the body 124, the channel material layer 126' and the drain material layer 128' to expose the bit line 110. In some embodiments, the second trench T2 may be formed before forming the first trench T1. The second trench T2 may be adjacent to one of the first trenches T1. The bottom of the second trench T2 is lower than the bottom of the first trench T1. The remaining portions of the channel material layer 126' and the drain material layer 128' serve as the channel 126 and the drain 128, as shown in FIG. Figure 2 shown.

[0041] Reference Figure 5 The dielectric layer 142 is formed along the top surface of the first trench T1 and the second trench T2 and the drain 128. In some embodiments, the dielectric layer 142 is made of silicon oxide, silicon nitride, or the like.

[0042] Reference Figure 6 , forming a word line 130 around the channel 126, wherein the word line 130 has a dielectric layer 142 between the channel 126. More specifically, a word line material layer may be first formed in the first trench T1 and the second trench T2. Subsequently, the word line material layer is patterned to form the word line 130 around the channel 126. In some embodiments, the word line 130 may also surround a portion of the drain 128. Since the bottom of the second trench T2 is lower than the bottom of the first trench T1, the bottom of the word line 130 in the second trench T2 is lower than the bottom of the word line 130 in the first trench T1. In some embodiments, the word line 130 may be made of a metal, such as tungsten (W), copper (Cu), or molybdenum (Mo), but is not limited thereto. After the word line 130 is formed, the dielectric layer 142 along the top surface of the drain 128 is removed by a cleaning process, and the dielectric layer 142 includes a portion 142A in the first trench T1 and a portion 142B in the second trench T2 .

[0043] Reference Figure 7 , an isolation structure 144 is formed in the first trench T1 and the second trench T2. The isolation structure 144 includes a first trench T1 (see Figure 6 ) in the first portion 144A and the second trench T2 (see Figure 6 ) in the second portion 144B. Specifically, the dielectric material may be first filled in the first trench T1 and the second trench T2. Then, a planarization process is performed to remove the excess dielectric material outside the first trench T1 and the second trench T2, so that the top surface of the isolation structure 144 is substantially flush with the top surface of the drain 128. In some embodiments, the isolation structure 144 is made of silicon oxide, silicon nitride, etc.

[0044] Reference Figure 8 , a third trench T3 is formed in the first portion 144A of the isolation structure and the dielectric layer 142, and the third trench T3 exposes the body 124. Therefore, the bottom surface of the third trench T3 is also flush with the bottom surface of the channel 126. The third trench T3 is spaced apart from the word line 130 and the channel 126. That is, the third trench T3 does not expose the word line 130 and the channel 126. In some embodiments, the third trench T3 may be formed adjacent to the first side 126S1 and the second side 126S2 of the channel 126.

[0045] Reference Fig. 9 , fill the third trench T3 (see Figure 8 ) to form a body contact 150 in the third trench T3. Then, a planarization process is performed to remove excess material of the p-type heavily doped material outside the third trench T3, so that the top surface of the body contact 150 is substantially flush with the top surface of the drain 128 and the top surface of the isolation structure 144. In some embodiments, the p-type heavily doped material can be made of polysilicon doped with boron or gallium. In some other embodiments, in the third trench T3 (see Figure 8 ) is filled with metal instead of p-type heavily doped material to form a body contact 150. The body contact 150 is in contact with the isolation structure 144 and the dielectric layer 142. In addition, the body contact 150 is surrounded by the first portion 144A of the isolation structure 144 and is separated from the word line 130 by the first portion 144A of the isolation structure 144. After the p-type heavily doped material or metal is filled into the third trench T3, the dielectric layer 142 extends from the sidewall of the drain 128, passes through the sidewall of the channel 126 and the top surface of the body 124, and reaches the body contact 150, and the bottom surface of the body contact 150 is flush with the bottom surface of the channel 126. The body contact 150 is in contact with the body 124 and is used to lead the accumulated holes out of the body 124, so that the off-state leakage current can be reduced. The body contact 150 and the source 122 are separated by the body 124. That is, the body contact 150 does not contact the source 122. Therefore, in some embodiments where the body contact 150 is made of a P-type heavily doped material, the interface between the P-type heavily doped region (ie, the body contact 150 ) and the N-type heavily doped region (ie, the source 122 ) does not exist, and the off-state leakage current will be further reduced.

[0046] Reference Fig.10 , a capacitor 170 is formed on the drain 128, and a terminal 180 is formed on the body contact 150. More specifically, first Fig. 9A dielectric layer is formed on the structure shown. Subsequently, a plurality of trenches are formed in the dielectric layer to expose the drain 128 and the body contact 150, and a dielectric layer 160 is formed. In some embodiments, the trenches exposing the drain 128 and the trenches exposing the body contact 150 are not formed at the same time. Subsequently, a capacitor 170 is formed on the drain 128, and a terminal 180 is formed on the body contact 150. The capacitor 170 and the terminal 180 are separated by the dielectric layer 160. It should be noted that Fig.10 The structure of capacitor 170 is simplified in FIG. In some embodiments, capacitor 170 may be a multi-layer structure.

[0047] Fig.11 FIG. 1 is a top view of a semiconductor device in some other embodiments of the present disclosure. Fig.12 Some other embodiments of the present disclosure are shown in FIG. Fig.11 A cross-sectional view of a semiconductor device taken along line BB in FIG. Figure 11 to Figure 12 The semiconductor device in Figure 1 to Figure 2 The difference is that Figure 11 to Figure 12 The semiconductor device in does not include the second body contact 150B. Figure 11 to Figure 12 , the first body contact 150A is adjacent to the first side 126S1 of the channel 126 , and there is no body contact adjacent to the second side 126S2 of the channel 126 . Figure 11 to Figure 12 The method for manufacturing the semiconductor device in is also similar to Figure 1 to Figure 2 A method for manufacturing a semiconductor device in Figures 3 to 10 The difference is that when forming Figure 11 to Figure 12 When the semiconductor device is formed in the embodiment of the present invention, the first trench T1 and the second trench T2 are alternately formed above the bit line 110. That is, when the first trench T1 and the second trench T2 are formed Figure 11 to Figure 12 When the semiconductor device is in Figure 4 The first trench T1 and the second trench T2 in the Figure 11 to Figure 12 Other details about the manufacturing method in are similar to Figures 3 to 10 The manufacturing method shown in will not be repeated here.

[0048] Fig.13 FIG. 1 is a top view of a semiconductor device in some other embodiments of the present disclosure. Fig.14 Some other embodiments of the present disclosure are shown in FIG. Fig.13 A cross-sectional view of a semiconductor device taken along line CC in FIG. Figure 13 to Figure 14 The semiconductor device in Figure 11 to Figure 12The difference is that the body contact 150 on the first one of the bit lines 110 is laterally offset from the body contact 150 on the second one of the bit lines 110 adjacent to the first one of the bit lines 110 along a first direction (e.g., X direction). The first direction (e.g., X direction) is the longitudinal direction of the bit line 110. The first direction is perpendicular to the second direction (e.g., Y direction), which is the longitudinal direction of the word line 130. Therefore, Figure 13 to Figure 14 The semiconductor device may have Fig.12 The section along the BB line and Fig.14 Two different cross-sections along the CC line. Figure 13 to Figure 14 The details of the method for manufacturing the semiconductor device are similar to those in Figures 3 to 10 The manufacturing method shown in will not be repeated here.

[0049] As mentioned above, the body contact in the semiconductor device can be used to reduce the off-state leakage current. More specifically, the body contact contacts the body and is used to lead the accumulated holes out of the body, so the off-state leakage current can be reduced. The body contact may be adjacent to one side of the channel or adjacent to both sides of the channel. In some embodiments, the body contact is made of a P-type heavily doped material, the source is made of an N-type heavily doped material, and the body is made of a P-type lightly doped material. The source and the body contact are separated by the body. Therefore, there is no interface between the P-type heavily doped region (i.e., the body contact) and the N-type heavily doped region (i.e., the source). The off-state leakage current will be further reduced.

[0050] Although the present disclosure has been described in considerable detail with reference to certain embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0051] It will be apparent to those skilled in the art that various modifications and variations may be made in the present invention without departing from the scope or spirit of the present invention. In view of the foregoing, the present disclosure is intended to cover modifications and variations of the present disclosure that fall within the scope of the appended claims.

[0052]

Explanation of symbols

[0053] 110: Bit line

[0054] 122: Source

[0055] 124: Main body

[0056] 126: Channel

[0057] 126': channel material layer

[0058] 126S1: First side

[0059] 126S2: Second side

[0060] 128: Drain

[0061] 128': drain material layer

[0062] 130: Character line

[0063] 142: Dielectric layer

[0064] 142A: Part

[0065] 142B: Part

[0066] 144: Isolation Structure

[0067] 144A: Part 1

[0068] 144B: Part 2

[0069] 150: Main body contact

[0070] 150A: First body contact

[0071] 150B: Second body contact

[0072] 160: Dielectric layer

[0073] 170:Capacitor

[0074] 180:Terminal

[0075] AA:Line

[0076] BB:Line

[0077] CC:Line

[0078] T1: First groove

[0079] T2: Second groove

[0080] T3: The third groove.

Claims

1. A semiconductor device, characterized in that: Include: bit line; a source located at the bit line; A main body, located on the source electrode; a channel located on the body; a drain electrode, located on the channel; a word line surrounding the channel and spaced apart from the channel; and A first body contact is located on the body, wherein the first body contact and the source are separated by the body.

2. The semiconductor device according to claim 1, wherein: The first body contact is adjacent to a first side of the channel.

3. The semiconductor device according to claim 2, wherein: Further included is a second body contact adjacent a second side of the channel, wherein the second side is opposite the first side.

4. The semiconductor device according to claim 1, wherein: The top surface of the first body contact is flush with the top surface of the drain.

5. The semiconductor device according to claim 1, wherein: The invention further includes a dielectric layer extending from the sidewall of the drain, through the sidewall of the channel and the top surface of the body, to the first body contact.

6. The semiconductor device according to claim 5, wherein: An isolation structure surrounding the first body contact and contacting the dielectric layer is further included.

7. The semiconductor device according to claim 6, wherein: The top surface of the first body contact is flush with the top surface of the isolation structure.

8. The semiconductor device according to claim 1, wherein: The bottom surface of the first body contact is flush with the bottom surface of the channel.

9. The semiconductor device according to claim 1, wherein: Further included is a capacitor located on the drain.

10. The semiconductor device according to claim 1, wherein: Further included is a terminal located on the first body contact.

11. The semiconductor device according to claim 10, wherein: The first body contact extends from the body to the terminal.

12. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: Sequentially forming a bit line, a source, a body, a channel material layer, and a drain material layer, wherein the source is located on the bit line, the body is located on the source, the channel material layer is located on the body, and the drain material layer is located on the channel material layer; forming a plurality of first trenches in the channel material layer and the drain material layer to expose the body, wherein the remaining portions of the channel material layer and the drain material layer form a plurality of channels and a plurality of drains; forming a dielectric layer along the plurality of first trenches; forming a plurality of word lines surrounding the plurality of channels, wherein the plurality of word lines and the plurality of channels are separated by the dielectric layer; forming a plurality of isolation structures in the plurality of first trenches; and A plurality of body contacts are formed in the plurality of isolation structures, wherein the plurality of body contacts contact the body.

13. The manufacturing method according to claim 12, characterized in that: Further including: After forming the plurality of first trenches, a second trench is formed in the source, the body, the channel material layer, and the drain material layer to expose the bit line.

14. The manufacturing method according to claim 12, characterized in that: Further comprising the following steps: A plurality of capacitors are formed on the plurality of drain electrodes.

15. The manufacturing method according to claim 12, characterized in that: Further comprising the following steps: A plurality of terminals are formed on the plurality of body contacts.

16. The manufacturing method according to claim 12, characterized in that: Wherein forming the plurality of body contacts comprises: forming a plurality of third trenches in the plurality of isolation structures and the dielectric layer and exposing the body; and A p-type heavily doped material is filled in the plurality of third trenches to form the plurality of body contacts.

17. The manufacturing method according to claim 16, characterized in that: The plurality of body contacts are in contact with the plurality of isolation structures and the dielectric layer.

18. The manufacturing method according to claim 16, characterized in that: The bottoms of the third grooves are flush with the bottom surfaces of the channels, so that the bottom surfaces of the body contacts are flush with the bottom surfaces of the channels.

19. The manufacturing method according to claim 12, characterized in that: The top surfaces of the body contacts are flush with the top surfaces of the drain electrodes.

20. The manufacturing method according to claim 12, characterized in that: The top surfaces of the body contacts are flush with the top surfaces of the isolation structures.

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