Memory device having hexagonal memory cells with pillar lattice

Abstract

The invention relates to a memory device having hexagonal memory cells with pillar lattices. Various applications may include a memory device having an array of memory cells, where each of the memory cells has a gate-all-around (GAA) transistor arranged as a hexagonal vertical channel transistor coupled to a capacitor. An access line may be coupled to a gate of the GAA transistor and a digital line may be coupled to a pillar channel of the GAA transistor. A lattice may be included between the access line and the digital line, wherein the lattice has a dielectric region between and contacting non-dielectric regions. Each non-dielectric region may be positioned on and contact a digital line, and may contain a digital contact junction to the pillar channel of a set of the GAA transistors extending from the non-dielectric region. Additional apparatus and methods are disclosed.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to integrated circuits and, more particularly, to memory devices and the formation thereof. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits (ICs) in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain its data, and includes random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), or synchronous dynamic random access memory (SDRAM), etc. Non-volatile memory can retain stored data when power is not supplied, and includes flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistance variable memory (such as phase change random access memory (PCRAM)), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), or three-dimensional (3D) XPoint TM Memory, etc. The properties of memory devices and other electronic devices can be improved by enhancing the design and fabrication of components of the electronic device, such as, but not limited to, memory devices in an IC of the electronic device. Summary of the invention

[0003] In one aspect, the present disclosure relates to a memory device comprising: an array of memory cells, each of the memory cells having a gate-all-around (GAA) transistor arranged as a hexagonal vertical channel transistor coupled to a capacitor; an access line coupled to a gate of the GAA transistor; a digit line coupled to a pillar channel of the GAA transistor; and a lattice between the access line and the digit line, the lattice having dielectric regions between and contacting non-dielectric regions, each non-dielectric region being on and contacting a digit line in the digit line and containing digital contact junctions to the pillar channels of a group of the GAA transistors extending from the non-dielectric region.

[0004] On the other hand, the present disclosure relates to a method of forming a memory device, the method comprising: forming a memory cell array, which includes forming each of the memory cells having a gate-all-around (GAA) transistor arranged as a hexagonal vertical channel transistor coupled to a capacitor; forming an access line coupled to the gate of the GAA transistor; forming a digit line coupled to a pillar channel of the GAA transistor, wherein the digit line and the access line are separated from each other in a vertical direction; and forming a lattice between the access line and the digit line, which includes dielectric regions formed between and contacting non-dielectric regions and forming each non-dielectric region, each non-dielectric region being on and contacting a digit line in the digit line and containing a digital contact junction to the pillar channels of a group of the GAA transistors extending from the non-dielectric region.

[0005] In another aspect, the present disclosure is directed to a method of forming a memory device, the method comprising: preparing an array wafer with an array of gate-all-around (GAA) transistors connected to access lines and digit lines, wherein the access lines and the digit lines are separated from each other by a lattice including dielectric regions between and contacting non-dielectric regions, wherein each non-dielectric region is on and contacts a digit line of the digit lines and contains a digital contact junction to pillar channels of a set of the GAA transistors extending from the non-dielectric regions; preparing a control circuitry wafer; and coupling the array wafer and the control circuitry wafer together. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The drawings, which are not necessarily drawn to scale, generally illustrate the various embodiments discussed in this document by way of example and not by way of limitation.

[0007] Figure 1 Representations of example structures of memory cell arrays having memory cells arranged as hexagonal shapes in accordance with various embodiments are illustrated.

[0008] Figure 2 Description of various embodiments in which Figure 1 A top view of an example of an open digital line architecture showing multiple examples of the structure.

[0009] Figure 3 Description of various embodiments Figure 1 The bottom part of the structure.

[0010] Figure 4 is a diagram illustrating a pillar channel supported by a lattice according to various embodiments Figure 1 A top view of a portion of a structure.

[0011] Figure 5 and 6A comparison of hexagonal cells and square cells according to various embodiments is provided.

[0012] Figures 7 to 28 The invention describes a method for forming a Figure 1 An example process flow of a memory device having a memory cell arrangement of the structure.

[0013] Fig.29 Description of various embodiments Fig.28 An example architecture in which a structure or similar structure may be located.

[0014] Fig.30 is a flow chart of features of an example method of forming a memory device in accordance with various embodiments.

[0015] Fig.31 is a flow chart of features of an example method of forming a memory device in accordance with various embodiments.

[0016] Fig.32 is a schematic diagram of an electrical arrangement of components of an example dynamic random access memory device that may include an architecture having hexagonal memory cells with all-around gate transistors in accordance with various embodiments. DETAILED DESCRIPTION

[0017] The following detailed description refers to the accompanying drawings that show various embodiments that can be implemented by explanation. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice these and other embodiments. Other embodiments may be utilized, and structural, logical, mechanical and electrical changes may be made to these embodiments. As used in this application, the term "horizontal" is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term "vertical" refers to a direction perpendicular to the horizontal defined above and may be in a direction from horizontal or to horizontal. Various features may have components perpendicular to the direction of their structure. Various embodiments are not necessarily mutually exclusive, because some embodiments may be combined with one or more other embodiments to form new embodiments. Therefore, the following detailed description should not be considered as intended to be limiting.

[0018] In various embodiments, a memory device may be structured with an array of memory cells arranged as hexagonal cells, wherein each of the memory cells has a gate all around (GAA) transistor coupled to a capacitor. A hexagonal memory cell is a memory cell surrounded by six other memory cells, such that the other memory cells are at the vertices of a hexagonal structure formed by connecting the centers of neighboring memory cells of the other memory cells. A GAA transistor is a transistor structured with a gate of a transistor coupled to a channel structure of the transistor on all sides of the channel structure. A GAA transistor may be structured as a thin film transistor (TFT). A GAA transistor may be structured into a pillar arrangement containing an active region (source and drain) and a channel structure around which a gate is structured. The gate may be separated from the channel structure by a gate dielectric. The pillar structure of the GAA transistor may be structured as a semiconductor nanowire.

[0019] Nanowires are nanostructures with nanoscale diameters. GAA nanowire transistors as access devices to capacitors in DRAM memory cells can provide enhanced I ON capability and transistor threshold voltage (V T ) can be adjusted flexibly. ON is the on-state current of the transistor, and I OFF is the off-state current of the transistor. The ratio I ON / I OFF It is the quality factor of the transistor for high performance and low leakage power. High performance and large I ON associated with low leakage power and smaller I OFF Associated.

[0020] A memory device having one or more hexagonal memory cell arrays of GAA transistors may be implemented with control logic and sensing circuitry in a variety of different architectures. The control logic and sensing circuitry may be located in a peripheral region adjacent to the hexagonal memory cell array on a wafer as an IC chip. Another compatible architecture includes control logic and sensing circuitry located under one or more memory arrays in a circuit under array (CuA) architecture. The control logic and sensing circuitry may be arranged for sensing the programming data states of memory cells of one or more memory arrays of a memory device, and may facilitate die size reduction or improve space utilization in a die or die combination. CuA generally refers to circuitry located in a memory die under a memory array of a memory die. When the control logic and sensing circuitry is manufactured under a memory array using semiconductor processing that may include complementary metal oxide semiconductor (CMOS) processing technology, CuA may also be referred to as CMOS under an array. Another compatible architecture may include control logic and sensing circuitry located on a memory array in a circuit on an array (CoA) architecture. The control logic and sensing circuit system can be arranged to sense the programming data state of the memory cells of one or more memory arrays of the memory device, and can promote the reduction of the die size or improve the space utilization in the die or die combination. CoA generally refers to the circuit system located in the memory die on one or more memory arrays of the memory die. When the control logic and sensing circuit system are manufactured on one or more memory arrays using semiconductor processing that may include CMOS, CoA may also be referred to as CMOS on array. CuA architecture and CoA architecture can be implemented by wafer and wafer architecture, wherein the control logic and sensing circuit system are formed on one wafer and one or more memory arrays are formed on another wafer, and the two wafers are combined. Wafer and wafer interconnection architecture may include wafer-on-wafer architecture. Wafer-to-wafer bonding of back-to-back wafers with CoA architecture can provide the movement of capacitor modules for data storage in DRAM to the bottom of the wafer stack. This arrangement can reduce interconnect congestion between stacked wafers.

[0021] The memory device may include a set of access lines (WLs), wherein each WL in the WL set may be coupled to the gates of a first set of multiple GAA transistors of a memory cell of a memory array. Each WL may be formed in a replacement gate process together with a corresponding gate of a GAA transistor, which may provide enhanced gate control. The memory device may include a set of digit lines (BLs), wherein each BL in the BL set may be coupled to a second set of multiple GAA transistors of a memory cell. The WL may be vertically separated from the BL. A lattice may be structured between the BL and the WL, wherein the lattice is a structure added to the process flow in the manufacture of the memory cell to ensure the structural stability of the cell by preventing the vertical structure of the cell from toppling. This lattice may significantly reduce the aspect ratio of the pillar etching in the manufacture, for example in the range of 40%. In addition, each BL may at least partially surround the active area of ​​the GAA transistor to which the given BL is coupled. When the BL at least partially surrounds the active area, a reduction in resistance-capacitance (RC) parameters may be achieved.

[0022] The memory device may have 4F 2 A memory array configuration in which a memory cell in a memory cell row coupled to a BL can share the BL with an adjacent memory cell in an immediately adjacent memory cell row. 2 The formula is used to measure 4F, where 'n' is a constant derived from the cell design and 'F' is the feature size of the process technology. 2 The unit repeating unit of the cell is a parallelogram with sides of equal length 2F. For the same feature size, as the cell size gets smaller, the memory capacity increases. 2 In the memory cell configuration, the WL pitch and the BL pitch are equal to 2F.

[0023] Figure 1 A structure 100 is illustrated having a memory cell arrangement, wherein each memory cell has an access transistor and a capacitor, wherein the access transistor is a GAA transistor having a pillar channel supported by a lattice. Various dielectric regions are not shown to focus on the active components of the structure 100. For ease of presentation, the components may be labeled Figure 1and one of similar features in subsequent figures, not all similar features are labeled. Memory cells are arranged on wafer 101, which may be referred to as array wafer 101 because the memory cells are structured at a step above wafer 101 during manufacturing. A bonding dielectric 122 is positioned on array wafer 101, wherein bonding dielectric 122 is structured in manufacturing to be bonded to array wafer 101, which may be used as a carrier during placement of structure 100 in a memory device. Dielectric 118 is positioned on bonding dielectric 122. BL is positioned above bonding dielectric 122 within dielectric 118, wherein BL has a central BL region 135 contacting side BL region 134, wherein central BL region 135 is on and in contact with dielectric 113. In this example, in a cross-sectional view of the BL, central BL region 135 and side BL region 134 have an H shape.

[0024] The structure 100 includes a pillar channel 107 supported by a lattice, which is a regular arrangement of materials over an area or volume. The lattice of the structure 100 has dielectric regions 120 between and contacting non-dielectric regions 104, wherein each non-dielectric region 104 is on and contacting the BL. The non-dielectric region 104 is on a central BL region 135, wherein portions of the non-dielectric region 104 contact the top portions of the side BL regions 134 (relative to the bonding dielectric 122 and the array wafer 101). The non-dielectric region 104 contains a digital contact junction (BL contact junction) to the pillar channel 107 of a set of GAA transistors, wherein the pillar channel extends from the non-dielectric region 104 and extends above the step at approximately the top of the dielectric region 120.

[0025] The pillar channels 107 may be vertical semiconductor pillars. The pillar channels 107 may be implemented as nanowires. Each pillar channel 107 includes a channel between two source / drain regions. For each pillar channel 107, a gate dielectric 123 may be positioned around the channel provided by the pillar channel 107. A gate 127 and a WL 130 contacting the gate 127 are positioned around each gate dielectric 123 and pillar channel 107. The gate 127 and the WL 130 may be structured into a format in which the WL 130 is integrated with multiple gates 127, such as Figure 1. The two source / drain regions of each pillar channel 107 are active regions. Each active region may include a contact junction. For each pillar channel 107, the channel is coupled to the capacitor 129 through the active region 108 having a cell contact junction and is coupled to the BL of the central BL region 135 having a contact side BL region 134 through the active region 106 having a digital contact junction (the digital contact may be referred to as a bit contact / bitcon). Each BL of the central BL region 135 having a contact side BL region 134 may be at least partially wrapped around the sidewall of the active region 106. The bit contact junction region may be configured as a shield to reduce the capacitance between the BLs. Alternatively, the digital shield may be structured between adjacent BLs.

[0026] A dielectric 169 is positioned above the WL 130 and the gate 127. The dielectric 169 is created by the processing of the structure 100 and provides electrical isolation for the conductive components in the structure 100. A group of capacitors 129 is above the dielectric 169. Each capacitor 129 includes a capacitor dielectric 159 between two electrodes 157 and 158. Electrode 158 may be referred to as a bottom electrode coupled to the active region 108 of the pillar channel 107, while electrode 157 is a top electrode that may be coupled to a reference node. The capacitor dielectric 159 may be, but is not limited to, a high-k dielectric. A high-k dielectric is a dielectric having a dielectric constant greater than that of silicon dioxide. The structure 100 may include a dielectric region 198 on the capacitor group 129 or a connecting wafer.

[0027] Figure 2 Explain which can be implemented Figure 1 An example of an open BL architecture of multiple examples of the structure 100 is shown in a top view 200, where a memory cell 221 in a memory cell row coupled to a BL can share the BL with an adjacent memory cell 221 in an immediately adjacent memory cell row. In the open BL architecture, the BL is divided into multiple segments and differential sense amplifiers (SAs) can be placed between the BL segments. The BL can be brought to the SA in pairs, where the BLs are from different array patches. An array patch (which may also be referred to as a pad) is a structure for a sub-array of memory cells of a larger memory array of a memory device, such as Figure 1 Example structure 100. The open BL architecture may be referred to as an open SA architecture.

[0028] The open BL architecture of 200 can be used for 4F 2The architecture is structured and includes a SA 239. BLs D1, D2, D3, and D4 are in an array tile 297 coupled to the SA 239. The array tile 297 includes a plurality of WLs 230, wherein each WL 230 is not shared with any neighboring bits, i.e., for a linear memory cell arrangement, a memory cell coupled to a given WL 230 does not share the given WL 230 with a memory cell directly adjacent to the linear memory cell arrangement. For example, the array tile 297 may include each WL 230 having a set of a plurality of memory cells 221, wherein a memory cell 221 directly adjacent to the given WL 230 is not addressed by the given WL 230. Each WL 230 may be integrated with the gate of a GAA transistor of each memory cell 121 in the set of a plurality of memory cells 221 addressable by the given WL 230. BL D1*, D2*, D3*, and D4* are in an array tile 298, which includes a plurality of WLs 230, wherein each WL 230 is not shared with any adjacent bits. For example, the array tile 298 may include each WL 230 having a set of a plurality of memory cells 221, wherein the memory cells 221 adjacent to the given WL 230 are not addressed by the given WL 230. Each WL 230 may be integrated with the gate of the GAA transistor of each memory cell 121 in the set of a plurality of memory cells 221 that the given WL 230 can address.

[0029] BLs D1, D2, D3, and D4 from array patch 297 may be paired with BLs D1*, D2*, D3*, and D4* from array patch 298, respectively, where array patch 297 is different from array patch 298. The BL pairs may be coupled to SA 239. Array patch 297 and array patch 298 may be formed in separate subtractive processes, where each array patch has Figure 1 Subtractive processes involve removing material from a solid block of starting material.

[0030] Figure 3 illustrate Figure 1 300 shows a lattice with dielectric regions 120 between WLs 130 and BLs (each BL having a central BL region 135 contacting side BL regions 134) and illustrates that the lattice can provide support for pillar trenches 107 to prevent toppling during fabrication of structure 100. Figure 4 is a further illustration of the support channel 107 supported by the dielectric region 120 of the lattice of the structure 100. Figure 1 A top view of a portion of structure 400 .

[0031] Figure 5 and 6 Provides implementation in 4F 2Comparison of the GAA hexagonal cells of structure 500 and the GAA square cells of structure 600 in the architecture. A hexagonal GAA cell 521 coupled to a given WL 530 has a margin d1 with a GAA cell 521 directly adjacent to WL 530. A hexagonal GAA cell 621 coupled to a given WL 630 has a margin d2 with a GAA cell 621 directly adjacent to WL 630, where d2 < d1. The hexagonal cell 521 of structure 500 has a better margin than the margin of the square cell 621 of structure 600. The staggered GAA cell arrangement in hexagonal form relaxes the WL spacing compared to the GAA cell arrangement in square form. The WL spacing is the minimum distance between the centers of adjacent WLs in a set of WLs. The margin between two cells is the minimum distance between two cells, which for cells with GAA access transistors can be the distance between the outer boundaries of the full surround gate of the GAA access transistor.

[0032] Figures 7 to 29 Description of the formation Figure 1 The memory cell arrangement of the structure 100 is similar to the example process flow of the memory device of the embodiment. The memory cell can be 4F 2 For the processes discussed herein, the process material selection may depend on the materials selected to form the various components of the memory device and the contacts to the components. The process material may be selected to allow one or more materials to be removed while retaining one or more other materials. In addition, typical deposition techniques for the materials formed, the dimensions of the materials formed, and the architecture in which the materials are formed may be used.

[0033] Figure 7Structure 700 is shown after a block of material is formed on substrate 701. The block may include semiconductor material. For example, the block may be formed from a silicon germanium (SiGe) layer 716 on substrate 701, where substrate 701 may be a silicon substrate. The SiGe may be 15% SiGe that may be formed by an appropriate deposition process. Materials other than SiGe may be used. The thickness of the SiGe from substrate 701 may be in a range of, but not limited to, about 10 to 20 nanometers. The formation of the block of material may include an epitaxial Si layer 704 formed on SiGe. Materials other than epitaxial Si may be used. The thickness of the epitaxial Si on SiGe may be in a range of, but not limited to, about 150 nm to 300 nm, such as 200 nm. Material 735 for BL has been formed on layer 704. Material 735 for BL may be a metal or other conductive material suitable for BL. Hard mask 713 has been formed on material 735 for BL. A hard mask is a material that can be used as an etch mask in an etching process, where the material is different from a polymer or other relatively soft material (e.g., a relatively soft resist material). A hard mask is typically a high density material used in an etching process to protect certain areas of the structure being processed from the etching chemicals used in the etching process. The material 735 for the BL and the hard mask 713 can be formed by a deposition process appropriate for these areas. For example, the material 735 for the BL can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0034] Figure 8 Display Processing Figure 7 800 after structure 700. The material 735 for the BL, the hard mask 713, and the top portion of the layer 704 have been patterned to form BL strips 835, hard mask strips 813, and non-dielectric strips 804. The patterning may be accomplished by removing selected portions of the hard mask 713 on the BL material 735 on the layer 704 through a substantial portion of the layer 704. The removal may be performed by etching down about 30% through the layer 704. The etching process may result in trenches 814 between the vertical regions of the combination of the hard mask strips 813 on the BL strips 835 on the non-dielectric strips 804. The trenches 814 provide a lattice in which the pillar channels will be placed to achieve Figure 1 The structural stability of the structure 100 is an integrated solution area.

[0035] Fig. 9 Display Processing Figure 8 The structure 900 is formed after the structure 800. The lattice dielectric 920 has been formed in the trench 814 of the structure 800 and is recessed to leave a smaller trench 914. The lattice dielectric 920 can be formed by a deposition process suitable for the material of the lattice dielectric 920. The lattice dielectric 920 can include nitrogen oxide (NO X ), Si-rich nitride, aluminum oxide (AlOX ) or a combination of dielectrics. At this point in the process flow, implants may be made into the BL contact junctions in the non-dielectric strips 804. Alternatively, implants into the BL contact junctions of the non-dielectric strips 804 may be made into layer 704 before material 735 for the BL is formed on layer 704.

[0036] Fig.10 Display Processing Fig. 9 FIG. 1000 is a structure 1000 that is a successor to structure 900 of FIG. 1000. Additional material 1034 for the BL has been formed on the surface of structure 900, covering the sides of lattice dielectric 920, hard mask strips 813, and BL strips 835. Trench 914 has been reduced to trench 1014. Additional material 1034 for the BL may be a metal, a combination of metals, or other suitable conductive material. Additional material 1034 for the BL may be formed to provide a sidewall wraparound for the active area of ​​the pillar trench to be formed. Additional material 1034 for the BL may be formed by a deposition process suitable for such additional material. For example, additional material 1034 for the BL may be an ALD metal or a CVD metal. Additional material 1034 for the BL may include a complementary alloy of the material of BL strips 835 to reduce the resistance of the BL formed by the combination of BL strips 835 and additional material 1034 for the BL. The additional material 1034 for the BL may include molybdenum (Mo), cobalt (Co), ruthenium (Ru), titanium nitride (TiN), tantalum (Ta), other metal materials or combinations of metal materials for the structure of the formed BL.

[0037] Fig.11 Display Processing Fig.10 1000. Portions of the additional material 1034 for the BL have been removed to form additional BL strips 1134 and provide trenches 1114 down to the top level of the lattice dielectric 920. The hard mask strips 813 have been exposed in this process. The removal of portions of the additional material 1034 for the BL may be performed as an etching operation, thereby forming an H-shaped BL with the BL strips 835 as the center BL region and the additional BL strips 1134 as the side BL regions of the H structure.

[0038] Fig.12 Display Processing Fig.11 1. The structure 1200 after the structure 1100 of FIG. 1. A dielectric 1218 has been formed on the surface of the structure 1100 to cover the sides of the hard mask strips 813 and the additional BL strips 1134. The trenches 1114 have been filled with the dielectric 1218. The dielectric 1218 may be deposited by deposition of a material suitable for the dielectric 1218. The dielectric 1218 may be, but is not limited to, an oxide. The dielectric 1218 may be a low-k dielectric. A low-k dielectric is a dielectric having a dielectric constant that is smaller than the dielectric constant of silicon dioxide.

[0039] Fig.13 Display Processing Fig.12 1200. A bonding dielectric 1322 has been formed on dielectric 1218 and a carrier wafer 1301 has been bonded to the bonding dielectric 1322. The bonding dielectric 1322 may be polished, subjected to a (chemical mechanical polishing) CMP process, and cleaned before being bonded to the carrier wafer 1301. The formation of the bonding dielectric 1322 may be performed using a deposition process suitable for the material selected for the bonding dielectric 1322. The material of the bonding dielectric 1322 may be, but is not limited to, tetraethoxysilane (TEOS), silicon nitride carbon (SiCN) BLOk (barrier low-k) layer, high aspect ratio process (HARP) material, or a combination of similar materials.

[0040] Fig.14 Display Processing Fig.13 Structure 1400 is a structure 1400 after structure 1300. Structure 1300 has been flipped over and substrate 701 and layer 716 have been thinned from the back side to stop at the interface of layer 716 and layer 704. For the silicon-on-insulator shell of layers 704, 716, and substrate 701, the oxide-buried oxide (Box) interface of SOI can be used as a backside etch stop layer.

[0041] Fig.15 Display Processing Fig.14 1400. Portions of layer 704 and non-dielectric strips 804 have been selectively etched using a hard mask to form pillar trenches 1507 connected to non-dielectric strips 804, with dielectric 1513 from the hard mask remaining on top of pillar trenches 1507. The pillar etch has stopped on the lattice dielectric 920. At this portion of the process flow, an approximately 40% reduction in aspect ratio has been provided and structural integrity has been achieved through lattice integration. Photolithography can be used to pattern and form pillar trenches 1507 using deep ultraviolet radiation (DUV) or extreme ultraviolet radiation (EUV).

[0042] Fig.16 Representation 1600 is shown of a top view of structure 1500. Lattice dielectric 920 fills the regions between non-dielectric strips 804 and at least partially surrounds pillar trenches 1507. Representation 1600 may have an aspect ratio of about 12.

[0043] Fig.17 Display Processing Fig.161500. A dielectric material 1718 has been formed on the exposed surface of the structure 1500. A dielectric material 1723 has been formed on the dielectric material 1718. The dielectric material 1723 covers the exposed portion of the pillar trench 1507 and will provide a gate dielectric for the GAA transistor formed around the pillar trench 1507. The dielectric material 1718 may be, but is not limited to, an oxide. The dielectric material 1723 may be, but is not limited to, a gate oxide material. The dielectric material 1723 may be formed by a deposition process suitable for a selected material of the dielectric material 1723. Alternatively, the dielectric material 1723 may be formed by in-situ steam generation (ISSG), wherein the ISSG process includes generating water vapor very close to the wafer surface, thereby providing wet oxidation.

[0044] Fig.18 Display Processing Fig.17 The structure 1800 is formed after the structure 1700. A liner 1813 has been formed on the exposed surface of the structure 1700. The formation of the liner 1813 can be performed using a deposition process suitable for the material of the liner 1813. The liner 1813 can be (but is not limited to) a nitride liner. The liner 1813 has been formed as a sacrificial liner in the process flow.

[0045] Fig.19 Display Processing Fig.18 Structure 1900 after structure 1800. Liner 1813 has been selectively etched back to expose portions of dielectric material 1723. A dry etch may be used. The dry etch may be selective to dielectric material 1723, which may be a high-k dielectric or a gate oxide.

[0046] Fig. 20 Display Processing Fig.19 The structure 2000 is formed after the structure 1900 of FIG. 1900. An isolation dielectric 2018 has been formed on the exposed surface of the structure 1900. The isolation dielectric 2018 may be subjected to a CMP process that exposes the top of the dielectric material 1723. The fill of the isolation dielectric 2018 may include oxide, spin-on dielectric (SOD) material, low-k polymer, or other dielectric material.

[0047] Fig.21 Display Processing Fig. 20 2000. A photolithography process has been performed to prepare the WL, thereby providing a carbon-based hard mask 2128 on selected sections of the isolation dielectric 2018. The carbon-based hard mask 2128 is produced in the photolithography process as an underlying layer placed under the photoresist. Dry etching can be used to form a pattern of the carbon-based hard mask 2128 that separates the rows of dielectric material 1723.

[0048] Fig. 22 Display Processing Fig.21The structure 2200 is a structure 2200 subsequent to the structure 2100 of FIG. 21. The carbon-based hard mask 2128 has been removed, thereby providing a top step of the structure 2200 at the top of the dielectric material 1723. The removal process may include an oxide etch that stops on the liner 1813 between the rows of dielectric material 1723.

[0049] Fig.23 Display Processing Fig. 22 2200. The liner 1813 has been selectively removed, wherein the liner 1813 is formed as a sacrificial liner. When the liner 1813 is a sacrificial nitride, the removal process may include using a selective wet etch to remove the liner 1813 to maintain the dielectric material 1723 and the lower portion of the dielectric 2018. When the liner 1813 is a nitride, the removal of the liner 1813 may be selective to maintain an oxide or other dielectric of the dielectric material 1723. For example, the selective etchant may include a thermal phosphide. The area where the removal process has maintained the dielectric 2018 is positioned to provide isolation between the linearly arranged pillar groups covered by the dielectric material 1723.

[0050] Fig.24 Display Processing Fig.23 The structure 2400 is formed after the structure 2300. A conductive material 2427 has been formed for a gate, which may be referred to as gate 2427, and a conductive material 2430 has been formed for a WL, which may be referred to as WL 2430. The conductive material 2427 may be formed as a metal deposited to form a gate of a GAA transistor, and the conductive material 2430 may be formed as a metal deposited to form a WL. The conductive material 2430 formed has been recessed to form the shape of the conductive material 2430, such as Fig.24 Displayed in.

[0051] Fig.25 Display Processing Fig.24 Structure 2500 after structure 2400. Dielectric 2518 has been formed as a partial fill, and then a CMP process is performed to expose the top of dielectric material 1723. Dielectric 2518 can be (but is not limited to) an oxide. The junction of the cell contact of pillar trench 1507 can be implanted for coupling to a capacitor. The implant can be an n+ implant.

[0052] Fig.26 Display Processing Fig.25 The structure 2600 after the structure 2500. An etch stop layer 2669 has been formed. The etch stop layer 2669 may be formed by a deposition process suitable for the material used for the etch stop layer 2669. The etch stop layer 2669 may be a nitride etch stop layer. The etch stop layer 2669 may be, but is not limited to, SiN having a thickness of about 100 nm (depth top surface of the etch stop layer 2669). The etch stop layer 2669 has been provided for the formation of the capacitor module.

[0053] Fig. 27 Display of various dielectric components not shown Fig.26 2700 of structure 2600. Representation 2700 illustrates the relationship of pillar channel 1507, gate 2427 of the GAA transistor, WL 2430, and the H-shaped BL formed by BL strips 835 and additional BL strips 1134 relative to the lattice dielectric 920 between and contacting the non-dielectric strips 804.

[0054] Fig.28 Display Processing Fig.26 2600. The integration of capacitor modules has been performed. A group of capacitors 2829 has been formed on the etch stop layer 2669. A capping layer 2898 has been formed on top of the capacitor group 2829. When forming the capacitor, a bottom electrode 2858 coupled to the pillar channel 1507 has been formed. A top electrode 2857 separated from the bottom electrode 2858 by a capacitor dielectric 2859 has been formed. The capacitor dielectric 2859 can be formed as (but not limited to) a high-k dielectric. The capacitor process can be implemented using the same mask set used to pattern the active area. The capacitor modules can be aligned on the junction of the cell contact-active area-channel arrangement provided by the pillar channel 1507. The structure 2800 provides an array structure ready to be processed with the control and sensing circuit system of a memory device (such as a DRAM device). The capping layer 2898 can be a wafer for mounting the structure 2800 to couple to the control and sensing circuit system.

[0055] Figures 7 to 28 The process flow of the present invention provides many enhancements for memory devices (such as DRAM devices). The WL can be formed as a replacement gate for the GAA transistor, which can provide enhanced gate control. The GAA hexagonal memory cell taught herein can provide a capacitor structure that allows the use of redistribution layers (RDL) to be skipped. Typical DRAMs use RDL interconnects to rotate the cell contacts into a hexagonal form to land the capacitor. The capacitor is preferably in hexagonal form because it has the highest surface area (and therefore storage capacity) when it is hexagonal. Having a hexagonal active area does not require patterning of hexagonal RDL modules.

[0056] Various deposition techniques for components in the process flows discussed herein may be used, which are typical for the materials formed, the dimensions of the materials formed, and the architectures in which the materials are formed in the manufacture of memory devices. The materials and structures may be formed by suitable processes, such as, but not limited to, deposition processes, wherein the deposition processes may include, but not limited to, PVD, CVD, ALD, or other deposition processes. Other processes may be used. In the processing discussed with respect to the process flows, selective etching may be used to remove selected areas. Selective etching is a process in which one or more materials are removed from a structure while one or more other materials remain in the structure with little or no removal. Selective etching may depend on the material to be etched, the material not to be etched, the etchant used, and the etching method. Etching types include wet etching and dry etching, wherein each of these two basic methods includes many different etching procedures. In addition, conventional masking techniques that provide protection zones in processing may be used to remove selected areas when forming components of a memory device.

[0057] Fig.29 illustrate Fig.28 The embodiment of the example architecture 2900 in which the structure 2800 or similar structure may be positioned. The architecture 2900 is structured as a wafer-to-wafer interconnect architecture, which includes a control wafer 2902 having a bonding area 2912-2 attached to an array wafer 2901 having a bonding area 2912-1. The combination of the control wafer 2902 attached to the array wafer 2901 can be mounted on a carrier wafer 2903 or other suitable platform. The control wafer 2902 can be attached to the array wafer 2901 by performing bonding from the bonding area 2912-1 to the bonding area 2912-2. The bonding process can be performed by fusion bonding. The array wafer 2901 may include one or more of the structure 2800 or similar structures having one or more memory cell arrays. The control wafer 2902 may include a control and sensing circuit system for the operation of the memory cell array of one or more structures 2800 of the array wafer 2901 in the CoA architecture. Alternatively, the vertical sequence on the carrier wafer 2903 of the control wafer 2902 attached to the array wafer 2901 may be reversed, thereby configuring the architecture 2900 as a CuA architecture.

[0058] Fig.30 3000 is a flow chart of features of an embodiment of an example method 3000 of forming a memory device. At 3010, a memory cell array is formed, including forming each of the memory cells having a GAA transistor arranged as a hexagonal vertical channel transistor coupled to a capacitor. At 3020, a WL coupled to the gate of the GAA transistor is formed. At 3030, a BL coupled to the pillar channel of the GAA transistor is formed. The BL and the WL are separated from each other in a vertical direction. The vertical direction can be upward or downward depending on the architecture of the memory device being manufactured.

[0059] At 3040, a lattice is formed between the WL and the BL. The lattice may be formed by dielectric regions formed between and contacting non-dielectric regions and each non-dielectric region formed on and contacting the BL in the BL. Each non-dielectric region may contain a BL contact junction to a pillar channel of a set of GAA transistors extending from the non-dielectric region. The formation of the memory cell, WL, BL, and lattice may be an integrated process, which may include changing the sequencing of the processes.

[0060] Variations of method 3000 or methods similar to method 3000 may include many different embodiments, which may be combined depending on the application of such methods and / or the architecture of a system including a memory device in which such methods are implemented. Such methods may include forming each BL on a sidewall of a BL contact junction that at least partially wraps around in a non-dielectric region of the BL contact.

[0061] Variations of method 3000 or methods similar to method 3000 may include performing several procedures to form the BL and the lattice. The procedures may include forming a material for the BL on an epitaxial semiconductor region and modifying the material for the BL into strips of BL material with trenches between the strips of BL material. The trenches may extend below the material for the BL, with each trench having walls formed by strips of BL material positioned on the walls of the epitaxial semiconductor. A dielectric region may be formed in the trench, with the dielectric region having a top step lower than the top of the walls of the epitaxial semiconductor. Additional BL material may be formed on the strips of BL material in the trench and on the walls of the epitaxial semiconductor in the trench from the top of the walls of the epitaxial semiconductor to the top step of the dielectric region. The trenches may be filled with an isolation dielectric between adjacent additional BL material in the trenches. Variations may include an epitaxial semiconductor with epitaxial silicon. Variations may include the material for the BL being a first metal and the additional BL material being a second metal. The second metal may be a complementary alloy of the first metal such that the resistance of the BL of the first and second metals is lower than the resistance of the BL of the first metal alone.

[0062] Variations of method 3000 or methods similar to method 3000 may include forming WL as metal WL to the gates of GAA transistors in a first row of hexagonal vertical channel transistors such that the formed metal WL is positioned not to contact the gates of GAA transistors in rows of hexagonal vertical channel transistors adjacent to the first row.

[0063] Fig.3131 is a flow chart of features of an embodiment of an example method 3100 of forming a memory device. At 3110, an array wafer is prepared with an array of GAA transistors connected to WL and BL. Access and BL separated from each other by a lattice are formed. A lattice having dielectric regions between and contacting non-dielectric regions may be formed. Each non-dielectric region may be formed on and contacting the BL in the BL and may contain a BL contact junction to a pillar channel of a set of GAA transistors extending from the non-dielectric region.

[0064] At 3120, a control circuit system wafer is prepared. At 3130, the array wafer and the control circuit system wafer are coupled together.

[0065] Variations of method 3100 or methods similar to method 3100 may include many different embodiments, which may be combined depending on the application of such methods and / or the architecture of the system including the memory device in which such methods are implemented. Such methods may include forming each BL on the sidewall of the BL contact junction at least partially wrapped around in the non-dielectric region of the BL contact. Variations may include forming a 4F in an adjacent row of pillar trenches corresponding to the non-dielectric region. 2 The pillar channel of the shared BL in the open BL architecture.

[0066] In various embodiments, a memory device may include a memory cell array, a WL, a BL, and a lattice between the WL and the BL. Each of the memory cells has a GAA transistor arranged as a hexagonal vertical channel transistor coupled to a capacitor. The WL is coupled to the gate of the GAA transistor, and the BL is coupled to the pillar channel of the GAA transistor. The pillar channel may be structured into a vertical nanowire. The lattice between the WL and the BL may have a dielectric region between and in contact with the non-dielectric region. The placement and material selection of the lattice may be tuned to control the mechanical stability of the vertical nanowire structure. Each non-dielectric region may be positioned on and contact the BL in the BL, and may contain a BL contact junction to the pillar channel of a group of GAA transistors extending from the non-dielectric region.

[0067] As taught herein, variations of such a memory device and features thereof may include many different embodiments and features, which may be combined depending on the application of such memory devices, the format of such memory devices, and / or the architecture in which such memory devices are implemented. Variations of such memory devices may include each BL at least partially wrapping around a sidewall of a BL contact junction in a non-dielectric region of a BL contact. Variations may include each of the BLs having a center BL contacting a pair of side BLs, wherein one side BL in the pair is on an opposite side of the center BL from the other side BL in the pair, the pair of side BLs extending above and below a center digit line.

[0068] Variations of this memory device and features thereof may include each BL having a center aligned between adjacent pillar channels contacting non-dielectric regions contacting the BL. Variations may include pillar channels in a row of adjacent pillar channels corresponding to non-dielectric regions being coupled to a common BL. A given one of the WLs may have a center aligned with an active area of ​​a GAA transistor to which the given WL is coupled.

[0069] Variations of the memory device and its features may include a memory cell array of the memory device having a 4F 2 Cell configuration. Variations may include memory devices having control logic and sensing circuitry above the array. The control logic and sensing circuitry and memory cell array may be arranged in a die-to-die interconnect architecture.

[0070] Fig.32 is a schematic diagram of the electrical arrangement of components of an embodiment of an example DRAM device 3200 that may include a physical architecture having an array of memory cells arranged as hexagonal cells, wherein each of the memory cells has a GAA transistor coupled to a capacitor. The memory cells may be coupled to a BL and a WL, wherein the WL may be structured to contact the gate of the GAA transistor of the memory cell to which a given WL is coupled. A lattice may be positioned between the WL and the BL, wherein the lattice has dielectric regions between and contacting non-dielectric regions, wherein each non-dielectric region is on and contacts the BL and contains BL contact junctions to pillar channels of a set of GAA transistors extending from the non-dielectric regions. The memory cell array may be structured as described herein with respect to Figures 1 to 31 DRAM device 3200 may include memory cells 3225 arranged in rows 3254-1, 3254-2, 3254-3, and 3254-4 and columns 3256-1, 3256-2, 3256-3, and 3256-4 (for ease of presentation, Fig.32 The physical orientation of the rows and columns is not limited to Fig.32 Furthermore, although only four rows 3254-1, 3254-2, 3254-3, and 3254-4 and four columns 3256-1, 3256-2, 3256-3, and 3256-4 of four memory cells are illustrated, a DRAM device such as DRAM device 3200 may have significantly more memory cells 3225 per row or column (e.g., tens, hundreds, or thousands of memory cells).

[0071] In this example, each memory cell 3225 may include a single transistor 3221 and a single capacitor 3229, which are collectively referred to as a 1T1C (1 transistor 1 capacitor cell). One plate of the capacitor 3229 (which may be referred to as a "node plate") is connected to the drain terminal of the transistor 3221, while the other plate of the capacitor 3229 is connected to the ground 3224 or other reference node. Each capacitor 3229 of the memory cell 3225 within the 1T1C memory cell array is typically used to store one data bit, and the corresponding transistor 3221 is used as an access device to write to or read from the storage capacitor 3229. Each transistor 3221 may be implemented by a GAA nanowire transistor, as described with respect to Figures 1 to 31 Discussion.

[0072] The transistor gate terminals within each of the rows 3254-1, 3254-2, 3254-3, and 3254-4 may be part of a respective WL 3230-1, 3230-2, 3230-3, and 3230-4, and the transistor source terminals within each of the columns 3256-1, 3256-2, 3256-3, and 3256-4 may be electrically connected to a respective BL 3235-1, 3235-2, 3235-3, and 3235-4. The row decoder 3232 may selectively drive the individual WLs 3230-1, 3230-2, 3230-3, and 3230-4 in response to a row address signal 3231 input to the row decoder 3232. Driving a given WL at a high voltage causes the access transistors within the corresponding row to turn on, thereby connecting the storage capacitors within the row to the corresponding BL so that charge can be transferred between the BL and the storage capacitors for read or write operations. Both read and write operations can be performed via SA circuitry 3240, which can transfer bit values ​​between the memory cells 3225 of a selected row of rows 3254-1, 3254-2, 3254-3, and 3254-4 and an input / output buffer 3246 (for write / read operations) or an external input / output data bus 3248.

[0073] The column decoder 3242 can select which of the memory cells 3225 within the selected row is read or written in response to the column address signal 3241. Alternatively, for a read operation, the storage capacitors 3229 within the selected row can be read and latched at the same time, and the column decoder 3242 can then select which latched bits are connected to the output data bus 3248. Because the readout of the storage capacitor destroys the stored information, the read operation is accompanied by a simultaneous rewrite of the capacitor charge. In addition, between read / write operations, the capacitor charge is repeatedly refreshed to prevent data loss. The details of the read / rewrite, write and refresh operations are well known to those of ordinary skill in the art.

[0074] DRAM device 3200 may be implemented as an IC within a package that includes pins for receiving supply voltages (eg, for providing source and gate voltages for transistor 3221) and signals (including data, address, and control signals). Fig.32 DRAM device 3200 is depicted in simplified form to illustrate basic structural components related to electrical interaction, omitting many details of memory cells 3225 and associated WLs 3230-1, 3230-2, 3230-3, and 3230-4 and BLs 3235-1, 3235-2, 3235-3, and 3235-4, as well as peripheral circuitry. For example, in addition to row decoder 3232, column decoder 3242, SA circuitry 3240, and buffer 3246, DRAM device 3200 may also include additional peripheral circuitry (e.g., a memory control unit that controls memory operations based on control signals (e.g., provided by an external processor), additional input / output circuitry, or other features associated with a memory device. The details of this peripheral circuitry are well known to those of ordinary skill in the art and are not further discussed herein. The peripheral circuitry may be positioned above memory cell array 3225 in a CoA architecture using a die-to-die interconnect architecture. Alternatively, the peripheral circuitry may be located below the memory cell array 3225 in the CuA architecture. Alternatively, the peripheral circuitry may be located in a region of the IC of the memory device adjacent to the array region of the memory cell array 3225.

[0075] In a two-dimensional (2D) DRAM array, the rows 3254-1, 3254-2, 3254-3, and 3254-4 and columns 3256-1, 3256-2, 3256-3, and 3256-4 of memory cells 3225 may be arranged along a single horizontal plane of the semiconductor substrate (i.e., a plane parallel to the layers), for example, in a rectangular lattice with WLs 3230-1, 3230-2, 3230-3, and 3230-4 in one plane and BLs 3235-1, 3235-2, 3235-3, and 3235-4 in another plane. In a 3D DRAM array, the memory cells 3225 may be arranged in a 3D lattice with one set of memory cells and associated WLs and BLs at a level above another set of memory cells and their associated WLs and BLs.

[0076] With and Figures 1 to 32The associated example DRAM device 3200 and memory devices with the same or similar structural features may be implemented in various electronic devices. Electronic devices such as mobile electronic devices (e.g., smartphones, tablets, and other similar communication-related devices), electronic devices used in automotive applications (e.g., automotive sensors, control units, driver assistance systems, passenger safety systems, comfort systems, or other similar systems), and Internet-connected appliances or devices (e.g., Internet of Things (IoT) devices or other network-related devices)) have different storage requirements depending on the type of electronic device, usage environment, performance expectations, or other criteria.

[0077] Such electronic devices may be broken down into several main components: a processor (e.g., a central processing unit (CPU) or other main processor); a memory (e.g., one or more volatile or non-volatile RAM memory devices, such as DRAM, mobile or low-power double data rate synchronous DRAM (DDR SDRAM), or other similar memory devices); and a storage device (e.g., a non-volatile memory (NVM) device, such as flash memory, ROM, solid-state drive (SSD), multimedia card (MMC), other memory card structures or assemblies, or other similar storage devices). In some examples, the electronic device may include a user interface (e.g., a display, a touch screen, a keyboard, one or more buttons, or other similar interfacing structures), a graphics processing unit (GPU), a power management circuit, a baseband processor, one or more transceiver circuits, or other similar devices. As used herein, a "processor device" means any type of computing circuit, such as (but not limited to) a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit, including a group of processors or a multi-core device.

[0078] The following examples are example embodiments of devices and methods according to the teachings herein.

[0079] An example memory device 1 may include: a memory cell array, wherein each of the memory cells has a GAA transistor arranged as a hexagonal vertical channel transistor coupled to a capacitor; a WL coupled to a gate of the GAA transistor; a BL coupled to a pillar channel of the GAA transistor; and a lattice between the WL and the BL, the lattice having dielectric regions between and contacting non-dielectric regions, each non-dielectric region being on and contacting a BL in the BL and containing a BL contact junction to the pillar channels of a group of the GAA transistors extending from the non-dielectric region.

[0080] Example memory device 2 may include the features of example memory device 1 and may include each BL at least partially wrapping around a sidewall of the BL contact junction in the non-dielectric region of the BL contact.

[0081] Example memory device 3 may include features of any of the aforementioned example memory devices and may include each BL having a center aligned between adjacent pillar channels in contact with the non-dielectric region in contact with the BL.

[0082] Example memory device 4 may include features of any of the aforementioned example memory devices and may include pillar channels in adjacent rows of pillar channels corresponding to non-dielectric regions coupled to a common BL.

[0083] Example memory device 5 may include features of any of the aforementioned example memory devices and may include a given one of the WLs having a center aligned with an active area of ​​the GAA transistor to which the given WL is coupled.

[0084] Example memory device 6 may include features of any of the aforementioned example memory devices and may include each of the digit lines having a center digit line contacting a pair of side digit lines, wherein one side digit line of the pair is on a side of the center digit line opposite the other side digit line of the pair, the pair of side digit lines extending above and below the center digit line.

[0085] Example memory device 7 may include features of any of the foregoing example memory devices and may include the memory cell array having 4F 2 Unit configuration.

[0086] Example memory device 8 may include features of any of the aforementioned example memory devices and may include control logic and sensing circuitry over the array.

[0087] Example memory device 9 may include features of example memory device 8 and any of the preceding example memory devices and may include the control logic and sensing circuitry and the memory cell array arranged in a die-to-die interconnect architecture.

[0088] The example memory device 10 may include features of any of the foregoing example memory devices and may include structuring of the pillar channels into vertical nanowires.

[0089] In example memory device 11, any of the memory devices of example memory devices 1-10 may include a memory device incorporated into an electronic device further including a host processor and a communication bus extending between the host processor and the memory device.

[0090] In example memory device 12, any of the memory devices of example memory devices 1-11 may be modified to include any structure presented in another of example memory devices 1-11.

[0091] In example memory device 13, any apparatus associated with the memory devices of example memory devices 1-12 may further include a machine-readable storage device configured to store instructions as a physical state, wherein the instructions may be used to perform one or more operations of the apparatus.

[0092] In example memory device 14, any of the memory devices of example memory devices 1-13 may be formed according to any of the following example methods 1-18 of forming a memory device.

[0093] An example method 1 of forming a memory device may include: forming a memory cell array, which includes forming each of the memory cells having a GAA transistor arranged as a hexagonal vertical channel transistor coupled to a capacitor; forming a WL coupled to a gate of the GAA transistor; forming a BL coupled to a pillar channel of the GAA transistor, wherein the BL and the WL are separated from each other in a vertical direction; and forming a lattice between the WL and the BL, which includes dielectric regions formed between and contacting non-dielectric regions and forming each non-dielectric region, each non-dielectric region being on and contacting the BL in the BL and containing a BL contact junction to a group of pillar channels of the GAA transistor extending from the non-dielectric region.

[0094] Example method 2 of forming a memory device may include features of example method 1 of forming a memory device and may include forming each BL that wraps at least partially around a sidewall of the BL contact junction in the non-dielectric region of the BL contact.

[0095] Example method 3 of forming a memory device may include features of example method 2 of forming a memory device and any of the foregoing example methods of forming a memory device and may include forming the BL and the lattice including: forming material for the BL on an epitaxial semiconductor region; modifying the material for the BL into strips of BL material with trenches between the strips of BL material extending below the material for the BL, wherein each trench has walls formed by the strips of BL material positioned on walls of the epitaxial semiconductor; forming the dielectric region in the trenches having a top step lower than a top of the walls of the epitaxial semiconductor; forming additional BL material on the strips of BL material in the trenches and on the walls of the epitaxial semiconductor in the trenches from the top of the walls of the epitaxial semiconductor to the top step of the dielectric region; and filling the trench between adjacent additional BL material in the trenches with an isolating dielectric.

[0096] Example method 4 of forming a memory device may include features of example method 3 and any of the preceding example methods of forming a memory device and may include the epitaxial semiconductor including epitaxial silicon.

[0097] Example method 5 of forming a memory device may include features of example method 3 and any of the preceding example methods of forming a memory device and may include the material for the BL being a first metal and the additional BL material being a second metal.

[0098] Example method 6 of forming a memory device may include features of example method 5 and any of the preceding example methods of forming a memory device and may include that the second metal is a complementary alloy of the first metal such that a resistance of the BL of the first and second metals is lower than a resistance of the BL of the first metal alone.

[0099] Example method 7 of forming a memory device may include features of example method 6 of forming a memory device and any of the foregoing example methods of forming a memory device and may include forming the WL to include a metal WL formed to the gates of the GAA transistors in a first row of the hexagonal vertical channel transistors, such that the forming metal WL is positioned to not contact the gates of the GAA transistors in a row of the hexagonal vertical channel transistors adjacent to the first row.

[0100] In example method 8 of forming a memory device, any of example methods 1-7 of forming a memory device may be performed in forming an electronic device further comprising a host processor and a communication bus extending between the host processor and the memory device.

[0101] In example method 9 of forming a memory device, any of the example methods 1-8 of forming a memory device may be modified to include operations set forth in any other of the example methods 1-8 of forming a memory device.

[0102] In example method 10 of forming a memory device, any of example methods 1-9 of forming a memory device may be implemented at least in part by using instructions stored as a physical state in one or more machine-readable storage devices.

[0103] Example method 11 of forming a memory device may include features of any of the foregoing example methods 1-10 of forming a memory device and may include forming features associated with any of the features of example memory devices 1-14.

[0104] An example method 12 of forming a memory device may include: preparing an array wafer with an array of GAA transistors connected to WLs and BLs, wherein the WLs and the BLs are separated from each other by a lattice including dielectric regions between and contacting non-dielectric regions, wherein each non-dielectric region is on and contacts a BL in the BLs and contains a BL contact junction to pillar channels of a set of the GAA transistors extending from the non-dielectric regions; preparing a control circuitry wafer; and coupling the array wafer and the control circuitry wafer together.

[0105] Example method 13 of forming a memory device may include the features of example method 12 of forming a memory device and may include forming each BL that wraps at least partially around a sidewall of the BL contact junction in the non-dielectric region of the BL contact.

[0106] Example method 14 of forming a memory device may include features of any of the foregoing example methods 12-13 of forming a memory device and may include forming a 4F in adjacent rows of pillar channels corresponding to non-dielectric regions. 2 The pillar trench of the shared BL in an open BL architecture.

[0107] In example method 15 of forming a memory device, any of example methods 12-14 of forming a memory device may be performed in forming an electronic device further comprising a host processor and a communication bus extending between the host processor and the memory device.

[0108] In example method 16 of forming a memory device, any of example methods 12-15 of forming a memory device may be modified to include operations set forth in any other of example methods 12-15 of forming a memory device.

[0109] In example method 17 of forming a memory device, any of example methods 12-16 of forming a memory device may be implemented at least in part by using instructions stored as a physical state in one or more machine-readable storage devices.

[0110] Example method 18 of forming a memory device may include features of any of the foregoing example methods 12-17 of forming a memory device and may include forming features associated with any features of example memory devices 1-14.

[0111] An example machine-readable storage device storing instructions that, when executed by one or more processors, cause the machine to perform operations may include instructions for performing functions associated with any feature of example memory devices 1-14 or performing methods associated with any feature of example methods 1-18 of forming a memory device.

[0112] Although specific embodiments have been illustrated and described herein, it should be appreciated by those of ordinary skill in the art that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. Various embodiments use permutations and / or combinations of the embodiments described herein. It should be understood that the above description is intended to be illustrative rather than limiting, and that the phraseology or terminology employed herein is for descriptive purposes.

Claims

1. A memory device, comprising: a memory cell array wherein each of the memory cells has a gate-all-around GAA transistor arranged as a hexagonal vertical channel transistor coupled to a capacitor; an access line coupled to a gate of the GAA transistor; a digit line coupled to the pillar channel of the GAA transistor; and a lattice between the access lines and the digit lines, the lattice having dielectric regions between and contacting non-dielectric regions, each non-dielectric region being on and contacting a digit line of the digit lines and containing digital contact junctions to the pillar channels of a group of the GAA transistors extending from the non-dielectric regions.

2. The memory device of claim 1, wherein each digit line at least partially wraps around a sidewall of the digit contact junction in the non-dielectric region of the digit line contact.

3. The memory device of claim 1, wherein each digit line has a center aligned between adjacent pillar channels in contact with the non-dielectric region in contact with the digit line.

4. The memory device of claim 1, wherein pillar channels in adjacent rows of pillar channels corresponding to non-dielectric regions are coupled to a common digit line.

5. The memory device of claim 1, wherein a given one of the access lines has a center aligned with an active area of ​​the GAA transistor to which the given access line is coupled.

6. The memory device of claim 1 , wherein each of the digit lines has a center digit line contacting a pair of side digit lines, wherein one side digit line of the pair is on a side of the center digit line opposite the other side digit line of the pair, the pair of side digit lines extending above and below the center digit line.

7. The memory device of claim 1, wherein the memory cell array has a 4F 2 Unit configuration.

8. The memory device of claim 1, wherein the memory device includes control logic and sensing circuitry above the array.

9. The memory device of claim 8, wherein the control logic and sensing circuitry and the memory cell array are arranged in a die-to-die interconnect architecture.

10. The memory device of claim 1, wherein the pillar channels are structured as vertical nanowires.

11. A method of forming a memory device, the method comprising: forming a memory cell array including forming each of the memory cells with a gate-all-around (GAA) transistor arranged as a hexagonal vertical channel transistor coupled to a capacitor; forming an access line coupled to a gate of the GAA transistor; forming a digit line coupled to a pillar channel of the GAA transistor, wherein the digit line and the access line are separated from each other in a vertical direction; and A lattice is formed between the access lines and the digit lines, including dielectric regions formed between and contacting non-dielectric regions and forming each non-dielectric region, each non-dielectric region being on and contacting a digit line in the digit lines and containing a digital contact junction to a pillar channel of a group of the GAA transistors extending from the non-dielectric regions.

12. The method of claim 11, wherein the method includes forming each digit line that wraps at least partially around a sidewall of the digit contact junction in the non-dielectric region of the digit line contact.

13. The method of claim 11 , wherein forming the digit lines and the lattice comprises: forming a material for the digital line on the epitaxial semiconductor region; modifying the material for the digit lines into strips of digit line material with trenches between the strips of digit line material, the trenches extending beneath the material for the digit lines, wherein each trench has walls formed by the strips of digit line material positioned on walls of the epitaxial semiconductor; forming the dielectric region in the trench having a top level lower than a top of the wall of the epitaxial semiconductor; forming additional digit line material over the strip of digit line material in the trench and on the walls of the epitaxial semiconductor in the trench from the top of the walls of the epitaxial semiconductor to the top step of the dielectric region; and The trenches between adjacent additional digit line materials in the trenches are filled with an isolation dielectric. The method of claim 13 , wherein the epitaxial semiconductor comprises epitaxial silicon.

15. The method of claim 13 wherein the material for the digit line is a first metal and the additional digit line material is a second metal.

16. The method of claim 15, wherein the second metal is a complementary alloy of the first metal such that a digit line of the first and second metals has a lower resistance than a digit line of the first metal alone.

17. The method of claim 16, wherein forming the access line comprises forming a metal access line to the gates of the GAA transistors in a first row of the hexagonal vertical channel transistors such that the formed metal access line is positioned to not contact the gates of the GAA transistors in a row of the hexagonal vertical channel transistors adjacent to the first row.

18. A method of forming a memory device, the method comprising: preparing an array wafer with an array of all-around gate GAA transistors connected to access lines and digit lines, wherein the access lines and the digit lines are separated from each other by a lattice including dielectric regions between and contacting non-dielectric regions, wherein each non-dielectric region is on and contacts a digit line of the digit lines and contains a digital contact junction to pillar channels of a group of the GAA transistors extending from the non-dielectric regions; Preparation of control circuit system chip; and The array chip and the control circuit system chip are coupled together.

19. The method of claim 18, wherein the method includes forming each digit line that wraps at least partially around a sidewall of the digit contact junction in the non-dielectric region of the digit line contact.

20. The method of claim 18, wherein the method comprises forming a 4F 2 The pillar channels of the shared digit lines in an open digit line architecture.

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