Memory device with hexagonal memory cells

Abstract

The invention relates to a memory device with hexagonal memory cells. Various applications may include a memory device having an array of memory cells arranged as hexagonal cells, wherein each of the memory cells has a gate-all-around (GAA) transistor coupled to a capacitor. An access line may be coupled to gates of a first plurality of GAA transistors of the memory cell. A digital line may be coupled to a second plurality of GAA transistors of the memory cell, wherein the digital line is separated from adjacent digital lines by an air gap. Additional apparatus and methods are disclosed.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to integrated circuits, and more particularly, to memory devices and the formation thereof. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices (ICs). There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain its data, and includes random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), or synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can retain stored data when power is not supplied, and includes flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistance variable memory (e.g., phase change random access memory (PCRAM)), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), or three-dimensional (3D) XPoint TM Memory, etc. The properties of memory devices and other electronic devices can be improved by enhancing the design and fabrication of components of the electronic devices, such as, but not limited to, memory devices used in ICs of the electronic devices. Summary of the invention

[0003] In one aspect, the present disclosure provides a memory device comprising: an array of memory cells arranged as hexagonal cells, wherein each of the memory cells has a gate all around (GAA) transistor coupled to a capacitor; access lines having a first access line coupled to gates of a plurality of GAA transistors of a first group of the memory cells; and digit lines having a first digit line coupled to a plurality of GAA transistors of a second group of the memory cells, each of the digit lines being separated from an adjacent digit line by an air gap.

[0004] In another aspect, the present disclosure provides a method of forming a memory device, the method comprising: forming an array of memory cells, comprising forming the memory cells of the array as hexagonal cells, and forming each of the memory cells as a gate-all-around (GAA) transistor having a capacitor coupled to it; forming access lines, wherein a first one of the access lines is coupled to gates of a plurality of GAA transistors of a first group of the memory cells; and forming digit lines, wherein a first one of the digit lines is coupled to a plurality of GAA transistors of a second group of the memory cells, each of the digit lines being separated from an adjacent digit line by an air gap.

[0005] In yet another aspect, the present disclosure provides a method of forming a memory device, the method comprising: preparing an array wafer having an array of gate-all-around (GAA) transistors connected to access lines and digit lines, wherein the digit lines are separated from adjacent digit lines by air gaps; preparing a control circuit system wafer; and coupling the array wafer and the control circuit system wafer together. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The drawings, which are not necessarily drawn to scale, generally illustrate the various embodiments discussed in this document by way of example and not by way of limitation.

[0007] Figure 1 Representations of example arrays of memory cells arranged as hexagonal memory cells are illustrated in accordance with various embodiments.

[0008] Figure 2 Example structures that may be arranged as part of a memory cell array of a memory device according to various embodiments are described.

[0009] Figure 3 Examples of arrangements of access lines and gates of gate-all-around transistors according to various embodiments are illustrated.

[0010] Figure 4 Examples of arrangements of access lines and gates of gate-all-around transistors according to various embodiments are illustrated.

[0011] Figure 5 Description of the usable Figure 2 1 is a top view of an example arrangement of a gate-all-around transistor for a memory cell implemented with a structure of FIG.

[0012] Figure 6 Embodiments of example structures having a folded architecture in which memory cells having gate-all-around transistors may be implemented are described according to various embodiments.

[0013] Figure 7 A top view illustrating a representation of an open digit line architecture of one or more memory cell arrays according to various embodiments, wherein each memory cell includes a gate-all-around transistor coupled to a capacitor.

[0014] Figure 8 A structure with an arrangement of memory cells according to various embodiments is illustrated, wherein each memory cell has an access transistor and a capacitor, wherein the access transistor is a gate-all-around transistor.

[0015] Figures 9 to 36 The invention describes a method for forming a Figure 8 An example process flow for a memory device of an arrangement of memory cells of a structure.

[0016] Fig.37 Description of the various embodiments of the present invention Fig.34 struct or an instance architecture of a similar structure.

[0017] Fig.38 is a flow chart of features of an example method of forming a memory device in accordance with various embodiments.

[0018] Fig.39 is a flow chart of features of an example method of forming a memory device in accordance with various embodiments.

[0019] Fig.40 is a schematic diagram of an electrical arrangement of components of an example dynamic random access memory device that may include an architecture having hexagonal memory cells with all-around gate transistors in accordance with various embodiments. DETAILED DESCRIPTION

[0020] The following detailed description refers to the accompanying drawings that show various embodiments that can be implemented in an illustrative manner. These embodiments are described in sufficient detail to enable those skilled in the art to practice these and other embodiments. Other embodiments may be utilized, and structural changes, logical changes, mechanical changes, and electrical changes may be made to these embodiments. The term "horizontal" used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term "vertical" refers to a direction perpendicular to the horizontal as defined above, and may be in a direction from horizontal or to horizontal. Various features may have a vertical component relative to their structural direction. Various embodiments are not necessarily mutually exclusive, because some embodiments may be combined with one or more other embodiments to form new embodiments. Therefore, the following detailed description should not be understood in a restrictive sense.

[0021] In various embodiments, a memory device may be structured to have an array of memory cells arranged as hexagonal cells, wherein each of the memory cells has a gate-all-around (GAA) transistor coupled to a capacitor. A hexagonal memory cell is a memory cell surrounded by six other memory cells, such that the other memory cells are located at the vertices of a hexagonal structure formed by connecting the centers of the neighboring memory cells of these other memory cells. A GAA transistor is a transistor structured such that the gate of the transistor is coupled to the channel structure of the transistor on all sides of the channel structure. A GAA transistor may be structured as a thin film transistor (TFT). A GAA transistor may be structured into a columnar arrangement containing an active region (source and drain) and a channel structure, with the gate structured around the channel structure. The columnar structure of the GAA transistor may be structured as a semiconductor nanowire. A nanowire is a nanostructure having a nanometer-scale diameter. A GAA nanowire transistor as an access device to a capacitor in a memory cell of a DRAM may provide an enhanced I ON capability and transistor threshold voltage (V T ) can be adjusted flexibly. ON is the on-state current of the transistor, where the current I OFF is the off-state current of the transistor. ON / I OFF It is the quality factor of the transistor for high performance and low leakage power. High performance and more I ON associated with low leakage power and less I OFF Associated.

[0022] A memory device having one or more arrays of hexagonal memory cells of GAA transistors can be implemented with control logic and sensing circuitry in several different architectures. The control logic and sensing circuitry can be positioned in a peripheral region adjacent to an array of hexagonal memory cells on a wafer as an IC chip. Another compatible architecture includes control logic and sensing circuitry positioned below one or more memory arrays in a circuit under array (CuA) architecture. The control logic and sensing circuitry can be arranged to sense the programmed data states of memory cells of one or more memory arrays of a memory device, and can enhance the reduction of die size or increase the utilization of space in a die or die combination. CuA generally refers to a circuitry positioned in a memory die below a memory array of a memory die. CuA can also be referred to as CMOS below an array by virtue of the control logic and sensing circuitry fabricated below a memory array using semiconductor processing that can include CMOS (complementary metal oxide semiconductor) processing technology. Another compatible architecture can include control logic and sensing circuitry positioned above a memory array in a circuit over array (CoA) architecture. The control logic and sensing circuit system may be arranged to sense the programmed data state of the memory cells of one or more memory arrays of the memory device, and may enhance the reduction of the die size or increase the utilization of the space in the die or die combination. CoA generally refers to the circuit system located in the memory die above one or more memory arrays of the memory die. CoA may also be referred to as CMOS above the array by virtue of the control logic and sensing circuit system manufactured above one or more memory arrays using semiconductor processing that may include CMOS. CuA architecture and CoA architecture may be implemented by wafer-to-wafer architecture, wherein the control logic and sensing circuit system are formed on one wafer, and one or more memory arrays are formed on another wafer, wherein the two wafers are combined. Wafer-to-wafer interconnect architecture may include wafer-on-wafer architecture. Wafer-to-wafer bonding of back-to-back wafers with CoA architecture may provide for the movement of capacitor modules for data storage in DRAM to the bottom of the wafer stack. This arrangement may reduce interconnect congestion between stacked wafers.

[0023] The memory device may include a set of access lines (WLs), wherein each WL in the set of WLs may be coupled to the gates of a first set of multiple GAA transistors of a memory cell of a memory array. Each WL may be formed together with a corresponding gate of a GAA transistor formed in a replacement gate process, which may provide enhanced gate control. The memory device may include a set of digit lines (BLs), wherein each BL in the set of BLs may be coupled to a second set of multiple GAA transistors of a memory cell. Each of the BLs may be separated from an adjacent BL by an air gap. An air gap is a low-k dielectric. A low-k dielectric is a dielectric having a dielectric constant less than that of silicon dioxide. Dielectrics having a dielectric constant lower than that of silicon dioxide (dielectric constant of approximately 3.9) and silicon nitride (dielectric constant of approximately 7) may provide better isolation, thereby reducing crosstalk between metal lines. An air gap in a structure or between structures is a gap or region filled with air. In this article, the term air gap may include an ambient gas enclosed in the gap, such as a gas used during gap formation or a gas byproduct formed during gap formation. The air gap may have a dielectric constant equal to 1. In addition, each of the WLs may be separated from an adjacent WL by an air gap. Each BL may at least partially wrap around the sidewalls of the active area of ​​each GAA transistor of the second group. The BL may be placed in the memory device at a 90° angle relative to the WL, with the BL and the WL separated vertically.

[0024] BL can be a damascene digital. In a damascene process, a dielectric is first formed and patterned on the structure, and then metal is formed to fill the patterned dielectric. Metal formation can be achieved by a process suitable for the metal being formed, such as suitable metal deposition. Damascene digital can provide better digital resistance.

[0025] The memory device may have 4F 2 Memory array configuration or 8F 2 Memory array configuration. Using nF 2 The formula measures memory cell size, where "n" is a constant derived from the cell design and "F" is the minimum feature size of the process technology. 2 The unit repeating unit of the unit may be a parallelogram having sides of equal length 2F. 8F 2 The unit repeating unit of the cell may be a parallelogram with sides of 2F and 4F. For the same feature size, as the cell size gets smaller, the memory capacity increases. 2 In the memory cell configuration, the WL pitch and the BL pitch are equal to 2F.

[0026] Figure 1 A representation 100 of an embodiment illustrates an example array of memory cells 121 arranged as hexagonal memory cells. For ease of presentation, the Figure 1and similar features in subsequent figures without labeling all similar features. The memory cells 121 are arranged as cells in the xy plane, where the nearest neighbors form a hexagon 133. The unit repeating unit of the memory cell 121 is a parallelogram with sides of equal length 2a and a height h, and its area is 2ah, which is approximately 3.46a 2 . With an area of ​​4a 2 Compared with the square unit repeating unit, the hexagonal unit can provide more than 4F 2 The square cell in the architecture is about 13.4% smaller than the cell in the architecture. The hexagonal memory cell with GAA transistor as the access transistor can be 2 The shared BL of the memory cells in the architecture provides a relaxed critical dimension (CD). In addition, GAA hexagonal 4F 2 The unit can provide more than GAA square 4F 2 The WL spacing between the nearest cells of different BLs is larger and the tolerance is shorter. The WL spacing is the minimum distance between the centers of adjacent WL lines in a set of WLs. The tolerance between two cells is the minimum distance between two cells, which for cells with GAA access transistors can be the distance between the outer boundaries of the full-surround gate of the GAA access transistor.

[0027] 8F 2 The GAA transistors in the architecture enable the implementation of a folded BL architecture. In a folded BL array architecture, BLs are wired in pairs across the array. The close proximity of the paired BLs provides superior common-mode noise rejection compared to an open BL array. In an open BL architecture, the BL is divided into multiple segments, and a differential sense amplifier (SA) for reading the state of the memory cell is placed between the BL segments.

[0028] The GAA hexagonal memory cell can be implemented in different three-dimensional compact architectures, such as CoA and CuA architectures. As taught herein, the GAA hexagonal memory cell can provide a capacitor structure that allows the use of redistribution layers (RDLs) to be skipped. Typical DRAMs use RDL interconnects to rotate the cell contacts into a hexagonal form for capacitor landing. The capacitor is preferably in hexagonal form because it has the highest surface area (and therefore storage capacity) when it is hexagonal. With a hexagonal active area, the need for patterning hexagonal RDL modules is removed. In addition, air gap integration of BL and WL to the GAA hexagonal cell can be direct, providing enhanced design control over BL capacitance and WL capacitance.

[0029] Figure 2An embodiment of an example structure 200 that can be arranged as part of a memory cell array of a memory device is illustrated. The structure 200 includes two vertical memory cells 221-1 and 221-2, each of which has a GAA transistor coupled to a capacitor. The memory cell 221-1 includes a GAA transistor implemented by a pillar 207-1, which provides a channel, and a full-surround gate 227-1 is positioned around the channel above the active area 206-1 of the pillar 207-1 and below the active area 208-1 of the pillar 207-1. The GAA transistor of the memory cell 221-1 can be coupled to the capacitor 239-1 of the memory cell 221-1 through a cell contact 219-1, which can be positioned around the junction of the active area 208-1. Memory cell 221-2 includes a GAA transistor implemented by pillar 207-2, which provides a channel, and a fully surrounding gate 227-2 is positioned around the channel above the active area 206-2 of pillar 207-2 and below the active area 208-2 of pillar 207-2. The GAA transistor of memory cell 221-2 can be coupled to a capacitor 239-2 of memory cell 221-2 through a cell contact 219-2, which can be positioned around the junction of active area 208-2.

[0030] Memory cell 221-1 is coupled to WL 230-1 through gate 227-1. Memory cell 221-2 is coupled to WL 230-2 through gate 227-2. WL 230-1 and WL 230-1 are separate WLs in the array in which memory cell 221-1 and memory cell 221-2 are located. Memory cell 221-1 and memory cell 221-2 share a common BL 235. BL 235 may at least partially wrap around active region 206-1 and may at least partially wrap around active region 206-2.

[0031] Where appropriate, Figure 2 The dielectric material isolating the electronic components of memory cells 221-1 and 221-2 is not shown in FIG. Although not shown, the separation of WL 330-1 and WL 330-2 from each other may include an air gap. BL 235 may be separated from an adjacent BL of the memory device by an air gap. In addition, Figure 2 The BL and air gap separating BL 235 are not shown in FIG. 2 to focus on the relative arrangement of memory cell 221-1 and memory cell 221-2. Optionally, although not shown, the separation of BL 235 from the additional BLs may include a digital shield, which is a conductive structure.

[0032] Pillars 207-1 and 207-2 may be implemented as nanowires. Pillar spacing may vary in the range of about 28 nm to about 50 nm, but is not limited thereto. In the case where WL 230-1 and WL 230-2 are in contact with or integrated with gates 227-1 and 227-2, respectively, WL height 205-3 may be about 50% greater than junction height 205-1 of active regions 206-1 and 206-2 and junction height 205-2 of active regions 208-1 and 208-2. Different relative heights may be implemented depending on the application.

[0033] Figure 3 An embodiment of an example arrangement 300 of a WL 330 and a gate 327 of a GAA transistor is illustrated. The WL 330 may contact the gate 327 at a bottom portion of the arrangement 300. The WL 330 may have, but is not limited to, a height 315-1 that is equal to a height 315-2 of the gate 327. Alternatively, although not shown, the WL 330 may contact the gate 327 at a top portion of the arrangement 300.

[0034] Figure 4 An embodiment of an example arrangement 400 of a WL 430 and a gate 427 of a GAA transistor is illustrated. The WL 430 is generally attached along the side of the gate 427. The WL 430 may be integrated with the gate 427 during manufacturing. The height 415 of the WL 430 may be, but is not limited to, the height of the gate 427 or substantially equal to the height of the gate 427. The height 415 may be less than Figure 3 The sum of the heights 315-1 and 315-2.

[0035] Figure 5 Description Available Figure 2 200. Each transistor includes a vertical channel 507 surrounded by a gate dielectric 523, wherein the gate dielectric 523 separates the vertical channel 507 from a fully surrounding gate 527. A WL 530 is coupled to each GAA transistor in a given set of GAA transistors. The vertical channel 507 can be, but is not limited to, a polysilicon channel, and the gate dielectric 523 can be an oxide. The fully surrounding gate 527 and the WL 530 can be metal structures. Figure 3 Arrangement 300 or Figure 4 The arrangement 400 is used to implement the coupling of a given set of GAA transistors to a particular WL 530.

[0036] The center of the WL 530 may be aligned with the center of the active area of ​​the GAA transistor, which may be structured as the center of the pillar providing the channel 507. The WL 530 is not shared with an immediately adjacent memory cell, where the separation from the immediately adjacent memory cell is provided by a dielectric 518. The dielectric 518 separates each of the WLs 530 from each other. Along a given WL 530, a plurality of GAA transistors in a group of GAA transistors are configured in a generally linear arrangement, where GAA transistors adjacent to the plurality of GAA transistors in the group are not electrically coupled to the given WL 530. An immediately adjacent GAA transistor in an immediately adjacent WL 530 may be separated from a GAA transistor in a given WL 530 by a distance d07, which may be equal to the separation from an immediately adjacent GAA transistor in the same given WL 530. In the case where the pillar for the channel 507 is a nanowire, the size of the components of the GAA transistors and the direct separation of the GAA transistors may be on the order of nanometers or tens of nanometers.

[0037] Figure 6 An embodiment of an example structure 600 having a folded architecture is illustrated in which memory cells having GAA transistors may be implemented. The structure 600 may include an array of memory cells 621. Different groups of memory cells 621 are coupled to different WLs 630. Each WL 630 is electrically coupled to a group of memory cells, and each WL 630 is not shared with adjacent bits in another group of memory cells electrically coupled to an adjacent WL 630, where the bits are stored in the memory cells 621. In the folded architecture, BLs are wired in pairs across the array, where the pairs may include D1 and D1*, D2 and D2*, D3 and D3*, and other pairs. Each pair of BLs may be adjacent to each other and pulled from the same array tile to the same SA. A tile (also referred to as a pad) is a structure for a sub-array of memory cells of a larger memory array of a memory device, such as Figure 8 Instance structure 800 and Fig.34 3400. The folded BL architecture may also be referred to as a folded SA architecture. Each BL in the pair is electrically coupled to a set of memory cells, and each BL is not shared with adjacent bits in another set of memory cells electrically coupled to an adjacent WL 630. In addition, each memory cell is coupled to one WL 630 and one BL of one of the pair of BLs, such as Figure 6 The pair of BLs is wired to SA 639 to read the state contained in the selected memory cell. 8F of a memory cell based on GAA transistors 2 The architecture may be implemented with a data topology of a folded BL architecture with separate WLs and separate BLs for each bit.Folded bit lines are advantageous due to their reduced array noise.

[0038] Figure 7A representation 700 of an open BL architecture is shown, where each memory cell includes a GAA transistor coupled to a capacitor. The BL is located on a different physical level of the memory device than the WL. In the open BL architecture, the BL is divided into multiple segments, and differential SAs are placed between the BL segments. The BL can be acquired in pairs, where the BL is acquired from different tiles. Each path can be composed of Figure 8 700. The open BL architecture may be referred to as an open SA architecture. The open BL architecture of representation 700 may include SA739-0, 739-1, and 739-2 in different portions of the memory device structure. BLs D1, D2, D3, and D4 are in a region 797 including multiple WLs, wherein each WL 730 is not shared with any adjacent bits. For example, region 797 may include each WL 730 having a set of multiple memory cells 721, wherein the memory cells 721 adjacent to a given WL 730 are not addressed by the given WL 730. Each WL 730 may be integrated with the gate of the GAA transistor of each memory cell 121 of the set of multiple memory cells 721 addressable by the given WL 730. BLs D1*, D2*, D3*, and D4* are in a region 796 including multiple WLs 730, wherein each WL 730 is not shared with any adjacent bits. For example, region 796 may include each WL 730 having a set of multiple memory cells 721, wherein memory cells 721 adjacent to a given WL 730 are not addressed by the given WL 730. Each WL 730 may be integrated with the gate of a GAA transistor of each memory cell 121 of the set of multiple memory cells 721 addressable by the given WL 730.

[0039] BL D1 and D3 may be coupled to SA 739-1, which may be referred to as an odd SA, and BL D2 and D4 may be coupled to SA 739-0, which may be referred to as an even SA. BL D1* and D3* may be coupled to SA 739-1, and BL D2* and D4* may be coupled to SA 739-2, which may be referred to as an even SA. Regions 797 and 796 may be formed in separate subtractive processes. A subtractive process includes removing material from a solid block of starting material.

[0040] Figure 8A structure 800 having a memory cell arrangement is illustrated, wherein each memory cell has an access transistor and a capacitor, wherein the access transistor is a GAA transistor coupled to a BL, wherein the BL is separated from the immediately adjacent BL by an air gap. Various dielectric regions are not shown to focus on the functional components of the structure 800. The memory cells are arranged on a wafer 801, which may be referred to as an array wafer 801 because the memory cells are structured at a level above the wafer 801. A bonding dielectric 822 is positioned on the array wafer 801, wherein the bonding dielectric 822 is structured to be bonded to the array wafer 801 during formation of the memory cells. A dielectric 813-2 is positioned on the bonding dielectric 822. A BL 835 is positioned above the bonding dielectric 822 and above the dielectric 813-1. Each BL 835 is separated from the immediately adjacent BL by an air gap 837.

[0041] The semiconductor pillars 807 extend above the level of approximately the top of the dielectric 813-2. The semiconductor pillars 807 can be implemented as nanowires. Each semiconductor pillar 807 includes a channel between two source / drain regions. For each semiconductor pillar 807, a gate dielectric (as shown) is positioned around the channel provided by the semiconductor pillar 807. A gate 827 is positioned around each gate dielectric and semiconductor pillar 807, with a WL 830 contacting the gate 827. The gates 827 and WL 830 can be structured in a format where the WL 830 is integrated with multiple gates 827, such as Figure 8 807 is shown in the x-direction. The two source / drain regions of each semiconductor pillar 807 are active regions. Each active region may include a contact junction. For each semiconductor pillar 807, the channel is coupled to the capacitor through an active region 808 having a cell contact junction, and is coupled to the BL 835 through an active region 806 having a digital contact junction (the digital contact may be referred to as a bit contact / bitcon). Each BL 835 may be at least partially wrapped around the sidewalls of the active region 806, which provides a BL integrated with a memory cell. The active region 806 and the BL 835 may be structured in a format in which the BL 835 is integrated with the active region 806, such as Figure 8 835. The bit contact junction region may be configured as a shield to reduce capacitance between BLs. Alternatively, a digital shield may be optionally structured between adjacent BLs 835.

[0042] A dielectric 869 is positioned above the WL 830 and the gate 827. The dielectric 869 is created by processing the structure 800 and provides electrical isolation for the conductive components in the structure 800. Above the dielectric 869 is a set of capacitors 829. Each capacitor 829 includes a capacitor dielectric 859 between two electrodes 857 and 858. The electrode 858 may be referred to as a bottom electrode coupled to the active region 808 of the semiconductor pillar 807, while the electrode 857 is a top electrode that may be coupled to a reference node. The capacitor dielectric may be, but is not limited to, a high-k dielectric. A high-k dielectric is a dielectric having a dielectric constant greater than that of silicon dioxide. The structure 800 may include a dielectric region 898 or a connection wafer on the set of capacitors 829.

[0043] Figures 9 to 36 Description of the formation has similar Figure 8 An example process flow of a memory device of the structure 800 is shown. The memory cells may be arranged to have 4F 2 Architecture or 8F 2 Architecture. For the processes discussed herein, the choice of process materials may depend on the materials selected to form the various components of the memory device and the contacts to the components of the memory device. The process materials may be selected to allow removal of one or more materials while retaining one or more other materials. In addition, deposition techniques that are typical for the materials being formed, the dimensions of the materials being formed, and the architecture in which the materials are formed may be used.

[0044] Fig. 9 The structure 900 is shown after a block of material is formed on a substrate 911. The block may be a semiconductor material. For example, the block may be formed with a silicon germanium (SiGe) layer 916 on a substrate 911, where the substrate 911 may be a silicon substrate. The SiGe may be 15% SiGe, which may be formed by an appropriate deposition process. Materials other than SiGe may be used. The thickness of the SiGe from the substrate 911 may be, but is not limited to, a range between approximately 10 and 20 nanometers. The formation of the block of material may include an epitaxial Si layer 904 formed on the SiGe. Materials other than epitaxial Si may be used. The thickness of the epitaxial Si on the SiGe may be, but is not limited to, a range between approximately 150nm and 300nm. After the epitaxial Si is formed, a hard mask 913 may be formed on the epitaxial Si. A hard mask is a material that can be used as an etch mask in an etching process, wherein the material is different from a polymer or other relatively soft material, such as a relatively soft resist material. A hard mask is typically a high-density material used in an etching process to protect certain areas of the structure being processed from the effects of etching chemicals used in the etching process.

[0045] Fig.10 Display in processing Fig. 91000 after structure 900 of FIG. The channel of the GAA transistor has been patterned and formed into a pillar 1007 from layer 904, wherein portions of layer 904 are removed, which leaves layer 916 or portions of layer 916. Alternatively, portions of layer 904 of structure 900 may remain with layer 916 in the substrate of pillar 1007 from the process of forming pillar 1007. In the case where layer 904 of structure 900 is epitaxial Si, pillar 1007 is a pillar of epitaxial Si. Photolithography may be used to pattern and form pillar 1007 using deep ultraviolet radiation (DUV) or extreme ultraviolet radiation (EUV). Pillar 1007 may be formed to have, but is not limited to, a channel diameter in the range of approximately 6 nm to 20 nm. A channel may be formed for a GAA access device having a diameter in the range of approximately 20 nm to 50 nm. Other diameters may be used.

[0046] Fig.11 Display in processing Fig.10 1000. A dielectric 1118 has been formed on layer 916 to fill the spaces between pillars 1007. Dielectric 1118 and pillars 1007 have been subjected to a chemical mechanical polishing (CMP) process, thereby exposing the top surfaces of pillars 1007 to dielectric 1118. Dielectric 1118 may be formed by a deposition process suitable for a material of dielectric 1118. Dielectric 1118 may be an oxide, such as, but not limited to, silicon oxide.

[0047] Fig.12 Display in processing Fig.11 1100. A hard mask 1213 has been formed on the top surface of the structure 1100 and patterned. The hard mask 1213 may be formed by a deposition process suitable for the material of the hard mask 1213. The hard mask 1213 has been patterned and a portion of the dielectric 1118 has been removed. The patterning provides a pattern for forming a damascene structure for forming a BL. The removal of a portion of the dielectric 1118 has exposed the sidewalls of the pillars 1007. The exposed sidewalls of the pillars 1007 are processed as active areas for the GAA transistors to be formed, wherein the exposed sidewalls are implanted to form a dielectric layer for use in forming a GAA transistor having a Figure 8 The structure 800 is a memory device process flow for forming a junction of a capacitor bit contact in the arrangement of the memory cell. After the implant process, the structure may be subjected to an implant cleaning process.

[0048] Fig.13 exhibit Fig.12 1300 is a representation of a top view of structure 1200. Patterning of hard mask 1213 provides separation lines of hard mask 1213. Each line of hard mask 1213 is over a group of pillars 1007, where pillars 1007 are effectively arranged in a row in a linear manner.

[0049] Fig.14 Display in processing Fig.12 The structure 1400 is formed after the structure 1200. Metal 1435 has been formed on the hard mask 1213 and in the spaces between the lines of the hard mask 1213, as shown in FIG. Fig.13 , on the exposed surface of structure 1200. Metal 1435 may be formed at the relevant location by a deposition process suitable for the metal formed on the exposed surface of structure 1200. Metal 1435 may be suitably formed at a pitch in the range of 7 nm to 12 nm.

[0050] Fig.15 exhibit Fig.14 1500 is a representation of a top view of structure 1400. In this view, metal 1435 formed on the top surface of hard mask 1213 is not shown to illustrate metal 1435 formed in the space between the lines of hard mask 1213 and the wrapped pillars 1007. The pillars 1007 are located on the left and right sides of each line of hard mask 1213.

[0051] Fig.16 Display in processing Fig.14 Structure 1600 is a structure after structure 1400. Metal 1435 has been etched through to form isolation trenches. Fig.17 exhibit Fig.16 A representation 1700 of a top view of structure 1600 is shown. Metal 1435 lines are formed on each side below the lines of hard mask 1213. Metal 1435 is formed to at least partially wrap around pillar 1007. Fig.15 Isolation provided by post metal stamping is shown with metal 1435 on both sides of the isolation trench. There may be a minimum metal to metal spacing, such as but not limited to about 5 nm.

[0052] Fig.18 Display in processing Fig.16 1600. A dielectric 1813 has been formed on the exposed surface of the structure 1600. The dielectric 1813 covers the hard mask 1213 and the metal 1435. The material of the dielectric 1813 may be the same as the material of the hard mask 1213. The formation of the dielectric 1813 may be performed using a deposition process suitable for the material selected for the dielectric 1813. The deposition process has been selected to provide an air gap 1837 between each line of the metal 1435 and the immediately adjacent line of the metal 1435. Typically, the air gap formation may be performed based on non-conformal deposition, which pinches off the top of the patterned structure without filling the small trenches between the metal lines. Physical vapor deposition (PVD) that does not fill the high aspect ratio gap structure may provide a relatively cheap and direct way to form the air gap. In the case where the dielectric 1813 is a nitride, PVD may be used to deposit the nitride to pinch off the top of the dielectric 1813 being formed.

[0053] Fig.19 Display in processing Fig.18 1800. A bonding dielectric 1922 has been formed on dielectric 1813. Bonding dielectric 1922 may be polished, subjected to a CMP process, and cleaned. The formation of bonding dielectric 1922 may be performed using a deposition process suitable for the material selected for bonding dielectric 1922. The material for bonding dielectric 1922 may be, but is not limited to, tetraethoxysilane (TEOS), silicon carbon nitride (SiCN), a material for high aspect ratio process (HARP), or a combination of similar materials.

[0054] Fig. 20 Display in processing Fig.19 Structure 2000 after structure 1900. Bonding dielectric 1922 has been bonded to carrier wafer 2001, and the bonded structure is flipped over so that substrate 911 is placed on top of structure 2000. Carrier wafer 2001 can be an inexpensive wafer or a glass carrier with an oxide deposition surface. Bonding can be performed by fusion bonding.

[0055] Fig.21 Display in processing Fig. 20 Structure 2100 is a structure 2100 after structure 2000. Structure 2000 has been subjected to a CMP process which exposes the tops of pillars 1007 for the channels of the GAA transistors formed in the process flow. These tops of pillars 1007 will provide junctions to the cell contacts of the capacitors. Substrate 911 and layer 916 have been removed.

[0056] Fig. 22 Display in processing Fig.21 100. Portions of dielectric 1118 have been selectively removed to a selected level of dielectric 1118, exposing pillar 1007. For dielectric 1118 as an oxide and pillar 1007 as silicon, the oxide of dielectric 1118 may be selectively recessed to the Si surface. Selective wet etching may be used for the purpose of recessing dielectric 1118 to a specified level. The selective wet etching may be a time controlled etch.

[0057] Fig.23 Display in processing Fig. 221007. A dielectric material 2323 has been formed on the exposed surface of the structure 2200. The dielectric material 2323 covers the exposed portion of the pillar 1007 and will provide a gate dielectric for the GAA transistor formed around the pillar 1007. The dielectric material 2323 may be, but is not limited to, a gate oxide material. The dielectric material 2323 may be formed by a deposition process suitable for the material selected for the dielectric material 2323. Alternatively, the dielectric material 2323 may be formed by in-situ steam generation (ISSG), wherein the ISSG process involves generating steam very close to the wafer surface, thereby providing wet oxidation.

[0058] Fig.24 Display in processing Fig.23 The structure 2400 after the structure 2300 is exposed. The liner 2413 has been formed on the exposed structure 2300. The formation of the liner 2413 can be performed using a deposition process suitable for the material of the liner 2413. The liner 2413 can be, but is not limited to, a nitride liner. The liner 2413 is formed as a sacrificial liner in the process flow.

[0059] Fig.25 Display in processing Fig.24 2400. The liner 2413 has been selectively etched back to expose a portion of the dielectric material 2323. The surface area of ​​the structure 2400 has been filled with a dielectric, such as but not limited to an oxide, subjected to a CMP process and dry etched to expose a portion of the dielectric material 2323. The dry etch may be selective to the dielectric material 2323 being a high-k dielectric or a gate oxide.

[0060] Fig.26 exhibit Fig.25 Representation 2600 of a top view of structure 2500 . Fig.26 The resulting cell array is shown. Each cell represented comprises a central pillar 1007 providing a channel surrounded by a dielectric material 2323 provided as gate material, wherein the dielectric material 2323 is surrounded by a liner 2413.

[0061] Fig. 27 Display in processing Fig.25 Structure 2700 after structure 2500. A photolithography process for preparing WL has been performed. Dielectric 2718 has been formed on Fig.16 The carbon-based hard mask 2728 has been applied to the surface of the dielectric 2718 and has been selectively removed down to the top surface of the dielectric 2718. Dry etching can be used to form Fig. 27 The pattern of the carbon-based hard mask 2728 is shown in FIG.

[0062] Fig.28 Display in processing Fig. 27 The structure 2800 after the structure 2700 of FIG. 2700 is shown in FIG. 2800 . The carbon-based hard mask 2728 has been stripped. The etching has removed most of the dielectric 2718, thereby exposing the top of the liner 2413 and the dielectric material 2323 above the liner 2413.

[0063] Fig.29 Display in processing Fig.28 2800. The liner 2413 has been selectively removed, wherein the liner 2413 is formed as a sacrificial liner. In the case where the liner 2413 is a sacrificial nitride, the removal process may include using a selective wet etch to remove the liner 2413 to maintain the dielectric material 2323 and the lower portion of the dielectric 2718. For example, the selective etchant may include thermal phosphide. The removal process has maintained areas of the dielectric 2718 positioned to provide isolation between the groups of linearly arranged pillars covered by the dielectric material 2323.

[0064] Fig.30 Display in processing Fig.29 The structure 3000 is formed after the structure 2900. A conductive material 3027 for the gate has been formed and a conductive material 3030 for the WL has been formed. The conductive material 3027 may be formed as a metal deposited to form the gate of the GAA transistor, and the conductive material 3030 may be formed as a metal deposited to form the WL. The conductive material 3030 formed has been recessed to form a Fig.30 The shape of the conductive material 3030 is shown in FIG.

[0065] Fig.31 Display in processing Fig.30 Structure 3100 after structure 3000. Dielectric 3118 has been formed as a partial fill followed by a wet recess. Dielectric 3118 may be, but is not limited to, an oxide. The junction of the cell contact of pillar 1007 has been implanted for coupling to a capacitor. The implant may be an n+ implant.

[0066] Fig.32 Display in optional processing Fig.30 3200 after forming an air gap between the conductive material 3030 for the WL and the immediately adjacent conductive material 3030 for the WL. The dielectric 3118 has been formed as a non-conformal dielectric seal, leaving an adjacent air gap 3238. The dielectric 3118 has been recessed.

[0067] Fig.33 Display in processing Fig.31Structure 3300 after structure 3100. Etch stop 3369 has been formed. Etch stop 3369 can be formed by a deposition process of a material suitable for etch stop 3369. Etch stop 3369 can be a nitride etch stop. A group of capacitors 3329 has been formed on etch stop 3369. If the structure Fig.32 A similar process flow may be performed for structure 3200.

[0068] Fig.34 Display in processing Fig.33 1007. A capping layer 3498 has been formed on top of the set of capacitors 3329. When forming the capacitor, a bottom electrode 3358 has been formed to couple to the pillar 1007. A top electrode 3357 has been formed, separated from the bottom electrode 3358 by a capacitor dielectric 3359. The capacitor dielectric 3359 may be formed, but is not limited to a high-k dielectric. The capacitor process may be implemented using the same mask set used for patterning the area. The capacitor modules may be aligned on the junction of the cell contact action area channel arrangement provided by the pillar 1007. The structure 3400 provides an array structure that is ready to be processed with the control and sensing circuitry of a memory device, such as a DRAM device. The capping layer 3498 may be a wafer for mounting the structure 3400 for coupling to the control and sensing circuitry.

[0069] Figures 35 to 36 exhibit Fig.34 Details of Structure 3400. Structure 3500 shows Fig.34 The area of ​​structure 3400 below capacitor 3329. To provide a more detailed view of structure 3400, Fig.35 The various dielectric layers formed when fabricating structure 3400 are not shown in structure 3500 of FIG. Metal 1435 for the digit line at least partially wraps around the junction cell contact of the active region 3506 of the GAA transistor having the channel formed by pillar 1007. Formed around pillar 1007 is conductive material 3027 for the gate of the GAA transistor, where conductive material 3027 for the gate contacts metal 3030 for the WL. Although in FIG. Fig.35 Not shown in FIG. 34 , pillar 1007 includes a junction contact contact to an active region of a GAA transistor that contacts electrode 3358 of capacitor 3329 of a memory cell of structure 3400 .

[0070] Fig.36 Representation 3600 of structure 3500 is shown with portions of metal 3030 removed to illustrate the Figures 8 to 34The dielectric material 2323 of the gate dielectric of the GAA transistor formed in the process flow of FIG. 1000 is formed. The metal 1435 of the structure 3400 may be referred to as BL 1435. The BL 1435 is separated from each other, wherein each BL 1435 contacts a plurality of memory cells by contacting a plurality of pillars 1007. The BL 1435 is separated from adjacent BL 1435 by an air gap 1837. The WL 3030 contacts the conductive material 3027 of the gate of the GAA transistor for the access device arranged as a capacitor of the structure 3400.

[0071] Figures 8 to 36 The process flow of provides several enhancements to memory devices such as DRAM devices. The WL can be formed as a replacement gate for the GAA transistor, which can provide enhanced gate control. The capacitor formation of this process flow allows the use of RDL to be skipped.

[0072] Various deposition techniques can be used for the components in the process flow discussed herein that are typical for the materials formed, the sizes of the materials formed, and the architectures in which the materials are formed when manufacturing memory devices. The materials and structures can be formed by suitable processes, such as but not limited to deposition processes, wherein the deposition processes may include but are not limited to PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD), or other deposition processes. Other processes can be used. Selective etching can be used to remove selected areas in the processing discussed with respect to the process flow. Selective etching is a process in which one or more materials are removed from the structure while one or more other materials remain in the structure without being removed or being removed less. Selective etching can depend on the material to be etched, the material to be not etched, the etchant used, and the method used for etching. The types of etching include wet etching and dry etching, wherein each of these two basic methods includes several different etching processes. In addition, conventional masking techniques that provide protection zones in the process can be used to remove selected areas when forming components of the memory device.

[0073] Fig.37 Description: Fig.34The embodiment of the example architecture 3700 of the structure 3400 or similar structure of the CoA architecture 3700. The architecture 3700 is structured as a wafer-to-wafer interconnect architecture, which includes a control wafer 3702 having a bonding area 3712-2 attached to an array wafer 3701 having a bonding area 3712-1. The combination of the control wafer 3702 attached to the array wafer 3701 can be mounted on a carrier wafer 3703 or other suitable platform. The control wafer 3702 can be attached to the array wafer 3701 by performing bonding from the bonding area 3712-1 to the bonding area 3712-2. The bonding process can be performed by fusion bonding. The array wafer 3701 can include one or more of the structure 3400 or similar structures having one or more memory cell arrays. The control wafer 3702 can include a control and sensing circuit system for the operation of an array of memory cells of one or more structures 3400 of the array wafer 3701 in the CoA architecture. Alternatively, the vertical order on the carrier wafer 3703 of the control wafer 3702 attached to the array wafer 3701 may be reversed, thereby configuring the architecture 3700 as a CuA architecture.

[0074] Fig.38 38 is a flow chart of features of an embodiment of an example method 3800 of forming a memory device. At 3810, an array of memory cells is formed. The memory cells of the array are formed as hexagonal cells. Each of the memory cells is formed to have a GAA transistor coupled to a capacitor. At 3820, WLs are formed, wherein a first WL of the WLs is coupled to gates of a plurality of GAA transistors of a first group of memory cells. At 3830, BLs are formed. A first BL of the BLs is coupled to a plurality of GAA transistors of a second group of memory cells. Each BL is formed to be separated from an adjacent BL by an air gap. The formation of the memory cells, WLs, and BLs may be an integrated process.

[0075] Variations of method 3800 or methods similar to method 3800 may include several different embodiments, which may be combined depending on the application of such methods and / or the architecture of the system including the memory device implementing such methods. Such methods include forming a vertical nanowire extending above a substrate, wherein the vertical nanowire has a channel structure around which the gate of the GAA transistor is formed. The vertical nanowire may include epitaxial silicon formed on silicon germanium above a silicon substrate.

[0076] Variations of method 3800 or methods similar to method 3800 may include performing several processes when forming a memory device. A vertical semiconductor pillar for a GAA transistor may be formed, wherein the vertical semiconductor pillar extends above a substrate. A dielectric may be formed between the vertical semiconductor pillars, and a damascene structure may be performed on the dielectric. The metal for the set of BLs may be formed to at least partially wrap around the sidewalls of the vertical semiconductor pillars. A top dielectric may be formed covering the metal, pinching off the top dielectric and forming an air gap adjacent to the BL. Variations may include forming the top dielectric by forming a nitride using PVD.

[0077] Variations may include performing several other processes. A bonding dielectric may be formed on the top dielectric and attached to a carrier wafer. The carrier wafer may be arranged as a bottom structure with a metal covered by an isolation dielectric surrounding the vertical semiconductor pillars arranged above the carrier wafer. A gate dielectric and a full surround gate for a GAA transistor may be formed above the isolation dielectric. The gate dielectric may be formed as a deposited high-k dielectric or as an oxide by in-situ steam generation on the vertical semiconductor pillars.

[0078] Fig.39 39 is a flow chart of features of an embodiment of an example method of forming a memory device. At 3910, an array wafer having a GAA transistor array connected to a WL and a BL, wherein the BL is separated from an adjacent BL by an air gap, may be prepared. At 3920, a control circuit system wafer is prepared. At 3930, the array wafer and the control circuit system wafer are coupled together. The coupling may be achieved by a fusion bonding process.

[0079] Variations of method 3900 or methods similar to method 3900 may include several different embodiments that may be combined depending on the application of such methods and / or the architecture of the system including the memory device implementing such methods. Such methods may include forming each WL separated from an adjacent WL by a second air gap. Variations may include forming an array of GAA transistors as 4F 2 Architecture or 8F 2 Hexagonal memory cells in the architecture.

[0080] In various embodiments, a memory device may include an array of memory cells arranged as hexagonal cells. Each of the memory cells may have a GAA transistor coupled to a capacitor. The WL may have a first WL coupled to gates of a plurality of GAA transistors of a first group of memory cells. The BL may have a first BL coupled to a plurality of GAA transistors of a second group of memory cells, wherein each of the BLs may be separated from an adjacent BL by an air gap.

[0081] As taught herein, variations of this memory device and features thereof may include several different embodiments and features, which may be combined depending on the application of such memory device, the format of such memory device, and / or the architecture in which such memory device is implemented. Variations of such memory device may include each WL separated from an adjacent WL by a second air gap. Variations may include a first set of multiple GAA transistors configured in a substantially linear arrangement and GAA transistors adjacent to the first set of multiple GAA transistors are not coupled to the first WL. Variations may include a second set of multiple GAA transistors configured in a substantially linear arrangement and GAA transistors adjacent to the second set of multiple GAA transistors are not coupled to the first BL.

[0082] A variation of this memory device may include a first BL coupled to a first sense amplifier and a second BL proximate to the first BL coupled to a second sense amplifier. A variation may include the first BL at least partially wrapping around a sidewall of an active region of each GAA transistor of the second group. A variation may include a memory cell array having 8F 2 Unit configuration.

[0083] Variations of this memory device may include the memory device having control logic and sensing circuitry above the array. Variations may include the control logic and sensing circuitry and the memory cell array arranged in a wafer-to-wafer interconnect architecture. The wafer-to-wafer interconnect architecture may include a wafer-on-wafer architecture. Variations may include structuring the channel structure and active area of ​​the GAA transistor of the memory cell into vertical nanowires.

[0084] Fig.40 4000, which may include a physical architecture having an array of memory cells arranged as hexagonal cells, wherein each of the memory cells has a GAA transistor coupled to a capacitor. The memory cells may be coupled to BLs, wherein each of the BLs is separated from an adjacent BL by an air gap. Each WL may be structured to contact the gate of the GAA transistor of the memory cell to which a given WL is coupled. The memory cell array may be described herein with respect to Figures 1 to 39 DRAM device 4000 may include memory cells 4025 arranged in rows 4054-1, 4054-2, 4054-3, and 4054-4 and columns 4056-1, 4056-2, 4056-3, and 4056-4 (for ease of presentation, the memory cells 4025 are shown in FIG. 4025 ). Fig.40 The physical orientation of the rows and columns is not limited to Fig.40Furthermore, while only four rows 4054-1, 4054-2, 4054-3, and 4054-4 and four columns 4056-1, 4056-2, 4056-3, and 4056-4 of four memory cells are illustrated, a DRAM device such as DRAM device 4000 may have significantly more memory cells 4025 per row or column (e.g., tens, hundreds, or thousands of memory cells).

[0085] In this example, each memory cell 4025 may include a single transistor 4021 and a single capacitor 4029, which is often referred to as a 1T1C (single transistor-single capacitor cell). One plate of the capacitor 4029, which may be referred to as a "node plate," is connected to the drain terminal of the transistor 4021, while the other plate of the capacitor 4029 is connected to ground 4024 or other reference node. Each capacitor 4029 of a memory cell 4025 within an array of 1T1C memory cells is typically used to store one bit of data, and a corresponding transistor 4021 is used as an access device to write to or read from the storage capacitor 4029. Each transistor 4021 may be implemented by a GAA nanowire transistor, as described with respect to Figures 1 to 39 discuss.

[0086] The transistor gate terminals within each of the rows 4054-1, 4054-2, 4054-3, and 4054-4 may be part of a respective WL 4030-1, 4030-2, 4030-3, and 4030-4, and the transistor source terminals within each of the columns 4056-1, 4056-2, 4056-3, and 4056-4 may be electrically connected to a respective BL 4035-1, 4035-2, 4035-3, and 4035-4. The row decoder 4032 may selectively drive the individual WLs 4030-1, 4030-2, 4030-3, and 4030-4 in response to a row address signal 4031 input to the row decoder 4032. Driving a given WL at a high voltage turns on the access transistor within the respective row, thereby connecting the storage capacitor within the row to the respective BL so that charge can be transferred between the BL and the storage capacitor for a read or write operation. Both read and write operations may be performed via SA circuitry 4040 which may transfer bit values ​​between memory cells 4025 of selected rows in rows 4054-1, 4054-2, 4054-3, and 4054-4 and input / output buffer 4046 (for write / read operations) or external input / output data bus 4048.

[0087] A column decoder 4042 responsive to a column address signal 4041 may select which memory cells 4025 within a selected row are read or written. Alternatively, for a read operation, the storage capacitors 4029 within the selected row may be read and latched simultaneously, and the column decoder 4042 may then select which latched bits are connected to the output data bus 4048. Since the readout of the storage capacitors destroys the stored information, a read operation is accompanied by a simultaneous rewrite of the capacitor charge. In addition, between read / write operations, the capacitor charge is repeatedly refreshed to prevent data loss. The details of the read / rewrite, write, and refresh operations are well known to those of ordinary skill in the art.

[0088] DRAM device 4000 may be implemented as an IC within a package that includes pins for receiving supply voltages (eg, to provide source and gate voltages for transistor 4021) and signals (including data, address, and control signals). Fig.40 The DRAM device 4000 is depicted in a simplified form to illustrate the basic structural components relative to electrical interaction, and many details of the memory cell 4025 and the associated WL 4030-1, 4030-2, 4030-3 and 4030-4 and BL 4035-1, 4035-2, 4035-3 and 4035-4 and peripheral circuit systems are omitted. For example, in addition to the row decoder 4032, the column decoder 4042, the SA circuit system 4040 and the buffer 4046, the DRAM device 4000 may also include another peripheral circuit system, such as a memory control unit that controls memory operations based on a control signal (e.g., provided by an external processor), additional input / output circuit systems, or other features associated with the memory device. The details of this peripheral circuit system are generally known to those of ordinary skill in the art and are not further discussed herein. The peripheral circuit system may be positioned above the array of memory cells 4025 in a CoA architecture using a wafer-to-wafer interconnect architecture. Alternatively, the peripheral circuit system may be positioned below the memory cell array 4025 in a CuA architecture. Alternatively, the peripheral circuitry may be located in a region of the IC of the memory device adjacent to the array region having the array of memory cells 4025 .

[0089] In a two-dimensional (2D) DRAM array, the rows 4054-1, 4054-2, 4054-3, and 4054-4 and columns 4056-1, 4056-2, 4056-3, and 4056-4 of memory cells 4025 may be arranged along a single horizontal plane of the semiconductor substrate (i.e., a plane parallel to the layers), for example, in a rectangular lattice with WLs 4030-1, 4030-2, 4030-3, and 4030-4 and BLs 4035-1, 4035-2, 4035-3, and 4035-4. In a 3D DRAM array, the memory cells 4025 may be arranged in a 3D lattice, with one set of memory cells and associated WLs and BLs at a level above another set of memory cells and associated WLs and BLs.

[0090] Having the same or similar features as the example DRAM device 4000 and Figures 1 to 40 The memory device of the associated structure can be implemented in various electronic devices. Electronic devices such as mobile electronic devices (e.g., smart phones, tablet computers, and other similar communication-related devices), electronic devices used in automotive applications (e.g., automotive sensors, control units, driver assistance systems, passenger safety, comfort systems, or other similar systems), and Internet connection appliances or devices (e.g., Internet of Things (IoT) devices or other network-related devices) have different storage requirements depending on the type of electronic device, usage environment, performance expectations, or other criteria.

[0091] Such electronic devices may be divided into several main components: a processor (e.g., a central processing unit (CPU) or other main processor); a memory (e.g., one or more volatile or non-volatile RAM memory devices, such as DRAM, mobile or low-power double data rate synchronous DRAM (DDR SDRAM), or other similar memory devices); and a memory device (e.g., a non-volatile memory (NVM) device, such as flash memory, ROM, solid-state drive (SSD), multimedia card (MMC), other memory card structures or assemblies, or other similar memory devices). In some examples, the electronic device may include a user interface (e.g., a display, a touch screen, a keyboard, one or more buttons or other similar docking structures), a graphics processing unit (GPU), a power management circuit, a baseband processor, one or more transceiver circuits, or other similar devices. As used herein, a "processor device" means any type of computing circuit, such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit (including a processor group or multi-core device).

[0092] The following examples are example embodiments of devices and methods according to the teachings herein.

[0093] An example memory device 1 may include: an array of memory cells arranged as hexagonal cells, wherein each of the memory cells has a GAA transistor coupled to a capacitor; a WL having a first WL coupled to gates of a plurality of GAA transistors of a first group of the memory cells; and a BL having a first BL coupled to a plurality of GAA transistors of a second group of the memory cells, each of the BLs being separated from an adjacent BL by an air gap.

[0094] Example memory device 2 may include features of example memory device 1 and may include each WL separated from an adjacent WL by a second air gap.

[0095] Example memory device 3 may include features of example memory device 2 and any of the foregoing example memory devices, and may include a first set of multiple GAA transistors configured in a substantially linear arrangement, and GAA transistors adjacent to the first set of multiple GAA transistors are not coupled to the first WL.

[0096] The example memory device 4 may include features of any of the foregoing example memory devices and may include a second set of multiple GAA transistors configured in a substantially linear arrangement and GAA transistors adjacent to the second set of multiple GAA transistors are not coupled to the first BL.

[0097] Example memory device 5 may include features of any of the aforementioned example memory devices, and may include a first BL coupled to a first sense amplifier and a second BL proximate to the first BL coupled to a second sense amplifier.

[0098] Example memory device 6 may include features of example memory device 5 and any of the above example memory devices, and may include a memory cell array having 8F 2 Unit configuration.

[0099] Example memory device 7 may include features of any of the aforementioned example memory devices, and may include a first BL at least partially wrapped around a sidewall of an active area of ​​each GAA transistor of the second set.

[0100] Example memory device 8 may include features of any of the aforementioned example memory devices, and may include the memory devices to include control logic and sensing circuitry above the array.

[0101] The example memory device 9 may include features of any of the aforementioned example memory devices, and may include control logic and sensing circuitry and an array of memory cells arranged in a wafer-to-wafer interconnect architecture.

[0102] The example memory device 10 may include features of any of the aforementioned example memory devices and may include the channel structure and active region of the GAA transistor of the memory cell being structured into vertical nanowires.

[0103] In example memory device 11, any of the memory devices of example memory devices 1-10 may include a memory device incorporated into an electronic device further including a host processor and a communication bus extending between the host processor and the memory device.

[0104] In example memory device 12, any one of the memory devices of example memory devices 1-11 may be modified to include any structure presented in another one of example memory devices 1-11.

[0105] In example memory device 13, any apparatus associated with the memory devices of example memory devices 1-12 may further include a machine-readable storage device configured to store instructions as a physical state, wherein the instructions may be used to perform one or more operations of the apparatus.

[0106] In example memory device 14, any of the memory devices of example memory devices 1-13 may be formed according to any of the following example methods 1-13 of forming a memory device.

[0107] An example method 1 of forming a memory device may include: forming a memory cell array, comprising forming memory cells of the array as hexagonal cells, and forming each of the memory cells as having a GAA transistor coupled to a capacitor; forming WLs, wherein a first WL of the WLs is coupled to gates of a plurality of GAA transistors of a first group of the memory cells; and forming BLs, wherein a first BL of the BLs is coupled to a plurality of GAA transistors of a second group of the memory cells, each of the BLs being separated from an adjacent BL by an air gap.

[0108] Example method 2 of forming a memory device may include features of example method 1 of forming a memory device, and may include forming a vertical nanowire extending over a substrate, wherein the vertical nanowire has a channel structure around which a gate of a GAA transistor is formed.

[0109] Example method 3 of forming a memory device may include features of example method 2 of forming a memory device and any of the previous example methods of forming a memory device, and may include forming vertical nanowires to include forming epitaxial silicon on silicon germanium over a silicon substrate.

[0110] Example method 4 of forming a memory device may include features of any of the foregoing example methods of forming a memory device, and may include: forming vertical semiconductor pillars for a GAA transistor, the vertical semiconductor pillars extending above a substrate; forming a dielectric between the vertical semiconductor pillars; patterning a damascene structure on the dielectric; forming a metal at least partially wrapped around sidewalls of the vertical semiconductor pillars for the set of BLs; forming a top dielectric covering the metal, pinching off the top dielectric, and forming an air gap adjacent to the BL.

[0111] Example method 5 of forming a memory device can include features of example method 4 and any of the preceding example methods of forming a memory device, and can include forming a top dielectric by forming a nitride using PVD.

[0112] Example method 6 of forming a memory device may include features of example method 4 of forming a memory device and any of the foregoing example methods of forming a memory device, and may include: forming a bonding dielectric on a top dielectric; attaching the bonding dielectric to a carrier wafer; arranging the carrier wafer as a bottom structure wherein the metal covered by an isolation dielectric surrounding the vertical semiconductor pillars is arranged above the carrier wafer; and forming a gate dielectric and a full surround gate for a GAA transistor above the isolation dielectric.

[0113] Example method 7 of forming a memory device may include features of example method 6 of forming a memory array and any of the foregoing example methods of forming a memory device, and may include forming a gate dielectric by forming a high-k dielectric or forming an oxide by in-situ vapor generation on a vertical semiconductor pillar.

[0114] In example method 8 of forming a memory device, any of example methods 1-7 of forming a memory device may be performed in forming an electronic device further comprising a host processor and a communication bus extending between the host processor and the memory device.

[0115] In example method 9 of forming a memory device, any of the example methods 1-8 of forming a memory device may be modified to include operations set forth in any other of the example methods 1-8 of forming a memory device.

[0116] In example method 10 of forming a memory device, any of example methods 1-9 of forming a memory device may be implemented at least in part by using instructions stored as a physical state in one or more machine-readable storage devices.

[0117] Example method 11 of forming a memory device may include features of any of the foregoing example methods 1-10 of forming a memory device, and may include forming features associated with any of the features of example memory devices 1-14.

[0118] An example method 12 of forming a memory device may include preparing an array wafer having a GAA transistor array connected to a WL and a BL, wherein the BL is separated from an adjacent BL by an air gap; preparing a control circuitry wafer; and coupling the array wafer and the control circuitry wafer together.

[0119] Example method 13 of forming a memory device may include features of example method 12 of forming a memory device, and may include forming each WL separated from an adjacent WL by a second air gap.

[0120] Example method 14 of forming a memory device may include the features of any of the foregoing example methods 12-13 of forming a memory device, and may include forming an array of GGA transistors as a 4F 2 Architecture or 8F 2 Hexagonal memory cells in the architecture.

[0121] In example method 15 of forming a memory device, any of example methods 12-14 of forming a memory device may be performed in forming an electronic device further comprising a host processor and a communication bus extending between the host processor and the memory device.

[0122] In example method 16 of forming a memory device, any of example methods 12-15 of forming a memory device may be modified to include operations set forth in any other of example methods 12-15 of forming a memory device.

[0123] In example method 17 of forming a memory device, any of example methods 12-16 of forming a memory device may be implemented at least in part by using instructions stored as a physical state in one or more machine-readable storage devices.

[0124] Example method 18 of forming a memory device may include features of any of the foregoing example methods 12-17 of forming a memory device, and may include forming features associated with any of the features of example memory devices 1-14.

[0125] An example machine-readable storage device storing instructions that, when executed by one or more processors, cause the machine to perform operations may include instructions to perform functions associated with any feature of the example memory devices 1-14 or to perform methods associated with any feature of the example methods 1-18 of forming a memory device.

[0126] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. Various embodiments utilize permutations and / or combinations of the embodiments described herein. It should be understood that the above description is intended to be illustrative and not limiting, and that the words or terminology employed herein are for descriptive purposes.

Claims

1. A memory device, comprising: an array of memory cells arranged as hexagonal cells, wherein each of the memory cells has a gate-all-around GAA transistor coupled to a capacitor; access lines having a first access line coupled to gates of a plurality of GAA transistors of a first group of said memory cells; and A digit line having a first digit line coupled to a plurality of GAA transistors of a second set of the memory cells, each of the digit lines being separated from an adjacent digit line by an air gap.

2. The memory device of claim 1, wherein each access line is separated from an adjacent access line by a second air gap. 3 . The memory device of claim 1 , wherein the plurality of GAA transistors of the first group are configured in a substantially linear arrangement, and GAA transistors adjacent to the plurality of GAA transistors of the first group are not coupled to the first access line. 4 . The memory device of claim 1 , wherein the plurality of GAA transistors of the second group are configured in a substantially linear arrangement, and GAA transistors adjacent to the plurality of GAA transistors of the second group are not coupled to the first digit line.

5. The memory device of claim 1, wherein the first digit line is coupled to a first sense amplifier and a second digit line immediately adjacent to the first digit line is coupled to a second sense amplifier.

6. The memory device of claim 1, wherein the memory cell array has 8F 2 Unit configuration.

7. The memory device of claim 1, wherein the first digit line wraps at least partially around a sidewall of an active area of ​​each GAA transistor of the second group.

8. The memory device of claim 1, wherein the memory device includes control logic and sensing circuitry above the array.

9. The memory device of claim 8, wherein the control logic and sensing circuitry and the memory cell array are arranged in a wafer-to-wafer interconnect architecture.

10. The memory device of claim 1, wherein a channel structure and an active area of ​​the GAA transistor of a memory cell are structured as vertical nanowires.

11. A method of forming a memory device, the method comprising: forming an array of memory cells, comprising forming the memory cells of the array as hexagonal cells, and forming each of the memory cells as a gate-all-around (GAA) transistor having a capacitor coupled to the transistor; forming access lines, wherein a first one of the access lines is coupled to gates of a plurality of GAA transistors of a first group of the memory cells; and Digit lines are formed, wherein a first one of the digit lines is coupled to a plurality of GAA transistors of a second set of the memory cells, each of the digit lines being separated from an adjacent digit line by an air gap. 12 . The method of claim 11 , wherein the method comprises forming a vertical nanowire extending above a substrate, wherein the vertical nanowire has a channel structure around which a gate of the GAA transistor is formed.

13. The method of claim 12, wherein forming the vertical nanowires comprises forming epitaxial silicon on silicon germanium over a silicon substrate.

14. The method of claim 11, wherein the method comprises: forming a vertical semiconductor pillar for the GAA transistor, the vertical semiconductor pillar extending above a substrate; forming a dielectric between the vertical semiconductor pillars; patterning a damascene structure on the dielectric; forming a metal wrap at least partially around a sidewall of the vertical semiconductor pillar for the digit lines of the group; and A top dielectric is formed overlying the metal, pinching off the top dielectric and forming an air gap adjacent to the digit line.

15. The method of claim 14, wherein the method comprises forming the top dielectric by forming a nitride using physical vapor deposition.

16. The method of claim 14, wherein the method comprises: forming a bonding dielectric on the top dielectric; attaching the bonding dielectric to a carrier wafer; arranging the carrier wafer as a bottom structure, wherein the metal covered by the isolation dielectric surrounding the vertical semiconductor pillars is arranged above the carrier wafer; and A gate dielectric and a fully surrounding gate for the GAA transistor are formed over the isolation dielectric.

17. The method of claim 16, wherein forming the gate dielectric comprises forming a high-k dielectric or forming an oxide by in-situ vapor generation on the vertical semiconductor pillar.

18. A method of forming a memory device, the method comprising: preparing an array wafer having an array of gate-all-around (GAA) transistors connected to access lines and digit lines separated from adjacent digit lines by air gaps; Preparation of control circuit system chip; and The array chip and the control circuit system chip are coupled together.

19. The method of claim 18, wherein the method includes forming each access line separated from an adjacent access line by a second air gap.

20. The method of claim 18, wherein the method comprises forming the GAA transistor array into a 4F 2 Architecture or 8F 2 Hexagonal memory cells in the architecture.

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