Memory device and forming method thereof

Abstract

The semiconductor memory device includes: a plurality of transistors disposed along a main surface of a substrate; a plurality of metallization layers including a plurality of metal tracks and disposed over the major surface of the substrate; and a plurality of memory cells formed within the one or more metal layers. At least one of the plurality of transistors is electrically coupled to the plurality of memory cells. Each of the plurality of memory cells includes an access transistor and a storage capacitor electrically coupled to each other in series and physically arranged relative to each other along a vertical direction. The embodiment of the disclosure also relates to a memory device and a method of forming the same.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to memory devices and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) In large part, this improvement in integration density comes from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. Summary of the invention

[0003] An embodiment of the present disclosure provides a memory device, comprising: a first metal track, arranged on a substrate; a first channel, arranged on the first metal track and coupled to the first metal track, the first channel comprising a semiconductor behavior material and extending along a vertical direction; a first gate structure, wrapping a sidewall of the first channel; a second metal track, arranged on the first channel and coupled to the first channel; and a first capacitor, arranged on the second metal track and coupled to the second metal track, the first capacitor comprising a first metal layer, a first capacitor dielectric layer and a second metal layer; wherein each of the first metal layer, the first capacitor dielectric layer and the second metal layer has at least a portion extending along the vertical direction.

[0004] Another embodiment of the present disclosure provides a memory device, comprising: a plurality of transistors arranged along a main surface of a substrate; and a plurality of metallization layers arranged above the main surface of the substrate, the metallization layers comprising a plurality of metal tracks; wherein a plurality of memory cells are formed within one or more of the metallization layers, at least one of the transistors being electrically coupled to the plurality of memory cells; and wherein each of the plurality of memory cells comprises an access transistor and a storage capacitor, the access transistor and the storage capacitor being electrically coupled to each other in series and being physically arranged relative to each other along a vertical direction.

[0005] Yet another embodiment of the present disclosure provides a method for forming a memory device, comprising: forming a first metal track above a plurality of transistors formed along a main surface of a substrate, wherein the first metal track extends along a first lateral direction; forming a channel above the first metal track, wherein the channel extends along a vertical direction; forming a second metal track above the channel; forming a gate structure, wherein the gate structure wraps a portion of a sidewall of the channel; and forming a capacitor above the second metal track; wherein the capacitor comprises a first metal layer, a capacitor dielectric layer surrounding the first metal layer, and a second metal layer further surrounding the capacitor dielectric layer, wherein each of the first metal layer, the capacitor dielectric layer, and the second metal layer has at least one portion extending along the vertical direction, and wherein the at least one portion of the first metal layer is directly disposed above the channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The method of the present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a perspective view showing a semiconductor memory device according to some embodiments.

[0008] Figure 2 It is shown along Figure 1 Schematic cross-sectional view of a semiconductor memory device taken along line AA of .

[0009] Figure 3 is a diagram showing a method according to some embodiments Figure 1 Top view of a semiconductor memory device.

[0010] Figure 4 is a flow chart illustrating a method for manufacturing a semiconductor memory device according to some embodiments.

[0011] Figures 5 to 11 is a diagram showing how the Figure 4 Schematic cross-sectional view of an intermediate stage of the method is shown.

[0012] Fig.12 is another flow chart illustrating a method for manufacturing a semiconductor memory device according to some embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the embodiments and / or configurations discussed.

[0014] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," "top," "bottom," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0015] The present disclosure relates to a semiconductor memory device and a method for manufacturing the same. According to some embodiments of the present disclosure, a semiconductor memory device includes a plurality of transistors arranged along a main surface (or front surface) of a substrate and thus formed in a front-end-of-line (FEOL) network, a plurality of metallization layers (such as M0, M1, M2, M3, M4, M5, M6, M7, M8, etc.) including a plurality of metal tracks and metal vias and arranged above the main surface of the substrate, and at least one array of memory cells formed in one or more metallization layers (such as M5, M6, and M7) and thus formed in a back-end-of-line (BEOL) network. As a peripheral circuit, such as a read / write circuit or a computing circuit, at least one of the plurality of transistors formed in the FEOL network is electrically coupled to the array of memory cells formed in the BEOL network. In this way, the array of memory cells in the BEOL network and the peripheral circuits in the FEOL network are stacked and integrated with each other in a three-dimensional (3D) manner, thereby saving space.

[0016] In some embodiments, each array of memory cells in the BEOL network includes an access transistor and a storage capacitor (a "1T1C" configuration), the access transistor and the storage capacitor being electrically coupled in series with each other and physically arranged relative to each other along a vertical direction. In some embodiments, the access transistor includes a channel extending along the vertical direction and including a semiconductor behavior material, thereby forming a vertical selection transistor. In some embodiments, the storage capacitor includes a first metal layer, a capacitor dielectric layer, and a second metal layer. Each of the first metal layer, the capacitor dielectric layer, and the second metal layer of the storage capacitor has at least a portion extending along the vertical direction. In some embodiments, the first metal layer of the storage capacitor is directly disposed above the channel of the access transistor along the vertical direction, wherein the capacitor dielectric layer surrounds the first metal layer, and the second metal layer further surrounds the capacitor dielectric layer.

[0017] In some embodiments, the semiconductor material of the channel of the access transistor having n-type conductivity includes at least one of indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In2O3), or tin oxide (SnO2). In other embodiments, the semiconductor material of the channel of the access transistor having p-type conductivity includes at least one of nickel oxide (NiO), cuprous oxide (Cu2O), copper aluminum oxide (CuAlO2), copper gallium oxide (CuGaO2), copper oxide / indium oxide particles (CuInO2), strontium copper oxide (SrCu2O2), or tin oxide (SnO).

[0018] In some embodiments, a first metal track among a plurality of metal tracks in the BEOL network is operable to serve as a bit line (BL) of a plurality of memory cells, extending along a first lateral direction; and a second metal track among a plurality of metal tracks in the BEOL network is operable to serve as a corresponding word line (WL) of the plurality of memory cells, extending along a second lateral direction perpendicular to the first lateral direction, and disposed above the bit line. In some embodiments, the WL is located on top of the BL in the BEOL network and is electrically connected to one or more peripheral circuits in the FEOL network through metal lines and / or metal vias that laterally extend beyond a memory array region of an array of memory cells. As a result, the routing of the BL and WL of the memory device is shortened, thereby improving the speed and performance of the memory device.

[0019] A semiconductor memory device having such a memory structure and placed in a BEOL network can present various advantages. For example, the semiconductor memory device and its manufacturing method can produce improved integration of computing and memory (CIM), reduced cost and area, reduced leakage, increased speed, thereby leading to improved performance thereof.

[0020] Figure 1is a perspective view showing a semiconductor memory device 100 according to some embodiments of the present disclosure. Figure 2 It is shown along Figure 1 Schematic cross-sectional view of the semiconductor memory device 100 taken along line AA. Figure 3 is a diagram showing how the Figure 1 A top view of a semiconductor memory device 100 is shown. The semiconductor memory device 100 includes a three-dimensional (3D) memory structure in a space defined by X, Y, and Z axes that are substantially perpendicular to each other. The memory structure includes at least one memory cell 10. Figure 1 100 is exemplarily depicted, but the number of memory cells 10 is not limited to the disclosure herein. Each memory cell 10 includes an access transistor 11 and a storage capacitor 12 electrically connected in series to the access transistor 11, and is therefore a memory cell of a 1T1C structure. In some embodiments, the semiconductor memory device 100 is manufactured in a BEOL process. In some embodiments, the memory structure of the semiconductor memory device 100 may be, for example, a DRAM. However, other suitable memory structures (such as RAM and NAND) are also within the intended scope of the present disclosure.

[0021] According to some embodiments, the semiconductor memory device 100 may be formed in an interlayer dielectric (ILD) layer of the BEOL. The ILD layer may include a dielectric material such as, but not limited to, oxide, silicon oxide, a low-k material, or a combination thereof. For example, the ILD layer may include, but is not limited to, silicon dioxide (SiO2), hafnium silicate (HfSiO4), zirconium silicate (ZrSiO4), or a combination thereof. In an optional embodiment, the ILD layer may include, but is not limited to, polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), other suitable polymer-based dielectric materials, or a combination thereof. Other suitable dielectric materials are within the intended scope of the present disclosure.

[0022] According to some embodiments, Figure 1 and Figure 2As shown, a plurality of transistors 16 (e.g., peripheral transistors) are disposed along a main surface (e.g., front surface) 20F of a substrate 20, and a plurality of metallization layers (such as M0, M1, M2, M3, M4, M5, M6, M7, M8, etc.) are disposed above the main surface 20F of the substrate 20. The metallization layers include a plurality of metal tracks (such as metal track 7) and metal vias. In some embodiments, a plurality of memory cells 10 are formed in one or more metallization layers (such as M5, M6, M7) and are located in a memory array region 15. In some embodiments, one or more transistors 16 (such as power circuits, read and write circuits, and input / output (I / O) circuits) are electrically coupled to the plurality of memory cells 10 through a plurality of first conductive connections 17 (including a plurality of metal lines and vias) and / or a plurality of second conductive connections 18 (including a plurality of metal lines and vias). In some embodiments, each of the plurality of memory cells 10 includes an access transistor 11 and a storage capacitor 12 (in a 1T1C structure), which are electrically coupled to each other in series and physically arranged relative to each other along a vertical direction (Z direction). For example, at least one of the plurality of transistors 16 may apply a voltage to the storage capacitor 12 of the memory cell 10 of the semiconductor memory device 100 through the second conductive connection 18.

[0023] According to some embodiments, the access transistor 11 of the memory cell 10 includes a channel 2 extending in a vertical direction and including a semiconductor-behaving material, a gate electrode (or terminal) 3 wrapping the sidewalls of the channel 2, and a gate dielectric 4 disposed between the vertical channel 2 and the gate electrode 3. In some embodiments, the semiconductor-behaving material has n-type conductivity, while in other embodiments, the semiconductor-behaving material has p-type conductivity. In some embodiments, the semiconductor-behaving material having n-type conductivity includes at least one of indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In2O3), or tin oxide (SnO2). In other embodiments, the semiconductor-behaving material having p-type conductivity includes at least one of nickel oxide (NiO), cuprous oxide (Cu2O), copper aluminum oxide (CuAlO2), copper gallium oxide (CuGaO2), copper oxide / indium oxide particles (CuInO2), strontium copper oxide (SrCu2O2), or tin oxide (SnO).

[0024] According to some embodiments, Figure 1 and Figure 2As shown, the access transistor 11 of the memory cell 10 includes a source contact 13 (such as a metal track), which is directly located above the vertical channel 2 along the vertical direction (Z direction) and electrically connects the source of the access transistor 11 to the storage capacitor 12. In some embodiments, the access transistor 11 of the memory cell 10 also includes a drain contact 14, which is directly located below the channel 2 and electrically connects the drain of the access transistor 11 to a bit line (BL) 6, which is directly located below the channel 2 and extends along a first horizontal direction (Y direction). The gate electrode 3 of the access transistor 11 is electrically connected to a word line (WL) 7. In some embodiments, one or more WLs 7 are directly located above one or more BLs 6 and extend in parallel along a second horizontal direction (X direction) perpendicular to the first horizontal direction.

[0025] According to some embodiments, Figure 1 and Figure 2 As shown, the storage capacitor 12 of the memory cell 10 includes a first metal layer 21, a capacitor dielectric layer 22, and a second metal layer 23, and each of the first metal layer 21, the capacitor dielectric layer 22, and the second metal layer 23 has at least a portion extending along the vertical direction (Z direction). In some embodiments, the first metal layer 21 is directly disposed on the vertical channel 2 along the vertical direction, the first metal layer 21 surrounds the capacitor dielectric layer 22, and the capacitor dielectric layer 22 further surrounds the second metal layer 23. In some embodiments, the source contact 13 directly located above the vertical channel 2 of the access transistor 11 is directly located below the first metal layer 21 of the storage capacitor 12 and is electrically connected to the first metal layer 21.

[0026] refer to Figure 1 , the semiconductor memory device 100 exemplarily includes three memory cells 10 and three WLs 7 located above the three BLs 6. However, the number of memory cells 10, WLs 7, and BLs 6 of the semiconductor memory device 100 is not limited to Figure 1 The example shown is Figure 1 and Figure 2 As shown, since the storage capacitor 12 is stacked above the access transistor 11, the memory cell 10 of the semiconductor memory device 100 is a stacked capacitor cell, forming a three-dimensional (3D) structure or configuration.

[0027] refer to Figure 2 ,from Figure 1 The schematic cross-sectional view is shown exemplarily at an angle Figure 1. For example, in each of the three memory cells 10, the access transistor 11 includes a channel layer (or channel) 2 extending in a vertical direction (Z direction), a gate electrode 3 wrapping the channel layer 2, a gate dielectric 4 between the channel layer 2 and the gate electrode 3, a source contact 13, and a drain contact 14. The source contact 13 is electrically connected to a storage capacitor 12 directly above the vertical channel layer 2, and the drain contact 14 is electrically connected to a bit line 6 directly below the vertical channel layer 2. The gate dielectric 4 is formed on the sidewalls of the channel layer 2 and completely surrounds the channel layer 2. The gate electrode 3 is formed on the sidewalls of the gate dielectric 4 and completely surrounds the gate dielectric 4. The gate electrode 3 is electrically connected to the WL 7, and the WL 7 is electrically connected to one or more of the transistors 16 (e.g., read and write circuits) through one or more of a plurality of second conductive connections 18. The second conductive connections 18 include a plurality of metal lines and metal vias that are laterally formed outside or out of the memory array region 15 of the memory device 100, thereby advantageously saving space for and improving the integration of the semiconductor memory device 100. The BL 6 is located directly below the one or more access transistors 11 and is electrically connected to the one or more access transistors 11 through one or more of the plurality of first conductive connections 17. Thus, the route from the one or more access transistors 11 to the BL 6 is shortened, thereby achieving improved speed.

[0028] like Figure 3 As shown, the semiconductor memory device 100 includes a plurality of memory cells 10, which are laterally located in a memory array region 15 and are electrically connected to a plurality of BLs 6 and a plurality of WLs 7. The plurality of BLs 6 extend in a first horizontal direction (Y direction), and the plurality of WLs 7 extend in a second horizontal direction (X direction) perpendicular to the first horizontal direction. In some embodiments, the semiconductor memory device 100 is formed in a manner such as Figure 2 Within one or more of the multiple metallization layers (such as M5, M6, M7) in the BEOL network shown.

[0029] Figure 4 The invention is a method for manufacturing a Figure 1 and Figure 2 4. The flowchart of the method 400 of the semiconductor memory device 100 is shown in FIG. Figure 4 The method 400 shown is merely an example and is not intended to limit the present disclosure. Figure 4 The order of the operations of method 400 shown may be changed, for example, Figure 4 Additional operations are provided before, during, and after method 400, and only some operations may be briefly described here.

[0030] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 and Fig.11 is a diagram showing how, according to some embodiments, Figure 4 A view taken along line BB at an intermediate stage of the method shown in FIG. Figure 1 A schematic cross-sectional view of a semiconductor memory device 100 is shown.

[0031] refer to Figure 4 , the method 400 begins at operation 401, where the first ILD layer 81 is patterned to form trenches. Figure 5 In the example shown, the first ILD layer 81 is patterned using a photolithography process and an etching process to form a trench (e.g., a bit line trench) 30 in the first ILD layer 81. In some embodiments, the first ILD layer can be a single material layer. In an optional embodiment, the first ILD layer 81 can include a plurality of films made of different materials. The first ILD layer can be formed by using, for example, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, a combination thereof, or other suitable techniques. In some embodiments, the material used to make the first ILD layer 81 is similar to the material used to make the ILD layer of the BEOL described above, and for the sake of brevity, its details are omitted here.

[0032] The photolithography process may include, for example, but not limited to, applying a photoresist, soft baking, exposing the photoresist through a photomask, baking after exposure, and developing the photoresist, followed by hard baking to form a patterned photoresist. The etching process for patterning the first ILD layer may be implemented by etching the first ILD layer through the patterned photoresist using, for example, but not limited to, a dry etching process, a wet etching process, other suitable processes, or a combination thereof. In some embodiments, operation 401 may be implemented in the BEOL of a manufacturing process.

[0033] refer to Figure 4 The method 400 then proceeds to operation 402, where a bit line 6 is formed in the first ILD layer 81. Figure 6In the example shown, the bit line 6 is formed in the trench 30 of the first ILD layer 81 by depositing a conductive material to fill the trench 30, and then removing the excess conductive material on the first ILD layer 81 by a planarization technique such as chemical mechanical planarization (CMP). In some embodiments, the conductive material may include: a metal material, such as but not limited to ruthenium (Ru), cobalt (Co), molybdenum (Mo), tungsten (W), nickel (Ni), iridium (Ir), rhodium (Rh), osmium (Os), etc.; a metal nitride, such as but not limited to titanium nitride (TiN), tantalum nitride (TaN), etc.; or a combination thereof. In some embodiments, the deposition of the metal material may be performed by a suitable manufacturing technique known to those skilled in the art of semiconductor manufacturing, such as but not limited to CVD, plasma enhanced CVD (PECVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD) or other suitable deposition techniques.

[0034] refer to Figure 4 The method 400 then proceeds to operation 403, where an ILD stack is formed on the first ILD layer 81 and the bit line 6. Figure 7 In the example shown, a second ILD layer 82 is formed on the first ILD layer 81 and the bit line 6, and then an etch stop layer (not shown) is formed on the second ILD layer 82, and then a third ILD layer 83 is formed on the etch stop layer. The second ILD layer, the etch stop layer and the third ILD layer constitute an ILD stack. The materials and processes used to form the second ILD layer and the third ILD layer are similar to those used to form the first ILD layer, and for the sake of brevity, the details thereof are omitted here. It should be noted that each of the second ILD layer and the third ILD layer may include a material different from the material of the first ILD layer, or a material that is exactly the same as the material of the first ILD. Similarly, the second ILD layer may include a material different from the material of the third ILD layer, or a material that is exactly the same as the material of the third ILD layer. The etch stop layer is formed on the second ILD layer by a suitable manufacturing technique known to those skilled in the art of semiconductor manufacturing, such as, but not limited to, CVD, ALD, PVD, PECVD, etc. In some embodiments, the etch stop layer can be made of a dielectric material, such as, but not limited to, silicon nitride, silicon nitride doped with carbon, silicon oxide, silicon oxynitride, silicon oxynitride doped with carbon, amorphous carbon materials, silicon carbide, other nitride materials, other carbide materials, aluminum oxide, other oxide materials, other metal oxides, boron nitride, boron carbide, other low-k dielectric materials, other low-k dielectric materials doped with one or more of carbon, nitrogen and hydrogen, or other suitable materials.

[0035] refer to Figure 4The method 400 then proceeds to operation 404, wherein a plurality of gate recesses 31 are formed in the third ILD layer 83, and drain contacts 14 (also formed in the plurality of gate recesses 31) are formed in the plurality of gate recesses 31. Figure 1 and Figure 2 Multiple conductive connections. Figure 8 In the example shown, the third ILD layer 83 is recessed through the patterned photoresist by an anisotropic etching process to form a plurality of gate grooves 31 in the third ILD layer 83. The anisotropic etching process may be a suitable anisotropic etching process, such as but not limited to anisotropic dry etching. Due to the presence of the etching stop layer, the etching of the third ILD layer will stop at the etching stop layer, and no grooves will be formed in the second ILD layer.

[0036] refer to Figure 4 The method 400 then proceeds to operation 405, where a plurality of gate components (such as the gate electrode 3 and the gate dielectric 4) of the access transistor 11 are formed. Fig. 9 In the example shown, a semiconductor material is filled in the gate recess 31 formed in the third ILD layer 83 , and then a planarization process (such as but not limited to CMP) is performed to remove excess semiconductor material above the third ILD layer 83 , and then a plurality of gate features are formed in the third ILD layer 83 . Fig. 9 1 is a cross-sectional view of a semiconductor memory device 100 to show gate components (such as a channel layer 2, a gate electrode 3 wrapping the channel layer 2, and a gate dielectric 4 (also in FIG. 4 ) between the channel layer 2 and the gate electrode 3) forming an access transistor 11. Figure 1 and Figure 2 )) is an intermediate stage. The vertical channel layer 2 of the access transistor 11 is electrically connected to the BL 6 through a drain contact 14 disposed directly below the vertical channel layer 2. Filling the semiconductor behavior material in the groove can be achieved by a blanket deposition process using CVD, PECVD, sub-atmospheric pressure CVD (SACVD), molecular layer deposition (MLD), PVD, ALD, sputtering, other suitable methods, or combinations thereof. Various semiconductor processes (such as lithography, etching, deposition, CMP, etc.) can be used to manufacture the gate components of the access transistor. The semiconductor behavior material is similar to the above-mentioned materials, and for the sake of brevity, its details are omitted here.

[0037] refer to Figure 4 The method 400 then proceeds to operation 406, wherein a fourth ILD layer 84 is formed, a plurality of connector recesses 32 are formed in the fourth ILD layer 84, and then a plurality of conductive connectors 13 (such as also in the plurality of connector recesses 32) are formed in the plurality of connector recesses 32. Figure 1 and Figure 2 Source contact 13 shown in FIG. Fig.10In the example shown, the fourth ILD layer 84 is recessed through the patterned photoresist by an anisotropic etching process to form a plurality of connector grooves 32 in the fourth ILD layer 84. The anisotropic etching process may be a suitable anisotropic etching process, such as but not limited to anisotropic dry etching. Due to the presence of the etch stop layer, the etching of the fourth ILD layer 84 will stop at the etch stop layer, and the grooves 32 will not be formed in the third ILD layer 83.

[0038] refer to Figure 4 The method 400 then proceeds to operation 407, where a fifth ILD layer 85 is formed on top of the fourth ILD layer 84, a plurality of capacitor recesses 33 are formed in the fifth ILD layer 85, and then a plurality of storage capacitors 12 are formed in the plurality of capacitor recesses 33. In some embodiments, as Fig.11 As shown, the storage capacitor 12 includes a first metal layer 21, a capacitor dielectric layer 22, and a second metal layer 23, and each of the first metal layer 21, the capacitor dielectric layer 22, and the second metal layer 23 has at least a portion extending along the vertical direction (Z direction). In some embodiments, the first metal layer 21 is directly disposed above the vertical channel 2 along the vertical direction, the first metal layer 21 surrounds the capacitor dielectric layer 22, and the capacitor dielectric layer 22 further surrounds the second metal layer 23. In some embodiments, the source contact 13 directly located above the vertical channel 2 of the access transistor 11 along the vertical direction is directly located below the first metal layer 21 of the storage capacitor 12 along the vertical direction and is electrically connected to the first metal layer 21. The materials and processes used to form the fifth ILD layer 85 are similar to those used to form the first ILD layer, and for the sake of brevity, the details thereof are omitted here. Various semiconductor processes (such as photolithography, etching, deposition, CMP, etc.) can be used to manufacture components of the plurality of storage capacitors 12, and therefore for the sake of brevity, the details thereof are omitted here.

[0039] like Fig.11 As shown, according to some embodiments of the present disclosure, a semiconductor memory device 100 includes a bit line (BL) 6 and a plurality of memory cells 10. Each of the plurality of memory cells 10 includes an access transistor 11 directly located above the bit line 6 along a vertical direction (Z direction), a storage capacitor 12 directly located above the access transistor 11 along the vertical direction and electrically connected in series with the access transistor 11, a source contact 13 electrically connecting the access transistor 11 to the storage capacitor 12, and a drain contact 14 electrically connecting the access transistor 11 to the bit line (BL) 6. In some embodiments, as shown in FIG. Figure 2As shown, the array of memory cells 10 of the semiconductor memory device 100 is formed in the BEOL network, for example, in the upper metallization layer (such as M5, M6, M7...). The upper metallization layer in the semiconductor memory device 100 is thicker than the lower metallization layer (such as M0), and the metal lines and vias in the upper metallization layer are wider than the metal lines and vias in the lower metallization layer. Thus, the semiconductor memory device 100 having the memory cells 10 formed in the upper metallization layer of the BEOL network can achieve reduced metal resistance, and thus reduce power IR drop, resulting in its improved performance.

[0040] like Fig.11 As shown, in some embodiments, the access transistor 11 includes a vertical channel layer 2 extending upward from the bit line 6 in the vertical direction, a gate electrode 3 laterally surrounding the vertical channel layer 2, and a gate dielectric 4 disposed between the vertical channel layer 2 and the gate electrode 3. In some embodiments, the storage capacitor 12 includes a first metal layer 21, a capacitor dielectric layer 22, and a second metal layer 23, and each of the first metal layer 21, the capacitor dielectric layer 22, and the second metal layer 23 has at least a portion extending in the vertical direction. In some embodiments, the first metal layer 21 is directly disposed on the vertical channel 2 in the vertical direction, the first metal layer 21 surrounds the capacitor dielectric layer 22, and the capacitor dielectric layer 22 further surrounds the second metal layer 23.

[0041] like Fig.11 As shown, in some embodiments, the source contact 13 is directly located above the vertical channel 2 of the access transistor 11 along the vertical direction, and is directly located below the first metal layer 21 of the storage capacitor 12 along the vertical direction, thereby electrically connecting the first metal layer 21 of the storage capacitor 12 to the access transistor 11. In some embodiments, the drain contact 14 is directly located below the vertical channel 2 of the access transistor 11 along the vertical direction, and is electrically connected to the bit line 6 directly below the vertical channel layer 2. As a result, the route from the vertical channel 2 of the access transistor 11 to the BL 6 is shortened, thereby advantageously increasing the speed of the semiconductor memory device 100 and improving its performance.

[0042] like Figure 2 and Fig.11 As shown, in some embodiments, the gate electrode 3 is electrically connected to WL7 and is therefore part of WL7, which is electrically coupled to one or more of the transistors (or peripheral transistors) 16 (e.g., read circuits and write circuits) through one or more of the plurality of second conductive connections 18. Figure 2 As shown, in some embodiments, the semiconductor memory device 100 is formed in one or more of a plurality of metallization layers (such as M5, M6, M7) in the BEOL network. Figure 3, the semiconductor memory device 100 includes a plurality of (e.g., three) memory cells 10, which are laterally located in a memory array region 15 and are electrically connected to a plurality of (e.g., three) BLs 6 and a plurality of (e.g., three) WLs 7, wherein the BLs 6 extend in a first horizontal direction (Y direction) and the WLs 7 extend in a second horizontal direction (X direction) perpendicular to the first horizontal direction. Since the second conductive connection 18 including a plurality of metal lines and metal vias is laterally located outside or outside the memory array region 15 of the semiconductor memory device 100, the area of ​​the semiconductor memory device is more efficient.

[0043] Fig.12 is a diagram showing a method for manufacturing a Figure 1 , Figure 2 , Figure 3 and Fig.11 Another flow chart of the method of the semiconductor memory device 100 is shown. It should be noted that Fig.12 The method 1200 shown is merely an example and is not intended to limit the present disclosure. Fig.12 The order of operations of method 1200 shown may be changed, for example, Fig.12 Additional operations are provided before, during, and after method 1200, and only some operations may be briefly described here.

[0044] In some embodiments, Figure 1 , Figure 2 , Figure 3 and Fig.11 The semiconductor memory device 100 shown includes a bit line (BL) 6 and an array of memory cells 10. Each array of memory cells 10 includes an access transistor 11 directly located above the bit line 6 in a vertical direction (Z direction), a storage capacitor 12 directly located above the access transistor 11 in the vertical direction and electrically connected in series with the access transistor 11, a source contact 13 for electrically connecting the access transistor 11 to the storage capacitor 12, and a drain contact 14 for electrically connecting the access transistor 11 to the bit line 6. In some embodiments, the memory cells 10 of the semiconductor memory device 100 are formed as shown in FIG. Figure 2 In the BEOL network shown, for example in the upper metallization layers (such as M5, M6, M7...).

[0045] refer to Fig.12 The method 1200 begins at operation 1201 by forming a first metal track over a plurality of transistors formed along a major surface of a substrate, wherein the first metal track extends along a first lateral direction. Figure 1 and Figure 2In the example shown, a plurality of transistors 16 (e.g., used as peripheral transistors) are formed along a main surface (e.g., front surface) 20F of a substrate 20, and a plurality of metallization layers (such as M0, M1, M2, M3, M4, M5, M6, M7, M8, etc.) are formed above the main surface 20F of the substrate 20. The plurality of metallization layers include a plurality of metal tracks. For example, in a BEOL process, a first metal track 6 is formed in a metallization layer (e.g., M5) of the plurality of metallization layers, and the first metal track 6 will be used as a bit line (BL) 6 in the semiconductor memory device 100. Various semiconductor processes (such as photolithography, etching, deposition, CMP, etc.) can be used to manufacture the first metal track, and therefore, for the sake of brevity, its details are omitted here.

[0046] refer to Fig.12 The method 1200 proceeds to operation 1202 to form a trench, the trench being located above the first metal track and extending in a vertical direction. Figure 1 and Figure 2 In the example shown, a vertical channel layer 2 is formed, and the vertical channel layer 2 extends upward from the bit line 6 in the vertical direction (Z direction). The channel layer 2 includes a semiconductor material having n-type or p-type conductivity. In some embodiments, the semiconductor material of the channel layer of the access transistor having n-type conductivity includes at least one of indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In2O3), or tin oxide (SnO2). In other embodiments, the semiconductor material of the channel layer of the access transistor having p-type conductivity includes at least one of nickel oxide (NiO), cuprous oxide (Cu2O), copper aluminum oxide (CuAlO2), copper gallium oxide (CuGaO2), copper oxide / indium oxide particles (CuInO2), strontium copper oxide (SrCu2O2), or tin oxide (SnO).

[0047] refer to Fig.12 , method 1200 proceeds to operation 1203, forming a second metal track above the vertical channel along the vertical direction. Figure 1 and Figure 2 In the example shown, the second metal track 13 (to be used as the source contact 13) is formed along the vertical direction above the vertical channel 2. Various semiconductor processes (such as lithography, etching, deposition, CMP, etc.) can be used to manufacture the second metal track, and therefore the details thereof are omitted here for the sake of brevity.

[0048] refer to Fig.12 The method 1200 proceeds to operation 1204 by forming a gate structure, the gate structure wrapping a portion of the sidewall of the channel. Figure 1 and Figure 2In the example shown, a gate structure is formed, and the gate structure wraps a portion of the sidewall of the vertical channel layer 2. For example, the vertical channel layer 2 extends upward from the bit line 6 in the vertical direction, the gate electrode 3 laterally surrounds the vertical channel layer 2, and the gate dielectric 4 is disposed between the vertical channel layer 2 and the gate electrode 3, thereby forming the access transistor 11. Various semiconductor processes (such as lithography, etching, deposition, oxidation, CMP, etc.) can be used to manufacture the access transistor, and therefore, for the sake of brevity, the details thereof are omitted here.

[0049] refer to Fig.12 , method 1200 proceeds to operation 1205 where a storage capacitor is formed over the second metal track. Figure 1 and Figure 2 In the example shown, the storage capacitor 12 is formed on the second metal track 13, which will be used as the source contact 13 in the finished product. In some embodiments, the storage capacitor 12 includes a first metal layer 21, a capacitor dielectric layer 22, and a second metal layer 23, and each of the first metal layer 21, the capacitor dielectric layer 22, and the second metal layer 23 has at least a portion extending along the vertical direction. In some embodiments, at least a portion of the first metal layer 21 is directly disposed on the vertical channel 2 along the vertical direction, the first metal layer 21 surrounds the capacitor dielectric layer 22, and the capacitor dielectric layer 22 further surrounds the second metal layer 23. The source contact 13 is electrically connected to the first metal layer 21 of the storage capacitor 12. Various semiconductor processes (such as lithography, etching, deposition, oxidation, CMP, etc.) can be used to manufacture the storage capacitor, and therefore, for the sake of brevity, its details are omitted here.

[0050] In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes: a first metal track disposed on a substrate; a first channel disposed on the first metal track and coupled to the first metal track, the first channel including a semiconductor behavior material and extending in a vertical direction; a first gate structure wrapping a sidewall of the first channel; a second metal track disposed on the first channel and coupled to the first channel; and a first capacitor disposed on the second metal track and coupled to the second metal track, the first capacitor including a first metal layer, a first capacitor dielectric layer, and a second metal layer. Each of the first metal layer, the first capacitor dielectric layer, and the second metal layer has at least a portion extending in a vertical direction.

[0051] In some embodiments, the semiconductor behavior material includes at least one of indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In2O3), or tin oxide (SnO2).

[0052] In some embodiments, the semiconductor behavior material includes at least one of nickel oxide (NiO), cuprous oxide (Cu2O), copper aluminum oxide (CuAlO2), copper gallium oxide (CuGaO2), copper oxide / indium oxide particles (CuInO2), strontium copper oxide (SrCu2O2) or stannous oxide (SnO).

[0053] In some embodiments, the first metal track, the first channel, the first gate structure, and the second metal track are operable to function as an access transistor of a first memory cell, wherein the first capacitor is operable to function as a storage element of the first memory cell.

[0054] In some embodiments, the first metal track is operable to function as part of a bit line (BL), and the first gate structure is operable to function as part of a word line (WL).

[0055] In some embodiments, the first metal track extends along a first lateral direction.

[0056] In some embodiments, the first metal track extends along a first lateral direction, and the memory device further includes: a second channel disposed above and coupled to the first metal track, the second channel also including the semiconductor behavior material and extending along the vertical direction; a second gate structure wrapping the sidewalls of the second channel; a third metal track disposed above and coupled to the second channel; and a second capacitor disposed above and coupled to the third metal track, the second capacitor including a third metal layer, a second capacitor dielectric layer and a fourth metal layer; wherein each of the third metal layer, the second capacitor dielectric layer and the fourth metal layer has at least a portion extending along the vertical direction.

[0057] In some embodiments, the first metal track extends along a first lateral direction, and the memory device further includes: a second channel, disposed above and coupled to the first metal track, the second channel also including the semiconductor behavior material and extending along the vertical direction; a second gate structure, wrapping the sidewalls of the second channel; a third metal track, disposed above and coupled to the second channel; and a second capacitor, disposed above and coupled to the third metal track, the second capacitor including a third metal layer, a second capacitor dielectric layer and a fourth metal layer; wherein each of the third metal layer, the second capacitor dielectric layer and the fourth metal layer has at least a portion extending along the vertical direction, wherein the first metal track, the second channel, the second gate structure and the third metal track are operable to serve as an access transistor of a second memory cell, wherein the second capacitor is operable to serve as a storage element of the second memory cell.

[0058] In some embodiments, the first metal track extends along a first lateral direction, and the memory device further includes: a second channel disposed above and coupled to the first metal track, the second channel also including the semiconductor behavior material and extending along the vertical direction; a second gate structure wrapping the sidewalls of the second channel; a third metal track disposed above and coupled to the second channel; and a second capacitor disposed above and coupled to the third metal track, the second capacitor including a third metal layer, a second capacitor dielectric layer and a fourth metal layer; wherein each of the third metal layer, the second capacitor dielectric layer and the fourth metal layer has at least a portion extending along the vertical direction, wherein the first gate structure and the second gate structure extend along a second lateral direction perpendicular to the first lateral direction.

[0059] In some embodiments, the memory device further comprises: a plurality of transistors disposed along a main surface of the substrate; wherein at least one of the plurality of transistors is configured to apply a voltage to the first capacitor through the first metal track.

[0060] In another aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes: a plurality of transistors arranged along a main surface of a substrate; and a plurality of metallization layers arranged above the main surface of the substrate, the metallization layers including a plurality of metal tracks. A plurality of memory cells are formed within the one or more metallization layers, and at least one transistor is electrically coupled to the plurality of memory cells. Each of the plurality of memory cells includes an access transistor and a storage capacitor, the access transistor and the storage capacitor being electrically coupled in series with each other and physically arranged relative to each other along a vertical direction.

[0061] In some embodiments, the access transistor includes a channel extending along the vertical direction and including a semiconductor behavior material, and the storage capacitor includes a first metal layer, a capacitor dielectric layer, and a second metal layer; and wherein each of the first metal layer, the capacitor dielectric layer, and the second metal layer has at least a portion extending along the vertical direction.

[0062] In some embodiments, the access transistor includes a channel extending along the vertical direction and including a semiconductor behavior material, and the storage capacitor includes a first metal layer, a capacitor dielectric layer, and a second metal layer; and wherein each of the first metal layer, the capacitor dielectric layer, and the second metal layer has at least a portion extending along the vertical direction, wherein the semiconductor behavior material having n-type conductivity includes at least one of indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In2O3), or tin oxide (SnO2).

[0063] In some embodiments, the access transistor includes a channel extending along the vertical direction and including a semiconductor behavior material, and the storage capacitor includes a first metal layer, a capacitor dielectric layer, and a second metal layer; and wherein each of the first metal layer, the capacitor dielectric layer, and the second metal layer has at least a portion extending along the vertical direction, wherein the semiconductor behavior material having p-type conductivity includes at least one of nickel oxide (NiO), cuprous oxide (Cu2O), copper aluminum oxide (CuAlO2), copper gallium oxide (CuGaO2), copper oxide / indium oxide particles (CuInO2), strontium copper oxide (SrCu2O2), or tin oxide (SnO).

[0064] In some embodiments, the access transistor includes a channel extending along the vertical direction and including a semiconductor behavior material, and the storage capacitor includes a first metal layer, a capacitor dielectric layer, and a second metal layer; and wherein each of the first metal layer, the capacitor dielectric layer, and the second metal layer has at least a portion extending along the vertical direction, wherein the first metal layer is directly disposed along the vertical direction above the channel, wherein the first metal layer surrounds the capacitor dielectric layer, and the capacitor dielectric layer further surrounds the second metal layer.

[0065] In some embodiments, a first metal track of the plurality of metal tracks is operable to function as a bit line for the plurality of memory cells, extending along a first lateral direction.

[0066] In some embodiments, a first metal track among the plurality of metal tracks is operable to function as a bit line for the plurality of memory cells, extending along a first lateral direction, wherein a second metal track among the plurality of metal tracks is operable to function as a corresponding word line for the plurality of memory cells, extending along a second lateral direction perpendicular to the first lateral direction.

[0067] In some embodiments, a first metal track among the plurality of metal tracks is operable to function as a bit line for the plurality of memory cells, extending along a first lateral direction, wherein a second plurality of metal tracks among the plurality of metal tracks is operable to function as corresponding word lines for the plurality of memory cells, extending along a second lateral direction perpendicular to the first lateral direction, wherein the word lines are disposed above the bit lines.

[0068] In yet another aspect of the present disclosure, a method for manufacturing a semiconductor device is disclosed. The method includes: forming a first metal track over a plurality of transistors formed along a main surface of a substrate, wherein the first metal track extends along a first lateral direction; forming a channel over the first metal track, wherein the channel extends along a vertical direction; forming a second metal track over the channel; forming a gate structure, the gate structure wrapping a portion of the sidewall of the channel; and forming a capacitor over the second metal track. The capacitor includes a first metal layer, a capacitor dielectric layer surrounding the first metal layer, and a second metal layer further surrounding the capacitor dielectric layer. Each of the first metal layer, the capacitor dielectric layer, and the second metal layer has at least a portion extending along a vertical direction. At least a portion of the first metal layer is disposed directly over the channel.

[0069] In some embodiments, the channel includes a semiconductor-behaving material having n-type conductivity or p-type conductivity.

[0070] As used herein, the terms "about" and "approximately" generally refer to a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" may refer to a value of a given quantity that varies, for example, within 10-30% of a value (e.g., ±10%, ±20%, or ±30% of a value).

[0071] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, comprising: A first metal track is disposed on the substrate; a first channel disposed on and coupled to the first metal track, the first channel comprising a semiconductor behavior material and extending along a vertical direction; a first gate structure, wrapping a sidewall of the first channel; a second metal track disposed above and coupled to the first channel; as well as a first capacitor disposed on and coupled to the second metal track, the first capacitor comprising a first metal layer, a first capacitor dielectric layer, and a second metal layer; Wherein, each of the first metal layer, the first capacitor dielectric layer and the second metal layer has at least a portion extending along the vertical direction.

2. The memory device according to claim 1, wherein: The semiconductor material includes at least one of indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In2O3) or tin oxide (SnO2).

3. The memory device according to claim 1, wherein: The semiconductor behavior material includes at least one of nickel oxide (NiO), cuprous oxide (Cu2O), copper aluminum oxide (CuAlO2), copper gallium oxide (CuGaO2), copper oxide / indium oxide particles (CuInO2), strontium copper oxide (SrCu2O2) or stannous oxide (SnO).

4. The memory device according to claim 1, wherein: The first metal track, the first channel, the first gate structure, and the second metal track are operable to function as an access transistor of a first memory cell, wherein the first capacitor is operable to function as a storage element of the first memory cell.

5. The memory device according to claim 1, wherein: The first metal track is operable to function as part of a bit line (BL), and the first gate structure is operable to function as part of a word line (WL).

6. The memory device according to claim 1, wherein: The first metal track extends along a first lateral direction.

7. The memory device according to claim 6, further comprising: a second channel disposed on the first metal track and coupled to the first metal track, the second channel also comprising the semiconductor material and extending along the vertical direction; a second gate structure, wrapping a sidewall of the second channel; a third metal track disposed above and coupled to the second channel; as well as a second capacitor disposed on and coupled to the third metal track, the second capacitor comprising a third metal layer, a second capacitor dielectric layer, and a fourth metal layer; Wherein, each of the third metal layer, the second capacitor dielectric layer and the fourth metal layer has at least a portion extending along the vertical direction.

8. The memory device according to claim 7, wherein: The first metal track, the second channel, the second gate structure, and the third metal track are operable to function as an access transistor of a second memory cell, wherein the second capacitor is operable to function as a storage element of the second memory cell.

9. A memory device comprising: A plurality of transistors are arranged along a major surface of the substrate; as well as a plurality of metallization layers disposed over the major surface of the substrate, the metallization layers comprising a plurality of metal tracks; wherein a plurality of memory cells are formed within one or more of the metallization layers, and at least one of the transistors is electrically coupled to the plurality of memory cells; and Each of the plurality of memory cells includes an access transistor and a storage capacitor, the access transistor and the storage capacitor being electrically coupled to each other in series and physically arranged relative to each other along a vertical direction.

10. A method of forming a memory device, comprising: forming a first metal track over a plurality of transistors formed along a major surface of the substrate, wherein the first metal track extends along a first lateral direction; forming a channel on the first metal track, wherein the channel extends along a vertical direction; forming a second metal track over the trench; forming a gate structure that wraps around a portion of a sidewall of the channel; and forming a capacitor over the second metal track; wherein the capacitor comprises a first metal layer, a capacitor dielectric layer surrounding the first metal layer, and a second metal layer further surrounding the capacitor dielectric layer, wherein each of the first metal layer, the capacitor dielectric layer, and the second metal layer has at least one portion extending along the vertical direction, and wherein the at least one portion of the first metal layer is directly disposed above the channel.

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