Memory device and manufacturing method thereof

Abstract

The invention relates to a memory device and a manufacturing method thereof. The memory device includes: a substrate; the source line is arranged on the substrate and is connected with the substrate; the gate lines are arranged on the sides, away from the substrate, of the source lines, and the gate lines are arranged at intervals in the first direction perpendicular to the substrate; the channel structure penetrates through the multiple gate lines in the first direction, and the bottom of the channel structure is connected with the source line; the channel structure comprises a gate insulating layer, a charge capturing layer, a tunneling layer, a channel layer and a core column which are sequentially arranged in the direction from the gate line to the center of the channel structure, and the core column comprises a first isolating layer, a conductive layer and a second isolating layer which are sequentially arranged in the direction away from the source line; and the bit line is arranged on one side, far away from the source line, of the channel structure. The charging and discharging time of the reading operation on the storage unit can be reduced, and the dynamic power consumption generated by the reading operation is reduced. The reading speed of the memory unit is improved, and the service life of the memory device is prolonged.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a memory device and a manufacturing method thereof. Background Art

[0002] NAND Flash (‌Not AND Flash, NAND) is a non-volatile memory. NAND Flash memory has the advantages of high storage density, low cost, long life and low power consumption. It is widely used in solid-state drives, mobile flash drives (USB flashdisk), memory cards and embedded systems.

[0003] Currently, NAND Flash memory improves storage density by vertically stacking and connecting storage in series using a vertical method, thereby achieving higher storage density and lower cost. However, NAND Flash memory still has many problems. Summary of the invention

[0004] Based on this, it is necessary to provide a storage device and a manufacturing method thereof to address the problems in the prior art.

[0005] In order to achieve the above object, on the one hand, the present disclosure provides a storage device, including:

[0006] substrate;

[0007] A source line, disposed on the substrate and connected to the substrate;

[0008] A plurality of gate lines are arranged on a side of the source line away from the substrate, and the plurality of gate lines are arranged at intervals along a first direction perpendicular to the substrate;

[0009] A channel structure, passing through the plurality of gate lines along the first direction, the bottom of the channel structure being connected to the source line; along the gate line pointing to the center direction of the channel structure, the channel structure comprises a gate insulating layer, a charge trapping layer, a tunneling layer, a channel layer and a core column arranged in sequence, the core column comprising a first isolation layer, a conductive layer and a second isolation layer arranged in sequence in a direction away from the source line;

[0010] The bit line is arranged on a side of the channel structure away from the source line.

[0011] In one embodiment, the plurality of gate lines include a source gate line, a plurality of word lines, and a drain gate line sequentially arranged along the first direction.

[0012] In one embodiment, the top surface of the first isolation layer is lower than the multiple word lines, the bottom surface of the second isolation layer is higher than the multiple word lines, and the conductive layer is disposed between the top surface of the first isolation layer and the bottom surface of the second isolation layer.

[0013] In one embodiment, the source lines are connected to the channel structures in a one-to-one correspondence; or, a plurality of adjacent channel structures are connected to the same source line.

[0014] In a second aspect, the present disclosure provides a storage device, including:

[0015] substrate;

[0016] A source line, disposed on the substrate and connected to the substrate;

[0017] A storage string is arranged on a side of the source line away from the substrate, the storage string is connected to the substrate through the source line, the storage string comprises a lower gate tube, a plurality of storage cells and an upper gate tube sequentially arranged along a first direction perpendicular to the substrate, the storage cell comprises a storage transistor and a bypass resistor connected in parallel with the storage transistor;

[0018] A plurality of word lines are arranged at intervals along the first direction, and the word lines are connected to control gates of the storage transistors arranged in the same layer;

[0019] A source gate line is provided below the plurality of word lines, and the source gate line is connected to a control gate of the lower gate tube;

[0020] A drain gate line is disposed above the plurality of word lines, and the drain gate line is connected to a control gate of the upper gate tube;

[0021] A bit line is arranged on a side of the upper selection tube away from the substrate, and the bit line is connected to the upper selection tube of at least one of the storage strings.

[0022] In one embodiment, the source lines are connected to the memory strings in a one-to-one correspondence; or, a plurality of adjacent memory strings are connected to the same source line.

[0023] In one embodiment, the storage strings are arranged in a plurality of columns along a second direction parallel to the substrate, and the plurality of columns of storage strings are arranged at intervals along a third direction, wherein the third direction is parallel to the substrate and intersects the second direction;

[0024] The bit lines extend on the memory strings along the second direction, and each of the bit lines is connected to each column of the memory strings.

[0025] In a third aspect, the present disclosure provides a method for manufacturing a memory device, comprising:

[0026] Providing a substrate, and forming a source line on one side of the substrate;

[0027] forming a stacked structure on a side of the source line away from the substrate, the stacked structure comprising alternating insulating layers and sacrificial layers;

[0028] forming a first hole, wherein the first hole penetrates the stacked structure along a first direction perpendicular to the substrate, and the first hole exposes a portion of the top surface of the source line;

[0029] A channel structure is formed in the first hole, and a direction pointing to the center of the channel structure along the stacked structure is formed, wherein the channel structure comprises a gate insulating layer, a charge trapping layer, a tunneling layer, a channel layer and a core column which are sequentially arranged, and the core column comprises a first isolation layer, a conductive layer and a second isolation layer which are sequentially arranged in a direction away from the source line;

[0030] removing the sacrificial layer, and filling a conductive material in the area where the sacrificial layer is removed to form a plurality of gate lines arranged at intervals along the first direction;

[0031] A bit line is formed on a side of the channel structure away from the source line.

[0032] In one embodiment, forming a channel structure in the first hole comprises:

[0033] forming a gate insulating layer, a charge trapping layer, a tunneling layer and a channel layer sequentially covering the inner sidewall of the first hole, wherein at least a portion of the bottom surface of the channel layer is in contact with the source line;

[0034] A first isolation layer, a conductive layer, and a second isolation layer are formed inside the channel layer. The first isolation layer, the conductive layer, and the second isolation layer are sequentially arranged in a direction away from the substrate.

[0035] In one embodiment, each of the first holes is formed on each of the source lines, and the source lines are connected to the channel structures in a one-to-one correspondence;

[0036] Alternatively, a plurality of the first holes are formed on each of the source lines, and a plurality of adjacent channel structures are connected to the same source line.

[0037] The memory device and the manufacturing method thereof disclosed in the present invention design the core column of the channel structure as a first isolation layer, a conductive layer and a second isolation layer which are sequentially arranged in a direction away from a source line. The conductive layer is arranged on the inner side of the channel layer to form a bypass resistor connected in parallel with the memory transistor. The existence of the bypass resistor enables the corresponding memory string to always form a current path regardless of whether the memory cells of the memory string are turned on or off. When performing a read operation on the memory cells of the memory string, it is only necessary to apply a read voltage to the read memory cells without applying a high voltage to the memory cells of the same memory string. This can reduce the charge and discharge time of the memory cells caused by the read operation and reduce the dynamic power consumption generated by the read operation. This is beneficial to improving the read speed of the memory cells and extending the service life of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 is a schematic structural diagram of a storage device provided in an embodiment;

[0040] Figure 2 is a schematic structural diagram of a storage device provided in another embodiment;

[0041] Figure 3 for Figure 2 A top view of a storage device;

[0042] Figure 4 is a circuit schematic diagram of a memory device provided in an embodiment;

[0043] Figure 5 is a circuit diagram of a memory device provided in an embodiment;

[0044] Figure 6 is a process flow chart of a method for manufacturing a memory device provided in an embodiment;

[0045] Figure 7 is a schematic diagram of a substrate integrated with a driving circuit layer provided in an embodiment;

[0046] Figure 8 is a schematic diagram after forming a second dielectric layer provided in an embodiment;

[0047] Fig. 9 is a schematic diagram after forming a first via hole provided in an embodiment;

[0048] Fig.10 is a schematic diagram after forming a connecting plug provided in an embodiment;

[0049] Fig.11 is a schematic diagram after a source line is formed according to an embodiment;

[0050] Fig.12 is a schematic diagram of a stacked structure after being formed provided in an embodiment;

[0051] Fig.13 is a schematic diagram after forming a first hole provided in an embodiment;

[0052] Fig.14 A schematic diagram of a process after forming a gate insulating layer, a charge trapping layer, and a tunneling layer sequentially covering the inner sidewall of the first hole provided in an embodiment;

[0053] Fig.15 is a schematic diagram after forming a protective layer in one embodiment;

[0054] Fig.16 It is a schematic diagram after removing the protection layer, the gate insulating layer, the charge trapping layer, and the tunneling layer on the bottom surface of the first hole provided in one embodiment;

[0055] Fig.17 is a schematic diagram after removing the protective layer provided in an embodiment;

[0056] Fig.18 is a schematic diagram after forming a channel layer provided in an embodiment;

[0057] Fig.19 is a schematic diagram after depositing a first isolation layer provided in an embodiment;

[0058] Fig. 20 A schematic diagram of a first isolation layer after etching back provided in an embodiment;

[0059] Fig.21 is a schematic diagram after depositing a conductive layer provided in an embodiment;

[0060] Fig. 22 is a schematic diagram of a conductive layer after etching back provided in an embodiment;

[0061] Fig.23 is a schematic diagram after depositing a second isolation layer provided in an embodiment;

[0062] Fig.24 A schematic diagram of the second isolation layer after etching back provided in an embodiment;

[0063] Fig.25 is a schematic diagram after a bit line contact portion is formed according to an embodiment;

[0064] Fig.26 is a schematic diagram after removing the sacrificial layer provided in an embodiment;

[0065] Fig. 27 FIG. 1 is a schematic diagram after forming a high dielectric material layer and a gate line according to an embodiment.

[0066] Description of reference numerals:

[0067] 10. substrate; 11. driving circuit layer; 11-1. source contact electrode; 191. first dielectric layer; 12. second dielectric layer; 121. first via hole; 13. connection plug; 141. protection layer; 20. laminated structure; 21. insulating layer; 22. sacrificial layer; 23. first hole; 30. channel structure; 31. gate insulating layer; 32. charge trapping layer; 33. tunneling layer; 34. channel layer; 35. core column; 36. first isolation layer; 37. conductive layer; 38. second isolation layer; 39. high dielectric material layer; SL, source line; SG, gate line; TR, storage cell; T, storage transistor; R, bypass resistor; SSL, source gate line; WL, word line; DSL, drain gate line; BM, lower gate tube; TM, upper gate tube; BL, bit line; BLC, bit line contact; Str, storage string;

[0068] Z, first direction; Y, second direction; X, third direction. DETAILED DESCRIPTION

[0069] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0070] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0071] As described in the background art, NAND Flash memory still has many shortcomings. The array structure of NAND Flash memory may cause problems such as response delay, power consumption, and bandwidth.

[0072] For example, the storage string of NAND Flash memory is composed of flash memory cells (Flash) connected in series. A current path can only be formed when all flash memory cells on the storage string are turned on. The storage string can only read the storage data of one flash memory cell at a time. When reading a flash memory cell, all flash memory cells on the same storage string need to be turned on, that is, a high voltage must be applied to the gate of the flash memory cell, resulting in a longer charging and discharging time and higher dynamic power consumption.

[0073] In addition, the storage strings of NAND Flash memory cannot be independently led out. On the side close to the upper gate tube, thousands of storage strings in a storage plane are connected to the same bit line (BL); on the side close to the bottom gate tube, tens of thousands of storage strings in a storage block are connected to the same source line (SL). This lead-out method means that each bit line (BL) can only read one storage string at a time, which limits the amount of storage information that can be read at a time and the sequential read bandwidth of NAND Flash memory.

[0074] According to an exemplary embodiment, the present disclosure provides a storage device such as Figure 1-Figure 5 As shown, the memory device includes a substrate 10, a source line SL, a plurality of gate lines SG, a channel structure 30 and a bit line BL; a driving circuit layer 11 may be integrated on the substrate 10, and the driving circuit layer 11 provides a voltage or current signal to the memory device to control the write or read operation of the memory device; the source line SL is arranged on the substrate 10 and connected to the substrate 10; a plurality of gate lines SG are arranged on a side of the source line SL away from the substrate 10, and the plurality of gate lines SG are arranged at intervals along a first direction Z perpendicular to the substrate 10; the channel structure 30 passes through the plurality of gate lines SG along the first direction Z, and the bottom of the channel structure 30 is connected to the source line SL; along the gate line SG pointing to the center direction of the channel structure 30, the channel structure 30 includes a gate insulating layer 31, a charge trapping layer 32, a tunneling layer 33, a channel layer 34 and a core column 35 arranged in sequence, and the core column 35 includes a first isolation layer 36, a conductive layer 37 and a second isolation layer 38 arranged in sequence in a direction away from the source line SL; the bit line BL is arranged on a side of the channel structure 30 away from the source line SL.

[0075] The conductive layer 37 is located between the first isolation layer 36 and the second isolation layer 38, and the conductive layer 37 forms a bypass resistor R connected in series with the storage transistor T of the storage string Str, so that the current of the storage string Str can form a current path through the bypass resistor R without turning on all the storage transistors T. In this way, the reading operation of the storage cell TR can be simplified. When reading the storage cell TR, it is only necessary to apply a high voltage to the read storage cell TR, without applying a high voltage to the storage cells TR of the entire storage string Str.

[0076] In the storage device of the present embodiment, the core column 35 of the channel structure 30 is designed to be a first isolation layer 36, a conductive layer 37 and a second isolation layer 38 which are sequentially arranged in a direction away from the source line SL. The conductive layer 37 is arranged on the inner side of the channel layer 34 to form a bypass resistor R connected in parallel with the storage transistor T. The existence of the bypass resistor R ensures that no matter the storage cell TR of the storage string Str is turned on or off, the corresponding storage string Str can always form a current path. When performing a read operation on the storage cell TR of the storage string Str, it is only necessary to apply a read voltage to the storage cell TR to be read, and there is no need to apply a high voltage to the storage cell TR of the same storage string Str. This can reduce the charge and discharge time of the storage cell TR caused by the read operation, and reduce the dynamic power consumption generated by the read operation. This is beneficial to improving the reading speed of the storage cell TR and extending the service life of the storage device.

[0077] In some embodiments, Figure 1-Figure 5 As shown, the plurality of gate lines SG include a source gate line SSL, a plurality of word lines WL, and a drain gate line DSL sequentially arranged along a first direction Z. The gate lines SG are arranged parallel to the top surface of the substrate 10 and arranged at intervals along the first direction Z. The channel structure 30 vertically penetrates the plurality of gate lines SG along the first direction Z and is arranged on the substrate 10. Each gate line SG surrounds and covers a portion of the peripheral surface of the channel structure 30.

[0078] In this embodiment, along the first direction Z, the lowest gate line SG among the multiple gate lines SG (the gate line SG closest to the substrate 10) is the source gate line SSL. The part where the source gate line SSL intersects with the channel structure 30 constitutes the lower gate tube BM. The source gate line SSL covers the channel of the lower gate tube BM and is connected to the control gate of the lower gate tube BM. The source gate line SSL is used to open and close the lower gate tube BM.

[0079] Along the first direction Z, the topmost gate line SG among the multiple gate lines SG (the gate line SG farthest from the substrate 10) is the drain gate line DSL. The part where the drain gate line DSL intersects with the channel structure 30 constitutes the upper gate tube TM. The drain gate line DSL covers the channel of the upper gate tube TM and is connected to the control gate of the upper gate tube TM. The drain gate line DSL is used to turn on and off the upper gate tube TM.

[0080] The plurality of gate lines SG between the source gate line SSL and the drain gate line DSL are a plurality of word lines WL (WL1, WL2...WL n ), the part where the word line WL intersects with the channel structure 30 constitutes a storage transistor T, and the word line WL surrounds the channel of the storage transistor T and is connected to the control gate of the storage transistor T. In this way, each word line WL can independently select its corresponding storage transistor T, thereby realizing the reading and writing operations of the stored data.

[0081] In some embodiments, Figure 1-Figure 5 As shown, the top surface of the first isolation layer 36 is lower than the multiple word lines WL, the bottom surface of the second isolation layer 38 is higher than the multiple word lines WL, and the conductive layer 37 is disposed between the top surface of the first isolation layer 36 and the bottom surface of the second isolation layer 38. Along the first direction Z, the first isolation layer 36 is disposed between the conductive layer 37 and the source line SL to isolate the conductive layer 37 from the source line SL and prevent the conductive layer 37 and the source line SL from forming a conductive path. The second isolation layer 38 is disposed between the conductive layer 37 and the bit lines BL (BL1, BL2, BL3) to isolate the conductive layer 37 from the bit lines BL (BL1, BL2, BL3) and prevent the conductive layer 37 and the bit lines BL (BL1, BL2, BL3) from forming a conductive path.

[0082] The first isolation layer 36 is located inside the channel layer 34 of the lower gate tube BM, the second isolation layer 38 is located inside the channel layer 34 of the upper gate tube TM, and the conductive layer 37 is provided inside the channel layer 34 of the plurality of storage transistors T. On one hand, the conductive layer 37 can form a bypass resistor R in parallel with the inner side of the storage transistors T in the same series, and on the other hand, the conductive layer 37 is prevented from extending to the region of the lower gate tube BM and the upper gate tube TM, thereby avoiding unnecessary interference to the lower gate tube BM or the upper gate tube TM, and avoiding unexpected conduction of the lower gate tube BM or the upper gate tube TM.

[0083] In some embodiments, Figure 1-Figure 5 As shown, the source line SL is connected to the channel structure 30 in a one-to-one correspondence; or, a plurality of adjacent channel structures 30 are connected to the same source line SL. In this way, on the one hand, in the third direction X, the number of storage strings Str processed by each source line SL can be reduced, and on the other hand, in the second direction Y, each bit line BL (BL1, BL2, BL3...) can be connected to a plurality of storage strings Str, and a column of storage strings Str connected to the same bit line BL (BL1, BL2, BL3) can be connected to a plurality of source lines SL, and a column of storage strings Str connected to the same bit line BL (BL1, BL2, BL3) can be read in parallel, thereby improving the read bandwidth.

[0084] In one example, each channel structure 30 is connected to a corresponding source line SL. Thus, each source line SL independently operates and controls a string of memory strings Str, thus increasing the speed of parallel reading of the memory strings Str of the plurality of channel structures 30 and further increasing the reading bandwidth.

[0085] In another example, several adjacent channel structures 30 are connected to one source line SL. For example, two, three, four or more adjacent channel structures 30 may be connected to one source line SL. In this way, the manufacturing difficulty and production cost can be reduced.

[0086] In some embodiments, Figure 1-Figure 5 As shown, the channel structures 30 are arranged in multiple columns along the second direction Y and in multiple rows along the third direction X. In other words, the channel structures 30 are arrayed along the second direction Y and the third direction X. The second direction Y and the third direction X are parallel to the substrate 10, and the second direction Y and the third direction X intersect. In this embodiment, the second direction Y is perpendicular to the third direction X.

[0087] In this embodiment, the source lines SL are also arranged in an array along the second direction Y and the third direction X. This facilitates the layout of the source lines SL and realizes a one-to-one connection between the source lines SL and the channel structures 30; or, a plurality of adjacent channel structures 30 are connected to the same source line SL.

[0088] In a second aspect, the present disclosure provides a storage device, such as Figure 1-Figure 5 As shown, the memory device includes a substrate 10, a source line SL, a memory string Str, a plurality of word lines WL, a source gate line SSL, a drain gate line DSL and a bit line BL; a driving circuit layer 11 may be integrated on the substrate 10, and the driving circuit layer 11 provides a voltage or current signal to the memory device to control the write or read operation of the memory device; the source line SL is arranged on the substrate 10 and connected to the substrate 10; the memory string Str is arranged on a side of the source line SL away from the substrate 10, and the memory string Str is connected to the substrate 10 through the source line SL, and the memory string Str includes a lower gate transistor BM, a plurality of memory units BL, and a plurality of memory units BL. The memory cell TR comprises a memory transistor T and an upper gate transistor TM, wherein the memory cell TR comprises a memory transistor T and a bypass resistor R connected in parallel with the memory transistor T; a plurality of word lines WL are arranged at intervals along a first direction Z, and the word lines WL are connected to the control gates of the memory transistors T arranged in the same layer; a source gate line SSL is arranged below the plurality of word lines WL, and the source gate line SSL is connected to the control gate of the lower gate transistor BM; a drain gate line DSL is arranged above the plurality of word lines WL, and the drain gate line DSL is connected to the control gate of the upper gate transistor TM; a bit line BL is arranged on a side of the upper gate transistor TM away from the substrate 10, and the bit line BL is connected to the upper gate transistor TM of at least one memory string Str.

[0089] The storage device of this embodiment improves the structure of the storage cell TR and connects the storage transistor T in parallel with the bypass resistor R, so that no matter whether the storage transistor T of the storage cell TR is turned on or off, the storage string Str where the storage cell TR is located can always form a current path. When performing a read operation on the storage cell TR of the storage string Str, it is only necessary to apply a read voltage to the read storage cell TR, and there is no need to apply a high voltage to the storage cell TR of the same storage string Str. This can reduce the charge and discharge time of the storage cell TR caused by the read operation, and reduce the dynamic power consumption generated by the read operation; it is beneficial to improve the read speed of the storage cell TR and extend the service life of the storage device.

[0090] In some embodiments, the resistance value R of the bypass resistor R is greater than the channel equivalent resistance Ron when the storage transistor T is turned on, and less than the channel equivalent resistance R when the storage transistor T is turned off. off .

[0091] The memory device of this embodiment controls the word line WL voltage V WL and the threshold voltage V of the storage transistor T T The size of the word line WL can control the switching state of the storage transistor T. WL >V T When the storage transistor T is turned on, the equivalent resistance of the storage unit TR is approximately equal to the channel equivalent resistance R when the storage transistor T is turned on. on , the current mainly flows through the storage transistor T; when V WL <V T When the storage transistor T is turned off, the equivalent resistance of the storage cell TR is close to the resistance of the bypass resistor R, and the current mainly passes through the bypass resistor R. Therefore, whether the storage transistor T is turned on or off, the storage string Str where the storage cell TR is located can always form a current path, thereby realizing that when performing a read operation on the storage cell TR of the storage string Str, only a read voltage needs to be applied to the read storage cell TR, and there is no need to apply a high voltage to the storage cell TR of the same storage string Str.

[0092] In some embodiments, Figure 1-Figure 5 As shown, the source line SL is connected to the storage string Str in a one-to-one correspondence; or, multiple adjacent storage strings Str are connected to the same source line SL. In this way, the number of storage strings Str processed by each source line SL can be reduced. Since each bit line BL (BL1, BL2, BL3) can be connected to multiple channel structures 30, parallel reading of storage strings Str of multiple channel structures 30 can be achieved, thereby improving the reading bandwidth. In one example, each channel structure 30 is connected to a source line SL in correspondence; in another example, several adjacent channel structures 30 are connected to one source line SL.

[0093] In some embodiments, Figure 1-Figure 5 As shown, the storage strings Str are arranged into multiple columns along a second direction Y parallel to the substrate 10, and the multiple columns of storage strings Str are arranged at intervals along a third direction X, which is parallel to the substrate 10 and intersects with the second direction Y; the bit lines BL (BL1, BL2, BL3) extend on the storage strings Str along the second direction Y, and each bit line BL is connected to each column of the storage strings Str.

[0094] The storage device design of this embodiment has good scalability, and the number of storage cells TR can be increased and / or the layout of word lines WL, source lines SL, bit lines BL, etc. can be adjusted to expand the storage capacity to meet different application requirements.

[0095] In the memory device of the disclosed embodiment, the read operation of each memory string Str is independent, and the storage state can be determined by detecting the accumulated voltage drop ΔV, so that parallel reading of multiple memory pages can be achieved, which significantly improves the bandwidth and efficiency of the memory device read operation.

[0096] For example, in some embodiments, when a read operation is performed on a memory device, a read voltage V is applied to the word line WL corresponding to the selected memory cell TR. read ; Apply a turn-off voltage V to the word line WL corresponding to the unselected memory cell TR shut , to prevent the unselected memory cell TR from interfering with the selected memory cell TR during the reading process; injecting a read current I from the source line SL into the memory string Str ref Among them, the read voltage V read The voltage value is between the high threshold voltage V of the storage transistor T to write logic "1" T,H And the low threshold voltage V of the storage transistor T to write logic "0" T,L between.

[0097] In this embodiment, the turn-off voltage V shut Less than the read voltage V read , high threshold voltage V T,H and low threshold voltage V T,L , ensuring that the storage transistor T can remain in the off state regardless of whether the threshold voltage of the storage transistor T is high or low.

[0098] By detecting the cumulative voltage drop ΔV of the storage string Str, when the storage transistor T is in the on or off state, the equivalent resistance of the storage unit TR will have a significant difference, the equivalent resistance difference is approximately R, the storage transistor T is turned on or off, and the detected cumulative voltage drop ΔV of the storage string Str will differ by approximately I ref R, the number of storage transistors T turned off in the selected storage cell TR can be calculated by the difference between the actual accumulated voltage drop of the storage string Str and the accumulated voltage drop of the unselected storage cells TR.

[0099] In this embodiment, when performing a read operation on the memory device, a turn-off voltage V is applied to the unselected memory cell TR. shut , there is no need to apply a high voltage to the unselected memory cell TR to turn on the storage transistor T to avoid interference with the reading process. By applying the read voltage V read and read current I ref Reading can be completed, thus reducing power consumption, latency and potential interference.

[0100] The above embodiments are merely exemplary implementations for performing a read operation on the memory device of the present disclosure and do not constitute a limitation on the memory device of the present disclosure.

[0101] In some other embodiments, when a read operation is performed on the memory device of the present disclosure, a read voltage V may be applied to the word line WL corresponding to the selected memory cell TR. read ; Apply a conduction voltage V to the word line WL corresponding to the unselected memory cell TR pass .

[0102] In this embodiment, V T,L <V read <V T,H <V pass That is, if and only if the threshold voltage of the storage transistor T is equal to V T,H And the word line voltage is equal to V read When the storage transistor T in the storage unit TR is in the off state and generates a voltage drop across the storage unit TR, the storage transistor T is turned on in other cases.

[0103] By detecting the accumulated voltage drop ΔV of the storage string Str, the number of the turned-off storage transistors T in the selected storage cell TR can be directly calculated.

[0104] According to an exemplary embodiment, the present disclosure provides a method for manufacturing a memory device, such as Figure 6 As shown, the method for manufacturing a memory device includes the following steps:

[0105] Step S10: providing a substrate 10, and forming a source line SL on one side of the substrate 10;

[0106] Step S20: forming a stacked structure 20 on a side of the source line SL away from the substrate 10, wherein the stacked structure 20 includes alternating insulating layers 21 and sacrificial layers 22;

[0107] Step S30: forming a first hole 23, wherein the first hole 23 penetrates the stacked structure 20 along a first direction Z perpendicular to the substrate 10, and the first hole 23 exposes a portion of the top surface of the source line SL;

[0108] Step S40: forming a channel structure 30 in the first hole 23, and pointing to the center direction of the channel structure 30 along the stacked structure 20, the channel structure 30 includes a gate insulating layer 31, a charge trapping layer 32, a tunneling layer 33, a channel layer 34 and a core column 35 arranged in sequence, and the core column 35 includes a first isolation layer 36, a conductive layer 37 and a second isolation layer 38 arranged in sequence along a direction away from the source line SL;

[0109] Step S50: removing the sacrificial layer 22, and filling the area where the sacrificial layer 22 is removed with a conductive material to form a plurality of gate lines SG arranged at intervals along the first direction Z;

[0110] Step S60 : forming a bit line BL on a side of the channel structure 30 away from the source line SL.

[0111] In the manufacturing method of the storage device of the present embodiment, the core column 35 of the channel structure 30 is formed into a first isolation layer 36, a conductive layer 37 and a second isolation layer 38 which are sequentially arranged along a direction away from the source line SL. The conductive layer 37 is arranged on the inner side of the channel layer 34 to form a bypass resistor R in parallel with the storage transistor T. The existence of the bypass resistor R enables the corresponding storage string Str to always form a current path regardless of whether the storage cell TR of the storage string Str is turned on or off. When performing a read operation on the storage cell TR of the storage string Str, it is only necessary to apply a high voltage to the read storage cell TR, and there is no need to apply a high voltage to the storage cell TR of the same storage string Str, which can reduce the charging and discharging time of the storage cell TR during the read operation and reduce the dynamic power consumption generated by the read operation; it is beneficial to improve the reading speed of the storage cell TR and extend the service life of the storage device; the storage device of the present embodiment can perform a read operation on a single storage cell TR in the storage string Str and finely control the single storage cell TR, thereby improving the operational flexibility of the storage device.

[0112] In step S10, Figure 7 As shown, the substrate 10 may be a semiconductor substrate, and the semiconductor substrate may include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. Ions may be doped in the semiconductor substrate, for example, the semiconductor substrate may be a P-type doped substrate or an N-type doped substrate. In this embodiment, the substrate is a silicon crystal substrate.

[0113] like Figure 7 As shown, a driving circuit layer 11 may be formed on the substrate 10 provided in this embodiment. For example, the driving circuit layer 11 may be formed on the substrate 10 using CUA technology. The driving circuit layer 11 is used to implement peripheral auxiliary circuit functions such as detection, amplification, and conversion. In this embodiment, the driving circuit layer 11 is used to provide a voltage or current signal to the storage device to control the write or read operation of the storage device.

[0114] It should be noted that CUA technology, also known as CMOS Under Array, is a design method that places most of the peripheral circuits of NAND chips (such as page buffers, read amplifiers, charge pumps, etc.) under the vertical stack of memory cells. This layout greatly saves wafer die space, allowing more area to be used for memory cell arrays, thereby improving storage density and performance.

[0115] Among them, Figure 7 As shown, source contact electrodes 11 - 1 are formed on the driving circuit layer 11 . The source contact electrodes 11 - 1 are used to be connected to the source line SL. A first dielectric layer 191 is filled between the source contact electrodes 11 - 1 .

[0116] In this embodiment, before forming the source line SL on one side of the substrate 10 , the process further includes: forming a connection plug 13 on the source contact electrode 11 - 1 for connecting the source contact electrode 11 - 1 and the source line SL.

[0117] like Figure 8 As shown, any one of the deposition processes of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD) or sputtering can be used to deposit and form the second dielectric layer 12, and the second dielectric layer 12 covers the top surface of the first dielectric layer 191 and the source contact electrode 11-1. Then, as shown in FIG. Fig. 9 As shown, the second dielectric layer 12 is etched to form a first via hole 121 penetrating the second dielectric layer 12, and the first via hole 121 correspondingly exposes the source contact electrode 11-1. Fig.10 As shown, any of the above-mentioned deposition processes can be used to fill the first via hole 121 with a conductive material to form a connecting plug 13 .

[0118] For example, the material of the second dielectric layer 12 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0119] For example, the material of the connecting plug 13 may include metal materials such as tungsten and copper.

[0120] In this embodiment, a source line SL is formed on one side of the substrate 10, and the following implementation methods may be adopted:

[0121] Any of the above deposition processes can be used to deposit and form a semiconductor layer (not shown in the figure), and the semiconductor layer covers the second dielectric layer and the top surface of the connecting plug 13. Then, a photoresist mask (not shown in the figure) is formed on the semiconductor layer. Fig.11 As shown, the semiconductor layer is etched according to the photoresist mask to form a plurality of independently arranged source lines SL, and the source lines SL are connected to the connection plugs 13 in a one-to-one correspondence.

[0122] For example, the material of the semiconductor layer may include silicon, germanium, silicon germanium, etc. The semiconductor layer may be doped with ions, for example, the semiconductor may be P-type doped or N-type doped.

[0123] For example, the semiconductor layer may be etched using a dry process, for example, a dry etching process such as reactive ion etching (RIE) or inductively coupled plasma etching (ICP) may be used.

[0124] In this embodiment, Fig.11 As shown, the source lines SL are arranged in an array along a second direction Y and a third direction X which are parallel to the substrate 10 , and the second direction Y is perpendicular to the third direction X.

[0125] In step S20, Fig.12 As shown, any one of chemical vapor deposition, physical vapor deposition, atomic layer deposition or sputtering can be used to alternately deposit insulating layer 21 and sacrificial layer 22 to form a stacked structure 20 on substrate 10. Sacrificial layer 22 has a high etching ratio relative to insulating layer 21. For example, the material of insulating layer 21 may include silicon oxide; the material of sacrificial layer 22 may include silicon nitride.

[0126] In this embodiment, the bottom layer and the top layer of the stacked structure 20 are both insulating layers 21. Thus, the bottom insulating layer 21 of the stacked structure 20 is used for electrical isolation between source lines SL and for electrical isolation between source lines SL and subsequently formed storage cells TR, thereby ensuring the safety of the storage device and improving the electrical performance of the storage device. The top insulating layer 21 of the stacked structure 20 is used to provide a process plane to facilitate the execution of subsequent processes.

[0127] It can be understood that the number of stacked layers of the stacked structure 20 can be flexibly adjusted according to manufacturing requirements, and this embodiment does not limit this.

[0128] In step S30, in this embodiment, a first mask layer (not shown in the figure) is formed on the top surface of the stacked structure 20. Fig.13As shown, the stacked structure 20 is etched according to the first mask layer until a portion of the top surface of the source line SL is exposed, thereby forming a first hole 23 penetrating the stacked structure 20 , and the bottom surface of the first hole 23 exposes a portion of the top surface of the source line SL.

[0129] In some embodiments, Fig.13 As shown, a plurality of first holes 23 are formed in the stacked structure 20 , and the plurality of first holes 23 are arranged in an array along the second direction Y and the third direction X.

[0130] In one example, each first hole 23 is formed on each source line SL, and the source line SL is connected to the channel structure 30 in a one-to-one correspondence. In another example, multiple first holes 23 are formed on each source line SL, and multiple adjacent channel structures 30 are connected to the same source line SL.

[0131] In step S40, a channel structure 30 is formed in the first hole 23, including the following steps:

[0132] Step S41 : forming a gate insulating layer 31 , a charge trapping layer 32 , a tunneling layer 33 and a channel layer 34 sequentially covering the inner sidewall of the first hole 23 , wherein at least a portion of the bottom surface of the channel layer 34 contacts the source line SL.

[0133] like Fig.14 As shown, a gate insulating layer 31, a charge trapping layer 32, and a tunneling layer 33 can be sequentially deposited by a chemical vapor deposition process or an atomic layer deposition process, and the gate insulating layer 31, the charge trapping layer 32, and the tunneling layer 33 sequentially cover the sidewalls of the first hole 23 and the bottom surface of the first hole 23.

[0134] The gate insulating layer 31 is made of at least one of silicon oxide, silicon nitride or silicon oxynitride. The charge trapping layer 32 is made of silicon nitride and is used to trap charges. The tunneling layer 33 is made of silicon oxide or silicon oxynitride.

[0135] Then, the gate insulating layer 31 , the charge trapping layer 32 , and the tunneling layer 33 on the bottom surface of the first hole 23 are removed by etching.

[0136] In this embodiment, Fig.15 As shown, the protective layer 141 can be formed by atomic layer deposition process, and the protective layer 141 covers the inner sidewall and bottom surface of the tunneling layer 33. The protective layer 141 is used to protect the gate insulating layer 31, the charge trapping layer 32 and the tunneling layer 33 located on the sidewall of the first hole 23. Fig.16 As shown, an anisotropic dry etching process is then used to remove the protective layer 141, the tunneling layer 33, the charge trapping layer 32 and the gate insulating layer 31 on the bottom surface of the first hole 23. Fig.17 As shown, the entire protection layer 141 is removed by etching using a wet process to expose the tunneling layer 33 located on the sidewall of the first hole 23 .

[0137] Then, if Fig.18 As shown, the channel layer 34 can be formed by plasma enhanced chemical vapor deposition, and the channel layer 34 covers the source line SL exposed at the bottom surface of the first hole 23 and the inner sidewall of the tunnel layer 33. In this way, the contact area between the channel layer 34 and the source line SL is larger, and the response rate of the source line SL controlling the channel structure 30 can be improved. The material of the channel layer 34 includes a semiconductor material (such as polysilicon) or a metal oxide material (such as IGZO).

[0138] IGZO is an amorphous or microcrystalline material with a relatively uniform molecular structure, a low processing temperature and no obvious grain boundaries. Using IGZO as the channel layer 34 can reduce the processing temperature, simplify the production process and reduce costs. IGZO has no obvious grain boundaries and can improve the carrier mobility of the channel layer 34, which helps to improve the switching speed and reliability of the transistor.

[0139] For example, the material of the metal oxide may be indium gallium zinc oxide (IGZO). The material of the metal oxide may also be ITO, IWO, ZnO x 、InO x 、In2O3、InWO、SnO2、TiO x 、InSnO x 、Zn x O y N z Mg x Zn y O z 、In x Zn y O z 、In x Ga y Zn z O a 、Zr x In y Zn z O a , Hf x In y Zn z O a Sn x In y Zn z O a 、Al x Sn y In z Zn a O d 、Six In y Zn z O a 、Zn x Sn y O z 、Al x Zn y Sn z O a , Ga x Zn y Sn z O a 、Zr x Zn y Sn z O a , InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZO x And other materials.

[0140] Step S42 : forming a first isolation layer 36 , a conductive layer 37 and a second isolation layer 38 on the inner side of the channel layer 34 , wherein the first isolation layer 36 , the conductive layer 37 and the second isolation layer 38 are sequentially arranged in a direction away from the substrate 10 .

[0141] First, if Fig.19 As shown, the first isolation layer 36 can be deposited by chemical vapor deposition or plasma enhanced chemical vapor deposition. The first isolation layer 36 covers the inner side of the channel layer 34 and fills at least a portion of the first hole 23. Fig. 20 As shown, the first isolation layer 36 is etched back so that the first isolation layer 36 is located at the bottom of the first hole 23.

[0142] For example, the material of the first isolation layer 36 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0143] The first isolation layer 36 may include a single-layer structure or a multi-layer structure. In this embodiment, the first isolation layer 36 includes silicon oxide, so that the electrical isolation effect of the first isolation layer 36 is better.

[0144] Then, if Fig.21 As shown, an atomic layer deposition or chemical vapor deposition conductive layer 37 is performed, and the conductive layer 37 covers the top surface of the first isolation layer 36 and fills the unfilled portion of the first hole 23, as shown in FIG. Fig. 22 As shown, the conductive layer 37 is etched back so that the conductive layer 37 is located in the first hole 23 .

[0145] For example, the material of the conductive layer 37 may include zinc oxide (ZnO2), vanadium oxide (VO x The material of the conductive layer 37 may also include a conductive metal, such as at least one of tungsten, titanium, and tantalum.

[0146] Then, if Fig.23 , Fig.24 As shown, the second isolation layer 38 may be deposited by chemical vapor deposition or plasma enhanced chemical vapor deposition. The second isolation layer 38 covers the conductive layer 37 and fills the unfilled portion of the first hole 23 .

[0147] The second isolation layer 38 may include a single-layer structure or a multi-layer structure. In this embodiment, the second isolation layer 38 includes a silicon oxide layer, a silicon nitride layer and a silicon oxide layer stacked in sequence, so that the electrical isolation effect of the second isolation layer 38 is better.

[0148] In step S50, the sacrificial layer 22 is removed, and a conductive material is filled in the area where the sacrificial layer 22 is removed to form a plurality of gate lines SG arranged at intervals along the first direction Z. The following implementations may be adopted:

[0149] like Fig.26 As shown, a second mask layer (not shown in the figure) is formed on the top surface of the stacked structure 20, and the stacked structure 20 is etched according to the second mask layer to form a second hole (not shown in the figure) penetrating the stacked structure 20, and the second hole is staggered with the first hole 23.

[0150] Then, an etching solution is injected into the second hole to dissolve and remove all the sacrificial layer 22. In this embodiment, the etching solution may be hot phosphoric acid.

[0151] Then, if Fig. 27 As shown, the high dielectric material layer 39 may be formed by atomic layer deposition or chemical vapor deposition, and the high dielectric material layer 39 covers the exposed surface of the insulating layer 21 and the exposed surface of the gate insulating layer 31 .

[0152] For example, the material of the high dielectric material layer 39 includes a high dielectric constant material (High-K dielectric), such as hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (AlO x ), titanium oxide (TiO2), tantalum oxide (TaO x ) at least one of the following.

[0153] Then, if Fig. 27 As shown, physical vapor deposition or plasma enhanced chemical vapor deposition or atomic layer deposition process can be used to deposit a conductive material to cover the high dielectric material layer 39 and fill the area where the sacrificial layer 22 is removed, forming a plurality of gate lines SG arranged at intervals along the first direction Z.

[0154] Exemplarily, the material of the gate line SG may include one or more selected from metal vanadium (V), metal niobium (Nb), metal ruthenium (Ru), metal tungsten (W), metal tantalum (Ta), tantalum nitride (TaN), metal titanium (Ti), titanium nitride (TiN), metal hafnium (Hf), metal iridium (Ir), metal manganese (Mn), metal zinc (Zn), metal platinum (Pt), metal palladium (Pd), metal copper (Cu), or alloys thereof.

[0155] In this embodiment, Fig. 27 As shown, after forming a plurality of gate lines SG, the conductive material and high dielectric material layer 39 in the second hole are removed by etching. Insulating material is deposited into the second hole to form an insulating column. The material of the insulating column may include at least one of silicon oxide, silicon nitride or silicon oxynitride.

[0156] In step S60, a bit line BL is formed on a side of the channel structure 30 away from the source line SL. The following implementations may be used:

[0157] First, if Fig.23 , Fig.24 As shown, the second isolation layer 38 is etched back so that the top surface of the second isolation layer 38 is lower than the top surface of the first hole 23 , and the second isolation layer 38 exposes a portion of the inner sidewall of the channel layer 34 .

[0158] Then, if Fig.25 As shown, an atomic layer deposition process can be used to deposit a contact layer (not shown in the figure), the contact layer covers the second isolation layer 38 to expose part of the inner sidewall of the channel layer 34 and fills the unfilled area of ​​the first hole 23, and the contact layer also covers the top surface of the stacked structure 20. The contact layer covering the top surface of the stacked structure 20 is removed by etching, and a bit line contact portion BLC is formed in the first hole 23. The bit line contact portion BLC is used to reduce the contact resistance between the bit line BL and the channel layer 34, which is beneficial to improve the response speed of the bit line BL and improve the electrical performance of the memory device.

[0159] By way of example, the material of the bit line contact BLC may include silicon.

[0160] Then, if Figure 1-5 As shown, the bit line conductive layer can be deposited by physical vapor deposition, plasma enhanced chemical vapor deposition or atomic layer deposition process, and the bit line conductive layer covers the top surface of the bit line conductive layer and the top surface of the stacked structure 20. The bit line conductive layer is patterned and etched to form the bit line BL, which extends along the second direction Y and is arranged at intervals along the third direction X.

[0161] For example, the material of the bit line BL may include tungsten, titanium, or the like.

[0162] It should be understood that although Figure 7The steps in the above-mentioned process steps are shown in sequence according to arrows or step sequence indications, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 7 At least part of the steps in the process described above may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0163] The order of manufacturing the storage unit, word line, bit line and source line in the above embodiments can be arbitrarily changed or combined with each other. Therefore, those skilled in the art can combine and / or change any number of manufacturing processes of the storage unit, word line, bit line and source line without creative work, which should all fall within the protection scope of the embodiments of the present disclosure.

[0164] In some embodiments, an electronic device is provided, including a memory as described in any of the embodiments of the present disclosure. The electronic device is, for example but not limited to, suitable types of electronic products such as consumer electronic products, home electronic products, vehicle-mounted electronic products, and financial terminal products. Consumer electronic products include mobile phones, tablet computers, laptop computers, desktop monitors, all-in-one computers, etc. Home electronic products include smart door locks, televisions, refrigerators, wearable devices, etc. Vehicle-mounted electronic products include vehicle-mounted navigation systems, vehicle-mounted DVDs, etc. Financial terminal products include ATM machines, self-service terminals, etc.

[0165] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided by the present disclosure can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive memory (ReRAM), magneto-resistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. The database involved in the embodiments provided by the present disclosure can include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited thereto. The processors involved in the various embodiments provided in the present disclosure may be general-purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, data processing logic devices based on quantum computing, etc., but are not limited thereto. The technical features of the above embodiments may be combined arbitrarily. In order to make the description concise, all possible combinations of the various technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0166] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.

[0167] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0168] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A storage device, characterized in that: include: substrate; A source line, disposed on the substrate and connected to the substrate; A plurality of gate lines are arranged on a side of the source line away from the substrate, and the plurality of gate lines are arranged at intervals along a first direction perpendicular to the substrate; A channel structure, passing through the plurality of gate lines along the first direction, the bottom of the channel structure being connected to the source line; along the gate line pointing to the center direction of the channel structure, the channel structure comprises a gate insulating layer, a charge trapping layer, a tunneling layer, a channel layer and a core column arranged in sequence, the core column comprising a first isolation layer, a conductive layer and a second isolation layer arranged in sequence in a direction away from the source line; The bit line is arranged on a side of the channel structure away from the source line.

2. The memory device according to claim 1, wherein: The plurality of gate lines include a source gate line, a plurality of word lines, and a drain gate line sequentially arranged along the first direction.

3. The memory device according to claim 2, wherein: The top surface of the first isolation layer is lower than the multiple word lines, the bottom surface of the second isolation layer is higher than the multiple word lines, and the conductive layer is arranged between the top surface of the first isolation layer and the bottom surface of the second isolation layer.

4. The memory device according to any one of claims 1 to 3, characterized in that: The source lines are connected to the channel structures in a one-to-one correspondence; or, a plurality of adjacent channel structures are connected to the same source line.

5. A storage device, characterized in that: include: substrate; A source line, disposed on the substrate and connected to the substrate; A storage string is arranged on a side of the source line away from the substrate, the storage string is connected to the substrate through the source line, the storage string comprises a lower gate tube, a plurality of storage cells and an upper gate tube sequentially arranged along a first direction perpendicular to the substrate, the storage cell comprises a storage transistor and a bypass resistor connected in parallel with the storage transistor; A plurality of word lines are arranged at intervals along the first direction, and the word lines are connected to control gates of the storage transistors arranged in the same layer; A source gate line is provided below the plurality of word lines, and the source gate line is connected to a control gate of the lower gate tube; A drain gate line is disposed above the plurality of word lines, and the drain gate line is connected to a control gate of the upper gate tube; A bit line is arranged on a side of the upper selection tube away from the substrate, and the bit line is connected to the upper selection tube of at least one of the storage strings.

6. The memory device according to claim 5, characterized in that The source lines are connected to the memory strings in a one-to-one correspondence; or, a plurality of adjacent memory strings are connected to the same source line.

7. The memory device according to claim 6, wherein: The storage strings are arranged in a plurality of columns along a second direction parallel to the substrate, and the plurality of columns of storage strings are arranged at intervals along a third direction, wherein the third direction is parallel to the substrate and intersects with the second direction; The bit lines extend on the memory strings along the second direction, and each of the bit lines is connected to each column of the memory strings.

8. A method for manufacturing a memory device, characterized in that: include: Providing a substrate, and forming a source line on one side of the substrate; forming a stacked structure on a side of the source line away from the substrate, the stacked structure comprising alternating insulating layers and sacrificial layers; forming a first hole, wherein the first hole penetrates the stacked structure along a first direction perpendicular to the substrate, and the first hole exposes a portion of the top surface of the source line; A channel structure is formed in the first hole, and a direction pointing to the center of the channel structure along the stacked structure is formed, wherein the channel structure comprises a gate insulating layer, a charge trapping layer, a tunneling layer, a channel layer and a core column which are sequentially arranged, and the core column comprises a first isolation layer, a conductive layer and a second isolation layer which are sequentially arranged in a direction away from the source line; removing the sacrificial layer, and filling a conductive material in the area where the sacrificial layer is removed to form a plurality of gate lines arranged at intervals along the first direction; A bit line is formed on a side of the channel structure away from the source line.

9. The method for manufacturing a memory device according to claim 8, characterized in that: forming a channel structure in the first hole, comprising: forming a gate insulating layer, a charge trapping layer, a tunneling layer and a channel layer sequentially covering the inner sidewall of the first hole, wherein at least a portion of the bottom surface of the channel layer is in contact with the source line; A first isolation layer, a conductive layer, and a second isolation layer are formed inside the channel layer. The first isolation layer, the conductive layer, and the second isolation layer are sequentially arranged in a direction away from the substrate.

10. The method for manufacturing a memory device according to claim 8, wherein: Each of the first holes is correspondingly formed on each of the source lines, and the source lines are connected to the channel structures in a one-to-one correspondence; Alternatively, a plurality of the first holes are formed on each of the source lines, and a plurality of adjacent channel structures are connected to the same source line.

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