Nonvolatile memory cell, manufacturing method and memory cell array

Abstract

The invention provides a nonvolatile memory cell. The nonvolatile memory cell includes a capacitor. The capacitor comprises an upper electrode, a lower electrode, a ferroelectric layer arranged between the upper electrode and the lower electrode, and an amorphous layer arranged between the upper electrode and the lower electrode, wherein the atomic arrangement form of the amorphous layer is different from the atomic arrangement form of the upper electrode and the lower electrode. A method of fabricating a nonvolatile memory cell and a memory cell array thereof are also disclosed herein.

Description

Technical Field

[0001] The invention relates to a non-volatile memory cell and a manufacturing method thereof, and a memory cell array. Background Art

[0002] Computer memory can be roughly divided into two categories: non-volatile memory and volatile memory. Volatile memory, such as dynamic random access memory (DRAM) and static random access memory (SRAM), often has faster read and write speeds and better optimization, but is also limited by the inability to retain information after the voltage is removed. In contrast, non-volatile memory, such as electrically erasable programmable read only memory (EEPROM) and flash RAM, can continue to retain information after the voltage is removed, but its read and write speeds are slower and its lifespan is shorter.

[0003] In recent years, with the development of thin film deposition technology, there has been an increasing amount of research on non-volatile semiconductor memory using ferroelectric thin films. Ferroelectric random access memory (FeRAM) uses ferroelectric capacitors as storage media. Ferroelectric capacitors can be polarized, either positively or negatively, to represent the data they store. Summary of the invention

[0004] One embodiment of the present invention provides a nonvolatile memory cell, comprising a capacitor, wherein the capacitor comprises an upper electrode, a lower electrode, a ferroelectric layer disposed between the upper electrode and the lower electrode, and an amorphous layer disposed between the upper electrode and the lower electrode, wherein the atomic arrangement of the amorphous layer is different from the atomic arrangement of the upper electrode and the lower electrode.

[0005] In some embodiments, the amorphous layer is formed by an atomic layer deposition process, and the thickness of the amorphous layer is between 0.5 nm and 5 nm.

[0006] In some embodiments, the memory window of the nonvolatile memory cell is greater than or equal to 0.2 volts.

[0007] In some embodiments, the amorphous layer is disposed between the ferroelectric layer and the lower electrode.

[0008] In some embodiments, the capacitor further includes another amorphous layer disposed between the ferroelectric layer and the top electrode.

[0009] In some embodiments, the amorphous layer is disposed between the ferroelectric layer and the top electrode.

[0010] In some embodiments, the nonvolatile memory cell further includes a transistor, an interlayer dielectric layer disposed on the transistor, and a conductive plug disposed in the interlayer dielectric layer to connect the capacitor to the transistor.

[0011] In some embodiments, the lower electrode protrudes from the interlayer dielectric layer, and the bottom of the lower electrode is surrounded by the dielectric layer.

[0012] In some embodiments, the amorphous layer, the ferroelectric layer, and the upper electrode are disposed on the sidewalls and the top surface of the lower electrode.

[0013] In some embodiments, the lower electrode includes a plurality of bumps, the amorphous layer, the ferroelectric layer and the upper electrode are disposed on the sidewalls and top surfaces of the bumps, and the spaces between the bumps are filled with the upper electrode.

[0014] In some embodiments, the material of the upper electrode and the lower electrode includes TiN, Ti, W, or Si.

[0015] In some embodiments, the material of the amorphous layer includes TiN, Ti, Si, or SiO 2 .

[0016] Another embodiment of the present invention provides a method for manufacturing a non-volatile memory cell, comprising: using a first deposition process to form a lower electrode; using a second deposition process to form an amorphous layer on the lower electrode, the second deposition process is different from the first deposition process, so that the atomic arrangement morphology of the amorphous layer is different from the atomic arrangement morphology of the lower electrode; forming a ferroelectric layer on the lower electrode; and forming an upper electrode on the ferroelectric layer and the amorphous layer.

[0017] In some embodiments, the memory window of the nonvolatile memory cell is greater than or equal to 0.2 volts.

[0018] In some embodiments, the second deposition process is an atomic layer deposition process, and the thickness of the amorphous layer is between 0.5 nm and 5 nm.

[0019] In some embodiments, the first deposition process is performed such that the atomic layer in the lower electrode is crystallized, and the second deposition process is performed such that the atomic layer in the amorphous layer is not substantially crystallized.

[0020] In some embodiments, the method further includes performing a planarization process on the bottom electrode before forming the amorphous layer and the ferroelectric layer.

[0021] Another embodiment of the present invention provides a memory cell array, comprising a plurality of bit lines arranged along a first direction, a plurality of word lines arranged along a second direction, a plurality of selection lines, and a plurality of memory cells. The memory cell comprises a transistor and a capacitor connected to the transistor. The capacitor is coupled between the bit line and the selection line, respectively, and comprises an upper electrode, a lower electrode, a ferroelectric layer arranged between the upper electrode and the lower electrode, and an amorphous layer arranged between the upper electrode and the lower electrode, wherein the atomic arrangement of the amorphous layer is different from the atomic arrangement of the upper electrode and the lower electrode.

[0022] In some embodiments, the selection lines are arranged along the first direction, and the selection lines and the bit lines are arranged alternately.

[0023] In some embodiments, the selection lines are arranged along the second direction, and the selection lines and the word lines are arranged alternately.

[0024] According to some embodiments of the present invention, a non-volatile memory cell having a capacitor is disclosed. The capacitor includes an upper electrode, a lower electrode, a ferroelectric layer disposed between the upper electrode and the lower electrode, and one or more amorphous layers disposed between the upper electrode and the lower electrode. The atomic arrangement of the amorphous layer is different from the atomic arrangement of the upper electrode and the lower electrode. By inserting the amorphous layer between the upper electrode and the lower electrode, the residual polarization of the capacitor can be increased, thereby increasing the memory window of the non-volatile memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to make the purpose, features, advantages and embodiments of the present invention more clearly understood, the detailed description of the accompanying drawings is as follows:

[0026] Figure 1 FIG. 4 is a transition diagram of the polarization (P) state of a capacitor according to some embodiments of the present invention.

[0027] Figures 2 to 4 Schematic cross-sectional views of nonvolatile memory cells according to different embodiments of the present invention.

[0028] Figures 5 to 9 Schematic cross-sectional views of methods for manufacturing a non-volatile memory cell at different stages according to some embodiments of the present invention.

[0029] Fig.10 The residual polarization (2P) of capacitors with different structures r ) in the table below.

[0030] Fig.11 and Fig.12 are cross-sectional views of nonvolatile memory cells according to different embodiments of the present invention.

[0031] Fig.13 and Fig.14Schematic diagrams of memory cell arrays according to different embodiments of the present invention.

[0032] [Description of Reference Numerals]

[0033] 100, 280, 340, 410: capacitors

[0034] 110: First electrode

[0035] 120: Second electrode

[0036] 130,283,370: Ferroelectric layer

[0037] 140,142,282,360: Amorphous layer

[0038] 200,300,300A: Non-volatile memory cells

[0039] 210,310:Substrate

[0040] 212,312: Semiconductor substrates

[0041] 220,320: Component layer

[0042] 222,322,420: Transistors

[0043] 224,324: Conductive embolism

[0044] 226,326: S / D area

[0045] 230,330,390: Interlayer dielectric layer

[0046] 240: Lower electrode material layer

[0047] 250: Amorphous material layer

[0048] 260: Ferroelectric material layer

[0049] 270: Upper electrode material layer

[0050] 281,350,350A: Lower electrode

[0051] 284,380: Upper electrode

[0052] 332: Dielectric layer

[0053] 352: Bump

[0054] 400: Memory unit DETAILED DESCRIPTION

[0055] The following will clearly illustrate the spirit of the present invention with drawings and detailed descriptions. After understanding the preferred embodiments of the present invention, those skilled in the art can make changes and modifications based on the techniques taught by the present invention without departing from the spirit and scope of the present invention.

[0056] Ferroelectric random access memory (FeRAM) is a non-volatile memory that achieves high-speed rewriting through rapid polarization reversal and remnant polarization of ferroelectric thin film layers. Figure 1 As shown, it is a conversion diagram of the polarization (P) state of a capacitor according to some embodiments of the present invention. The capacitor can be a ferroelectric capacitor, and the ferroelectric material in the capacitor exhibits a nonlinear relationship between the applied electric field (V) and the stored charge (Q). Specifically, the capacitor exhibits a characteristic hysteresis loop. Due to the effect of the semi-permanent electric dipole formed in the crystal structure of the ferroelectric material, the dielectric constant of the ferroelectric material is generally much higher than that of the linear dielectric material. When an external electric field is applied to the dielectric material, the dipoles tend to align with the direction of the electric field, which produces a shift in the atomic position and the corresponding charge distribution within the unit storage unit in the crystal structure of the ferroelectric material, which can represent the "up" and "down" states, respectively. After the charge is removed, the dipoles retain their polarization state. Typically, in each data storage unit, the binary "0" and "1" are stored as one of two possible electric polarizations. For example, referring to Figure 1 , usually using the negative remnant polarization "-P r ” to encode “1”, using the positive residual polarization “+P r " to encode "0".

[0057] The memory window is an important factor affecting the programming voltage of the FeRAM cell, where the memory window can be expressed as (2PrxA) / C BL , of which 2P r is the residual polarization, A is the area between the upper electrode and the lower electrode in the capacitor, and C BL is the capacitance of the bit line. In order to increase the memory window of the FeRAM cell, a large residual polarization (2P r ) and increased area are desired in the present invention.

[0058] Reference Figure 2, which is a cross-sectional schematic diagram of a nonvolatile memory cell according to some embodiments of the present invention. The nonvolatile memory cell, such as a FeRAM cell, includes a capacitor 100, such as a ferroelectric capacitor. The capacitor 100 includes a first electrode 110, a second electrode 120, a ferroelectric layer 130 disposed between the first electrode 110 and the second electrode 120, and an amorphous layer 140 disposed between the first electrode 110 and the second electrode 120. The atomic arrangement morphology of the amorphous layer 140 is different from the atomic arrangement morphology of the first electrode 110. The atomic arrangement morphology of the amorphous layer 140 is different from the atomic arrangement morphology of the second electrode 120.

[0059] By inserting the amorphous layer 140 between the first electrode 110 and the second electrode 120 , the remanent polarization of the capacitor 100 may be increased.

[0060] More specifically, the first electrode 110 and the second electrode 120 are formed using a first deposition process, and the amorphous layer 140 is formed using a second deposition process, and the second deposition process is different from the first deposition process. For example, in some embodiments, the first electrode 110 and the second electrode 120 are formed using a process such as physical vapor deposition. The thickness of the first electrode 110 and the second electrode 120 is thick enough so that the atomic layers in the first electrode 110 and the second electrode 120 present obvious crystallized characteristics. For example, the thickness of the first electrode 110 and the second electrode 120 is greater than 10nm.

[0061] In contrast, the amorphous layer 140 may be formed using an atomic layer deposition (ALD) process, such as a plasma enhanced atomic layer deposition (PEALD) process. Therefore, the thickness of the amorphous layer 140 is extremely thin, for example, between 0.5 nm and 5 nm, so that the atomic layer of the amorphous layer 140 will not be substantially crystallized. In some embodiments, if the thickness of the amorphous layer 140 is greater than 5 nm, the atomic layer of the amorphous layer 140 will be crystallized, and the effect of increasing the residual polarization of the capacitor 100 cannot be achieved.

[0062] In some embodiments, the material of the first electrode 110 and the second electrode 120 may be TiN, Ti, W, or Si. In some embodiments, the material of the ferroelectric layer 130 may be HZO, a ferroelectric material based on HfO2, a ferroelectric material based on ZrO2, etc. In some embodiments, the material of the amorphous layer 140 may be TiN, Ti, Si, or SiO2, etc. In some embodiments, the first electrode 110, the second electrode 120, and the amorphous layer 140 may have different materials, respectively, or, in some other embodiments, the first electrode 110, the second electrode 120, and the amorphous layer 140 may have the same material but different atomic arrangement forms.

[0063] In some embodiments, the first electrode 110 serves as a lower electrode of the capacitor 100 , the second electrode 120 serves as an upper electrode of the capacitor 100 , and the amorphous layer 140 is located between the first electrode 110 and the ferroelectric layer 130 .

[0064] In some other embodiments, such as Figure 3 As shown, the first electrode 110 serves as a lower electrode of the capacitor 100 , the second electrode 120 serves as an upper electrode of the capacitor 100 , and the amorphous layer 140 is located between the second electrode 120 and the ferroelectric layer 130 .

[0065] In some other embodiments, such as Figure 4 As shown, the capacitor 100 further includes another amorphous layer 142. The amorphous layer 142 can be substantially the same as the amorphous layer 140, or have a different composition. The amorphous layer 140 is disposed between the first electrode 110 and the ferroelectric layer 130, while the amorphous layer 142 is disposed between the second electrode 120 and the ferroelectric layer 130.

[0066] Reference Figures 5 to 9 ,in Figures 5 to 9 The following are cross-sectional schematic diagrams of methods for manufacturing non-volatile memory cells according to some embodiments of the present invention at different stages. Figure 5, a substrate 210 including a semiconductor substrate 212 and a device layer 220 formed on the semiconductor substrate 212 is provided. The device layer 220 includes a plurality of integrated circuit devices including active devices and / or passive devices, wherein the active devices are transistors 222, switches, etc., and the passive devices are resistors, capacitors, inductors, transformers, etc. An interlayer dielectric layer 230 is then formed on the device layer 220. A plurality of contact openings are formed in the interlayer dielectric layer 230 to expose the source / drain region (also referred to as S / D region) 226 of the transistor 222. The interlayer dielectric layer 230 may be subjected to one or more planarization processes, such as chemical mechanical polishing (CMP) process, to provide a planarized surface for subsequent processes. A plurality of conductive plugs 224 are formed in the contact openings to provide a path for electrical connection of each S / D region 226 of the transistor 222.

[0067] like Figure 6 As shown, a deposition process, such as a physical vapor deposition process, is performed to form a lower electrode material layer 240 on the interlayer dielectric layer 230. In some embodiments, the material of the lower electrode material layer 240 can be TiN, Ti, W, Si, etc., and the thickness of the lower electrode material layer 240 is greater than 10nm. The lower electrode material layer 240 is formed so that the atomic layer of the lower electrode material layer 240 has obvious crystallization.

[0068] like Figure 7 As shown, a planarization process is selectively performed on the lower electrode material layer 240, so that the roughness of the upper surface of the lower electrode material layer 240 is improved. For example, before the planarization process is performed, the surface roughness of the lower electrode material layer 240 is about 3nm, and after the planarization process is performed, the surface roughness of the lower electrode material layer 240 is about 0.5nm. The improved roughness of the upper surface of the lower electrode material layer 240 is beneficial to the subsequent deposition process.

[0069] like Figure 8 As shown, a series of deposition processes are performed to form an amorphous material layer 250, a ferroelectric material layer 260, and an upper electrode material layer 270 on the lower electrode material layer 240. In some embodiments, the amorphous material layer 250 is deposited on the lower electrode material layer 240, the ferroelectric material layer 260 is deposited on the amorphous material layer 250, and the upper electrode material layer 270 is deposited on the ferroelectric material layer 260.

[0070] In some other embodiments, the ferroelectric material layer 260 is deposited on the lower electrode material layer 240, the amorphous material layer 250 is deposited on the ferroelectric material layer 260, and the upper electrode material layer 270 is deposited on the amorphous material layer 250. In some other embodiments, performing a series of deposition processes further includes depositing another amorphous layer (not shown), so that the two amorphous layers are respectively located between the lower electrode material layer 240 and the ferroelectric material layer 260 and between the ferroelectric material layer 260 and the upper electrode material layer 270.

[0071] In some embodiments, the material of the amorphous material layer 250 may be TiN, Ti, Si, SiO2, etc. The amorphous material layer 250 may be formed using atomic layer deposition, such as a plasma enhanced atomic layer deposition process. In this way, the thickness of the amorphous material layer 250 may be controlled between 0.5 nm and 5 nm, and the atomic layer of the amorphous material layer 250 may not be substantially crystallized.

[0072] In some embodiments, the material of the ferroelectric material layer 260 can be HZO, HfO2-based ferroelectric material, ZrO2-based ferroelectric material, etc. The ferroelectric material layer 260 is formed by chemical vapor deposition, and the thickness of the ferroelectric material layer 260 is between 5nm and 50nm.

[0073] In some embodiments, the material of the upper electrode material layer 270 may be TiN, Ti, W, Si, etc. The upper electrode material layer 270 may be formed by a physical vapor deposition process, and the thickness of the upper electrode material layer 270 is greater than 10 nm.

[0074] Due to different deposition processes and thicknesses, the atomic arrangement of the amorphous material layer 250 is different from that of the lower electrode material layer 240 or the upper electrode material layer 270. More specifically, the atomic arrangement of the amorphous material layer 250 is substantially non-crystallized, while the atomic arrangement of the lower electrode material layer 240 or the upper electrode material layer 270 is substantially crystallized.

[0075] Finally, if Fig. 9As shown, a patterning process is performed to form a capacitor 280 on the interlayer dielectric layer 230, and the capacitor 280 is electrically connected to the transistor 222 of the device layer 220 through the conductive plug 224. The capacitor 280 includes a lower electrode 281 directly in contact with the conductive plug 224, an upper electrode 284, a ferroelectric layer 283 between the lower electrode 281 and the upper electrode 284, and one or more amorphous layers 282 between the lower electrode 281 and the upper electrode 284. Thus, a common memory cell is formed, which includes a capacitor and a transistor connected thereto, so this memory cell can also be called a "1T-1C" or "1TC" memory cell, which is applied to the non-volatile memory cell 200.

[0076] Reference Fig.10 , which is the residual polarization (2P r ). Structure 1 is a common capacitor, which includes a lower electrode, an upper electrode, and a ferroelectric layer between the upper and lower electrodes. In the capacitor of Structure 1, the materials of the upper and lower electrodes are TiN, and the material of the ferroelectric layer is HZO.

[0077] Structure 2 is an improved capacitor, which includes a lower electrode, an upper electrode, and a ferroelectric layer between the upper and lower electrodes, wherein the lower electrode is planarized by a CMP process. In the capacitor of Structure 2, the materials of the upper and lower electrodes are TiN, and the material of the ferroelectric layer is HZO.

[0078] Structure 3 is a capacitor according to some embodiments of the present invention, which includes a lower electrode, an upper electrode, a ferroelectric layer between the upper and lower electrodes, and at least one amorphous layer between the upper and lower electrodes, wherein the lower electrode is planarized by a CMP process. In the capacitor of Structure 3, the material of the upper and lower electrodes is TiN, and the material of the ferroelectric layer is HZO. The material of the amorphous layer in the capacitor of Structure 3 is TiN, which is formed by an atomic layer deposition process, and the thickness of the amorphous layer is about

[0079] According to the test results, the residual polarization is the average value of 10 dies. The residual polarization of the capacitor of structure 1 is about 20μC / cm 2 The residual polarization of the capacitor of structure 2 is about 26μC / cm 2 The residual polarization of the capacitor of structure 3 is about 31μC / cm 2 .

[0080] The present invention increases the residual polarization of the capacitor by setting one or more amorphous layers between the lower electrode and the upper electrode of the non-volatile memory unit capacitor, and the memory window of the non-volatile memory unit is greater than or equal to 0.2 volts, which helps to improve the programming voltage of the non-volatile memory unit.

[0081] Reference Fig.11 , which is a cross-sectional view of a nonvolatile memory cell according to some embodiments of the present invention. The nonvolatile memory cell 300 includes a substrate 310, the substrate 310 includes a semiconductor substrate 312 and at least one device layer 320 formed on the semiconductor substrate 312. The device layer 320 includes a transistor 322. An interlayer dielectric layer 330 is formed on the device layer 320, and a conductive plug 324 is formed in the interlayer dielectric layer 330 to provide a path for electrical connection of the S / D region 326 of the transistor 322.

[0082] The nonvolatile memory cell 300 further includes a capacitor 340 disposed on the interlayer dielectric layer 330, and the capacitor 340 is further electrically connected to the S / D region 326 of the transistor 322 through the conductive plug 324. In some embodiments, the capacitor 340 includes a lower electrode 350 connected to the conductive plug 324. The lower electrode 350 is a conductive block and protrudes from the interlayer dielectric layer 330. The capacitor 340 further includes one or more amorphous layers 360, a ferroelectric layer 370, and an upper electrode 380. An exemplary stacking method of the one or more amorphous layers 360 and the ferroelectric layer 370 between the lower electrode 350 and the upper electrode 380 can be referred to. Figures 2 to 4 .

[0083] In some embodiments, the amorphous layer 360 is disposed on the sidewalls and top surface of the lower electrode 350 and is in direct contact with the sidewalls and top surface of the lower electrode 350. The amorphous layer 360 further extends over the transistor 322. The dielectric layer 332 is interposed between the amorphous layer 360 and the interlayer dielectric layer 330, and the bottom of the lower electrode 350 is surrounded by the dielectric layer 332. The ferroelectric layer 370 is disposed on the amorphous layer 360, and the upper electrode 380 is disposed on the ferroelectric layer 370. More specifically, the amorphous layer 360, the ferroelectric layer 370, and the upper electrode 380 are conformally formed on the sidewalls and top surface of the lower electrode 350 to cover the sidewalls and top surface of the lower electrode 350. The nonvolatile memory cell 300 also includes another interlayer dielectric layer 390 formed on the capacitor 340 to seal the capacitor 340.

[0084] The area between the lower electrode 350 and the upper electrode 380 includes the area of ​​the top surface of the lower electrode 350 and the area of ​​the sidewall of the lower electrode 350. Fig.10 The illustrated embodiment, Fig.11The area between the lower electrode 350 and the upper electrode 380 of the capacitor 340 is significantly increased, thereby further increasing the memory window of the nonvolatile memory cell 300.

[0085] Reference Fig.12 , which is a cross-sectional view of a nonvolatile memory cell according to some embodiments of the present invention. Fig.12 The nonvolatile memory cell 300A is connected to Fig.11 One of the main differences between the nonvolatile memory cell 300 and the nonvolatile memory cell 300 is that the bottom electrode 350A of the nonvolatile memory cell 300A is further patterned to increase the surface area of ​​the bottom electrode 350A, thereby increasing the area between the bottom electrode 350A and the top electrode 380, thereby further increasing the memory window of the nonvolatile memory cell 300A.

[0086] For example, the lower electrode 350A is patterned into a comb-shaped structure having a plurality of bumps 352. The amorphous layer 360 and the ferroelectric layer 370 are disposed to cover the sidewalls and top surfaces of the bumps 352 of the lower electrode 350A, and the upper electrode 380 is formed on the amorphous layer 360 and the ferroelectric layer 370. In some embodiments, the upper electrode 380 is deposited to have a thicker thickness so that the space between the bumps 352 of the lower electrode 350A is filled with the upper electrode 380.

[0087] In some other embodiments, the upper electrode 380 may also be formed to cover the sidewalls and top surface of the lower electrode 350A, and the space between the bumps 352 of the lower electrode 350A may be filled with another dielectric layer so that the upper electrodes 380 on the sidewalls of different bumps 352 will not be bonded together.

[0088] Reference Fig.13 and Fig.14 , which are schematic diagrams of memory cell arrays according to different embodiments of the present invention. The memory cell is in the form of 1T1C, that is, the memory cell 400 includes a capacitor 410 and a transistor 420 coupled to the capacitor 410. The capacitor 410 includes one or more amorphous layers and a ferroelectric layer between an upper electrode and a lower electrode. The stacking of an exemplary capacitor 410 can be referred to Figures 2 to 4 , and the structural design between the capacitor 410 and the transistor 420 can refer to Fig. 9 , Fig.11 , Fig.12 .

[0089] The capacitor 410 is connected between the bit line BL and the select line SL. The voltage of the capacitor 410 is the voltage difference between the bit line BL and the select line SL when the word line WL is enabled. The bit lines BL such as the bit lines BL1, BL2, ... are arranged along a first direction, such as along the X-axis direction, and the word lines WL such as the word lines WL1, WL2, ... are arranged along a second direction, such as along the Y-axis direction, wherein the second direction is orthogonal to the first direction.

[0090] In some embodiments, Fig.13 As shown, the selection lines SL, such as the selection lines SL1, SL2, ... are also arranged along a first direction, such as along the X-axis direction, and the selection lines SL and the bit lines BL are arranged alternately. In other words, each selection line SL is located between adjacent pairs of bit lines BL.

[0091] In some other embodiments, such as Fig.14 As shown, the selection lines SL, such as the selection lines SL1, SL2, ... are arranged along the second direction, such as along the Y-axis direction, and the selection lines SL and the word lines WL are arranged alternately. In other words, each selection line SL is located between adjacent pairs of word lines WL.

[0092] According to some embodiments of the present invention, a non-volatile memory cell having a capacitor is invented. The capacitor includes an upper electrode, a lower electrode, a ferroelectric layer disposed between the upper electrode and the lower electrode, and one or more amorphous layers disposed between the upper electrode and the lower electrode. The atomic arrangement of the amorphous layer is different from the atomic arrangement of the upper electrode and the lower electrode. By inserting the amorphous layer between the upper electrode and the lower electrode, the residual polarization of the capacitor can be increased, thereby increasing the memory window of the non-volatile memory cell.

[0093] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A non-volatile memory cell, characterized in that: Include: A capacitor comprising: an upper electrode; One electrode; a ferroelectric layer disposed between the upper electrode and the lower electrode; and An amorphous layer is disposed between the upper electrode and the lower electrode, wherein an atomic arrangement of the amorphous layer is different from an atomic arrangement of the upper electrode and the lower electrode. 2 . The non-volatile memory cell according to claim 1 , wherein the amorphous layer is formed by an atomic layer deposition process, and the thickness of the amorphous layer is between 0.5 nm and 5 nm. 3 . The nonvolatile memory cell of claim 1 , wherein a memory window of the nonvolatile memory is greater than or equal to 0.2 volts.

4. The nonvolatile memory cell of claim 1, wherein the amorphous layer is disposed between the ferroelectric layer and the bottom electrode.

5. The non-volatile memory cell of claim 4, wherein the capacitor further comprises another amorphous layer disposed between the ferroelectric layer and the top electrode.

6. The nonvolatile memory cell of claim 1, wherein the amorphous layer is disposed between the ferroelectric layer and the top electrode.

7. The non-volatile memory cell according to claim 1, further comprising: A transistor; an interlayer dielectric layer disposed on the transistor; A conductive plug is disposed in the interlayer dielectric layer to connect the capacitor to the transistor. 8 . The nonvolatile memory cell according to claim 7 , wherein the lower electrode protrudes from the interlayer dielectric layer, and a bottom of the lower electrode is surrounded by a dielectric layer.

9. The nonvolatile memory cell of claim 8, wherein the amorphous layer, the ferroelectric layer and the upper electrode are disposed on sidewalls and a top surface of the lower electrode.

10. The nonvolatile memory cell according to claim 8, wherein the lower electrode comprises a plurality of bumps, the amorphous layer, the ferroelectric layer and the upper electrode are disposed on sidewalls and top surfaces of the bumps, and spaces between the bumps are filled by the upper electrode. 11 . The nonvolatile memory cell according to claim 1 , wherein materials of the upper electrode and the lower electrode include TiN, Ti, W, or Si.

12. The nonvolatile memory cell according to claim 1, wherein a material of the amorphous layer comprises TiN, Ti, Si or SiO2.

13. A method for manufacturing a non-volatile memory cell, characterized in that: Include: Using a first deposition process to form a lower electrode; Using a second deposition process to form an amorphous layer on the lower electrode, the second deposition process is different from the first deposition process, so that an atomic arrangement of the amorphous layer is different from an atomic arrangement of the lower electrode; forming a ferroelectric layer on the lower electrode; and A top electrode is formed on the ferroelectric layer and the amorphous layer.

14. The method of claim 13, wherein a memory window of the nonvolatile memory cell is greater than or equal to 0.2 volts. 15 . The method of claim 13 , wherein the second deposition process is an atomic layer deposition process, and the thickness of the amorphous layer is between 0.5 nm and 5 nm. 16 . The method according to claim 13 , wherein the first deposition process is performed such that the atomic layer in the lower electrode is crystallized, and the second deposition process is performed such that the atomic layer in the amorphous layer is not substantially crystallized. 17 . The method according to claim 13 , further comprising performing a planarization process on the bottom electrode before forming the amorphous layer and the ferroelectric layer.

18. A memory cell array, characterized in that: Include: A plurality of bit lines are arranged along a first direction; A plurality of word lines are arranged along a second direction; Multiple selection lines; as well as A plurality of memory cells, each of which comprises a transistor and a capacitor connected to the transistor, wherein the capacitors are respectively coupled between the bit lines and the selection lines, and each of which comprises an upper electrode, a lower electrode, a ferroelectric layer disposed between the upper electrode and the lower electrode, and an amorphous layer disposed between the upper electrode and the lower electrode, wherein the atomic arrangement of the amorphous layer is different from the atomic arrangement of the upper electrode and the lower electrode. 19 . The memory cell array according to claim 18 , wherein the select lines are disposed along the first direction, and the select lines and the bit lines are alternately arranged. 20 . The memory cell array as claimed in claim 18 , wherein the select lines are disposed along the second direction, and the select lines and the word lines are alternately arranged.

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