Memory device and forming method thereof

Abstract

A memory device includes a spin-orbit torque ("SOT") conductor, a magnetic tunnel junction ("MTJ") structure over the SOT conductor, a two-terminal read selector over the MTJ structure, a two-terminal write selector under the MTJ structure, and a bit line under the SOT conductor. The two-terminal read selector is conductively connected with a pinned layer in the MTJ structure. The two-terminal write selector is conductively connected to the first terminal of the SOT conductor. The bit line is conductively connected to the second terminal of the SOT conductor. The embodiment of the invention also discloses a method for forming the memory device.

Description

Technical Field

[0001] Embodiments of the present application relate to memory devices and methods of forming the same. Background Art

[0002] MRAM ("Magnetoresistive Random Access Memory") is a non-volatile memory technology that uses magnetic states to store information. In MRAM, information is stored by manipulating the magnetic orientation of ferromagnetic materials. The basic structure of an MRAM cell includes a magnetic tunnel junction, which includes two ferromagnetic layers separated by a tunnel barrier layer. The resistance of the magnetic tunnel junction depends on the relative alignment of the magnetization of the two ferromagnetic layers. In spin-orbit torque MRAM ("SOT-MRAM"), a conductive layer is deposited near the magnetic tunnel junction in the memory cell, and the flow of current through the conductive layer generates a spin-orbit torque, which is used to manipulate the magnetic state of the magnetic tunnel junction of the memory cell. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a memory device is provided, comprising: a spin-orbit torque ("SOT") conductor; a magnetic tunnel junction ("MTJ") structure, arranged above the SOT conductor, wherein the MTJ structure has a free layer, a pinned layer, and a tunnel barrier layer sandwiched between the free layer and the pinned layer, and wherein the free layer is conductively contacted with the SOT conductor; a two-terminal read selector, conductively connected to the pinned layer in the MTJ structure, wherein the two-terminal read selector is arranged above the MTJ structure; a two-terminal write selector, conductively connected to a first terminal of the SOT conductor, wherein the two-terminal write selector is arranged above the MTJ structure; and a bit line, conductively connected to a second terminal of the SOT conductor, wherein the bit line is arranged below the SOT conductor.

[0004] According to another aspect of an embodiment of the present application, a memory device is provided, comprising: a spin-orbit torque ("SOT") conductor; a magnetic tunnel junction ("MTJ") structure, arranged above the SOT conductor, wherein the MTJ structure has a free layer, a pinned layer, and a tunnel barrier layer sandwiched between the free layer and the pinned layer, and wherein the free layer is conductively contacted with the SOT conductor; a two-terminal read selector, conductively connected to the pinned layer in the MTJ structure, wherein the two-terminal read selector is arranged above the MTJ structure; a two-terminal write selector, conductively connected to a first terminal of the SOT conductor, wherein the two-terminal write selector is arranged below the MTJ structure; a write word line, conductively connected to the two-terminal write selector, wherein the write word line is arranged below the two-terminal write selector; and a bit line, conductively connected to a second terminal of the SOT conductor, wherein the bit line is arranged below the write word line.

[0005] According to another aspect of an embodiment of the present application, a method for forming a memory device is provided, comprising: forming a spin-orbit torque ("SOT") conductor extending in a first direction; forming a magnetic tunnel junction ("MTJ") structure above the SOT conductor, wherein forming the MTJ structure comprises depositing a free layer above the SOT conductor, depositing a tunnel barrier layer above the free layer, and depositing a pinned layer above the tunnel barrier layer; and forming a dual-terminal read selector above the MTJ structure, wherein the dual-terminal read selector is conductively connected to the pinned layer in the MTJ structure; and forming a dual-terminal write selector, the dual-terminal write selector being conductively connected to a first terminal of the SOT conductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A is a three-dimensional view of a SOT-MRAM device having a two-terminal write selector and a two-terminal read selector according to some embodiments.

[0008] Figure 1B According to some embodiments Figure 1A Schematic diagram of a SOT-MRAM device.

[0009] Figure 1C is a layout diagram of an integrated circuit according to some embodiments, the integrated circuit having each implemented as Figure 1A Matrix of SOT-MRAM devices of the device.

[0010] Figure 2A is a three-dimensional view of a SOT-MRAM device having a two-terminal write selector and a two-terminal read selector according to some embodiments.

[0011] Figure 2B According to some embodiments Figure 2A Schematic diagram of a SOT-MRAM device.

[0012] Figure 2C is a layout diagram of an integrated circuit according to some embodiments, the integrated circuit having each implemented as Figure 2A Matrix of SOT-MRAM devices of the device.

[0013] Figure 3 and Figure 4A-4B is a circuit diagram of integrated circuits each having a matrix of SOT-MRAM devices according to some embodiments.

[0014] Figure 5 is a circuit diagram of an integrated circuit having a matrix of SOT-MRAM devices configured to perform matrix operations on vectors, according to some embodiments.

[0015] Figure 6A-6H According to some embodiments, Figure 2A Cross-sectional view of various device structures formed during the SOT-MRAM device process.

[0016] Fig. 7A is a flow chart of a method of manufacturing a memory device according to some embodiments.

[0017] Figure 7B is a flow chart of a method of manufacturing a memory device according to some embodiments. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0019] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0020] In some embodiments, a SOT-MRAM device of a memory device includes a spin-orbit torque ("SOT") conductor, a magnetic tunnel junction ("MTJ") structure disposed above the SOT conductor, a dual-terminal read selector and a dual-terminal write selector disposed above the MTJ structure. The read word line above the SOT conductor is conductively connected to the MTJ structure through the dual-terminal read selector. The write word line located above or below the SOT conductor is conductively connected to the first terminal of the SOT conductor through the dual-terminal write selector. The bit line below the SOT conductor is conductively connected to the second terminal of the SOT conductor.

[0021] In some embodiments, the dual-terminal write selector is located above the MTJ structure. In some embodiments, each of the dual-terminal read selector and the dual-terminal write selector has a switching layer made of the same switching material layer above the MTJ structure. In an embodiment where the dual-terminal read selector and the dual-terminal write selector are both above the MTJ structure, the SOT-MRAM device reduces the number of stacked conductive layers measured from the bit line below the SOT conductor to the read word line above the SOT conductor compared to some other alternative implementations. Reducing the number of stacked conductive layers in a single SOT-MRAM device can improve the efficiency of stacking more SOT-MRAM devices on a substrate. Therefore, given the same thickness limit of the total stack height of the SOT-MRAM device, more SOT-MRAM device layers are deposited above the substrate.

[0022] In some embodiments, the dual-terminal write selector is located below the MTJ structure but above the bit line, which enables the SOT conductor and the bit line to be vertically stacked on top of each other above the substrate. Vertically stacking the SOT conductor and the bit line can reduce the memory cell area occupied by the SOT-MRAM device, thereby increasing the memory density of the single-layer SOT-MRAM device.

[0023] Figure 1A is a three-dimensional view of a SOT-MRAM device 100 having a dual-terminal write selector and a dual-terminal read selector according to some embodiments. The SOT-MRAM device 100 is a memory device that uses magnetic states to store information. Figure 1A , the SOT-MRAM device 100 includes a magnetic tunnel junction structure ("MTJ structure") 150, a spin-orbit torque conductor ("SOT conductor") 160, a dual-terminal write selector 110, and a dual-terminal read selector 120. The dual-terminal write selector 110 and the dual-terminal read selector 120 are labeled as selector S1 and selector S2, respectively. The MTJ structure 150 is arranged above the SOT conductor 160.

[0024] exist Figure 1A In the embodiment, the MTJ structure 150 has a free layer 152, a pinned layer 158, and a tunnel barrier layer 155. The tunnel barrier layer 155 is sandwiched between the free layer 152 and the pinned layer 158. Each of the free layer 152 and the pinned layer 158 is a conductive layer made of a ferromagnetic material, but the tunnel barrier layer 155 is a thin insulating layer made of a high resistance material. The thickness of the tunnel barrier layer 155 is thin enough to enable electrons to perform quantum mechanical tunneling via the thin insulating layer between the two ferromagnetic layers. The probability of tunneling is affected by the relative alignment of the magnetic moments of the two ferromagnetic layers.

[0025] While the magnetic moment of the pinned layer 158 is generally fixed in orientation, the magnetic moment of the free layer 152 is manipulated by an external magnetic field, application of an electric current, or other means. When the magnetic moment of the free layer 152 is parallel to the magnetic moment of the pinned layer 158, the tunneling probability is higher, resulting in a lower resistance. Conversely, when the magnetic moment of the free layer 152 is antiparallel to the magnetic moment of the pinned layer 158, the tunneling probability is reduced, resulting in a higher resistance. Two different resistance values ​​based on the relative orientation of the magnetic moments of the two ferromagnetic layers are used to represent binary information zero ("0") and binary information one ("1") in the MRAM cell.

[0026] exist Figure 1A In the MTJ structure 150, the magnetic moment of the free layer 152 is manipulated by a current flowing through a SOT conductor 160 deposited near the free layer 152. The free layer 152 is also in conductive contact with the SOT conductor 160. When a current flows through the SOT conductor 160, the spin-orbit torque effect induces an electron spin flow within the SOT conductor 160. The spin-orbit torque generated by the spin current applies a torque to the magnetic moment of the free layer 152 in the MTJ structure 150. Under conditions where the spin-orbit torque becomes strong enough, the magnetic moment in the free layer 152 can be redirected or flipped in the magnetization direction by the spin-orbit torque. A sufficiently large current flowing through the SOT conductor 160 determines the orientation of the magnetic moment in the free layer 152. Because the resistance of the magnetic tunnel junction depends on the orientation of the magnetic moment in the free layer 152, the write current applied to the SOT conductor 160 provides a mechanism to set the resistance of the magnetic tunnel junction, thereby writing binary information into the MRAM cell.

[0027] exist Figure 1A In the embodiment, a write current is applied to one terminal of the SOT conductor 160 through the two-terminal write selector 110. The resistance value of the magnetic tunnel junction is detected based on the current value reaching the SOT conductor 160 through the two-terminal read selector 120 and the MTJ structure 150 in series.

[0028] The dual-terminal write selector 110 is arranged below the MTJ structure 150 and the SOT conductor 160, while the dual-terminal read selector 120 is arranged above the MTJ 150. Each of the dual-terminal write selector 110 and the dual-terminal read selector 120 includes a switching layer sandwiched between two conductor layers. In the dual-terminal write selector 110, the switching layer 115 is sandwiched between two conductor layers 111 and 112. The conductor layer 111 is conductively connected to the first terminal of the spin-orbit torque conductor 160 (which is the terminal adjacent to the first edge 161 of the spin-orbit torque conductor 160) via the vertical conductor C1. In the dual-terminal read selector 120, the switching layer 125 is sandwiched between the two conductor layers 121 and 122. The conductor layer 121 is conductively connected to the pinning layer 158 in the MTJ structure 150.

[0029] Each of the two-terminal write selector 110 and the two-terminal read selector 120 is a two-terminal device (e.g., a nonlinear diode) having a highly nonlinear current-voltage characteristic, such as a nonlinear diode. As long as the voltage applied to the two-terminal device is much smaller than the threshold voltage, the leakage current through the two-terminal device can be ignored. On the other hand, once the voltage applied to the two-terminal device becomes greater than the threshold voltage, the current through the two-terminal device increases rapidly as the applied voltage increases. When a first voltage less than the threshold voltage is applied to the two-terminal device, the two-terminal device is actually set to a non-conducting state, and when a second voltage greater than the threshold voltage is applied to the two-terminal device, the two-terminal device is actually set to a conducting state. When the device is in the non-conducting state, the first voltage is selected to increase the off-resistance Roff of the two-terminal device, and when the device is in the conducting state, the second voltage is selected to reduce the on-resistance Ron of the two-terminal device. Generally, it is better to have a two-terminal device with a large off-to-on ratio Roff / Ron (i.e., the ratio between the off-resistance Roff and the on-resistance Ron). The nonlinearity of a two-terminal device generally depends on a switching layer sandwiched between two conductor layers in the two-terminal device.

[0030] In some embodiments, the switching layer 115 in the dual-terminal write selector 110 includes a chalcogenide material, a solid electrolyte material, a phase change material, or an oxide insulating material. In some embodiments, the switching layer 125 in the dual-terminal read selector 120 also includes a chalcogenide material, a solid electrolyte material, a phase change material, or an oxide insulating material. In some embodiments, each of the dual-terminal write selector 110 and the dual-terminal read selector 120 is a bidirectional diode. In some embodiments, while the dual-terminal write selector 110 is a bidirectional diode, the dual-terminal read selector 120 is a unidirectional diode.

[0031] Figure 1A The SOT-MRAM device 100 further includes a bit line 190 extending in the X direction, a write word line 130 extending in the Y direction, and a read word line 140 extending in the Y direction. Here, the Y direction is perpendicular to the X direction. The read word line 140 is fabricated in a conductive layer above the dual-terminal read selector 120. The write word line 130 is fabricated in a conductive layer below the dual-terminal write selector 110. The bit line 190 is fabricated in a conductive layer below the write word line 130.

[0032] The bit line 190 is conductively connected to the second terminal of the SOT conductor 160 (which is the terminal adjacent to the second edge 162 of the SOT conductor 150) through the vertical conductor C2. In some embodiments, the vertical conductor C2 includes a conductor segment 172 that is located in the same conductive layer as the write word line 130. The vertical conductor C2 also includes one or more through-hole connectors for connecting the conductor segment 172 to the SOT conductor 160 and connecting the conductor segment 172 to the bit line 190. The write word line 130 is conductively connected to the conductor layer 112 of the dual-terminal write selector 110 (also referred to as selector S1). The read word line 140 is conductively connected to the conductor layer 122 of the dual-terminal read selector 120 (also referred to as selector S2). In Figure 1A In FIG. 1 , the dual-terminal write selector 110 is electrically coupled between the write word line 130 and the first terminal of the SOT conductor 160 , and the dual-terminal read selector 120 is electrically coupled between the read word line 140 and the MTJ structure 150 .

[0033] Figure 1B According to some embodiments Figure 1A Schematic diagram of a SOT-MRAM device. Figure 1B describe Figure 1A Write operations and read operations on the SOT-MRAM device.

[0034] During a write operation, the read word line 140 is set to a read cutoff voltage V read-off , which sets the two-terminal read selector 120 to a non-conductive state, so the leakage current through the two-terminal read controller 120 and the MTJ structure 150 is almost negligible. In some alternative implementations, the read word line 140 is set to a floating voltage, which keeps the two-terminal read selector 120 in a non-conductive state.

[0035] During a write operation, the bit voltage V B is applied to bit line 190. In some embodiments, bit voltage V B is set to a negative voltage -|V - | or set to a positive voltage |V + |. Bit voltage V B is set to a negative voltage -|V - |, used to write a first binary value (such as a value "1") into the SOT MRAM device 100. The bit voltage V B is set to a positive voltage |V + |, for writing a second binary value (such as a value “0”) into the SOT-MRAM device 100. In some alternative embodiments, the bit voltage V B is set to one of three voltage values: negative voltage -|V - |、Positive voltage|V +| and zero voltage |V 0 |(usually zero voltage, |V 0 |=0).

[0036] The write operation of multiple SOT-MRAM devices connected to the same write word line is usually performed in a write time period, which is divided into a positive current write time period and a negative current write time period. The write operation of the SOT-MRAM device is performed in the positive current write time period to receive a first binary value (such as a value of "1"). The write operation of the SOT-MRAM device is performed in the negative current write time period to receive a second binary value (such as a value of "0").

[0037] During the positive current write period, a positive selection voltage |V + on |. The voltage difference between the write word line 130 and the bit line 190 is |V + on |-V B , which depends on the bit voltage V applied to the bit line 190 B .

[0038] If the bit voltage V at the bit line 190 B is a negative voltage -|V - |, then the voltage difference between the write word line 130 and the bit line 190 becomes |V + on |+|V - |Forward bias voltage |V + on |+|V - | is large enough to set the two-terminal write selector 110 to an on state, which causes a positive current to flow from the write word line 130 to the SOT conductor 160 to the bit line 190. The positive current in the SOT conductor 160 sets the magnetic moment in the free layer 152 to a first orientation, thereby writing a first binary value (e.g., a value of “1”) to the SOT-MRAM device 100.

[0039] If the bit voltage V at the bit line 190 B is a positive voltage |V + |, then the voltage difference between the write word line 130 and the bit line 190 becomes |V + on |-|V + |Forward bias voltage |V + on |-|V +| is insufficient to set the two-terminal write selector 110 to the on state. Therefore, no current flows from the write word line 130 through the SOT conductor 160 to the bit line 190, and the magnetic moment in the free layer 152 of the SOT-MRAM device 100 remains unchanged.

[0040] If the bit voltage V at the bit line 190 B is zero voltage |V 0 |(For example, |V 0 |=0), the voltage difference between the write word line 130 and the bit line 190 becomes |V + on |-|V 0 |Forward bias voltage |V + on |-|V 0 | is insufficient to drive the two-terminal write selector 110 to the on state. Therefore, no current flows from the write word line 130 through the SOT conductor 160 to the bit line 190, and the magnetic moment in the free layer 152 of the SOT-MRAM device 100 remains unchanged. 0 In the example embodiment |=0, if the voltage |V + on | is less than the threshold voltage of the two-terminal write selector 110, then the voltage difference |V + on |-|V 0 |(between the write word line 130 and the bit line 190 ) is still less than the threshold of the two-terminal write selector 110 .

[0041] During the negative current write period, a negative select voltage -|V is applied to the write word line 130. - on |. The voltage difference between the write word line 130 and the bit line 190 is -|V - on |-V B , which depends on the bit voltage V applied to the bit line 190 B .

[0042] If the bit voltage V at the bit line 190 B is a negative voltage -|V - |, the voltage difference between the write word line 130 and the bit line 190 becomes -|V - on |+|V - |, where |V - on |>|V - |. Reverse bias voltage |V - on |-|V -| is insufficient to set the two-terminal write selector 110 to the on state. Therefore, no current flows from the write word line 130 through the SOT conductor 160 to the bit line 190, and the magnetic moment in the free layer 152 of the SOT-MRAM device 100 remains unchanged.

[0043] If the bit voltage V at the bit line 190 B is a positive voltage |V + |, the voltage difference between the write word line 130 and the bit line 190 becomes -|V - on |-|V + |. Reverse bias voltage |V - on |+|V + | is large enough to set the two-terminal write selector 110 to a conductive state under reverse bias, which causes a negative current to flow from the write word line 130 to the SOT conductor 160 to the bit line 190 (i.e., a positive current flows from the bit line 190 to the write word line 190). The negative current in the SOT conductor 160 sets the magnetic moment in the free layer 152 to a second direction, thereby writing a second binary value (e.g., a value of "0") to the SOT-MRAM device 100.

[0044] If the bit voltage V at the bit line 190 B is zero voltage |V 0 |(For example, |V 0 |=0), the voltage difference between the write word line 130 and the bit line 190 becomes -|V - on |-|V 0 |. Reverse bias voltage |V - on |-|V 0 | is insufficient to drive the two-terminal write selector 110 to the on state. Therefore, no current flows from the write word line 130 through the SOT conductor 160 to the bit line 190, and the magnetic moment in the free layer 152 of the SOT-MRAM device 100 remains unchanged. 0 In the example embodiment |=0, if the voltage |V - on | is less than the threshold voltage of the two-terminal write selector 110, then the reverse bias voltage applied to the two-terminal write selector 100 | V - on |+|V 0 |Still less than the threshold of the dual-terminal write selector 110.

[0045] In addition, since the bit line 190 is generally connected to a plurality of SOT-MRAM devices in the SOT-MRAM device matrix, when the SOT-MRAM device 100 connected to the bit line 190 is selected for a write operation, other SOT-MRAM devices connected to the same bit line (i.e., 190) are generally not selected for a write operation.

[0046] During a write operation, when the bit voltage V B When applied to the bit line 190, in order to deselect another SOT-MRAM device also connected to the same bit line (i.e., 190), a word unselect voltage V is applied to the corresponding write word line connected to the unselected SOT-MRAM device. off . Voltage difference |V off -V B | is set to a value that keeps the two-terminal write selector 110 in each unselected SOT-MRAM device in a non-conductive state.

[0047] During a read operation, the write word line 130 is set to a write cutoff voltage V wrtie-off , which sets the two-terminal write selector 110 to a non-conducting state, so the leakage current through the two-terminal write controller 110 and the SOT conductor 160 is almost negligible. In some alternative implementations, the write word line 130 is set to a floating voltage, which keeps the two-terminal write selector 110 in a non-conducting state.

[0048] During a read operation, in order to select the SOT-MRAM device 100 for reading, a word read voltage V is applied to the read word line 140. R on , to drive the two-terminal read selector 120 into the on state. Word read voltage V R on is chosen to have a voltage difference |V R on -V RB | Significantly greater than the threshold voltage of the two-terminal read selector 120, where the voltage V RB is the voltage at the bit line 190. In some embodiments, the bit line 190 is connected to the sense amplifier SA, and the voltage V RB is the voltage across the bit capacitor coupled between the bit line 190 and the common ground. RB The rate of change over time is proportional to the current through the MTJ structure 150. In some alternative embodiments, the bit line 190 is connected to one of the differential inputs of the current-to-voltage converter, and the voltage V at the bit line 190 is RB The current-to-voltage converter maintains the virtual common voltage V G .

[0049] When the SOT-MRAM device 100 is selected for reading, the current flowing from the read word line 140 to the bit line 190 is the current passing through the two-terminal read selector 120 and the MTJ structure 150. The current flowing from the read word line 140 to the bit line 190 is inversely proportional to the resistance of the magnetic tunnel junction. Once the current flowing from the read word line 140 to the bit line 190 is detected, the binary information stored in the MRAM cell is read out.

[0050] Because the bit line 190 is usually connected to multiple SOT-MRAM devices in the SOT-MRAM device matrix, when the SOT-MRAM device 100 connected to the bit line 190 is selected for a read operation, other SOT-MRAM devices connected to the same bit line (i.e., 190) are usually not selected for a read operation. During a read operation, in order to deselect another SOT-MRAM device also connected to the same bit line (i.e., 190), the word deselect voltage V R off Applied to the corresponding read word lines connected to the unselected SOT-MRAM devices. Voltage difference |V R off –V RB | is set to a value that keeps the two-terminal read selector 120 in each unselected SOT-MRAM device in a non-conductive state, where the voltage V RB is the voltage at bit line 190. In some embodiments, bit line 190 is connected to a current-to-voltage converter that maintains the voltage on bit line 190 at a virtual common voltage V G , voltage difference |V R off –V G | is set to a value that maintains the two-terminal read selector 120 in each unselected SOT-MRAM device in a non-conductive state.

[0051] Figure 1C is a layout diagram of an integrated circuit having a matrix of SOT-MRAM devices according to some embodiments, each device being implemented as Figure 1A Devices. Figure 1C In an example layout of FIG. 1 , the integrated circuit includes four SOT-MRAM cells arranged in a matrix of two rows and two columns. Each SOT-MRAM cell in the two-by-two matrix has a SOT-MRAM device that uses Figure 1A The same device structure as the device in is implemented.

[0052] exist Figure 1CIn the embodiment, the integrated circuit includes bit lines 190 and 190B extending in the X direction, write word lines 130 and 130B extending in the Y direction, and read word lines 140 and 140B extending in the Y direction. Each of the four SOT-MRAM cells in the two-by-two matrix has a corresponding MTJ structure deposited at the intersection area between one of the bit lines and one of the read word lines. Specifically, the MTJ structure 150 in the SOT-MRAM cell of the first row and the first column is deposited at the intersection area between the bit line 190 and the read word line 140. The MTJ structure 150AB in the SOT-MRAM cell of the first row and the second column is deposited at the intersection area between the bit line 190 and the read word line 140B. The MTJ structure 150BA in the SOT-MRAM cell of the second row and the first column is deposited at the intersection area between the bit line 190B and the read word line 140. The MTJ structure 150BB in the SOT-MRAM cell of the second row and the second column is deposited at the intersection area between the bit line 190B and the read word line 140B.

[0053] exist Figure 1C In the embodiment, read word lines 140 and 140B are located in the conductive layer above the MTJ structure. The MTJ structure in each SOT-MRAM cell is electrically connected to one of the read word lines through a corresponding dual-terminal read selector above the MTJ structure. For example, MTJ structures 150 and 150BA are electrically connected to read word line 140 through dual-terminal read selector S2 above MTJ structure 150 and dual-terminal read selector S2 above MTJ structure 150BA, respectively. MTJ structures 150AB and 150BB are electrically connected to read word line 140B through dual-terminal read selector S2 above MTJ structure 150AB and dual-terminal read selector S2 above MTJ structure 150BB, respectively.

[0054] exist Figure 1C In the SOT-MRAM cell, each of the four SOT-MRAM cells has a corresponding SOT conductor deposited under the MTJ structure in the SOT-MRAM cell. For example, in the SOT-MRAM cell in the first row and the first column of the matrix, the SOT conductor 160 is arranged under the MTJ structure 150. In the SOT-MRAM cell in the first row and the second column, the SOT conductor 160AB is arranged under the MTJ structure 150AB. In the SOT-MRAM cell in the second row and the first column, the SOT conductor 160BA is arranged under the MTJ structure 150BA. In the SOT-MRAM cell in the second row and the second column, the SOT conductor 160BB is arranged under the MTJ structure 150BB.

[0055] exist Figure 1CIn the embodiment, write word lines 130 and 130B are located in the conductive layer below the SOT conductor. The first terminal of the SOT conductor in each SOT-MRAM cell is electrically connected to one of the write word lines through the corresponding dual-terminal write selector under the SOT conductor. For example, the first terminals of SOT conductors 160 and 160BA are electrically connected to write word line 130 respectively through the dual-terminal write selector S1 under SOT conductor 160 and the dual-terminal write selector S1 under SOT conductor 160BA. The first terminals of SOT conductors 160AB and 160BB are electrically connected to write word line 130B through the dual-terminal write selector S1 under SOT conductor 160AB and the dual-terminal write selector S1 under SOT conductor 160BB.

[0056] exist Figure 1C In the SOT-MRAM cell, bit lines 190 and 190B are located in a conductive layer below write word lines 130 and 130B, and write word lines 130 and 130B are located below the SOT conductor. The second terminal of the SOT conductor in each SOT-MRAM cell is electrically connected to one of the bit lines through a corresponding vertical conductor under the SOT conductor. For example, the second terminals of SOT conductors 160 and 160AB are electrically connected to bit line 190 through a vertical conductor C2 under SOT conductor 160 and a vertical conductor C2 under SOT conductor 160AB, respectively. The second terminals of SOT conductors 160BA and 160BB are electrically connected to bit line 190B through a vertical conductor C2 under SOT conductor 160BA and a vertical conductor C2 under SOT conductor 160BB, respectively.

[0057] exist Figure 1C In the embodiment, each SOT conductor 160 and 160AB above the bit line 190 is vertically stacked with the bit line 190, and each SOT conductor 160BA and 160BB above the bit line 190B is vertically stacked with the bit line 190B. Each of the bit lines 190 and 190B has a line width equal to one F unit, and the bit lines 190 and 190B are separated by a pitch equal to one F unit. Therefore, Figure 1C The SOT-MRAM device in FIG. 1 has a cell height (along the Y direction) of two F cells (“2F”). Here, the F unit is a unit used to measure the sizes of various components in the layout diagram. Figure 1C , the length of the SOT conductor in each SOT-MRAM device is 3F. For example, the length measured from the first edge 161 of the SOT conductor 160 to the second edge 162 of the SOT conductor 160 is equal to three F units ("3F"). The SOT conductors in two adjacent SOT-MRAM cells are separated by a gap of one F unit along the X direction. Therefore, Figure 1C The SOT-MRAM device in has a cell length (along the X direction) of four F cells (“4F”). Figure 1CThe unit area of ​​each SOT-MRAM device is 8F 2 .

[0058] exist Figure 1C In the SOT-MRAM device, since the SOT conductor is vertically stacked with the bit line, as long as the width of the SOT conductor (along the Y direction) is less than or equal to the width of the bit line (along the Y direction), the SOT conductor will not cause an additional increase in the cell height. Figure 1C The cell height of the SOT-MRAM device is kept at two F units. Figure 1C The cell area of ​​the SOT-MRAM device in is smaller than that of some SOT-MRAM devices implemented with some other cell designs in which the cell height of the SOT-MRAM device is greater than two F units and the SOT conductor is not vertically stacked with the bit line.

[0059] Apart from Figure 1A-Figure 1C In addition to the embodiments of the SOT-MRAM device, Figure 2A-2C Alternative embodiments of SOT-MRAM devices are also shown.

[0060] Figure 2A is a three-dimensional view of a SOT-MRAM device 200 having a two-terminal write selector and a two-terminal read selector according to some embodiments. Figure 1A The SOT-MRAM device 100 and Figure 2A The main difference between the SOT-MRAM devices 200 is the vertical position of the two-terminal write selector 110 and the write word line 130 relative to the SOT conductor 160. Other differences are the vertical positions of the bit line 190 and the vertical conductor C2 associated with the bit line 190.

[0061] exist Figure 1A In the SOT-MRAM device 100 of FIG. 1 , the dual-terminal write selector 110 and the write word line 130 are arranged below the SOT conductor 160 , and the dual-terminal read selector 120 is arranged above the SOT conductor 160 . Figure 2A In the SOT-MRAM device 200 , the dual-terminal write selector 110 and the write word line 130 are arranged above the SOT conductor 160 , and the dual-terminal read selector 120 is also arranged above the SOT conductor 160 .

[0062] exist Figure 2A, a write word line 130 extending in the Y direction is fabricated in the same conductive layer as a read word line 140. The write word line 130 and the read word line 140 extending in the same direction are located in parallel in the same conductive layer, and are separated from each other by a gap, which is usually filled with an insulating material. A dual-terminal write selector 110 is arranged below the write word line 130 but above the SOT conductor 160. The dual-terminal write selector 110 includes a switching layer 115 sandwiched between two conductor layers 111 and 112. The conductor layer 111 below the switching layer 115 is conductively connected to a first terminal of the SOT conductor 160 (the terminal is adjacent to a first edge 161 of the SOT conductor 160). The conductor layer 112 above the switching layer 115 is conductively connected to the write word line 130.

[0063] In some embodiments, the switching layer 115 in the dual-terminal write selector 110 and the switching layer 125 in the dual-terminal read selector 120 are made of the same layer of switching material (formed from one of a chalcogenide material, a solid electrolyte material, a phase change material, or an oxide insulating material). In some embodiments, the conductor layer 111 in the dual-terminal write selector 110 and the conductor layer 121 in the dual-terminal read selector 120 are made of the same conductive material layer. In some embodiments, the conductor layer 112 in the dual-terminal write selector 110 and the conductor layer 122 in the dual-terminal read selector 120 are made of the same conductive material layer.

[0064] Figure 2A The bit line 190 in the embodiment is fabricated in a conductive layer which is closer to the SOT conductor 160 than Figure 1A The conductive layer including the bit line 190 is short because Figure 2A Median 190 is now manufactured in Figure 1A When the connecting conductor segment 172 is connected to the conductive layer of the connecting conductor segment 172, Figure 1A When the vertical conductor C2 is removed, Figure 2A The vertical conductor C2 in is shortened accordingly.

[0065] Figure 2B According to some embodiments Figure 2A Schematic diagram of a SOT-MRAM device. Figure 2A SOT-MRAM devices in 200 and Figure 1A There are differences between the SOT-MRAM devices 100 in Figure 2B The equivalent circuit in Figure 2A The SOT-MRAM device 200) is functionally similar to Figure 1B The equivalent circuit in Figure 1A The SOT-MRAM device 100 is the same as in the embodiment of the present invention. Figure 2A The write operation of the SOT-MRAM device 200 is Figure 1A The write operation on the SOT-MRAM device 100 is the same. Figure 2A The read operation of the SOT-MRAM device 200 is Figure 1A The read operation on the SOT-MRAM device 100 is the same.

[0066] Figure 2C is a layout diagram of an integrated circuit having a matrix of SOT-MRAM devices according to some embodiments, each device being implemented as Figure 2A Device. Figure 2C The layout and Figure 1C The differences between the layouts in include different layout positions of the write word line relative to the read word line, different layout positions of the two-terminal write selector relative to the MTJ structure, different lengths of the SOT conductors, and different cell lengths of the SOT-MRAM cells.

[0067] exist Figure 2C In FIG. 1 , the write word line 130 and the read word line 140 are separated by a gap of one F unit along the X direction. The write word line 130B and the read word line 140B are similarly separated by a gap of one F unit along the X direction. Figure 2C In, with Figure 1C Compared to the layout of , the two-terminal write selector S1 at the intersection area between the write word line and the bit line is moved along the X direction, further away from the MTJ structure in the same SOT-MRAM cell. Figure 2C In, with Figure 1C Compared to the layout in FIG. 1 , the length of the SOT conductor is enlarged to four F units (“4F”), and the cell length of the SOT-MRAM device is enlarged to five F units. Figure 2C The cell area of ​​each SOT-MRAM device in 2 .

[0068] Figure 3 and Figure 4A-4B is a circuit diagram of integrated circuits each having a matrix of SOT-MRAM devices according to some embodiments. Figure 3 and Figure 4A-4B In the embodiment, the SOT-MRAM devices are arranged in a four-by-four matrix: the first row of the matrix includes SOT-MRAM devices 300AA-300AD, the second row of the matrix includes SOT-MRAM devices 300BA-300BD, the third row of the matrix will include SOT-MRAM devices 300CA-300CD, and the last row of the matrix includes SOT-MRAM devices 300DA-300DD. In some embodiments, each SOT-MRAM device in the SOT-MRAM device matrix is ​​implemented as Figure 1AIn some embodiments, each SOT-MRAM device in the SOT-MRAM device matrix is ​​implemented as Figure 2A A SOT-MRAM device 200 .

[0069] The SOT conductor in each SOT-MRAM device in the first row is connected to the write word line 130A through the dual-terminal write selector S1, and the MTJ structure in each SOT-MRAM device in the first row is connected to the read word line 140A through the dual-terminal read selector S2. The SOT conductor in each SOT-MRAM device in the second row is connected to the write word line 130B through the dual-terminal write selector S1, and the MTJ structure of each SOT-MRAM device in the second row is connected to the read word line 140B through the dual-terminal read selector S2. The SOT conductor in each SOT-MRAM device in the third row is connected to the write word line 130C through the dual-terminal write selector S1, and the MTJ structure of each SOT-MRAM device in the third row is connected to the read word line 140C through the dual-terminal read selector S2. The SOT conductor in each SOT-MRAM device in the fourth row is connected to the write word line 130D through a two-terminal write selector S1, and the MTJ structure of each SOT-MRAM device in the fourth row is connected to the read word line 140D through a two-terminal read selector S2. Each of the write word lines 130A-130D is connected to the write selection circuit 330. Each of the read word lines 140A-140D is connected to the read selection circuit 340.

[0070] The second terminal of the SOT conductor in each SOT-MRAM device 300AA-300DA in the first column is connected to the bit line 190A. The second terminal of the SOT conductor in each SOT-MRAM device 300AB-300DB in the second column is connected to the bit line 190B. The second terminal of the SOT conductor in each SOT-MRAM device 300AC-300DC in the third column is connected to the bit line 190C. The second terminal of the SOT conductor in each SOT-MRAM device 300AD-300DD in the fourth column is connected to the bit line 190D. Each of the bit lines 190A-190D is connected to the memory input-output circuit 390.

[0071] Reference Figure 3 The read operation of the SOT-MRAM device matrix is ​​described. During the read operation, the write selection circuit 330 applies a write cutoff voltage V to each write word line 130A-130D. wrtie-off . Read line by line Figure 3In other words, in each read time period, a row of SOT-MRAM devices is selected for read operation. In the first read time period, the second read time period, the third read time period, and the fourth read time period, the SOT-MRAM devices 300AA-300AD in the first row, the SOT-MRAM devices 300BA-300BD in the second row, the SOT-MRAM devices 300CA-300CD in the third row, and the SOT-MRAM devices 300DA-300DD in the fourth row are read accordingly.

[0072] In each read time period, when a row of SOT-MRAM devices is selected for a read operation, the remaining rows of SOT-MRAM devices are not selected for a read operation. Figure 3 As shown, during the third read time period, the SOT-MRAM devices 300CA-300CD in the third row are selected for the read operation, while the SOT-MRAM devices 300AA-300AD, the SOT-MRAM devices 300BA-300BD, and the SOT-MRAM devices 300DA-300DD are not selected for the read operation. During the third read time period, the word read voltage V R on is applied to the read word line 140C, which drives the two-terminal read selector S2 in each of the SOT-MRAM devices 300CA-300CD to a conductive state. In addition, during the third read time period, the word unselect voltage V R off is applied to each of the read word lines 140A-140B and 140D, which drives the two-terminal read selector S2 in each of the SOT-MRAM devices 300AA-300AD, 300BA-300BD, and 300DA-300DD to a non-conductive state.

[0073] During the third read time period, when the two-terminal read selector S2 in each of the SOT-MRAM devices 300CA-300CD is maintained in the on state, the current through the MTJ structure in each of the SOT-MRAM devices 300CA-300CD flows into one of the bit lines 190A-190D accordingly and charges each bit capacitor connected to the bit line 190A-190D accordingly. The voltage V at the bit line 190A-190D RB [0], V RB [1] V RB [2], and V RB [3] The binary information stored in each SOT-MRAM device 300CA-300CD is read out by detecting with sense amplifiers 398A-398D accordingly.

[0074] Reference Figure 4A-4B The write operation to the SOT-MRAM device matrix is ​​described. During the write operation, the read selection circuit 340 applies a read cutoff voltage V to each read word line 140A-140D. read-off . Figure 4A-4B The matrix of SOT-MRAM devices in is written row by row. That is, in each writing time period, a row of SOT-MRAM devices is selected for writing operation. The SOT-MRAM devices 300AA-300AD in the first row, the SOT-MRAM devices 300BA-300BD in the second row, the SOT-MRAM devices 300CA-300CD in the third row, and the SOT-MRAM devices 300DA-300DD in the fourth row are written in the first writing time period, the second writing time period, the third writing time period, and the fourth writing time period, respectively.

[0075] In each write time period, when a row of SOT-MRAM devices is selected for a write operation, the remaining rows of SOT-MRAM devices are not selected for a write operation. Figure 4A-4B As shown, during the second write time period, the SOT-MRAM devices 300BA-300BD in the second row are selected for the write operation, while the SOT-MRAM devices 300AA-300AD, the SOT-MRAM devices 300CA-300CD, and the SOT-MRAM devices 300DA-300DD are not selected for the write operation. In addition, each of the first write time period, the second write time period, the third write time period, and the fourth write time period is further divided into a positive current write time period and a negative current write time period.

[0076] As an example, see Figure 4A-4B The writing operation during the second writing period is described. Figure 4A The writing operation during the positive current writing period of the second writing period is described. Figure 4B The writing operation during the negative current writing period of the second writing period is described.

[0077] like Figure 4A As shown, during the positive current writing period of the second writing period, the positive selection voltage |V + on | is applied to the write word line 130B, and the word is not selected voltage V off is applied to each write word line 130A and 130C-130D. The word unselect voltage V offThe two-terminal write selector S1 in each of the SOT-MRAM devices 300AA-300AD, 300CA-300CD, and 300DA-300DD is driven to a non-conductive state. Whether the two-terminal write selector S1 in a particular SOT-MRAM device in the second row (i.e., one of the SOT-MRAM devices 300BA-300BD) is driven to a conductive state depends on the bit voltage V on the bit line connected to the particular SOT-MRAM device. B [i] Here, the bit voltage V B [i] Used to identify V B [0], V B [1] V B [2] or V B [3]. If the bit voltage V B [i] is a negative voltage - |V - |, then when the two-terminal write selector S1 in the specific SOT-MRAM device is driven to the on state, the first binary value (such as the value "1") is written into the specific SOT-MRAM device. On the other hand, if the bit voltage V B [i] is a positive voltage |V + | or zero voltage |V 0 |, the bit value stored in the specific SOT-MRAM device does not change because the two-terminal write selector S1 in the specific SOT-MRAM device remains in a non-conducting state.

[0078] like Figure 4B As shown, during the negative current writing period of the second writing period, the negative selection voltage -|V - on | is applied to the write word line 130B, and the word is not selected voltage V off is applied to each write word line 130A and 130C-130D. The word unselect voltage V off The two-terminal write selector S1 in each of the SOT-MRAM devices 300AA-300AD, 300CA-300CD, and 300DA-300DD is driven to a non-conductive state. Whether the two-terminal write selector S1 in a particular SOT-MRAM device in the second row (i.e., one of the SOT-MRAM devices 300BA-300BD) is driven to a conductive state depends on the bit voltage V on the bit line connected to the particular SOT-MRAM device. B [i] Here, the bit voltage V B [i] Used to identify V B [0], V B [1] V B [2] or V B [3]. If the bit voltage VB [i] is a negative voltage |V - | or zero voltage |V 0 |, the bit value stored in the specific SOT-MRAM device does not change because the two-terminal write selector S1 in the specific SOT-MRAM device remains in a non-conductive state. On the other hand, if the bit voltage V on the bit line B [i] is a positive voltage |V + |, then when the two-terminal write selector S1 in the specific SOT-MRAM device is driven to the on state, the second binary value (such as the value "0") is written into the specific SOT-MRAM device.

[0079] In one example, assume that before the write operation is performed on the second row, the bit pattern of the word stored in the second row (i.e., in the SOT-MRAM devices 300BA-300BD) is in the form of "xxxx", where each bit "x" represents a value "1" or a value "0" that has been stored in the SOT-MRAM device. In the example implementation, the bit voltage V on the bit lines 190A-190D is B [0], V B [1] V B [2] and V B [3] is set accordingly to the value |V + |、-|V - |、-|V - | and |V + |. After the write operation is performed on the second row (i.e., after the positive current write period and the negative current write period), a bit pattern of the form "0110" is stored in the second row (i.e., stored in the SOT-MRAM devices 300BA-300BD). In some example designs of various voltage values, |V - |=|V + |=(1 / 2)|V + on |=(1 / 2)|V - on |.

[0080] In another example embodiment, during the positive current write period, the bit voltage V on the bit lines 190A-190D is B [0], V B [1] V B [2] and V B [3] is set accordingly to the value |V 0 |、-|V - |、-|V - | and |V 0 |, but during the negative current write period, the bit voltage V on the bit line B [0], VB [1] V B [2], and V B [3] is set accordingly to the value |V + |、|V 0 |、|V 0 | and |V + |. Then, after a write operation is performed on the second row, a bit pattern of the form "0110" is stored in the second row (ie, in the SOT-MRAM devices 300BA-300BD). In some example designs of various voltage values, |V - |=|V + |=|V + on |=|V - on |, and |V 0 |=0.

[0081] In some embodiments, Figure 4A The write operation shown for writing a first binary value (eg, a value of "1") is shown in FIG. Figure 4B The write operation of writing the second binary value (such as the value "0") is performed before. During the positive current write time period, the bit pattern of the word stored in the second row (i.e., the SOT-MRAM device 300BA-300BD) changes from the form of "xxxx" to the form of "x11x". During the negative current write time period, the bit pattern of the word stored in the second row (i.e., the SOT-MRAM device 300BA-300BD) changes from the form of "x11x" to the form of "0110".

[0082] In some embodiments, Figure 4B The write operation shown for writing a second binary value (eg, a value of "0") is shown in FIG. Figure 4A The write operation of writing the first binary value (e.g., value "1") is performed before. During the negative current write period, the bit pattern of the word stored in the second row (i.e., in the SOT-MRAM devices 300BA-300BD) changes from the form of "xxxx" to the form of "0xx0". During the positive current write period, the bit pattern of the word stored in the second row (i.e., in the SOT-MRAM devices 300BA-300BD) changes from the form of "0xx0" to the form of "0110".

[0083] In some embodiments, the two-terminal write selector S1 in each SOT-MRAM device has a symmetrical current-voltage curve with respect to the forward bias voltage and the reverse bias voltage, and each of the forward bias threshold voltage and the reverse bias threshold voltage is composed of the same threshold voltage |V th | Characterization. Positive selection voltage applied to the write word line |V +on | and negative selection voltage |V - on Each of | is chosen to be α|V th |. Absolute voltage value|V - | and |V + Each of | is chosen to be β|V th |.

[0084] In the first example embodiment, each bit voltage V on the bit line B [i] is set to one of two voltage values: negative voltage -β|V th |Used to write a first binary value (such as a value “1”) into a corresponding SOT-MRAM device, a positive voltage β|V th |Used to write a second binary value (such as a value "0") into a corresponding SOT-MRAM device. During the positive current writing period and the negative current writing period, a negative voltage -β|V is applied to each bit line th | to write a binary value of "1" and apply a positive voltage β|V to each bit line th | to write a binary value of “0”. In some example designs, β=α / 2, 2 / 3<α<2.

[0085] In the second example embodiment, each bit voltage V on the bit line B [i] is set to one of three voltage values: a negative voltage -β|V for writing the first binary value (e.g., value “1”) to the corresponding SOT-MRAM device th |, a positive voltage β|V used to write a second binary value (e.g., a value of “0”) into the corresponding SOT-MRAM device th |, and a zero voltage for maintaining the binary value of the corresponding SOT-MRAM device |V 0 |. During the positive current writing period, a negative voltage -β|V is applied to each bit line th |To write a binary value of "1", apply zero voltage to the remaining bit lines |V 0 |=0. During the negative current writing period, a positive voltage β|V is applied to each bit line. th | to write a binary value of "0" and apply zero voltage to the remaining bit lines |V 0 |=0. In some example designs, β=α, 1 / 2<α<1.

[0086] Figure 5 is a circuit diagram of an integrated circuit having a matrix of SOT-MRAM devices configured to perform matrix operations on vectors according to some embodiments. Figure 5 In the embodiment of the present invention, each write word line 130A- 130D is connected to a write selection circuit 330 . Figure 5The write selection circuit 330 and Figure 3 as well as Figure 4A-4B The write selection circuit 330 in performs the same function. Figure 5 Each read word line 140A-140D is connected to a vector input circuit 540 (which is from Figure 3 and Figure 4A-4B The read selection circuit 340 in FIG. 1 is modified from FIG. 1 ). Figure 5 In the example, each of the bit lines 190A-190D is connected to a memory input-output circuit 590 (which is connected to the memory input-output circuit 590). Figure 3 and Figure 4A-4B Memory input circuit 390 in FIG. 3 is modified from the memory input circuit 390 in FIG. 3 ).

[0087] In the matrix operation of vectors, the input vector is the voltage V generated by the vector input circuit 540. A 、V B 、V C and V D The voltage V A 、V B 、V C and V D In response to the voltage applied to the read word line, currents I are induced in the bit lines 190A, 190B, 190C, and 190D, respectively. A ,I B ,I C and I D Current I A ,I B ,I C and I D The current-to-voltage converters 598A, 598B, 598C, and 598D are used to measure accordingly. In one example embodiment, each current-to-voltage converter has a feedback resistor R F , and the output voltages at the current-to-voltage converters 598A, 598B, 598C, and 598D have voltage values ​​R accordingly. F I A , R F I B , R F I C and R F I D .

[0088] The current I in the bit line 190A A is the current I AA ,I BA ,I CA and I DAThe sum of these currents is the current of the self-read word lines 140A, 140B, 140C and 140D following the bit line 190A accordingly. The current I in the bit line 190B B is the current I AB ,I BB ,I CB and I DB The current I in bit line 190C is the sum of the currents from read word lines 140A, 140B, 140C, and 140D that follow bit line 190B accordingly. C is the current I AC ,I BC ,I CC and I DC The sum of these currents is the current of the self-read word lines 140A, 140B, 140C and 140D following the bit line 190C accordingly. The current I in the bit line 190D D is the current I AD ,I BD ,I CD and I DD The sum of these currents is the current from read word lines 140A, 140B, 140C and 140D following bit line 190D accordingly.

[0089] Current I AA ,I BA ,I CA and I DA Each of the SOT-MRAM devices 300AA, 300BA, 300CA, and 300DA has a corresponding conductance G AA , G BA , G CA and G DA Current I AB ,I BB ,I CB and I DB Each of the SOT-MRAM devices 300AB, 300BB, 300CB, and 300DB has a corresponding conductance G AB , G BB , G CB and G DB Related. Current I AC ,I BC ,I CC and I DC Each of the SOT-MRAM devices 300AC, 300BC, 300CC and 300DC has a corresponding conductance G AC , G BC , G CC and G DC Related. Current I AD ,IBD ,I CD and I DD Each of the SOT-MRAM devices 300AD, 300BD, 300CD, and 300DD has a corresponding conductance G AD , G BD , G CD and G DD Related.

[0090] exist Figure 5 In FIG. 1 , each bit line 190A-190D is connected to a virtual ground due to current-to-voltage converters 598A, 598B, 598C, and 598D. Therefore, the current I AA ,I BA ,I CA and I DA Correspondingly equal to G AA V A , G BA V B , G CA V C and G DA V D Current I AB ,I BB ,I CB and I DB Correspondingly equal to G AB V A , G BB V B , G CB V C and G DB V D Current I AC ,I BC ,I CC and I DC Correspondingly equal to G AC V A , G BC V B , G CC V C and G DC V D Current I AD ,I BD ,I CD and I DD Correspondingly equal to G AD V A , G BD V B , G CD V C and G DD V D Therefore, the current I A ,IB ,I C and I D The corresponding equation is given by:

[0091] I A =G AA V A +G BAV B+G CA V C +G DA V D ,

[0092] I B =G AB V A +G BB V B +G CB V C +G DB V D ,

[0093] I C =G AC V A +G BC V B +G CC V C +G DC V D ,and

[0094] I D =G AD V A +G BD V B +G CD V C +G DD V D .

[0095] Written in linear algebra, the output vector (consisting of the current I A ,I B ,I C and I D ) through the conductivity matrix From the input vector (consisting of voltage V A 、V B 、V C and V D ) as shown in the following equation:

[0096]

[0097] Conductivity Matrix Each element in is a SOT-MRAM device (e.g., Figure 1Aand Figure 2A 100 or 200 in the SOT-MRAM), as measured between the conductor layer 122 of the two-terminal read selector 120 and the second terminal of the SOT conductor 160. In some embodiments, as the on-resistance Ron of the two-terminal read selector 120 in the SOT-MRAM decreases, the conductance of the SOT-MRAM device is dominated by the conductance of the MTJ structure 150. Figure 4A-4B The conductance of the MTJ structure 150 in each SOT-MRAM device is individually reprogrammable, so the ... A 、V B 、V C and V D array) into an output vector (such as the current I A ,I B ,I C and I D The conductivity matrix of is reprogrammable. Figure 5 In the present invention, an integrated circuit having a matrix of SOT-MRAM devices can be operated as a compute-in-memory ("CIM") device to perform reprogrammable matrix operations on vectors.

[0098] because Figure 5 Matrix configuration of SOT-MRAM devices, conductivity matrix is a 4 by 4 matrix arranged in 4 rows and 4 columns. Figure 5 The matrix of SOT-MRAM devices in FIG. 1 is provided as an example, and matrices of other sizes are also within the contemplated scope of the present disclosure. For example, a CIM device having a matrix of SOT-MRAM devices arranged in 3 rows and 4 columns can be used to convert a 3D input vector (such as a voltage V A 、V B and V C ) is converted into a four-dimensional output vector (such as the current I A ,I B ,I C and I D ). A CIM device having a matrix of SOT-MRAM devices arranged in 4 rows and 3 columns is operable to convert a 4-dimensional input vector (such as a voltage V A 、V B 、V C and V D ) is converted into a three-dimensional output vector (such as the current I A ,I B and I C ). Generally speaking, a CIM device having a matrix of SOT-MRAM devices arranged in m rows and n columns can be used to convert an m-dimensional input vector into an n-dimensional output vector.

[0099] In some embodiments, the voltage of each element in the input vector (eg, voltage V A 、V B 、V C or V D ) is a variable of analog value. In some embodiments, the voltage of each element in the input vector (e.g., voltage V A 、V B 、V C or V D ) is a digital value variable represented by a plurality of bits. In some embodiments, the voltage of each element in the input vector (e.g., the voltage V A 、V B 、V C or V D ) is a single bit variable that takes one of two binary values. In one example, the voltage of each element in the input vector takes one of two binary values, namely, V R，OFF =0 or V R，ON >V TH , where V TH is the selector threshold voltage.

[0100] exist Figure 5 In the conductivity matrix Each element in is determined based on the conductance of the SOT-MRAM device having one MTJ structure (i.e., 150), because a single SOT-MRAM device having one MTJ structure is a storage element connected between a bit line and a write word line and a read word line. In some alternative embodiments, the storage element connected between a bit line and each of the write word line and the read word line includes a configuration of multiple SOT-MRAM devices, each device having one MTJ structure, and the conductance matrix The elements in are determined based on the combination of the conductances of the plurality of SOT-MRAM devices. For an alternative embodiment, even if a single SOT-MRAM device having one MTJ structure is implemented as a conductance having a single bit of binary value, the conductance matrix The elements in are also multi-bit variables.

[0101] Figure 6A-6H According to some embodiments, Figure 2A 6. A cross-sectional view of various device structures formed during the process of manufacturing a SOT-MRAM device. After the device structure 610 is manufactured using a front-end-of-line (FEOL) process, in which individual components such as transistors, capacitors, and resistors are formed on a substrate, during steps during a back-end-of-line (BEOL) process, such as Fig. 6AAs shown, the bit lines 190 extending in the X direction are fabricated over the insulating material layer 672 over the device structure 610. Various other material or component layers between the device structure 610 and the insulating material layer 672 are not explicitly shown.

[0102] In the next step, if Figure 6B As shown, a SOT conductor 160 extending in the X direction is fabricated on an insulating material layer 674 above the bit line 190. In addition, a vertical conductor C2 connecting the SOT conductor 160 and the bit line 190 forms a through-hole connector passing through the insulating material layer 674. In some embodiments, the SOT conductor 160 is made of one or more heavy metals or materials doped with heavy metals. Examples of materials used in the SOT conductor 160 include Pt, W, Ta, AuPt, W3Ta, BixSey, BiSeTe, or a combination thereof.

[0103] In the next step, if Figure 6C As shown, a stack of multiple layers of various materials covering the SOT conductor 160 and the insulating material layer 676 above the insulating material layer 674 is manufactured. The multilayer stack includes two layers of ferromagnetic materials 652 and 658, a thin insulating layer 655, and a layer of synthetic antiferromagnetic ("SAF") material 659. The ferromagnetic material layer 652 is deposited on the SOT conductor 160 and the insulating material layer 676. The thin insulating layer 655 is deposited on the ferromagnetic material layer 652. The ferromagnetic material layer 658 is deposited on the thin insulating layer 655. The synthetic antiferromagnetic material layer 659 is deposited on the layer 658 of the ferromagnetic material. In some embodiments, the synthetic antiferromagnetic material layer 659 includes a stack of ferromagnetic layers separated by one or more non-magnetic layers. In some embodiments, the synthetic antiferromagnetic material layer 659 includes a stack of alternating non-magnetic layers and ferromagnetic layers, wherein each non-magnetic layer is sandwiched between two ferromagnetic layers.

[0104] In the next step, if Fig.6D As shown, the film is covered with a mask having a pattern formed by photolithography. Figure 6C After the multilayer stack in , the multilayers of various materials (labeled as 652, 655, 658 and 659) are etched using dry etching techniques to manufacture the MTJ structure 150 above the SOT conductor 160. The synthetic antiferromagnetic material layer 659, the ferromagnetic material layer 658, the thin insulating layer 655 and the ferromagnetic material layer 652 are etched in sequence. Fig.6DThe MTJ structure 150 fabricated in FIG. 1 includes a SAF layer 159 in contact with a pinned layer 158. The exchange coupling between the SAF layer 159 and the pinned layer 158 causes the magnetic moment of the pinned layer 158 to be aligned in a preferred direction. The SAF layer 159 of the MTJ structure 150 is formed by etching a synthetic antiferromagnetic material layer 659. The pinned layer 158 of the MTJ structure 150 is formed by etching a ferromagnetic material layer 658. The tunnel barrier layer 155 of the MTJ structure 150 is formed by etching a thin insulating layer 655. The free layer 152 of the MTJ structure 150 is formed by etching a ferromagnetic material layer 652.

[0105] In the next step, if Fig. 6E As shown, conductive segment 648 and conductive segment 638 are fabricated over SAF layer 159 over interlayer dielectric 678 (“ILD”). Conductive segment 648 is in conductive contact with SAF layer 159. Since SAF layer 159 is also conductive, conductive segment 648 becomes a terminal of MTJ structure 150. Conductive segment 638 is conductively connected to a first terminal of SOT conductor 160 through vertical conductor C1, which is formed by one or more through-hole connectors passing through interlayer dielectric 678.

[0106] In the next step, if Fig. 6F As shown, a stack of multiple layers of various materials is fabricated covering the conductive segments 638 and 648 and covering the ILD 682 above the interlayer dielectric 678. The multilayer stack includes a conductive material layer 611, a switching material layer 615, and a conductive material layer 612. The conductive material layer 611 is deposited over the conductive segments 638 and 648 and the ILD 682. The switching material 615 is deposited over the conductive material layer 611. The conductive material layer 612 is deposited over the switching material layer 615. Examples of the switching material include a chalcogenide material, a solid electrolyte material, a phase change material, or an oxide insulating material.

[0107] In some embodiments, the switching material 615 is made of HfOx (where 0 < x ≤ 2), which is doped with one or more materials such as Cu, Al, N, P, S, Si, Zr, Gd, Ti, La, or Te. In some embodiments, the switching material 615 is made of GeSe doped with one or more elements selected from N, P, S, Si, and Te. In some embodiments, the switching material 615 is made of AsGeSe doped with one or more elements selected from N, P, S, Si, and Te. In some embodiments, the switching material 615 is made of AsGeSeSi doped with one or more elements selected from N, P, S, Si, and Te. In some embodiments, the switching material 615 includes GeCTe, NGeCTe, SiNGeCTe, or a combination thereof. In some embodiments, the switching material 615 is made of a chalcogenide or a solid electrolyte material containing one or more of Ge, Sb, S, and Te. In some embodiments, the switching material 615 is made of a material including SiO x 、TiO x 、AlO x 、WO x 、Ti x N y O z 、TaO x 、Nb x or a combination thereof, where x, y, and z are non-stoichiometric values. In some embodiments, the switching material 615 is made of an oxygen-deficient transition metal oxide or a two-way threshold switching (OTS) material.

[0108] In the next step, as Figure 6G shown, after covering the multi-layer stack in Fig. 6F with a mask having a pattern formed by a lithography technique, the multi-layers of various materials (labeled 611, 615, and 612) are etched using a dry etching technique, thereby manufacturing the two-terminal write selector 110 above the conductive section 638 and the two-terminal read selector 120 above the conductive section 648. The conductive material layer 612, the switching material layer 615, and the conductive material layer 611 are etched in sequence. Each of the conductive sections 638 and 648 serves as an etch stopper during the etching process. The conductor layer 112 of the two-terminal write selector 110 and the conductor layer 122 of the two-terminal read selector 120 are formed by etching the conductive material layer 612. The switching layer 115 of the two-terminal write selector 110 and the switching layer 125 of the two-terminal read selector 120 are formed by etching the switching material layer 615. The conductor layer 111 of the two-terminal write selector 110 and the conductor layer 121 of the two-terminal read selector 120 are formed by etching the conductive material layer 611.

[0109] In the next step, as Figure 6HAs shown, a write word line 130 is fabricated over the conductor layer 112 of the dual-terminal write selector 110, and a read word line 140 is fabricated over the conductor layer 122 of the dual-terminal read selector 120. The write word line 130 and the read word line 140 are fabricated in the same conductive layer over the ILD 684, which covers the conductive segments 638 and 648 and the ILD 682. Each of the write word line 130 and the read word line 140 extends in the Y direction.

[0110] Fig. 7A is a flow chart of a method 700A of manufacturing a memory device according to some embodiments. Fig. 7A The order in which the operations of method 700A are described is for illustration only; the operations of method 700A can be performed in the same order as described in Fig. 7A It should be understood that the Fig. 7A Additional operations may be performed before, during, and / or after the method 700A shown in FIG. 7 , and some other processes may only be briefly described herein.

[0111] In operation 710 of method 700A, a bit line extending in the X direction is formed above the device structure fabricated in the FEOL process. Fig. 6A In the example shown, the bit lines 190 extending in the X-direction are fabricated overlying an insulating material layer 672 over the device structure 610 fabricated in a FEOL process.

[0112] In operation 740A of method 700A, a SOT conductor extending in the X direction is formed over the bit line. Figure 6B In the example shown, a SOT conductor 160 extending in the X-direction is fabricated over a layer of insulating material 674 over the bit line 190 .

[0113] In operation 750 of method 700A, an MTJ structure is formed on the SOT conductor. Figure 6C-D In the example shown, the MTJ structure 150 is fabricated over the SOT conductor 160 .

[0114] In operation 760A of method 700A, a two-terminal read selector and a two-terminal write selector are formed over the MTJ structure. Figure 6F-6G In the example shown, the two-terminal write selector 110 is fabricated over the conductive segment 638 and the two-terminal read selector 120 is fabricated over the conductive segment 648. The conductive segments 638 and 648 are located in a conductive layer over the MTJ structure 150.

[0115] In operation 770 of method 700A, a read word line extending in the Y direction is formed above the two-terminal read selector. Figure 6HIn the example shown, a read word line 140 extending in the Y direction is fabricated over the conductor layer 122 of the two-terminal read selector 120 .

[0116] In operation 780A of method 700A, a write word line extending in the Y direction is formed above the dual-terminal write selector. Figure 6H In the example shown, a write word line 130 extending in the Y direction is fabricated over the conductor layer 112 of the two-terminal write selector 110 .

[0117] In addition, in Figure 6H In the example shown, the write word line 130 fabricated in operation 780A and the read word line 140 fabricated in operation 770 are fabricated in the same conductive layer above the ILD 684 .

[0118] Figure 7B is a flow chart of a method 700B of manufacturing a memory device according to some embodiments. Figure 7B The order in which the operations of method 700B are described is for illustration only; the operations of method 700B can be performed in the same order as described in Figure 7B It should be understood that the Figure 7B Additional operations may be performed before, during, and / or after the method 700B shown in FIG. 7 , and some other processes may only be briefly described herein.

[0119] In operation 710 of method 700B, a bit line extending in the X direction is formed above the device structure manufactured in the FEOL process. Figure 1A When the SOT-MRAM device 100 is manufactured using the method 700B, a bit line 190 extending along the X direction is manufactured above a device structure (not explicitly shown) formed in a FEOL process.

[0120] In operation 720B of method 700B, a write word line extending in the Y direction is formed above the bit line. Figure 1A When the SOT-MRAM device 100 is manufactured using the method 700B, the write word line 130 is formed in a conductive layer above the bit line 190 .

[0121] In operation 730B of method 700B, a two-terminal write selector is formed above the write word line. Figure 1A When the SOT-MRAM device 100 is manufactured using the method 700B, the dual-terminal write selector 110 is formed above the write word line 130 .

[0122] In operation 740B of method 700B, a SOT conductor extending in the X direction is formed above the dual-terminal write selector. Figure 1AWhen the SOT-MRAM device 100 is manufactured using the method 700B, the SOT conductor 160 extending in the X direction is manufactured above the dual-terminal write selector 110 .

[0123] In operation 750 of method 700B, an MTJ structure is formed over the SOT conductor. Figure 1A When the SOT-MRAM device 100 is manufactured using the method 700B, the MTJ structure 150 is manufactured above the SOT conductor 160 .

[0124] In operation 760B of method 700B, a two-terminal read selector is formed above the MTJ structure. Figure 1A When the SOT-MRAM device 100 is manufactured using the method 700B, the two-terminal read selector 120 is manufactured above the MTJ structure 150 .

[0125] In operation 770 of method 700B, a read word line extending in the Y direction is formed above the two-terminal read selector. Figure 1A When the SOT-MRAM device 100 is manufactured using the method 700B, a read word line 140 extending in the Y direction is manufactured above the conductor layer 122 of the two-terminal read selector 120 .

[0126] One aspect of the present disclosure relates to a memory device. The memory device includes a spin-orbit torque ("SOT") conductor and a magnetic tunnel junction ("MTJ") structure arranged above the SOT conductor. The MTJ structure has a free layer, a pinned layer, and a tunnel barrier layer sandwiched between the free layer and the pinned layer, and wherein the free layer is in conductive contact with the SOT conductor. The memory device also includes a dual-terminal read selector and a dual-terminal write selector. The dual-terminal read selector is conductively connected to the pinned layer in the MTJ structure, and the dual-terminal read selector is arranged above the MTJ structure. The dual-terminal write selector is conductively connected to a first terminal of the SOT conductor, and the dual-terminal write selector is arranged above the MTJ structure. The memory device also includes a bit line conductively connected to a second terminal of the SOT conductor. The bit line is arranged below the SOT conductor.

[0127] In some embodiments, the memory device further includes: a read word line conductively connected to the two-terminal read selector, wherein the read word line is arranged above the two-terminal read selector.

[0128] In some embodiments, the memory device further includes: a write word line conductively connected to the dual-terminal write selector, wherein the write word line is arranged above the dual-terminal write selector.

[0129] In some embodiments, the memory device further includes: a read word line conductively connected to the two-terminal read selector; and a write word line conductively connected to the two-terminal write selector.

[0130] In some embodiments, the read word line and the write word line are located in a same conductive layer above the two-terminal write selector.

[0131] In some embodiments, each of the SOT conductor and the bit line extends in a first direction, and wherein the write word line and the read word line extend in a second direction perpendicular to the first direction.

[0132] In some embodiments, each of the two-terminal read selector and the two-terminal write selector is a non-linear diode.

[0133] In some embodiments, each of the two-terminal read selector and the two-terminal write selector includes a switching layer sandwiched between a first conductor layer and a second conductor layer.

[0134] In some embodiments, the switching layer in the two-terminal read selector and the switching layer in the two-terminal write selector are formed of the same switching material layer.

[0135] In some embodiments, at least the switching layer in the two-terminal write selector comprises a phase change material.

[0136] In some embodiments, at least the switching layer in the two-terminal write selector includes a chalcogenide material or a solid electrolyte material.

[0137] Another aspect of the present disclosure relates to a memory device. The memory device includes a spin-orbit torque ("SOT") conductor and a magnetic tunnel junction ("MTJ") structure arranged above the SOT conductor. The MTJ structure has a free layer, a pinned layer, and a tunnel barrier layer sandwiched between the free layer and the pinned layer, and wherein the free layer is in conductive contact with the SOT conductor. The memory device also includes a dual-terminal read selector and a dual-terminal write selector. The dual-terminal read selector is conductively connected to the pinned layer in the MTJ structure, and the dual-terminal read selector is arranged above the MTJ structure. The dual-terminal write selector is conductively connected to the first terminal of the SOT conductor, wherein the dual-terminal write selector is arranged below the MTJ structure. The memory device also includes a write word line and a bit line. The write word line is conductively connected to the dual-terminal write selector, and the write word line is arranged below the dual-terminal write selector. The bit line is conductively connected to the second terminal of the SOT conductor, and the bit line is arranged below the write word line.

[0138] In some embodiments, the memory device further includes a read word line conductively connected to the two-terminal read selector, wherein the read word line is disposed above the two-terminal read selector.

[0139] In some embodiments, the SOT conductor extends in a first direction, and wherein the write word line and the read word line extend in a second direction perpendicular to the first direction.

[0140] In some embodiments, the bit line extends in the first direction and is vertically stacked with the SOT conductor.

[0141] Another aspect of the present disclosure relates to a method for forming a memory device. The method includes forming a spin-orbit torque ("SOT") conductor extending in a first direction and forming a magnetic tunnel junction ("MTJ") structure above the SOT conductor. In the method, forming the MTJ structure includes depositing a free layer above the SOT conductor, depositing a tunnel barrier layer above the free layer, and depositing a pinned layer above the tunnel barrier layer. The method also includes forming a dual-terminal read selector above the MTJ structure, and forming a dual-terminal write selector. The dual-terminal read selector is conductively connected to the pinned layer in the MTJ structure. The dual-terminal write selector is conductively connected to a first terminal of the SOT conductor.

[0142] In some embodiments, the method further includes forming a read word line extending in a second direction over the two-terminal read selector, wherein the second direction is perpendicular to the first direction.

[0143] In some embodiments, the method further includes: forming the dual-terminal write selector over the MTJ structure; and forming a write word line extending in a second direction over the dual-terminal write selector.

[0144] In some embodiments, forming the SOT conductor includes forming the SOT conductor over the dual-terminal write selector, and wherein the dual-terminal write selector is formed after forming a write word line extending in the second direction.

[0145] In some embodiments, the method further includes: forming a bit line extending in a first direction; and forming the SOT conductor, the SOT conductor being above the bit line and having a second terminal conductively connected to the bit line, wherein the SOT conductor is vertically stacked with the bit line.

[0146] Those skilled in the art will readily appreciate that one or more of the disclosed embodiments achieve one or more of the above advantages. After reading the above description, those skilled in the art will be able to effect various changes, substitutions of equivalents, and various other embodiments broadly disclosed herein. Therefore, the protection granted herein is limited only by the definitions contained in the attached claims and their equivalents.

Claims

1. A memory device, comprising: Spin-orbit torque conductor; a magnetic tunnel junction structure disposed above the spin-orbit torque conductor, wherein the magnetic tunnel junction structure has a free layer, a pinned layer, and a tunnel barrier layer sandwiched between the free layer and the pinned layer, and wherein the free layer is in conductive contact with the spin-orbit torque conductor; a two-terminal read selector conductively connected to the pinned layer in the magnetic tunnel junction structure, wherein the two-terminal read selector is arranged above the magnetic tunnel junction structure; a two-terminal write selector conductively connected to a first terminal of the spin-track torque conductor, wherein the two-terminal write selector is disposed above the magnetic tunnel junction structure; and A bit line is conductively connected to the second terminal of the spin-track torque conductor, wherein the bit line is arranged below the spin-track torque conductor.

2. The memory device according to claim 1, further comprising: A read word line is conductively connected to the two-terminal read selector, wherein the read word line is arranged above the two-terminal read selector.

3. The memory device according to claim 1, further comprising: A write word line is conductively connected to the dual-terminal write selector, wherein the write word line is arranged above the dual-terminal write selector.

4. The memory device according to claim 1, further comprising: a read word line conductively connected to the two-terminal read selector; as well as A write word line is conductively connected to the two-terminal write selector.

5. The memory device according to claim 4, wherein: Each of the spin-track torque conductor and the bit line extends in a first direction, and wherein the write word line and the read word line extend in a second direction perpendicular to the first direction.

6. The memory device according to claim 1, wherein: Each of the two-terminal read selector and the two-terminal write selector includes a switching layer sandwiched between a first conductor layer and a second conductor layer.

7. A memory device comprising: Spin-orbit torque conductor; a magnetic tunnel junction structure disposed above the spin-orbit torque conductor, wherein the magnetic tunnel junction structure has a free layer, a pinned layer, and a tunnel barrier layer sandwiched between the free layer and the pinned layer, and wherein the free layer is in conductive contact with the spin-orbit torque conductor; a two-terminal read selector conductively connected to the pinned layer in the magnetic tunnel junction structure, wherein the two-terminal read selector is arranged above the magnetic tunnel junction structure; a two-terminal write selector conductively connected to a first terminal of the spin-track torque conductor, wherein the two-terminal write selector is arranged below the magnetic tunnel junction structure; a write word line conductively connected to the two-terminal write selector, wherein the write word line is arranged below the two-terminal write selector; and A bit line is conductively connected to the second terminal of the spin-track torque conductor, wherein the bit line is arranged below the write word line.

8. The memory device according to claim 7, further comprising: A read word line is conductively connected to the two-terminal read selector, wherein the read word line is arranged above the two-terminal read selector.

9. The memory device according to claim 8, wherein: The spin-track torque conductor extends in a first direction, and wherein the write word line and the read word line extend in a second direction perpendicular to the first direction.

10. A method of forming a memory device, comprising: forming a spin-orbit torque conductor extending in a first direction; forming a magnetic tunnel junction structure over the spin-orbit torque conductor, wherein forming the magnetic tunnel junction structure comprises depositing a free layer over the spin-orbit torque conductor, depositing a tunnel barrier layer over the free layer, and depositing a pinned layer over the tunnel barrier layer; and forming a two-terminal read selector over the magnetic tunnel junction structure, wherein the two-terminal read selector is conductively connected to the pinned layer in the magnetic tunnel junction structure; and A two-terminal write selector is formed and conductively connected to the first terminal of the spin-track torque conductor.

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