Semiconductor discharge tube and method of manufacturing the same

Abstract

The application discloses a semiconductor discharge tube and a preparation method thereof. The semiconductor discharge tube comprises an N-type substrate, a first P-type doped region, a second P-type doped region, a third P-type doped region and an N-type emitting region, and the first surface and the second surface are opposite to each other. The N-type emitting region and the third P-type doped region are not overlapped in the orthographic projection of the N-type substrate. The first P-type doped region, the second P-type doped region, the third P-type doped region and the N-type emitting region on the first surface are respectively symmetric to the first P-type doped region, the second P-type doped region, the third P-type doped region and the N-type emitting region on the second surface about the center of the N-type substrate. The orthographic projection of the third P-type doped region on the N-type substrate covers at least part of the orthographic projection of the first P-type doped region on the N-type substrate. The semiconductor discharge tube can improve the current-carrying capacity and the overvoltage protection capacity.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor discharge tube and its fabrication method. Background Technology

[0002] A semiconductor discharge tube is an overvoltage protection device. When the voltage exceeds the avalanche voltage of the semiconductor discharge tube, it clamps the transient voltage within the breakover voltage range. As the voltage continues to increase, the semiconductor discharge tube enters the conducting state due to the negative resistance effect, allowing it to discharge large surge currents or pulse currents. When using a semiconductor discharge tube, it can be connected in parallel across the equipment, protecting downstream power-receiving equipment within its breakdown voltage range. The current-carrying capacity of the semiconductor discharge tube determines its overvoltage protection capability. Summary of the Invention

[0003] This invention provides a semiconductor discharge tube and its preparation method to improve the current carrying capacity and overvoltage protection capability of the semiconductor discharge tube.

[0004] According to one aspect of the present invention, a semiconductor discharge tube is provided, comprising:

[0005] An N-type substrate, comprising a first surface and a second surface opposite to each other;

[0006] The first P-type doped region, the second P-type doped region, the third P-type doped region, and the N-type emitter region are all located on one side of the first surface and one side of the second surface; wherein, the second P-type doped region is located on the side of the first P-type doped region away from the N-type substrate, and the second P-type doped region is connected to the N-type substrate; the third P-type doped region and the N-type emitter region are located inside the second P-type doped region and on the side away from the first P-type doped region;

[0007] The orthographic projection of the N-type emitter region onto the N-type substrate does not overlap with the orthographic projection of the third P-type doped region onto the N-type substrate; the first P-type doped region, the second P-type doped region, the third P-type doped region, and the N-type emitter region located on the first surface are respectively symmetrical with respect to the center of the N-type substrate with respect to the first P-type doped region, the second P-type doped region, the third P-type doped region, and the N-type emitter region located on the second surface;

[0008] Wherein, the orthographic projection of the third P-type doped region onto the N-type substrate covers at least a portion of the orthographic projection of the first P-type doped region onto the N-type substrate.

[0009] Optionally, the orthographic projection of the third P-type doped region onto the N-type substrate completely coincides with the orthographic projection of the first P-type doped region onto the N-type substrate.

[0010] Optionally, the doping concentration of the third P-type doped region is much greater than the doping concentration of the first P-type doped region.

[0011] Optionally, there is a first preset depth between the side of the first P-type doped region near the N-type substrate and the side of the second P-type doped region near the N-type substrate;

[0012] There is a second predetermined depth between the side of the second P-type doped region near the N-type substrate and the side of the third P-type doped region near the N-type substrate;

[0013] The third P-type doped region has a third preset depth;

[0014] Wherein, the first preset depth is greater than the second preset depth, and the second preset depth is greater than the third preset depth.

[0015] Optionally, the range of the first preset depth includes 30 to 50 μm;

[0016] The second preset depth ranges from 15 to 30 μm;

[0017] The range of the third preset depth includes 5 to 10 μm.

[0018] Optionally, the center position of the N-type emitter region located on the first surface corresponds to the center position of the first P-type doped region located on the second surface;

[0019] Along the thickness direction perpendicular to the N-type substrate, the N-type emission region includes at least three sub-N-type emission regions, which are arranged at intervals.

[0020] Optionally, the semiconductor discharge tube further includes an inner trench, the inner wall of which is provided with a passivation layer;

[0021] In the thickness direction perpendicular to the N-type substrate, the inner trench is disposed on both sides of the second P-type doped region located on the first surface; and the inner trench is disposed on both sides of the second P-type doped region located on the second surface.

[0022] The preset depth of the inner trench is greater than the depth of the second P-type doped region.

[0023] Optionally, the semiconductor discharge tube further includes: a metal layer;

[0024] On the first surface side of the N-type substrate, the metal layer is located on the side of the third P-type doped region away from the first surface;

[0025] Furthermore, on the second surface side of the N-type substrate, the metal layer is located on the side of the third P-type doped region away from the second surface.

[0026] According to another aspect of the present invention, a method for fabricating a semiconductor discharge tube is provided, comprising:

[0027] An N-type substrate is provided; the N-type substrate includes opposing first and second surfaces;

[0028] A first P-type doped region is formed inward from the first surface and the second surface, respectively;

[0029] A second P-type doped region is formed from the first surface and the second surface inwards, respectively; the second P-type doped region is located on the side of the first P-type doped region away from the N-type substrate, and the second P-type doped region is connected to the N-type substrate;

[0030] A third P-type doped region is formed from the first surface and the second surface inwards, respectively;

[0031] An N-type emission region is formed inward from the first surface and the second surface, respectively;

[0032] The third P-type doped region and the N-type emitter region are located inside the second P-type doped region and away from the first P-type doped region. The orthographic projection of the N-type emitter region onto the N-type substrate does not overlap with the orthographic projection of the third P-type doped region onto the N-type substrate. The first P-type doped region, the second P-type doped region, the third P-type doped region, and the N-type emitter region located on the first surface are symmetrical about the center of the N-type substrate with respect to the first P-type doped region, the second P-type doped region, the third P-type doped region, and the N-type emitter region located on the second surface, respectively.

[0033] Wherein, the orthographic projection of the third P-type doped region onto the N-type substrate covers at least a portion of the orthographic projection of the first P-type doped region onto the N-type substrate.

[0034] Optionally, the method for fabricating the semiconductor discharge tube further includes:

[0035] Inner trenches are formed by etching from the first surface and the second surface inwards, respectively; wherein, in the thickness direction perpendicular to the N-type substrate, the inner trenches are respectively disposed on both sides of the second P-type doped region located on the first surface and the second surface;

[0036] A passivation material is deposited inside the inner trench to form a passivation layer;

[0037] A metal layer is formed on the first surface and the second surface.

[0038] The semiconductor discharge tube provided in this embodiment of the invention has a bidirectional structure. It has a first P-type doped region, a second P-type doped region, a third P-type doped region, and an N-type emitter region disposed on opposite first and second surfaces, respectively, and is symmetrical about the center of the N-type substrate. The first P-type doped region has a deep push-in depth, which reduces the distance between it and the second P-type doped region and the N-type emitter region located on the other surface, thereby reducing the width of the base region and improving the current carrying capacity of the semiconductor discharge tube. However, due to the deep push-in depth of the first P-type doped region, the doping concentration is low, limiting the semiconductor discharge tube's ability to discharge surge current. By providing a third P-type doped region with a shallow push-in depth at a surface position at least partially corresponding to the first P-type doped region, the surface carrier concentration of the semiconductor discharge tube in the corresponding portion of the third P-type doped region and the first P-type doped region can be increased with minimal modification to the overall structure of the semiconductor discharge tube. This further enhances the current carrying capacity of the semiconductor discharge tube in the conducting state, discharges high surge currents, and improves the overvoltage protection capability of the semiconductor discharge tube.

[0039] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic cross-sectional view of a semiconductor discharge tube according to an embodiment of the present invention;

[0042] Figure 2 This is a cross-sectional structural schematic diagram of another semiconductor discharge tube provided according to an embodiment of the present invention;

[0043] Figure 3 This is a schematic flowchart of a method for fabricating a semiconductor discharge tube according to an embodiment of the present invention;

[0044] Figure 4 This is a schematic flowchart of another method for preparing a semiconductor discharge tube according to an embodiment of the present invention. Detailed Implementation

[0045] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0046] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0047] This invention provides a semiconductor discharge tube. Figure 1 This is a schematic cross-sectional view of a semiconductor discharge tube provided in an embodiment of the present invention. Figure 1 As shown, the semiconductor discharge tube includes: an N-type substrate 10, including a first surface 11 and a second surface 12 opposite to each other; a first P-type doped region 21, a second P-type doped region 22, a third P-type doped region 23 and an N-type emitter region 24, all located on one side of the first surface 11 and one side of the second surface 12; wherein, the second P-type doped region 22 is located on the side of the first P-type doped region 21 away from the N-type substrate 10, and the second P-type doped region 22 is connected to the N-type substrate 10; the third P-type doped region 23 and the N-type emitter region 24 are located inside the second P-type doped region 22 and on the side away from the first P-type doped region 21.

[0048] The orthographic projection of the N-type emitter region 24 onto the N-type substrate 10 does not overlap with the orthographic projection of the third P-type doped region 23 onto the N-type substrate 10. The first P-type doped region 21, the second P-type doped region 22, the third P-type doped region 23, and the N-type emitter region 24 located on the first surface 11 are respectively symmetrical about the center of the N-type substrate 10 with the first P-type doped region 21, the second P-type doped region 22, the third P-type doped region 23, and the N-type emitter region 24 located on the second surface 12. The orthographic projection of the third P-type doped region 23 onto the N-type substrate 10 covers at least a portion of the orthographic projection of the first P-type doped region 21 onto the N-type substrate 10.

[0049] Specifically, the same first P-type doped region 21, second P-type doped region 22, third P-type doped region 23, and N-type emitter region 24 are provided on both the first surface 11 and the second surface 12 of the N-type substrate 10. Furthermore, the first P-type doped region 21 located on the first surface 11 side is symmetrical to the first P-type doped region 21 located on the second surface 12 side about the center of the N-type substrate 10; the second P-type doped region 22 located on the first surface 11 side is symmetrical to the second P-type doped region 22 located on the second surface 12 side about the center of the N-type substrate 10; the third P-type doped region 23 located on the first surface 11 side is symmetrical to the third P-type doped region 23 located on the second surface 12 side about the center of the N-type substrate 10; and the N-type emitter region 24 located on the first surface 11 side is symmetrical to the N-type emitter region 24 located on the second surface 12 side about the center of the N-type substrate 10. Therefore, the semiconductor discharge tube provided in this embodiment of the invention can achieve bidirectional discharge effect. That is, regardless of whether the semiconductor discharge tube is subjected to a positive surge or a negative surge, it can undergo avalanche breakdown, thereby discharging the surge current.

[0050] By providing an N-type emitter region 24 and a second P-type doped region 22 on both the first surface 11 and the second surface 12, the NPN transistor structure formed by the N-type emitter region 24, the second P-type doped region 22, and the N-type substrate 10 can have a large negative resistance characteristic, thereby improving the ability to discharge surge current. Since the structures on the first surface 11 are identical to those on the second surface 12, this embodiment will describe the structures on the first surface 11. The deeper push-in depth of the first P-type doped region 21 results in a smaller distance between the first P-type doped region 21 on the first surface 11, the second P-type doped region 22 on the second surface 12, and the N-type emitter region 24, which helps to reduce the width of the base region. When the semiconductor discharge tube is in the conducting state, current flows from the first P-type doped region 21 on the first surface 11 to the second P-type doped region 22 and the N-type emitter region 24 on the second surface 12. By setting the first P-type doped region 21 to have a deeper push-junction depth, the width of the base region can be reduced, which is beneficial to improving the current carrying capacity of the semiconductor discharge tube in the conducting state, realizing the discharge of surge current and providing overvoltage protection for the equipment.

[0051] However, due to the deep bonding depth and low doping concentration of the first P-type doped region 21, the semiconductor discharge tube's ability to discharge surge current is limited. Therefore, a third P-type doped region 23 with a shallow bonding depth is provided at a position on the surface layer of the first surface 11 of the N-type substrate 10 that at least partially corresponds to the first P-type doped region 21. That is, the third P-type doped region 23 corresponds at least partially to the first P-type doped region 21, thus minimizing the overall structural changes to the semiconductor discharge tube caused by the addition of the third P-type doped region 23. Since the doping concentration of the third P-type doped region 23 is higher than that of the first P-type doped region 21, it is beneficial to increase the surface carrier concentration of the semiconductor discharge tube in the portion where the third P-type doped region 23 corresponds to the first P-type doped region 21. This further enhances the current-carrying capacity of the semiconductor discharge tube in the conducting state, discharges high surge current, and improves the overvoltage protection capability of the semiconductor discharge tube.

[0052] The semiconductor discharge tube provided in this embodiment of the invention has a bidirectional structure. It has a first P-type doped region, a second P-type doped region, a third P-type doped region, and an N-type emitter region disposed on opposite first and second surfaces, respectively, and is symmetrical about the center of the N-type substrate. The first P-type doped region has a deep push-in depth, which reduces the distance between it and the second P-type doped region and the N-type emitter region located on the other surface, thereby reducing the width of the base region and improving the current carrying capacity of the semiconductor discharge tube. However, due to the deep push-in depth of the first P-type doped region, the doping concentration is low, limiting the semiconductor discharge tube's ability to discharge surge current. By providing a third P-type doped region with a shallow push-in depth at a surface position at least partially corresponding to the first P-type doped region, the surface carrier concentration of the semiconductor discharge tube in the corresponding portion of the third P-type doped region and the first P-type doped region can be increased with minimal modification to the overall structure of the semiconductor discharge tube. This further enhances the current carrying capacity of the semiconductor discharge tube in the conducting state, discharges high surge currents, and improves the overvoltage protection capability of the semiconductor discharge tube.

[0053] Optionally, based on the above embodiments, see below. Figure 1 The orthographic projection of the third P-type doped region 23 onto the N-type substrate 10 completely coincides with the orthographic projection of the first P-type doped region 21 onto the N-type substrate 10.

[0054] Specifically, the width of the third P-type doped region 23 is set to be the same as the width of the first P-type doped region 21, meaning that the orthographic projection of the third P-type doped region 23 onto the N-type substrate 10 completely overlaps with the orthographic projection of the first P-type doped region 21 onto the N-type substrate 10. This increases the surface carrier concentration of the semiconductor discharge tube and the corresponding surface portion of the first P-type doped region 21, improving the current-carrying capacity of the semiconductor discharge tube, thereby enabling the discharge of high surge current and strengthening the overvoltage protection of the equipment. It should be noted that if the width of the third P-type doped region 23 is greater than the width of the first P-type doped region 21, the portion of the third P-type doped region 23 that extends beyond the first P-type doped region 21 in the width direction has a weaker effect on improving the current-carrying capacity of the semiconductor discharge tube, and will significantly alter the overall structure of the semiconductor discharge tube. Therefore, setting the width of the third P-type doped region 23 to be the same as the width of the first P-type doped region 21 is the optimal solution.

[0055] Optionally, based on the above embodiments, see below. Figure 1 The doping concentration of the third P-type doped region 23 is much greater than that of the first P-type doped region 21.

[0056] Specifically, the first P-type doped region 21, the second P-type doped region 22, and the third P-type doped region 23 are all heavily doped regions doped with group III elements. For example, they can be heavily doped regions of boron, but this is not a limitation. In the surface region corresponding to the first P-type doped region 21, a third P-type doped region 23 with a shallower bonding depth is provided, while the first P-type doped region 21 has a deeper bonding depth. For example, there is a first preset depth between the side of the first P-type doped region 21 near the N-type substrate 10 and the side of the second P-type doped region 22 near the N-type substrate 10; there is a second preset depth between the side of the second P-type doped region 22 near the N-type substrate 10 and the side of the third P-type doped region 23 near the N-type substrate 10; and the third P-type doped region 23 has a third preset depth. The first preset depth is greater than the second preset depth, and the second preset depth is greater than the third preset depth. In other words, the push-in depth of the third P-type doped region 23 is a third preset depth, the push-in depth of the second P-type doped region 22 is the sum of the second preset depth and the third preset depth, and the push-in depth of the first P-type doped region 21 is the sum of the first preset depth, the second preset depth, and the third preset depth. For example, the range of the first preset depth includes 30–50 μm; the range of the second preset depth includes 15–30 μm; and the range of the third preset depth includes 5–10 μm. Thus, the push-in depths of the first P-type doped region 21, the second P-type doped region 22, and the third P-type doped region 23 can be determined.

[0057] Optionally, Figure 2 This is a cross-sectional structural schematic diagram of another semiconductor discharge tube provided in an embodiment of the present invention. Based on the above embodiments, as follows... Figure 2As shown, the center of the N-type emission region 24 located on the first surface 11 corresponds to the center of the first P-type doped region 21 located on the second surface 12; along the thickness direction perpendicular to the N-type substrate 10, the N-type emission region 24 includes at least 3 sub-N-type emission regions 241, and each sub-N-type emission region 241 is arranged at intervals.

[0058] Specifically, by setting the center position of the N-type emitter region 24 on one side of the first surface 11 to correspond to the center position of the first P-type doped region 21 on one side of the second surface 12, that is, the N-type emitter region 24 on one side of the first surface 11 and the first P-type doped region 21 on one side of the second surface 12 are axially symmetrical about the straight line where the center of the N-type emitter region 24 or the straight line where the first P-type doped region 21 is located, the current conduction path between the first P-type doped region 21 and the N-type emitter region 24 is minimized, that is, the breakdown current path is minimized when the semiconductor discharge tube undergoes avalanche breakdown, making it easiest to achieve conduction, and the current conduction is uniform, which is beneficial to discharging high surge current and strengthening the overvoltage protection of the equipment.

[0059] The N-type emitter region 24 may include at least three sub-N-type emitter regions 241, each sub-N-type emitter region 241 being equally spaced along a direction perpendicular to the thickness of the N-type substrate 10. For example, Figure 2 The diagram illustrates an N-type emitter region 24 comprising four sub-N-type emitter regions 241. A short-circuit via is provided between each adjacent sub-N-type emitter region 241. Without this via, a large-area semiconductor discharge tube would experience current concentration in one area, while other areas would have no current flow. By providing multiple short-circuit vias, the interference immunity of the semiconductor discharge tube is improved.

[0060] Optionally, based on the above embodiments, see below. Figure 2 The semiconductor discharge tube also includes an inner trench 30, the inner wall of which is provided with a passivation layer 31.

[0061] In the thickness direction perpendicular to the N-type substrate 10, the inner trench 30 is disposed on both sides of the second P-type doped region 22 located on the first surface 11; and the inner trench 30 is disposed on both sides of the second P-type doped region 22 located on the second surface 12; the preset depth of the inner trench 30 is greater than the depth of the second P-type doped region 22.

[0062] Specifically, an inner trench 30 is provided at the junction of the second P-type doped region 22 and the N-type substrate 10 in the semiconductor discharge tube. The inner trench 30 is U-shaped. A U-shaped inner trench 30 is provided on one side of the first surface 11 and one side of the second surface 12, and the bottom of the inner trench 30 extends beyond the second P-type doped region 22, meaning the depth of the inner trench 30 is greater than the push-in depth of the second P-type doped region 22. For example, the dimension by which the bottom of the inner trench 30 extends beyond the second P-type doped region 22 can be set to 15–30 μm. A passivation layer 31 covering the inner wall is also provided inside the inner trench 30. The passivation layer 31 can be prepared using glass powder, which helps improve the withstand voltage of the semiconductor discharge tube, reduces high-temperature leakage current, and thus improves the reliability of the semiconductor discharge tube.

[0063] Optionally, based on the above embodiments, see below. Figure 2 The semiconductor discharge tube also includes a metal layer 40.

[0064] On the first surface 11 side of the N-type substrate 10, the metal layer 40 is located on the side of the third P-type doped region 23 away from the first surface 11; and on the second surface 12 side of the N-type substrate 10, the metal layer 40 is located on the side of the third P-type doped region 23 away from the second surface 12.

[0065] Specifically, a metal layer 40 is provided on the surface of the third P-type doped region 23 located on the first surface 11 and on the surface of the third P-type doped region 23 located on the second surface 12, serving as the electrode of the semiconductor discharge tube and connected to the second P-type doped region 22, the third P-type doped region 23 and the N-type emitter region 24, thereby achieving the effect of bidirectional discharge.

[0066] This invention also provides a method for preparing a semiconductor discharge tube. Figure 3 This is a schematic flowchart illustrating a method for fabricating a semiconductor discharge tube according to an embodiment of the present invention. Figure 3 As shown, the fabrication method of this semiconductor discharge tube specifically includes the following steps:

[0067] S110, Provide an N-type substrate; the N-type substrate includes opposing first and second surfaces.

[0068] S120, a first P-type doped region is formed from the first surface and the second surface inwards respectively.

[0069] For example, a patterning process involving double-sided coating, exposure, and development is performed on the first and second surfaces, respectively. Boron diffusion is then performed on the corresponding areas at 1000–1200°C for 50–100 minutes, resulting in a sheet resistance of 3–10 Ω / sq for the formed doped region. Subsequently, the formed doped region is subjected to boron oxidation at 1000–1300°C for 40–60 hours, resulting in an oxide layer thickness of [missing information]. This forms the first P-type doped region.

[0070] S130, a second P-type doped region is formed from the first surface and the second surface inwards respectively; the second P-type doped region is located on the side of the first P-type doped region away from the N-type substrate, and the second P-type doped region is connected to the N-type substrate.

[0071] For example, a patterning process involving double-sided coating, exposure, and development is performed on the first and second surfaces, respectively. Boron diffusion is then performed on the corresponding areas at 1000–1200°C for 50–100 minutes, resulting in a sheet resistance of 10–25 Ω / sq for the formed doped region. Subsequently, the formed doped region is subjected to boron oxidation at 1000–1300°C for 15–20 hours, resulting in an oxide layer thickness of [missing information]. This forms the second P-type doped region.

[0072] S140, a third P-type doped region is formed from the first surface and the second surface inwards.

[0073] For example, a patterning process involving double-sided coating, exposure, and development is performed on the first and second surfaces, respectively. Boron diffusion is then performed on the corresponding areas at 1000–1200°C for 100–300 min, resulting in a sheet resistance of 1–5 Ω / sq for the formed doped region. Subsequently, the formed doped region is subjected to boron oxidation at 1000–1300°C for 100–200 min, resulting in an oxide layer thickness of [missing information]. This forms the third P-type doped region.

[0074] S150, an N-type emission region is formed from the first surface and the second surface inwards respectively.

[0075] For example, a patterning process involving double-sided coating, exposure, and development is performed on the first and second surfaces, respectively. Phosphorus diffusion is then performed on the corresponding areas at 1000–1100°C for 50–100 min, resulting in a sheet resistance of 1–5 Ω / sq for the formed doped region. Subsequently, the formed doped region is subjected to boron oxidation at 1000–1300°C for 100–200 min, resulting in an oxide layer thickness of [missing information]. This forms an N-type emission region.

[0076] The third P-type doped region and the N-type emitter region are located inside the second P-type doped region and on the side away from the first P-type doped region; the orthographic projection of the N-type emitter region onto the N-type substrate does not overlap with the orthographic projection of the third P-type doped region onto the N-type substrate; the first P-type doped region, the second P-type doped region, the third P-type doped region, and the N-type emitter region located on the first surface are respectively symmetrical about the center of the N-type substrate with respect to the first P-type doped region, the second P-type doped region, the third P-type doped region, and the N-type emitter region located on the second surface; wherein the orthographic projection of the third P-type doped region onto the N-type substrate covers at least a portion of the orthographic projection of the first P-type doped region onto the N-type substrate.

[0077] In summary, the semiconductor discharge tube prepared by the method provided in the embodiments of the present invention has similar beneficial effects to the semiconductor discharge tube provided in any of the above embodiments, and will not be elaborated further here.

[0078] Optionally, Figure 4 This is a schematic flowchart of another method for fabricating a semiconductor discharge tube according to an embodiment of the present invention. Based on the above embodiments, as follows... Figure 4 As shown, the fabrication method of this semiconductor discharge tube may further include the following steps:

[0079] S210, Provide an N-type substrate; the N-type substrate includes opposing first and second surfaces.

[0080] S220, a first P-type doped region is formed from the first surface and the second surface inwards respectively.

[0081] S230, a second P-type doped region is formed from the first surface and the second surface inwards respectively; the second P-type doped region is located on the side of the first P-type doped region away from the N-type substrate, and the second P-type doped region is connected to the N-type substrate.

[0082] S240, a third P-type doped region is formed from the first surface and the second surface inwards.

[0083] S250, with an N-type emission region formed from the first surface and the second surface inwards respectively.

[0084] S260, an inner trench is formed by etching from the first surface and the second surface inward; wherein, in the thickness direction perpendicular to the N-type substrate, the inner trench is respectively disposed on both sides of the second P-type doped region located on the first surface and the second surface.

[0085] For example, a patterning process involving double-sided coating, exposure, and development is performed on the first and second surfaces, respectively, and inner trenches are formed by etching the corresponding areas on both sides of the second P-type doped region using silicon etchant. The bottom of the inner trenches extends 15–30 μm beyond the second P-type doped region.

[0086] S270. Passivating material is deposited inside the inner trench to form a passivation layer.

[0087] For example, glass powder can be used as the passivation material. Glass powder is deposited inside the inner trenches on both sides, and a glass passivation layer is formed by high-temperature sintering to passivate and protect the semiconductor discharge tube.

[0088] S280, A metal layer is formed on the first surface and the second surface.

[0089] For example, metal materials are evaporated on both the first and second surfaces, and then double-sided metal photolithography is performed. The photolithographic areas are etched using a metal etching solution to form the metal films on both sides, and an alloy layer is formed in the photolithographic areas under vacuum.

[0090] Optionally, based on the above embodiments, before forming the first P-type doped region from the first surface and the second surface inwards, the first and second surfaces of the N-type substrate need to be double-sided oxidized, and the thickness of the resulting oxide layer is [missing information].

[0091] In the formation of the first P-type doped region in step S220, the formation of the second P-type doped region in step S230, the formation of the third P-type doped region in step S240, and the formation of the N-type emitter region in step S250, after the double-sided patterning process, the surface oxide layer of the photolithographic area must be removed using buffered oxide etchant (BOE).

[0092] Furthermore, in the formation of the inner trench in step S260, after the double-sided patterning process, the surface oxide layer of the photolithographic area also needs to be removed using BOE solution.

[0093] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A semiconductor discharge tube, characterized in that, include: An N-type substrate, comprising a first surface and a second surface opposite to each other; The first P-type doped region, the second P-type doped region, the third P-type doped region, and the N-type emitter region are all located on one side of the first surface and one side of the second surface; wherein, the second P-type doped region is located on the side of the first P-type doped region away from the N-type substrate, and the second P-type doped region is connected to the N-type substrate; the third P-type doped region and the N-type emitter region are located inside the second P-type doped region and on the side away from the first P-type doped region; The orthographic projection of the N-type emitter region onto the N-type substrate does not overlap with the orthographic projection of the third P-type doped region onto the N-type substrate; the first P-type doped region, the second P-type doped region, the third P-type doped region, and the N-type emitter region located on the first surface are respectively symmetrical with respect to the center of the N-type substrate with respect to the first P-type doped region, the second P-type doped region, the third P-type doped region, and the N-type emitter region located on the second surface; Wherein, the orthographic projection of the third P-type doped region onto the N-type substrate completely coincides with the orthographic projection of the first P-type doped region onto the N-type substrate; the doping concentration of the third P-type doped region is much greater than the doping concentration of the first P-type doped region.

2. The semiconductor discharge tube according to claim 1, characterized in that, There is a first predetermined depth between the side of the first P-type doped region near the N-type substrate and the side of the second P-type doped region near the N-type substrate; There is a second predetermined depth between the side of the second P-type doped region near the N-type substrate and the side of the third P-type doped region near the N-type substrate; The third P-type doped region has a third preset depth; Wherein, the first preset depth is greater than the second preset depth, and the second preset depth is greater than the third preset depth.

3. The semiconductor discharge tube according to claim 2, characterized in that, The first preset depth ranges from 30 to 50 μm; The second preset depth ranges from 15 to 30 μm; The range of the third preset depth includes 5 to 10 μm.

4. The semiconductor discharge tube according to claim 1, characterized in that, The center position of the N-type emission region located on the first surface corresponds to the center position of the first P-type doped region located on the second surface; Along the thickness direction perpendicular to the N-type substrate, the N-type emission region includes at least three sub-N-type emission regions, which are arranged at intervals.

5. The semiconductor discharge tube according to claim 1, characterized in that, Also includes: An inner groove, wherein the inner wall of the inner groove is provided with a passivation layer; In the thickness direction perpendicular to the N-type substrate, the inner trench is disposed on both sides of the second P-type doped region located on the first surface; and the inner trench is disposed on both sides of the second P-type doped region located on the second surface. The preset depth of the inner trench is greater than the depth of the second P-type doped region.

6. The semiconductor discharge tube according to claim 1, characterized in that, Also includes: Metal layer; On the first surface side of the N-type substrate, the metal layer is located on the side of the third P-type doped region away from the first surface; Furthermore, on the second surface side of the N-type substrate, the metal layer is located on the side of the third P-type doped region away from the second surface.

7. A method for fabricating a semiconductor discharge tube, characterized in that, include: Provide an N-type substrate; The N-type substrate includes opposing first and second surfaces; A first P-type doped region is formed inward from the first surface and the second surface, respectively; A second P-type doped region is formed from the first surface and the second surface inwards, respectively; the second P-type doped region is located on the side of the first P-type doped region away from the N-type substrate, and the second P-type doped region is connected to the N-type substrate; A third P-type doped region is formed from the first surface and the second surface inwards, respectively; An N-type emission region is formed inward from the first surface and the second surface, respectively; The third P-type doped region and the N-type emitter region are located inside the second P-type doped region and away from the first P-type doped region. The orthographic projection of the N-type emitter region onto the N-type substrate does not overlap with the orthographic projection of the third P-type doped region onto the N-type substrate. The first P-type doped region, the second P-type doped region, the third P-type doped region, and the N-type emitter region located on the first surface are symmetrical about the center of the N-type substrate with respect to the first P-type doped region, the second P-type doped region, the third P-type doped region, and the N-type emitter region located on the second surface, respectively. Wherein, the orthographic projection of the third P-type doped region onto the N-type substrate completely coincides with the orthographic projection of the first P-type doped region onto the N-type substrate; the doping concentration of the third P-type doped region is much greater than the doping concentration of the first P-type doped region.

8. The method for preparing a semiconductor discharge tube according to claim 7, characterized in that, Also includes: Inner trenches are formed by etching from the first surface and the second surface inwards, respectively; wherein, in the thickness direction perpendicular to the N-type substrate, the inner trenches are respectively disposed on both sides of the second P-type doped region located on the first surface and the second surface; A passivation material is deposited inside the inner trench to form a passivation layer; A metal layer is formed on the first surface and the second surface.

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