Manufacturing method of array substrate and display panel

Abstract

The invention discloses a manufacturing method of an array substrate and a display panel, and relates to the technical field of display, and the manufacturing method of the array substrate comprises the following steps: providing a substrate; depositing a metal material on the surface of the substrate to form a first metal layer; etching the first metal layer to form a first data line and a grid electrode on the surface, corresponding to the non-opening region, of the substrate; depositing a barrier material on the surfaces of the gate, the first data line and the substrate to form a first barrier layer; depositing an insulating material on the surface of the first barrier layer to form a gate insulating layer; and sequentially removing the gate insulating layer and the first barrier layer formed on the surface, corresponding to the opening region, of the substrate. According to the manufacturing method provided by the invention, the problem that the etching depth of the film layer cannot be accurately controlled easily when the film layer of the opening area of the array substrate is etched in the prior art can be solved, and the display uniformity of the display area and the use experience of a user are improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a method for manufacturing an array substrate and a display panel. Background Art

[0002] As a widely used display technology, the working principle of liquid crystal display panel is based on the optical anisotropy of liquid crystal material. It changes the arrangement state of liquid crystal molecules through external electric field, thereby controlling the transmittance of light and realizing the function of image display. Liquid crystal display panel includes light source, array substrate, liquid crystal molecule layer and color filter substrate.

[0003] The light emitted by the light source will be transmitted and reflected when passing through different film layers, thus causing the interference effect of light. Since there are many film layers stacked on the substrate surface of the array substrate, the light will interfere multiple times when passing through the array substrate. This interference effect will cause uneven brightness and color deviation of the display screen.

[0004] The applicant has made improvements to the problem of light interference when passing through the array substrate. When the array substrate is processed and formed, part of the film layer of the array substrate in the opening area is etched to reduce the number of film layers in the opening area of ​​the array substrate, thereby reducing the number of light interferences. However, when etching the film layer in the opening area of ​​the array substrate, since most of the film layers are inorganic non-metallic or organic light-transmitting materials, and the composition is the same or similar to that of the substrate material, the etching selectivity between the film layers is relatively low. When etching the film layer on the surface of the substrate, it is easy to fail to accurately control the etching depth, resulting in incomplete etching of the film layer, or etching of the substrate material, which in turn leads to uneven display in the display area, affecting the visual experience. Summary of the invention

[0005] The main purpose of the present invention is to provide a method for manufacturing an array substrate and a display panel, aiming to solve the problem that the etching depth of the film layer cannot be accurately controlled when etching the film layer in the opening area of ​​the array substrate.

[0006] To achieve the above object, the present invention provides a method for manufacturing an array substrate, comprising the steps of:

[0007] providing a substrate;

[0008] Depositing a metal material on the surface of the substrate to form a first metal layer;

[0009] Etching the first metal layer to form a first data line and a gate on the surface of the substrate corresponding to the non-opening area;

[0010] Depositing a barrier material on the surface of the gate, the first data line and the substrate to form a first barrier layer;

[0011] Depositing an insulating material on a surface of the first barrier layer to form a gate insulating layer;

[0012] The gate insulating layer and the first barrier layer formed on the surface of the substrate corresponding to the opening area are removed in sequence.

[0013] In one embodiment of the present invention, the step of removing the gate insulating layer includes:

[0014] providing a first mask;

[0015] Covering the first mask plate on the surface of the gate insulation layer;

[0016] The gate insulating layer formed on the surface of the substrate corresponding to the opening area is dry-etched.

[0017] In one embodiment of the present invention, the step of removing the first barrier layer includes:

[0018] The first barrier layer formed on the surface of the substrate corresponding to the opening area is wet-etched.

[0019] In one embodiment of the present invention, after the step of depositing a barrier material to form a first barrier layer, before the step of depositing an insulating material on a surface of the first barrier layer to form a gate insulating layer, the step includes:

[0020] providing a second mask;

[0021] Covering the second mask plate on the surface of the first barrier layer;

[0022] The portion of the first barrier layer corresponding to the non-opening area is etched and removed.

[0023] In one embodiment of the present invention, the barrier material is indium tin oxide;

[0024] The step of depositing a barrier material to form a barrier layer comprises:

[0025] The indium tin oxide is physically vapor deposited on the surface of the gate, the surface of the first data line, and the surface of the substrate corresponding to the opening area to form a first barrier layer.

[0026] In one embodiment of the present invention, the thickness of the first barrier layer is in the range of

[0027] In one embodiment of the present invention, after the step of etching the first barrier layer, the step further includes:

[0028] The gate insulating layer formed by etching the surface of the first data line;

[0029] Depositing the metal material on a surface of the gate insulating layer and on a surface of the substrate corresponding to the opening region to form a second metal layer;

[0030] The second metal layer is etched at a portion corresponding to the opening area to form a second data line on a surface of the first data line, and a semiconductor layer, a source electrode, and a drain electrode are formed on a surface of the gate insulating layer.

[0031] In one embodiment of the present invention, after the step of etching the portion of the second metal layer corresponding to the opening area to form a second data line on the surface of the first data line and forming a semiconductor layer, a source electrode and a drain electrode on the surface of the gate insulating layer, the step further includes:

[0032] Depositing the barrier material on a surface of the second metal layer, a surface of the gate insulating layer, and a surface of the substrate corresponding to the opening area to form a second barrier layer;

[0033] Depositing the insulating material on the surface of the second barrier layer to form a first insulating layer;

[0034] The first insulating layer and the second barrier layer in the substrate corresponding to the opening area are etched in sequence.

[0035] In one embodiment of the present invention, the step of depositing a barrier material on the second data line in the opening area and on the surface of the substrate to form a second barrier layer includes:

[0036] providing a third mask plate;

[0037] Depositing the barrier material on the surface of the second metal layer, the surface of the gate insulating layer, and the surface of the substrate corresponding to the opening area to form the second barrier layer,

[0038] Covering the third mask plate on the surface of the second barrier layer;

[0039] The portion of the second barrier layer corresponding to the non-opening area is etched.

[0040] The present invention further provides an array substrate, the array substrate comprising:

[0041] substrate;

[0042] A thin film transistor, wherein the thin film transistor is disposed on a surface of the substrate corresponding to the non-opening area, and the thin film transistor comprises a gate electrode, a gate insulating layer, a semiconductor layer, a drain electrode, and a source electrode which are sequentially stacked on the surface of the substrate;

[0043] A data line is arranged on a surface of the substrate corresponding to the non-opening area and is electrically connected to the thin film transistor.

[0044] The present invention also proposes a display panel, which includes a color filter substrate, a liquid crystal layer and the array substrate as described above, wherein the array substrate and the color filter substrate are enclosed to form a liquid crystal box, the liquid crystal layer is filled in the liquid crystal box and is located between the array substrate and the color filter substrate.

[0045] The present invention further provides a display device, comprising a backlight module and the display panel as described above, wherein the display panel is arranged on the light emitting side of the backlight module.

[0046] The manufacturing method of the array substrate proposed by the present invention includes first depositing a metal material on the surface of the substrate to form a first metal layer, then patterning the first metal layer, and etching the first metal layer to form a first data line and a gate on the surface of the substrate corresponding to the non-opening area. Then, a barrier material is deposited on the gate, the first data line and the surface of the substrate, and a first barrier layer is formed on the surface thereof, and then an insulating material is deposited on the surface of the first barrier layer to form a gate insulating layer. Finally, the gate insulating layer and the first barrier layer of the opening area are sequentially etched, and the first barrier layer is selected from a material having a large etching selectivity ratio between the substrate and the gate insulating layer. Therefore, when etching the gate insulating layer, the first barrier layer plays a role in blocking etching to prevent etching to the substrate material, and due to the protective effect of the first barrier layer, the etching time or etching depth can be increased when etching the gate insulating layer to ensure that the gate insulating layer is completely etched. Then, the first barrier layer is etched, and since the first barrier layer also has a large etching selectivity ratio with the substrate, when etching the first barrier layer, the damage to the substrate material can also be effectively reduced. Therefore, the manufacturing method proposed in the present application can solve the problem that the etching depth of the film layer cannot be accurately controlled when etching the film layer in the opening area of ​​the array substrate, thereby improving the display uniformity of the display area and the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0048] Figure 1 A schematic structural diagram of an embodiment of an array substrate provided by the present invention;

[0049] Figure 2 for Figure 1 Section view along AA;

[0050] Figure 3 for Figure 1 Sectional view along BB;

[0051] Figure 4 for Figure 1 A cross-sectional view of another embodiment of the array substrate along the line BB;

[0052] Figure 5 A flow chart of an embodiment of a method for manufacturing an array substrate provided by the present invention;

[0053] Figure 6 for Figure 5 A flow chart of the steps for removing the gate layer;

[0054] Figure 7 for Figure 5 A flowchart of the steps for removing the first barrier layer;

[0055] Figure 8 for Figure 5 A flow chart after the step of forming a first barrier layer and before the step of forming a gate insulating layer;

[0056] Fig. 9 for Figure 5 A flow chart of steps for forming a first barrier layer;

[0057] Fig.10 for Figure 5 A flow chart of the steps after etching the first barrier layer;

[0058] Fig.11 for Fig.10 A flowchart of steps for forming a second data line, a semiconductor layer, a source electrode and a drain electrode;

[0059] Fig.12 for Fig.11 Flow chart of the steps for forming the second barrier layer.

[0060] Description of Figure Numbers:

[0061] 1. array substrate; 10. substrate; 21. gate; 22. first data line; 30. gate insulating layer; 31. first barrier layer; 41. source; 42. drain; 43. second data line; 44. semiconductor layer; 50. first insulating layer; 60. planar layer; 70. common electrode; 80. second insulating layer; 90. pixel electrode; 100. opening area; 200. non-opening area.

[0062] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0063] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0064] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components in a certain specific posture. If the specific posture changes, the directional indication will also change accordingly.

[0065] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features limited to "first" and "second" may explicitly or implicitly include at least one of the features. In addition, if "and / or" or "and / or" appears in the full text, its meaning includes three parallel solutions. Taking "A and / or B" as an example, it includes solution A, solution B, or solutions that satisfy both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in this field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0066] The present invention provides a method for manufacturing an array substrate 1. The array substrate 1 may be a FFS (Fringe Field Switching) structure, a VA (Vertical Alignment) structure, an IPS (In-Plane Switching) structure, etc. The inventive concept proposed in this application can be applied to the above-mentioned various structures. In the FFS structure, the IGZO (Indium Gallium Zinc Oxide) oxide product has more film layers stacked on the array substrate 1, and light is more likely to interfere. Therefore, this application takes the IGZO oxide product in the FFS structure as an example to explain the method for manufacturing the array substrate 1, and other structures are not explained one by one.

[0067] Combination Figures 1 to 4 , Figure 5 As shown, in one embodiment of the present invention, the method for manufacturing the array substrate 1 comprises the steps of:

[0068] Providing a substrate 10, an insulating material, a metal material, and a barrier material;

[0069] S100: depositing a metal material on the surface of the substrate 10 to form a first metal layer;

[0070] S200: etching the first metal layer to form a first data line 22 and a gate 21 on the surface of the substrate 10 corresponding to the non-opening area 100;

[0071] S300 : depositing a barrier material on the surface of the gate 21 , the first data line 22 and the substrate 10 to form a first barrier layer 31 ;

[0072] S400: depositing an insulating material on the surface of the first barrier layer 31 to form a gate insulating layer 30;

[0073] S500 : sequentially removing the gate insulating layer 30 and the first barrier layer 31 formed on the surface of the substrate 10 corresponding to the opening area 100 .

[0074] In this embodiment, the material of the substrate 10 can be a transparent material such as glass or plastic, so that the backlight source of the subsequent display panel can pass through the substrate 10. The insulating material can be selected from silicon dioxide, silicon nitride or other suitable inorganic non-metallic insulating materials, which have good insulation properties and stability. The metal material can be selected from metals with good conductivity such as aluminum, copper, molybdenum, etc. to ensure that the first metal layer has good conductivity. The barrier material can be indium tin oxide (ITO), zinc oxide (ZnO) or other materials that are relatively large with the etching of the substrate 10 and the gate insulating layer 30.

[0075] When forming the first metal layer on the surface of the substrate 10 , a physical vapor deposition (PVD) or chemical vapor deposition (CVD) method may be used to deposit a metal material on the surface of the substrate 10 to form the first metal layer.

[0076] After the first metal layer is deposited, it is necessary to pattern the first metal layer to form the circuit pattern required by the array substrate 1. Specifically, a pre-designed first metal layer mask is placed on the surface of the first metal layer, and a wet etching or dry etching technique is used to etch the first metal layer corresponding to the mask window, thereby transferring the pattern of the mask to the first metal layer to form the first data line 22 and the gate 21 in the non-opening area 100. Of course, the first metal layer can also be patterned by photolithography and etching processes, for example, a photoresist is coated on the surface of the first metal layer, and then the photoresist layer is exposed, developed, and patterned; then the first metal layer is etched again, and the portion blocked by the photoresist layer is retained to form the first data line 22 and the gate 21, and the first metal layer exposed in the photoresist layer window is etched away, thereby achieving patterning of the first metal layer.

[0077] After etching is completed, the array substrate 1 needs to be cleaned. Pure water or organic solvents can be used for cleaning to remove the etching residues of the first metal layer, while improving the surface adhesion of the first metal layer and the substrate 10, thereby improving the connection strength between the first metal layer, the substrate 10 and the film layer thereon.

[0078] The gate 21 is used to receive a scanning signal and turn on the thin film transistor according to the cycle of the scanning signal. Since the thin film transistor is arranged in the non-opening area 100 and the gate 21 is made of metal material, the gate 21 will block the propagation of light. Therefore, the gate 21 is arranged in the non-opening area 100, which is convenient for the connection between the gate 21 and the thin film transistor, and can also avoid affecting the area of ​​the display area of ​​the display panel (that is, increasing the aperture ratio of the display panel).

[0079] The first data line 22 is connected to the source electrode 41 of the thin film transistor, and transmits the voltage signal and the image signal to the pixel electrode 90 in each pixel unit to display the image.

[0080] After the first metal layer is patterned, a barrier material is then deposited on the surfaces of the gate 21, the first data line 22, and the opening area 100 corresponding to the substrate 10 to form the first barrier layer 31. Specifically, a barrier material can be deposited on the surfaces of the substrate 10 and the first metal layer by a method such as physical vapor deposition (PVD) or chemical vapor deposition (CVD) to form the first barrier layer 31.

[0081] Then, a gate insulating layer 30 is deposited on the surface of the first barrier layer 31. Specifically, an insulating material is deposited on the surface of the first barrier layer 31 by chemical vapor deposition (CVD) or atomic layer deposition (ALD) to form the gate insulating layer 30. The material of the gate insulating layer 30 is SiNx (silicon nitride) or SiOx (silicon oxide). SiNx and SiOx have a high dielectric constant, which can improve the insulation performance between the first metal layer and other film layers, and between the gate 21 and the first data line 22 in the first metal layer, and improve the breakdown voltage. In addition, SiNx and SiOx have good light transmittance, which can reduce the absorption and reflection of light.

[0082] Since the gate insulating layer 30 deposited in the opening area 100 will cause interference of light, and the first barrier layer 31 deposited in the opening area 100 will affect the transmission of light, it is necessary to etch the gate insulating layer 30 and the first barrier layer 31 in the opening area 100 in sequence. The first barrier layer 31 has a large etching selectivity with the substrate 10 and the gate insulating layer 30, so the first barrier layer 31 is arranged between the substrate 10, the first metal layer and the gate insulating layer 30. When etching the gate insulating layer 30 in the opening area 100, the first barrier layer 31 located under the gate insulating layer 30 acts as an etching barrier, so the gate insulating layer 30 in the opening area 100 can be fully etched by optimizing the etching parameters (for example, extending the etching time, increasing the gas flow rate). Due to the etching barrier of the first barrier layer 31, the substrate 10 material will not be etched away when etching the gate insulating layer 30.

[0083] Since the first barrier layer 31 will affect the transmission of light, after the etching of the gate insulating layer 30 is completed, the first barrier layer 31 is etched again, so that the surface of the substrate 10 in the opening area 100 has neither the gate insulating layer 30 nor the first barrier layer 31, which not only reduces the number of light interferences, but also avoids the problem of etching residues of the gate insulating layer 30 or etching of the substrate 10. Since the etching selectivity of the first barrier layer 31 to the substrate 10 is also large, when the first barrier layer 31 is etched, the surface of the substrate 10 can also be ensured to be relatively complete.

[0084] After the etching is completed, the substrate 10 and the film layer structures deposited on the surface of the substrate 10 are cleaned to remove the residual etching products and impurities.

[0085] Combination Figure 6 As shown, in one embodiment of the present invention, the step of removing the gate insulating layer 30 includes:

[0086] providing a first mask;

[0087] S510: Covering the surface of the gate insulating layer 30 with a first mask;

[0088] S520 : using a dry etching method to etch the gate insulating layer 30 formed on the surface of the substrate 10 corresponding to the opening area 100 .

[0089] In this embodiment, although the material of the gate insulating layer 30 has good light transmittance, due to the different materials between different film layers, light will interfere with each other. Therefore, after the gate insulating layer 30 is deposited, it is necessary to remove the gate insulating layer 30 at the opening area 100 corresponding to the substrate 10. The gate insulating layer 30 located in the non-opening area 100 plays an insulating role for the thin film transistor, so it is necessary to retain the gate insulating layer 30 in the non-opening area 100. The specific steps are as follows:

[0090] The window of the first mask plate corresponds to the position of the opening area 100. When the first mask plate is placed on the surface of the gate insulating layer 30, the gate insulating layer 30 in the non-opening area 100 is covered by the first mask plate, and the gate insulating layer 30 in the opening area 100 is exposed from the window of the first mask plate.

[0091] The etching gas is then ionized to form plasma, and the plasma is bombarded on the surface of the first mask plate under the acceleration of the electric field. At this time, the gate insulation layer 30 exposed at the window of the first mask plate is etched away, while the gate insulation layer 30 in the non-opening area 100 is covered by the first mask plate and is retained.

[0092] Since the gate insulating layer 30 is an inorganic non-metallic material, and the display panel generally has high requirements for the dimensional accuracy of the opening area 100, compared with wet etching, dry etching technology can achieve anisotropic etching with high etching accuracy, and can transfer a more refined first mask pattern to the gate insulating layer 30.

[0093] Combination Figure 7 As shown, in one embodiment of the present invention, the step of removing the first barrier layer 31 includes:

[0094] S530: wet-etching the first barrier layer 31 formed on the surface of the substrate 10 corresponding to the opening area 100.

[0095] In this embodiment, after the gate insulating layer 30 in the opening area 100 is dry-etched, the first barrier layer 31 in the opening area 100 needs to be removed to prevent the first barrier layer 31 from affecting the light transmission in the opening area 100. The specific steps are as follows:

[0096] First, a suitable wet etching solution is selected. For transparent conductive materials such as indium tin oxide (ITO) or zinc oxide (ZnO), a diluted acid solution such as phosphoric acid, nitric acid or hydrochloric acid can be used. These solutions can effectively dissolve the first barrier layer 31, while causing less erosion to the substrate 10 and the gate insulating layer 30, thereby improving the etching selectivity.

[0097] The substrate 10 deposited with the first barrier layer 31 is immersed in an etching solution, and the etching time and solution concentration are controlled so that the first barrier layer 31 is completely removed without affecting the substrate 10 and the gate insulating layer 30. When etching the first barrier layer 31, the advantage of wet etching over dry etching is that it has better etching uniformity and can etch a large area in a short time.

[0098] After etching is completed, the substrate 10 is taken out of the solution and thoroughly cleaned to remove residual etching solution and impurities. Deionized water or other suitable cleaning agents can be used during the cleaning process to ensure that the surface is clean and free of contamination.

[0099] Combination Figure 8 As shown, in one embodiment of the present invention, after the step of depositing a barrier material to form a first barrier layer 31, before the step of depositing an insulating material on the surface of the first barrier layer 31 to form a gate insulating layer 30, the step includes:

[0100] providing a second mask;

[0101] S310: Covering the second mask plate on the surface of the first barrier layer 31;

[0102] S320 : etching and removing the portion of the first barrier layer 31 corresponding to the non-opening area 100 .

[0103] In this embodiment, after the deposition of the first barrier layer 31 is completed, although the first barrier layer 31 located in the non-opening area 100 will not affect the display effect of the display panel, in order to achieve a large etching selectivity between the first barrier layer 31 and the gate insulating layer 30 and the substrate 10, when a metal material or a metal oxide (such as indium tin oxide) is selected as the material of the first barrier layer 31, the first barrier layer 31 has a high conductivity, which will cause the metal wiring of the thin film transistor to short-circuit. Therefore, the first barrier layer 31 in the non-opening area 100 needs to be removed before depositing the gate insulating layer 30. The specific steps are as follows:

[0104] The window of the second mask plate corresponds to the position of the non-opening area 100. The second mask plate is covered on the surface of the first barrier layer 31. The first barrier layer 31 in the opening area 100 is covered by the second mask plate, and the first barrier layer 31 in the non-opening area 100 is exposed from the window of the second mask plate.

[0105] Then, dry etching technology is used to bombard the surface of the second mask plate with accelerated plasma. At this time, the first barrier layer 31 exposed at the window of the second mask plate is etched away, while the first barrier layer 31 located in the opening area 100 is covered by the second mask plate and is retained. Therefore, through this manufacturing method, the problem that the first barrier layer 31 may cause a short circuit of the thin film transistor in the non-opening area 100 is solved, and the first barrier layer 31 in the opening area 100 is also retained, so as to play a blocking role for the etching of the gate insulation layer 30 in the opening area 100.

[0106] In other embodiments, a process combining photolithography and etching can also be used to remove the first barrier layer 31 in the non-opening area 100. Specifically, a photoresist layer is coated on the surface of the first barrier layer 31, and then the photoresist layer is exposed and developed to form a photoresist pattern, in which the window corresponds to the non-opening area 100, and the photoresist blocks the opening area 100. Then, a wet etching process is used to etch away the first barrier layer 31 located at the window using the photoresist as an etching stop layer, and then the photoresist layer is removed, thereby achieving the purpose of removing the first barrier layer 31 in the non-opening area 100.

[0107] Combination Fig. 9 As shown, in one embodiment of the present invention, the barrier material is indium tin oxide;

[0108] The step of depositing the barrier material and forming the barrier layer includes:

[0109] S301 : Physical vapor deposition of indium tin oxide is performed on the surface of the gate 21 , the surface of the first data line 22 , and the surface of the substrate 10 corresponding to the opening area 100 , to form a first barrier layer 31 .

[0110] In the present embodiment, indium tin oxide (ITO) is selected as the barrier material because: indium tin oxide has a high etching selectivity with the substrate 10 and the gate insulating layer 30, and can accurately control the etching depth of the gate insulating layer 30. At the same time, the materials of the common electrode 70 and the pixel electrode 90 in the array substrate 1 are generally indium tin oxide, so by selecting the same material, the types of raw materials can be reduced, and the same deposition equipment and process parameters as the common electrode 70 and the pixel electrode 90 can be selected, which reduces the production cost and shortens the research and development cycle.

[0111] In one embodiment of the present invention, the thickness of the first barrier layer 31 is in the range of

[0112] In this embodiment, the thickness range of the first barrier layer 31 is controlled within The reason is that a thicker first barrier layer 31 will increase production time and processing costs, while a thinner thickness will affect the etching barrier effect, and at the same time, it requires a higher process level and cannot ensure the uniformity of the film thickness. Therefore, the first barrier layer 31 within this thickness range is convenient for the processing and molding of the film layer, and ensures the subsequent etching barrier effect.

[0113] Combination Fig.10 As shown, in one embodiment of the present invention, after etching the portion of the second metal layer corresponding to the opening area 100 to form the second data line 43 on the surface of the first data line 22 and forming the semiconductor layer 44, the source 41 and the drain 42 on the surface of the gate insulating layer 30, the following steps are further included:

[0114] S600: etching the gate insulating layer 30 formed on the surface of the first data line 22;

[0115] S700: depositing a metal material on a surface of the gate insulating layer 30 and on a surface of the substrate 10 corresponding to the opening region 100 to form a second metal layer;

[0116] S800 : etching the portion of the second metal layer corresponding to the opening area 100 to form the second data line 43 on the surface of the first data line 22 , and forming the semiconductor layer 44 , the source 41 and the drain 42 on the surface of the gate insulating layer 30 .

[0117] In this embodiment, the step of depositing the second metal layer can be achieved by physical vapor deposition (PVD) or chemical vapor deposition (CVD). For example, PVD technology can be used to control the deposition rate and the thickness of the second metal layer by adjusting parameters such as sputtering power, pressure of the working gas, and deposition time.

[0118] Then, the second metal layer is patterned. Specifically, the second metal layer is etched using a wet etching or dry etching technique to form the required second data line 43, source 41, and drain 42. In this process, a mask plate can be set, and then the mask plate is covered on the surface of the second metal layer, and then the pattern of the mask plate is transferred to the second metal layer by dry etching; or a photoresist etching barrier layer can be formed on the surface of the second metal layer by photolithography and etching processes, and then the second metal layer exposed in the photoresist etching barrier layer window is etched by a wet etching process. The specific steps can refer to the above-mentioned etching steps for the first metal layer, and no further description is given here.

[0119] Since the data line is made of metal, it will block the transmission of light, resulting in a decrease in the aperture ratio of the display panel. Therefore, the width of the data line needs to be designed to be smaller to increase the aperture ratio. Then reducing the width of the data line will increase the impedance of the data line. The larger impedance causes mischarging or insufficient charging of each pixel of the display panel, resulting in poor uniformity of display quality. Therefore, it is necessary to increase the thickness of the data line. The present application etches the gate insulating layer 30 and then deposits the second metal layer on the surface of the first metal layer so that the opening area 100 forms two metal lines superimposed on each other, that is, the second data line 43 covers the first data line 22, thereby increasing the overall thickness of the data line and improving the above-mentioned problem of poor uniformity of display quality.

[0120] After the second metal layer is patterned, a source 41 and a drain 42 are formed in the non-opening area 100. The source 41 and the drain 42 are respectively connected to the semiconductor layer 44 (the semiconductor layer 44 is formed on the surface of the gate insulating layer 30 corresponding to the gate 21 before the second metal layer is deposited), and are responsible for transmitting and receiving current signals.

[0121] Combination Fig.11 As shown, in one embodiment of the present invention, after etching the portion of the second metal layer corresponding to the opening area 100 to form the second data line 43 on the surface of the first data line 22 and forming the semiconductor layer 44, the source 41 and the drain 42 on the surface of the gate insulating layer 30, the following steps are further included:

[0122] S900: depositing a barrier material on a surface of the second metal layer, a surface of the gate insulating layer 30 , and a surface of the substrate 10 corresponding to the opening region 100 to form a second barrier layer;

[0123] S1000: depositing an insulating material on the surface of the second barrier layer to form a first insulating layer 50;

[0124] S1100 : sequentially etching the first insulating layer 50 and the second barrier layer of the substrate 10 corresponding to the opening area 100 .

[0125] In this embodiment, the material of the first insulating layer 50 is the same as or similar to that of the gate insulating layer 30, such as SiNx (silicon nitride) or SiOx (silicon oxide). Therefore, in order to reduce the number of interferences caused by light passing through the array substrate 1, the first insulating layer 50 located in the opening area 100 needs to be etched away to further improve the brightness uniformity and color consistency of the display panel. When etching the first insulating layer 50, since the etching selectivity between the first insulating layer 50 and the substrate 10 is relatively low, it is still easy to have the problem of etching residues of the first insulating layer 50 or etching of the substrate 10. Therefore, in this embodiment, a physical vapor deposition (PVD) or chemical vapor deposition (CVD) technology is used to deposit a barrier material, such as indium tin oxide (ITO) or other transparent conductive materials, on the surface of the second data line 43 and the substrate 10 in the opening area 100, and form a second barrier layer. Then, an insulating material is deposited on the surface of the second barrier layer to form the first insulating layer 50.

[0126] Since the second barrier layer has a large etching selectivity ratio with the first insulating layer 50, the second barrier layer is used as an etching stop layer, and when etching the first insulating layer 50 in the opening area 100, the problem of the first insulating layer 50 being etched with residue or the substrate 10 being etched can be effectively solved. Since the second barrier layer affects the transmission of light, after the first insulating layer 50 is etched, the second barrier layer in the opening area 100 is etched to ensure the display effect of the display panel.

[0127] Combination Fig.12 As shown, in one embodiment of the present invention, the step of depositing a barrier material on the surface of the second metal layer, the surface of the gate insulating layer 30, and the surface of the substrate 10 corresponding to the opening area 100 to form a second barrier layer includes:

[0128] providing a third mask plate;

[0129] S910: depositing a barrier material on the surface of the second metal layer, the surface of the gate insulating layer 30, and the surface of the substrate 10 corresponding to the opening area 100 to form a second barrier layer.

[0130] S920: placing a third mask plate on the surface of the second barrier layer;

[0131] S930: etching the portion of the second barrier layer corresponding to the non-opening area 100 .

[0132] In this embodiment, after the deposition of the second barrier layer is completed, although the second barrier layer located in the non-opening area 100 will not affect the display effect of the display panel, in order to achieve a larger etching selectivity between the second barrier layer and the gate insulating layer 30 and the substrate 10, when a metal material or a metal oxide (such as indium tin oxide) is selected as the material of the second barrier layer, the second barrier layer has a higher conductivity, which will cause the metal wiring of the thin film transistor to short-circuit. Therefore, the second barrier layer in the non-opening area 100 needs to be removed before depositing the first insulating layer 50. The specific steps are as follows:

[0133] The window of the third mask plate corresponds to the position of the non-opening area 100. The third mask plate is covered on the surface of the second barrier layer. At this time, the second barrier layer of the opening area 100 is covered by the third mask plate, and the second barrier layer of the non-opening area 100 is exposed from the window of the third mask plate.

[0134] Then, the second barrier layer in the non-opening area 100 is further etched to remove the non-opening second barrier layer and retain the second barrier layer in the opening area 100. This manufacturing method solves the problem that the second barrier layer may cause the thin film transistor in the non-opening area 100 to short-circuit, and at the same time, the second barrier layer retained in the opening area 100 plays a blocking role in the etching of the first insulating layer 50 in the opening area 100.

[0135] Finally, a planar layer 60 is formed on the surface of the first insulating layer 50 ; a common electrode 70 , a second insulating layer 80 and a pixel electrode 90 are sequentially formed on the surface of the planar layer 60 .

[0136] The present invention further provides an array substrate 1, which is manufactured by the above manufacturing method. The specific steps of the manufacturing method can refer to the introduction in the above embodiment, and no further description is given here.

[0137] Among them, the array substrate 1 includes a substrate 10, a thin film transistor and a data line; the thin film transistor is arranged on the surface of the substrate 10 corresponding to the non-opening area 100, and the thin film transistor includes a gate 21, a gate insulating layer 30, a semiconductor layer 44, a drain 42 and a source 41 stacked in sequence on the surface of the substrate 10; the data line is arranged on the surface corresponding to the opening area 100 and is electrically connected to the thin film transistor.

[0138] In this embodiment, the gate 21 is used to receive a scanning signal and control the opening and closing of the thin film transistor; the gate insulating layer 30 isolates the gate 21 from the semiconductor layer 44, the gate 21 from the drain 42 and the source 41 to prevent short circuits between them; the semiconductor layer 44 is IGZO oxide or other semiconductor materials, which is used to form the channel region of the thin film transistor; the source 41 and the drain 42 are respectively connected to the data line and the pixel electrode 90, responsible for transmitting and receiving current signals. The data line is electrically connected to the thin film transistor to transmit the image signal and the voltage signal to the pixel unit. The thin film transistor of this array substrate 1 is set in the non-opening area 100 to prevent the thin film transistor from interfering with the transmission of light.

[0139] In addition, the gate insulating layer 30 located in the opening area 100 is removed so that the gate insulating layer 30 is only arranged in the non-opening area 100, thereby reducing the number of film layers in the opening area 100 and reducing the number of interferences that occur when light passes through the array substrate 1, thereby improving the brightness uniformity and color consistency of the display panel.

[0140] In another embodiment, the data line includes a first data line 22 and a second data line 43, wherein the first data line 22 is disposed on the surface of the substrate 10, and the second data line 43 is disposed on the surface of the first data line 22. The first data line 22 and the second data line 43 are sequentially formed through two deposition processes, wherein the first data line 22 is disposed on the surface of the substrate 10 and is a metal of the same layer as the gate 21, and the second data line 43 is disposed on the surface of the first data line 22 and is a metal wiring of the same layer as the drain 42 and the source 41. This design can realize the formation of two or more metal wirings by using one deposition and etching process, thereby reducing the processing cost.

[0141] Since the metal routing will affect the aperture ratio, the line width of the data line needs to be designed to be narrower, which leads to an increase in the resistance of the data line. The resistance can be reduced by increasing the metal film thickness of the routing, but since the data line and the gate 21 are the same layer of metal, increasing the thickness of the data line will also increase the overall thickness of the first metal layer, which will lead to an increase in production costs. Therefore, the present invention adopts a double-layer metal routing design of the first data line 22 and the second data line 43. This double-layer metal routing structure can not only reduce the impedance of the data line, thereby improving the mischarging, insufficient charging and other quality problems caused by excessive routing impedance, but also the setting of the second data line 43 does not increase the thickness of the first metal layer, which can reduce production costs.

[0142] Furthermore, the first data line 22 is located within the orthographic projection of the second data line 43 on the first data line 22 , and both sides of the second data line 43 in the width direction extend along both side surfaces of the first data line 22 in the width direction and are both connected to the substrate 10 .

[0143] The cross section of the first data line 22 is a trapezoid, and the line width of the first data line 22 on the side facing away from the substrate 10 is smaller than the line width on the side facing the substrate 10, and the angle between the two side surfaces of the first data line 22 and the substrate 10 is an acute angle. The width of the second data line 43 is greater than the width of the first data line 22, and the cross section of the second data line 43 is stepped and spans the surface of the first data line 22. Since the thicker data line is steeper on both sides along the width direction, cracks or gaps are prone to occur when depositing other film layers. The structural design of the present application not only increases the overall thickness of the data line, but also reduces the overall slope of the data line, so as to facilitate the deposition of other film layers on the surface of the data line, thereby improving the reliability of the array substrate 1.

[0144] The present invention also proposes a display panel, which includes an array substrate 1, a liquid crystal layer and a color film substrate. The specific structure of the array substrate 1 refers to the above-mentioned embodiment. Since the display panel adopts all the technical solutions of all the embodiments of the above-mentioned array substrate 1, it has at least all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here one by one.

[0145] The array substrate 1 and the color filter substrate are combined to form a liquid crystal box. The liquid crystal layer is filled in the liquid crystal box and is located between the array substrate 1 and the color filter substrate. The color filter substrate includes a color filter and a glass substrate. The color filter includes filters of three colors: red, green, and blue, for realizing color display. The liquid crystal layer is arranged between the array substrate 1 and the color filter substrate. The liquid crystal molecules in the liquid crystal layer can change the arrangement direction under the action of the electric field, thereby controlling the transmittance of light. Since the present application improves the etching process of the gate insulating layer 30 and the first insulating layer 50 of the array substrate 1, the etching uniformity and accuracy are improved, thereby improving the display effect of the display panel.

[0146] The present invention also proposes a display device, which includes a backlight module and a display panel. The specific structure of the display panel refers to the above-mentioned embodiment. Since the display device adopts all the technical solutions of all the above-mentioned display panel embodiments, it at least has all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here one by one.

[0147] The display device can be a display panel arranged on the light-emitting side of the backlight module, and the light emitted by the backlight module passes through the array substrate 1, the liquid crystal layer, and the color film substrate in sequence to display the picture. The display device can be various types of electronic devices, such as televisions, computer monitors, mobile phones, and tablet computer screens. Since the present application improves the etching process of the gate insulating layer 30 and the first insulating layer 50 of the array substrate 1, the etching uniformity and accuracy are improved, thereby improving the display effect of the display panel.

[0148] The above description is only an exemplary embodiment of the present invention, and does not limit the patent scope of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the technical concept of the present invention, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A method for manufacturing an array substrate, characterized in that: Includes steps: providing a substrate; Depositing a metal material on the surface of the substrate to form a first metal layer; Etching the first metal layer to form a first data line and a gate on the surface of the substrate corresponding to the non-opening area; Depositing a barrier material on the surface of the gate, the first data line and the substrate to form a first barrier layer; Depositing an insulating material on a surface of the first barrier layer to form a gate insulating layer; The gate insulating layer and the first barrier layer formed on the surface of the substrate corresponding to the opening area are removed in sequence.

2. The method for manufacturing an array substrate according to claim 1, wherein: The step of removing the gate insulating layer comprises: providing a first mask; Covering the first mask plate on the surface of the gate insulation layer; The gate insulating layer formed on the surface of the substrate corresponding to the opening area is dry-etched.

3. The method for manufacturing an array substrate according to claim 2, wherein: The step of removing the first barrier layer comprises: The first barrier layer formed on the surface of the substrate corresponding to the opening area is wet-etched.

4. The method for manufacturing an array substrate according to any one of claims 1 to 3, characterized in that: After the step of depositing a barrier material to form a first barrier layer, and before the step of depositing an insulating material on a surface of the first barrier layer to form a gate insulating layer, the step includes: providing a second mask; Covering the second mask plate on the surface of the first barrier layer; The portion of the first barrier layer corresponding to the non-opening area is etched and removed.

5. The method for manufacturing an array substrate according to any one of claims 1 to 3, characterized in that: The barrier material is indium tin oxide; The step of depositing a barrier material to form a first barrier layer comprises: The indium tin oxide is physically vapor deposited on the surface of the gate, the surface of the first data line, and the surface of the substrate corresponding to the opening area to form a first barrier layer.

6. The method for manufacturing an array substrate according to claim 5, wherein: The thickness of the first barrier layer is in the range of 7. The method for manufacturing an array substrate according to any one of claims 1 to 3, characterized in that: After the step of etching the first barrier layer, the step further includes: The gate insulating layer formed by etching the surface of the first data line; Depositing the metal material on a surface of the gate insulating layer and on a surface of the substrate corresponding to the opening region to form a second metal layer; The second metal layer is etched at a portion corresponding to the opening area to form a second data line on a surface of the first data line, and a semiconductor layer, a source electrode, and a drain electrode are formed on a surface of the gate insulating layer.

8. The method for manufacturing an array substrate according to claim 7, wherein: After the step of etching the portion of the second metal layer corresponding to the opening area to form a second data line on the surface of the first data line, and forming a semiconductor layer, a source electrode and a drain electrode on the surface of the gate insulating layer, the step further includes: Depositing the barrier material on a surface of the second metal layer, a surface of the gate insulating layer, and a surface of the substrate corresponding to the opening area to form a second barrier layer; Depositing the insulating material on the surface of the second barrier layer to form a first insulating layer; The first insulating layer and the second barrier layer in the substrate corresponding to the opening area are etched in sequence.

9. The method for manufacturing an array substrate according to claim 8, wherein: The step of depositing a barrier material on the surface of the second metal layer, the surface of the gate insulating layer, and the surface of the substrate corresponding to the opening area to form a second barrier layer includes: providing a third mask plate; Depositing the barrier material on the surface of the second metal layer, the surface of the gate insulating layer, and the surface of the substrate corresponding to the opening area to form the second barrier layer, Covering the third mask plate on the surface of the second barrier layer; The portion of the second barrier layer corresponding to the non-opening area is etched.

10. A display panel, characterized in that: The display panel includes an array substrate, a color film substrate and a liquid crystal layer manufactured by the array substrate manufacturing method described in any one of claims 1 to 9. The array substrate and the color film substrate are combined to form a liquid crystal box. The liquid crystal layer is filled in the liquid crystal box and is located between the array substrate and the color film substrate.

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