Array substrate and display panel

Abstract

This application provides an array substrate and a display panel. The array substrate has a display area and includes a substrate, a first active structure, a first gate, a first source, a passivation layer, and a first drain. The first active structure includes a semiconductor layer and a conductor layer. The conductor layer is disposed on the side of the semiconductor layer near the substrate and has an opening. At least a portion of the semiconductor layer is disposed within the opening. By controlling the width of this opening, an ultra-short channel effect for thin-film transistors can be achieved, overcoming the limitation of existing array substrate thin-film transistor device size due to photolithography processes. This reduces device size while increasing current throughput, meeting the requirements for high pixel density.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to an array substrate and a display panel. Background Technology

[0002] Various electronic devices requiring small displays, such as Virtual Reality (VR) devices and Augmented Reality (AR) devices, are emerging, with portable mobile display devices being particularly widely used. Because these mobile display devices require both high resolution and miniaturization, reducing power consumption while increasing the integration density of the thin-film transistors (TFTs) that make up the subpixels has become a crucial factor.

[0003] However, as the size of thin-film transistors (TFTs) decreases, their size is determined and limited by the precision of the exposure machine. Furthermore, smaller channels make it difficult to stabilize switching characteristics, leading to increased leakage current. Existing short-channel devices are limited by the process precision of current high-precision exposure machines, with a length of approximately 2–3 micrometers. This length corresponds to a very large exposure volume, further limiting the size reduction and making it difficult to meet the device size requirements for high pixel density. Summary of the Invention

[0004] This application provides an array substrate and a display panel that can achieve an ultra-short channel effect for thin-film transistors in the display area, thereby reducing device size while improving current carrying capacity and meeting the requirements of high pixel density. In addition, the array substrate and display panel provided by this application can also prevent current conduction between the source and drain.

[0005] This application provides an array substrate, which includes a display area, and the array substrate includes:

[0006] substrate;

[0007] A first active structure is disposed on the substrate and located in the display area. The first active structure includes a semiconductor layer and a conductor layer. The conductor layer is disposed on the side of the semiconductor layer close to the substrate. The conductor layer has an opening, and at least a portion of the semiconductor layer is disposed within the opening.

[0008] A first gate is disposed on the substrate and located in the display area;

[0009] The first source electrode is disposed on the first active structure and located in the display area, and is connected to the first active structure;

[0010] A passivation layer is disposed on the side of the first source electrode away from the substrate;

[0011] The first drain is disposed on the passivation layer, located in the display area, and connected to the first active structure.

[0012] Optionally, in some embodiments of this application, the material of the first drain electrode is a transparent conductive material.

[0013] Optionally, in some embodiments of this application, the semiconductor layer is provided with a first via and a second via, the first source is connected to the conductor layer through the first via, and the first drain is connected to the conductor layer through the second via.

[0014] Optionally, in some embodiments of this application, the conductor layer includes a first conductor portion and a second conductor portion connected together. The first conductor portion is disposed on the side of the second conductor portion near the opening. The semiconductor layer fills the opening and covers the side of the first conductor portion away from the substrate. The first source and the first drain are respectively connected to the second conductor portion.

[0015] Optionally, in some embodiments of this application, the semiconductor layer includes a channel region and a doped region, the doped region being located on both sides of the channel region, the channel region covering the opening, the doped region being located on the side of the semiconductor layer away from the substrate, and the first source and the first drain being connected to the doped region respectively.

[0016] Optionally, in some embodiments of this application, a first gate insulating layer is disposed on the side of the substrate near the first active structure; a light-shielding layer is disposed on the side of the first gate insulating layer away from the substrate, and the orthographic projection of the opening on the substrate is located within the orthographic projection of the light-shielding layer on the substrate; a second gate insulating layer is disposed on the side of the substrate light-shielding layer away from the substrate, the conductor layer is disposed on the side of the second gate insulating layer away from the substrate, and the semiconductor layer is disposed on the side of the conductor layer away from the second gate insulating layer; a third gate insulating layer is disposed on the side of the first active structure away from the substrate, and the first gate is located on the side of the third gate insulating layer away from the substrate; an interlayer dielectric layer is disposed on the side of the first gate away from the substrate, a third via penetrates the interlayer dielectric layer and the third gate insulating layer, the first source is disposed on the interlayer dielectric layer and connected to the first active structure through the third via; a fourth via penetrates the passivation layer, the interlayer dielectric layer and the third gate insulating layer, and the first drain is connected to the first drain through the fourth via.

[0017] Optionally, in some embodiments of this application, the light-shielding layer is reused as a second gate.

[0018] Optionally, in some embodiments of this application, the array substrate further includes a non-display area located on at least one side of the display area. The array substrate further includes: a second active structure disposed on the substrate and located in the non-display area; a third gate located in the non-display area and made of the same layer and material as the light-shielding layer; a second source and a second drain located in the non-display area, the second source and the second drain being respectively connected to the second active structure, and the second source and the second drain being made of the same layer and material as the first gate.

[0019] Optionally, in some embodiments of this application, the semiconductor layer is a metal oxide semiconductor material, and the second active structure is a polycrystalline silicon semiconductor material.

[0020] This application also provides a display panel, including the array substrate described in any of the above embodiments.

[0021] The beneficial effects of this application are as follows: The first active structure of the display area of ​​this application includes a semiconductor layer and a conductor layer. At least a portion of the semiconductor layer is disposed in the opening of the conductor layer to form a channel. The length of the channel is defined by the width of the opening, thereby obtaining a thin film transistor with an ultra-short channel. This reduces the size of the device to meet the requirements of high display density, and at the same time, it can improve the current carrying capacity of the device. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the first film layer structure of the array substrate provided in the first embodiment of this application.

[0023] Figure 2 This is a schematic diagram of a second film layer structure of an array substrate provided in a second embodiment of this application.

[0024] Figure 3 This is a schematic diagram of the third film layer structure of the array substrate provided in the third embodiment of this application.

[0025] Figure 4 This is a schematic diagram of the fourth film layer structure of the array substrate provided in the fourth embodiment of this application.

[0026] Figure 5 This is a schematic diagram of the fifth film layer structure of the array substrate provided in the fifth embodiment of this application.

[0027] Figure 6 This is a schematic diagram of the sixth film layer structure of the array substrate provided in the sixth embodiment of this application.

[0028] Figure 7 A flowchart illustrating a method for fabricating an array substrate according to an embodiment of this application.

[0029] Figures 8-19This is a schematic diagram illustrating a method for fabricating an array substrate according to an embodiment of this application. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0031] The terms "first," "second," etc., used in this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or modules is not limited to the listed steps or modules, but may optionally include steps or modules not listed, or may optionally include other steps or modules inherent to these processes, methods, products, or devices.

[0032] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand, explicitly and implicitly, that the embodiments described herein can be combined with other embodiments. Furthermore, it should be noted that the accompanying drawings only provide structures closely related to this application, omitting some details less relevant to the invention. The purpose is to simplify the drawings and make the inventive points clear at a glance, not to indicate that the actual device is identical to the accompanying drawings. Figure 1 It is identical, but this is not a limitation of the actual device.

[0033] This application provides an array substrate including a display area. The array substrate includes a substrate, a first active structure, a first gate, a first source, a passivation layer, and a first drain. The passivation layer is disposed on the side of the first source away from the substrate, and the first drain is disposed on the passivation layer. The source and drain are separated to prevent current conduction. The first active structure is disposed on the substrate and located in the display area. The first active structure includes a semiconductor layer and a conductor layer. The conductor layer is disposed on the side of the semiconductor layer closest to the substrate and has an opening. A portion of the semiconductor layer is disposed within this opening. The width of this opening defines the channel length, resulting in a thin-film transistor with an ultra-short channel. This reduces the device size to meet the requirements of high pixel density and also improves the device's current carrying capacity.

[0034] The array substrate provided in this application will be described in detail below through specific embodiments.

[0035] Please see Figure 1 , Figure 1 This is a schematic diagram of a first type of film layer structure for an array substrate provided in an embodiment of this application. The array substrate provided in the first embodiment of this application has a display area 110 and a non-display area 120, including a substrate 100, a buffer layer 35, a second active structure 26, a first gate insulating layer 18, a third gate 27, a light-shielding layer 25, a second gate insulating layer 17, a first active structure 11, a third gate insulating layer 16, a second source 28, a second drain 29, a first gate 15, an interlayer dielectric layer 19, a third via 23, a first source 13, a fourth via 24, a first drain 14, a planarization layer 36, and a pixel electrode 30. It is understood that the display area 110 is the area used for displaying images, and the non-display area 120 may be a gate driver on array (GOA) area or a demultiplexer (Demux) area, not used for displaying images.

[0036] In this embodiment, a buffer layer 35 is disposed on the substrate 100, and a second active structure 26 is disposed on the buffer layer 35 and located in the non-display area 120. Furthermore, the second active structure is made of low-temperature polycrystalline silicon. Due to the high mobility of low-temperature polycrystalline silicon, the thin-film transistor in the non-display area 120 has a better driving effect. A first gate insulating layer 18 is disposed on the second active structure 26 and covers both the second active structure 26 and the buffer layer 35. A third gate 27 and a light-shielding layer 25 are both disposed on the first gate insulating layer 18, and the third gate 27 and the light-shielding layer 25 are made of the same material. The third gate 27 is located in the non-display area 120, and the light-shielding layer 25 is located in the display area 110. The third gate 27 and the light-shielding layer 25 can be formed using the same patterning process, saving on photomasks and reducing the thickness of the array substrate.

[0037] Optionally, the material of the buffer layer 35 can be SiN. x or SiO x The material of the first gate insulating layer 18 includes SiO2. x or SiN x or SiN x / SiO x or SiNO x The materials of the third gate 27 and the light-shielding layer 25 include Mo or Mo / Al or Mo / Cu or MoTi / Cu or MoTi / Cu / MoTi or Ti / Al / Ti or Ti / Cu / Ti or Mo / Cu / IZO or IZO / Cu / IZO or Mo / Cu / ITO.

[0038] The second gate insulating layer 17 is disposed on the third gate 27 and the light-shielding layer 25 and covers the third gate 27, the light-shielding layer 25 and the first gate insulating layer 18. The first active structure 11 is disposed on the second gate insulating layer 17 and is located in the display area 110. The first active structure 11 includes a semiconductor layer 11a and a conductor layer 11b. The semiconductor layer 11a is disposed on the conductor layer 11b. The conductor layer 11b has an opening 12. A portion of the semiconductor layer 11a is disposed in the opening 12 to form a channel 31. In the first embodiment of this application, the width d of the opening 12 is used to limit the length of the channel 31. The width d of the opening 12 is controlled within the range of 0.1 to 1.3 micrometers, that is, the length of the channel 31 can reach the range of 0.1 to 1.3 micrometers. Compared with the existing short-channel thin-film transistor channel length of about 2 to 3 micrometers, the channel length provided by the first embodiment of this application is greatly reduced, which can achieve the effect of ultra-short channel, further reduce the size of thin-film transistor devices, and improve the current carrying capacity of thin-film transistors, meeting the requirements for smaller device size of thin-film transistors under high pixel density. Furthermore, in the first embodiment of this application, the semiconductor layer 11a is selected from metal oxides, including indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium zinc tin oxide (IZTO), indium gallium zinc tin oxide (IGZTO), etc., which have good uniformity, low leakage current, and high transmittance. In addition, the orthographic projection of the opening 12 on the substrate 100 is located within the orthographic projection of the light-shielding layer 25 on the substrate 100, that is, the light-shielding layer 25 can block the channel 31. Therefore, the array substrate provided in the first embodiment of this application can also prevent the channel 31 from being affected by light, thereby improving the stability and reliability of the device.

[0039] Optionally, the material of the second gate insulating layer 17 includes SiO2. x or SiN x or SiN x / SiO x or SiNO x The conductor layer 11b material includes Al, Mo, Ti, Si, Cu, amorphous metal oxides, amorphous metal elements, and amorphous metal alloys.

[0040] The third gate insulating layer 16 is disposed on the semiconductor layer 11a. The first gate 15, the second source 28, and the second drain 29 are disposed on the same film layer using the same material, all located on the side of the third gate insulating layer away from the substrate. Furthermore, the second source 28 and the second drain 29 are located in the non-display area 120, and the first gate 15 is located in the display area 110. It is understood that in this embodiment, the first gate 15 is located above the semiconductor layer 11a, which allows for a larger light-transmitting area in the display area, thereby increasing the aperture ratio. Furthermore, in the first embodiment of this application, the second source 28, the second drain 29, and the first gate 15 are formed using the same patterning process, saving on photomasks while reducing the thickness of the array substrate. Optionally, the material of the third gate insulating layer includes SiO2. x or SiN x or SiN x / SiO x or SiNO x The film materials of the second source 28, the second drain 29, and the first gate 15 include Mo or Mo / Al or Mo / Cu or MoTi / Cu or MoTi / Cu / MoTi or Ti / Al / Ti or Ti / Cu / Ti or Mo / Cu / IZO or IZO / Cu / IZO or Mo / Cu / ITO.

[0041] An interlayer dielectric layer 19 is disposed on the first gate 15 and covers the first gate 15, the second source 28, and the second drain 29. A third via 23 is disposed on the interlayer dielectric layer 19 and the third gate insulating layer 16. A first source 13 is disposed on the interlayer dielectric layer 19, and a portion of the first source 13 fills the third via 23 and is connected to the first active structure 11. A passivation layer 20 is disposed on the first source 13 and covers the first source 13 and the interlayer dielectric layer 19. A fourth via is disposed on the passivation layer 20, the interlayer dielectric layer 19, and the third gate insulating layer 16. A first drain 14 is disposed on the passivation layer 20, and a portion of the first drain 14 is connected to the first active structure 11 through the fourth via 24. A planarization layer 36 is disposed on the first drain 14 and fills the fourth via 24. A pixel electrode 30 is disposed on the planarization layer 36 and is connected to the pixel electrode 30. It is understood that, in terms of film structure, the first source 13 and the first drain 14 are not disposed in the same layer in the first embodiment of this application, which can prevent current conduction between them. Furthermore, the first drain 14 adopts a transparent conductive material, including indium tin oxide (ITO), indium zinc oxide (IZO), a transparent conductive film structure composed of two layers of indium tin oxide (ITO) and one layer of silver (Ag) (ITO / Ag / ITO), a transparent conductive film structure composed of two layers of indium zinc oxide (IZO) and one layer of silver (Ag) (IZO / Ag / IZO), and other transparent amorphous metal oxides and crystalline metal oxides, which can avoid the reduction of aperture ratio caused by drain metal and improve the display effect.

[0042] Optionally, the interlayer dielectric layer 19 may be made of SiO2. x or Al2O3 / SiN x / SiO x or SiO x / SiN x / SiO x The first source electrode 13 film material includes Mo or Mo / Al or Mo / Cu or MoTi / Cu or MoTi / Cu / MoTi or Ti / Al / Ti or Ti / Cu / Ti or Mo / Cu / IZO or IZO / Cu / IZO or Mo / Cu / ITO, and the passivation layer 20 film material includes SiO x or SiN x or Al2O3 or SiO x / SiN x or Al2O3 / SiN x / SiO x or SiO x / SiN x / SiO xThe planarization layer 36 film material includes organic photoresist or SiO2. x or SiN x or Al2O3 or SiO x / SiN x or Al2O3 / SiN x / SiO x or SiO x / SiN x / SiO x The material of the pixel electrode 30 may include ITO, IZO, ITO / Ag / ITO, or IZO / Ag / IZO, etc.

[0043] like Figure 2 As shown, in the second embodiment of this application, the difference from the first embodiment is that the semiconductor layer 11a is provided with a first via 21 and a second via 22. The first source 13 is connected to the conductor layer 11b through the first via 21, and the first drain 14 is connected to the conductor layer 11b through the second via 22. It is not necessary to conduct the contact area between the semiconductor layer 11a and the first source 13 and the first drain, which can simplify the manufacturing process and reduce costs.

[0044] like Figure 3 As shown, in the third embodiment of this application, the semiconductor layer 11a includes a channel region 31 and a doped region 32. The doped region 32 is located on the side of the semiconductor layer 11a away from the substrate and on both sides of the channel region 31. The channel region 31 covers the opening 12. The difference between this embodiment and the first and second embodiments is that the first source 13 and the first drain 14 are connected to the doped region 32 on the semiconductor layer 11a, eliminating the need for vias on the semiconductor layer 11a and avoiding plasma contamination caused by openings in the semiconductor layer.

[0045] In the fourth embodiment of this application, such as Figure 4 As shown, the conductor layer 11b includes a first conductor portion 33 and a second conductor portion 34 connected together. The first conductor portion 33 is disposed on the side of the second conductor portion 34 near the opening 12. The semiconductor layer 11a fills the opening 12 and covers the first conductor portion 33. The first source 13 and the first drain 14 are connected to the second conductor portion 34. It can be understood that the difference between this embodiment and the first, second and third embodiments described above is that this embodiment does not require the connection area between the semiconductor layer 11a and the first source 13 and the first drain 14 to be conductord, which simplifies the process and reduces costs. At the same time, in this embodiment, the first source 13 and the first drain 14 do not need to be connected to the second conductor portion 33 through vias provided on the semiconductor layer 11a, which can avoid plasma contamination caused by openings in the semiconductor layer 11a and reduce diffusion to both sides of the channel 31 due to excessively high carrier concentration.

[0046] like Figure 5 As shown, in the fifth embodiment of this application, the light-shielding layer 25 located in the display area 110 is reused as the second gate 36. That is, the difference between this embodiment and the first embodiment is that the thin film transistor in the display area of ​​this embodiment has a dual-gate structure, which has a faster switching speed and a higher current density, and can improve the device performance of the thin film transistor.

[0047] In the sixth embodiment of this application, as Figure 6 As shown, the display area 110 no longer has a light-shielding layer. The first gate 37 and the third gate 27 are set in the same layer and with the same material, and are no longer set in the same layer as the second source 28 and the second drain 29. That is, the difference between this embodiment and the first embodiment is that the thin film transistor of the display area 110 in this embodiment has a bottom gate structure, which makes the manufacturing process more efficient and helps to reduce production costs.

[0048] like Figures 8 to 19 As shown, the method for fabricating an array substrate provided in this application includes the following steps:

[0049] S10. Provide a substrate 100, which may be a glass substrate or a polyimide flexible substrate.

[0050] S20. A buffer layer 35 and a second active structure 26 are formed on the substrate.

[0051] S30. A first gate insulating layer 18, a third gate 27, and a light-shielding layer 25 are formed on the side of the buffer layer 35 and the second active structure 26 away from the substrate.

[0052] S40, a second gate insulating layer 17 and a conductor layer 11b are formed on the side away from the substrate on the first gate insulating layer 18, the third gate 27 and the light-shielding layer 25, and the conductor layer 11b is patterned to form an opening 12.

[0053] S50. A semiconductor layer 11a is formed on the side of the conductor layer 11b away from the substrate. The semiconductor layer fills the portion of the opening 12 to form a channel 31. The semiconductor layer 11a and the conductor layer 11b together constitute the first active structure 11.

[0054] S60. A third gate insulating layer 16 is formed on the side of the semiconductor layer 11a away from the substrate. The third gate insulating layer 16 covers the semiconductor layer 11a and the second gate insulating layer 17. The third gate insulating layer 16, the second gate insulating layer 17, and the third gate insulating layer 18 are patterned.

[0055] S70, a second source 28, a second drain 29, and a first gate 15 are formed on the side of the third gate insulating layer 16 away from the substrate.

[0056] S80, an interlayer dielectric layer 19 is formed on the side of the second source 28, the second drain 29 and the first gate 15 away from the substrate, and the interlayer dielectric layer 19 and the third gate insulating layer 16 are patterned to form a third via 23.

[0057] S90. A first source electrode 13 is formed on the side of the interlayer dielectric layer 19 away from the substrate. A portion of the first source electrode 13 is filled in the third via 23 and connected to the semiconductor layer 11a of the first active structure 11.

[0058] S100, a passivation layer 20 is formed on the side of the first source electrode 13 away from the substrate. The passivation layer 20 covers the first source electrode 13 and the interlayer dielectric layer 19. The passivation layer 20, the interlayer dielectric layer 19 and the third gate insulating layer are patterned to form a fourth via 24.

[0059] S110, A first drain 14 is formed on the side of the passivation layer 20 away from the substrate, and a portion of the first drain 14 is connected to the semiconductor layer 11a in the first active structure 11 through a fourth via 24.

[0060] S120, a planarization layer 36 is formed on the side of the first drain 14 away from the substrate. The planarization layer 36 covers the first drain 14 and the passivation layer 20, and fills the fourth via 24.

[0061] S130, A display electrode 30 is formed on the side of the planarization layer 36 away from the substrate and is in contact with the first drain electrode 14.

[0062] In summary, the embodiments of this application provide an opening 12 in the conductor layer 11b, and a portion of the semiconductor layer 11a is disposed within the opening 12 to form a channel 31. By controlling the width d of the opening 12, a shorter channel 31 can be obtained, resulting in a thin-film transistor with an ultra-short channel. This reduces the size of the TFT device, meets the needs of high-density pixels, and effectively improves the current carrying capacity of the thin-film transistor.

[0063] In addition, this application embodiment also provides a display panel, which includes any of the array substrates described in the above embodiments. The display panel in this application embodiment can be a liquid crystal display panel or an organic light-emitting display panel.

[0064] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0065] The array substrate and display panel provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An array substrate, characterized in that, The array substrate includes a display area, and the array substrate includes: substrate; A first active structure is disposed on the substrate and located in the display area. The first active structure includes a semiconductor layer and a conductor layer. The conductor layer is disposed on the side of the semiconductor layer near the substrate. The conductor layer has an opening, and at least a portion of the semiconductor layer is disposed within the opening. A first gate is disposed on the substrate and located in the display area; The first source electrode is disposed on the first active structure and located in the display area, and is connected to the first active structure; A passivation layer is disposed on the side of the first source electrode away from the substrate; The first drain is disposed on the passivation layer, located in the display area, and connected to the first active structure; The conductor layer includes a first conductor portion and a second conductor portion connected together. The first conductor portion is disposed on the side of the second conductor portion near the opening. The semiconductor layer fills the opening and covers the side of the first conductor portion away from the substrate. The first source and the first drain are respectively connected to the second conductor portion.

2. The array substrate according to claim 1, characterized in that, The first drain electrode is made of a transparent conductive material.

3. The array substrate according to claim 1, characterized in that, The semiconductor layer is provided with a first via and a second via. The first source is connected to the conductor layer through the first via, and the first drain is connected to the conductor layer through the second via.

4. The array substrate according to claim 1, characterized in that, The semiconductor layer includes a channel region and a doped region. The doped region is located on both sides of the channel region. The channel region covers the opening. The doped region is located on the side of the semiconductor layer away from the substrate. The first source and the first drain are respectively connected to the doped region.

5. The array substrate according to claim 1, characterized in that, The array substrate further includes: A first gate insulating layer is disposed on the side of the substrate near the first active structure; A light-shielding layer is disposed on the side of the first gate insulating layer away from the substrate, and the orthographic projection of the opening on the substrate is located within the orthographic projection of the light-shielding layer on the substrate; A second gate insulating layer is disposed on the side of the substrate light-shielding layer away from the substrate, a conductor layer is disposed on the side of the second gate insulating layer away from the substrate, and a semiconductor layer is disposed on the side of the conductor layer away from the second gate insulating layer; A third gate insulating layer is disposed on the side of the first active structure away from the substrate, and the first gate is located on the side of the third gate insulating layer away from the substrate; An interlayer dielectric layer is disposed on the side of the first gate away from the substrate. A third via penetrates the interlayer dielectric layer and the third gate insulating layer. The first source is disposed on the interlayer dielectric layer and connected to the first active structure through the third via. The fourth via penetrates the passivation layer, the interlayer dielectric layer, and the third gate insulating layer, and the first drain is connected to the first drain through the fourth via.

6. The array substrate according to claim 5, characterized in that, The light-shielding layer is reused as a second gate.

7. The array substrate according to claim 5, characterized in that, The array substrate further includes a non-display area, the non-display area being located on at least one side of the display area, and the array substrate further includes: A second active structure is disposed on the substrate and located in the non-display area; The third gate is located in the non-display area and is made of the same layer and material as the light-shielding layer. The second source and the second drain are located in the non-display area. The second source and the second drain are respectively connected to the second active structure. The second source and the second drain are in the same layer and made of the same material as the first gate.

8. The array substrate according to claim 7, characterized in that, The semiconductor layer is a metal oxide semiconductor material, and the second active structure is a polycrystalline silicon semiconductor material.

9. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1 to 8.

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