Array substrate and display panel

Abstract

This application provides an array substrate and a display panel, including multiple scan lines, multiple data line groups, and multiple pixel electrode groups. The pixel electrode groups include first-type pixel electrodes and second-type pixel electrodes, which are alternately arranged in a first direction. The data line groups include first-type data lines and second-type data lines, which are also alternately arranged in the first direction. The first-type data lines connect the second-type pixel electrodes in the first-type pixel row and the first-type pixel electrodes in the second-type pixel row, and the second-type data lines connect the first-type pixel electrodes in the first-type pixel row and the second-type pixel electrodes in the second-type pixel row. This application improves the aperture ratio of the display panel by arranging the data lines in an interlaced manner.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] In related technologies, the bottom metal layer typically serves as the gate line and common electrode line, used to transmit gate signals and common signals. To prevent signal short circuits, a safe distance needs to be reserved between the gate line and the common electrode line, which leads to a decrease in pixel aperture ratio and transmittance. Summary of the Invention

[0003] Embodiments of this application provide an array substrate and a display panel to solve the problem of decreased pixel aperture ratio and transmittance in array substrates in related technologies.

[0004] To solve the above problems, the technical solution provided in this application is as follows:

[0005] In a first aspect, this application provides an array substrate, comprising:

[0006] Multiple scan lines and multiple data line groups are provided, with the multiple data line groups arranged along a first direction, the scan lines extending along the first direction, and the multiple scan lines arranged along a second direction intersecting the first direction; the multiple scan lines and multiple data line groups are intersected to form multiple pixel regions; and

[0007] Multiple pixel electrode groups are provided, with one pixel electrode group correspondingly disposed in one pixel region. The multiple pixel electrode groups are arranged along the first direction to form a pixel row. The pixel row includes a first type of pixel row and a second type of pixel row. The first type of pixel row and the second type of pixel row are arranged alternately along the second direction. In the second direction, the pixel electrode groups of the first type of pixel row are correspondingly disposed between two adjacent pixel electrode groups of the second type of pixel row.

[0008] The pixel electrode group includes a first type of pixel electrode and a second type of pixel electrode, which are arranged alternately in the first direction.

[0009] In one embodiment, the data line group includes a first type of data line and a second type of data line, which are arranged alternately in a first direction; the first type of data line connects the second type of pixel electrode of the first type of pixel row and the first type of pixel electrode of the second type of pixel row, and the second type of data line connects the first type of pixel electrode of the first type of pixel row and the second type of pixel electrode of the second type of pixel row.

[0010] In one embodiment, the first type of data line includes a first trace portion, a second trace portion, a third trace portion, a fourth trace portion, a fifth trace portion, and a sixth trace portion. The first trace portion and the second trace portion are disposed in the first type of pixel row, the fourth trace portion and the fifth trace portion are disposed in the second type of pixel row, and the third trace portion and the sixth trace portion are disposed between the first type of pixel row and the second type of pixel row. The third trace portion is connected from one end of the second trace portion to the fourth trace portion in the opposite direction of the first direction, and the sixth trace portion is connected from one end of the fifth trace portion to the first trace portion in the first direction.

[0011] The second type of data line includes a seventh routing section, an eighth routing section, a ninth routing section, a tenth routing section, an eleventh routing section, and a twelfth routing section. The seventh routing section and the eighth routing section are arranged in the first type of pixel row, the tenth routing section and the eleventh routing section are arranged in the second type of pixel row, and the ninth routing section and the twelfth routing section are arranged between the first type of pixel row and the second type of pixel row. The ninth routing section connects the eighth routing section and the tenth routing section, and the twelfth routing section connects the eleventh routing section and the seventh routing section.

[0012] The first and second routing portions are connected to the second type of pixel electrodes of the first type of pixel row, the fourth and fifth routing portions are connected to the first type of pixel electrodes of the second type of pixel row, the seventh and eighth routing portions are connected to the first type of pixel electrodes of the first type of pixel row, and the ninth and tenth routing portions are connected to the second type of pixel electrodes of the second type of pixel row.

[0013] In one embodiment, the first routing portion and the seventh routing portion are parallel to each other, the second routing portion and the eighth routing portion are parallel to each other, the fourth routing portion and the tenth routing portion are parallel to each other, and the fifth routing portion and the eleventh routing portion are parallel to each other;

[0014] The first wiring section and the second wiring section have a first included angle, and the fourth wiring section and the fifth wiring section have a second included angle.

[0015] In one embodiment, the array substrate further includes a plurality of thin-film transistor groups, which are disposed between two adjacent pixel electrode groups and located in the corner region of the pixel electrode groups. Each thin-film transistor group includes a first thin-film transistor and a second thin-film transistor. The control terminals of the first thin-film transistor and the second thin-film transistor are connected to the scan line. The input terminal of the first thin-film transistor is connected to a first type of data line, and the input terminal of the second thin-film transistor is connected to a second type of data line. In the first pixel row, the output terminal of the first thin-film transistor is connected to a second type of pixel electrode, and the output terminal of the second thin-film transistor is connected to a first type of pixel electrode. In the second pixel row, the output terminal of the first thin-film transistor is connected to a first type of pixel electrode, and the output terminal of the second thin-film transistor is connected to a second type of pixel electrode.

[0016] The first thin-film transistor and the second thin-film transistor are arranged alternately in a row along the first direction; in each group of thin-film transistors, the first thin-film transistor is disposed on the side of the first type of data line away from the second type of data line, and the second thin-film transistor is disposed on the side of the second type of data line away from the first type of data line.

[0017] In one embodiment, each pixel region is a dual-pixel domain region, with the first type of pixel electrode and the second type of pixel electrode each corresponding to a pixel domain region.

[0018] In one embodiment, the array substrate further includes a common trace extending along the first direction. In the array substrate viewed from above, the common trace is disposed between two adjacent pixel domains in the second direction.

[0019] In one embodiment, a plurality of pixel electrode groups are co-located on the pixel electrode layer, and the array substrate further includes a first common electrode layer connected to the common trace. The pixel electrode layer and the first common electrode layer are co-located on different layers. The first common electrode layer includes a plurality of first common electrodes, and a first common electrode is correspondingly disposed in a pixel region.

[0020] In the array substrate viewed from above, a first common electrode simultaneously overlaps with a first type of pixel electrode and a second type of pixel electrode in the same pixel electrode group.

[0021] The first common electrode layer has a slit.

[0022] In one embodiment, a plurality of pixel electrode groups are co-located on a pixel electrode layer, and the array substrate further includes a first common electrode layer and a second common electrode layer connected to the common trace. The pixel electrode layer and the first common electrode layer are disposed on different layers, and the pixel electrode layer and the second common electrode layer are co-located.

[0023] The first common electrode layer includes a plurality of first common electrodes, and each first common electrode is disposed in a pixel region. In the array substrate viewed from above, each first common electrode overlaps with a first type of pixel electrode and a second type of pixel electrode in the same pixel electrode group.

[0024] The second common electrode layer includes a plurality of second common electrodes, and in the array substrate viewed from above, one of the second common electrodes partially overlaps with the data line group;

[0025] The second common electrode has at least one through hole;

[0026] The pixel electrode layer has slits.

[0027] In one embodiment, in the second direction, the first type of pixel electrode and the second type of pixel electrode are alternately arranged into pixel columns, and a plurality of pixel columns are arranged along the first direction, wherein, in the same frame, the voltage polarity of the first type of data line and the voltage polarity of the second type of data line are opposite.

[0028] Secondly, this application provides a display panel, including the array substrate described above and a counter substrate disposed opposite to the array substrate.

[0029] In one embodiment, the display panel further includes a plurality of spacers disposed between the first type of pixel rows and the second type of pixel rows;

[0030] In the display panel viewed from above, at least one of the scan lines and the data line group is partially overlapped with the spacer, which is located at the intersection of the first light-shielding strip and the second light-shielding strip.

[0031] In one embodiment, a third light-shielding portion is connected to both sides of the intersection of the first light-shielding strip and the second light-shielding strip; in the display panel viewed from above, the third light-shielding portion and portions of the first light-shielding strip and the second light-shielding strip respectively connected to the third light-shielding portion cover the padding material as a whole.

[0032] The array substrate of this application includes multiple scan lines and multiple data line groups. The multiple data line groups are arranged along a first direction, and the scan lines extend along the first direction (x). The multiple scan lines are arranged along a second direction (y) intersecting the first direction. The multiple scan lines and multiple data line groups are intersected to form multiple pixel regions. Multiple pixel electrode groups are also included, with one pixel electrode group corresponding to one pixel region. The multiple pixel electrode groups are arranged along the first direction to form pixel rows. The pixel rows include first-type pixel rows and second-type pixel rows, which are alternately arranged along the second direction. In the second direction, the... The pixel electrode groups of the first type of pixel row are correspondingly disposed between two adjacent pixel electrode groups of the second type of pixel row; wherein, the pixel electrode group includes a first type of pixel electrode and a second type of pixel electrode, and the first type of pixel electrode and the second type of pixel electrode are alternately arranged in the first direction; the data line group includes a first type of data line and a second type of data line, and the first type of data line and the second type of data line are alternately arranged in the first direction; the first type of data line connects the second type of pixel electrode of the first type of pixel row and the first type of pixel electrode of the second type of pixel row, and the second type of data line connects the first type of pixel electrode of the first type of pixel row and the second type of pixel electrode of the second type of pixel row. Through the above scheme, there is no data line between the first type of pixel electrode and the second type of pixel electrode in the pixel electrode group, which greatly reduces the distance between the first type of pixel electrode and the second type of pixel electrode in the pixel electrode group. Although a data line is added between the pixel electrode groups, the small distance between the first data line and the second data line reduces the wiring area in the first direction, thereby improving the aperture ratio. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Appendix Figure 1 This is a schematic diagram of the structure of an optional array substrate in an embodiment of this application;

[0035] Appendix Figure 2 This is a schematic cross-sectional view of an optional array substrate in an embodiment of this application.

[0036] Appendix Figure 3 This is a schematic diagram of another optional array substrate in the embodiments of this application;

[0037] Appendix Figure 4 This is a schematic cross-sectional view of another optional array substrate in the embodiments of this application;

[0038] Appendix Figure 5 This is a schematic diagram of the structure of an optional display panel in an embodiment of this application;

[0039] Appendix Figure 6 This is a schematic diagram of the structure of an optional light-shielding layer in an embodiment of this application;

[0040] Appendix Figure 7 This is a schematic diagram of the through hole structure in two optional second common electrodes in the embodiments of this application.

[0041] Explanation of the reference numerals in the figure:

[0042] 1. Display panel; 10. Array substrate; 10a. Pixel area; 20. Black matrix layer; 21. First light-shielding strip; 22. Second light-shielding strip; 22a. First light-shielding part; 22b. Second light-shielding part; 22c. Third light-shielding part; 30. Spacer;

[0043] 100. Scan lines;

[0044] 200. Data cable assembly; 210. Type 1 data cable; 211. First wiring section; 212. Second wiring section; 213. Third wiring section; 214. Fourth wiring section; 215. Fifth wiring section; 216. Sixth wiring section; 220. Type 2 data cable; 221. Seventh wiring section; 222. Eighth wiring section; 223. Ninth wiring section; 224. Tenth wiring section; 225. Eleventh wiring section; 226. Twelfth wiring section;

[0045] 300, Pixel electrode group; 300a, First type pixel row; 300b, Second type pixel row; 311, First type pixel electrode; 312, Second type pixel electrode;

[0046] 400, Thin-film transistor array; 410, First thin-film transistor; 420, Second thin-film transistor;

[0047] 500. Public wiring;

[0048] 600, First common electrode layer; 610, First common electrode;

[0049] 700, Second common electrode layer; 700a, Through hole; 710, Second common electrode. Detailed Implementation

[0050] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0051] It should be noted that the first direction x can be a direction parallel to one side of the array substrate 10 in a plan view, and for example, it can be the lateral direction of the array substrate 10. The second direction y can be a direction parallel to the other side of the array substrate 10 in a plan view, and it can be the longitudinal direction of the array substrate 10. Optionally, in some embodiments, the first direction x and the second direction y may not intersect perpendicularly.

[0052] Optionally, the array substrate 10 can be driven by a Fringe Field Switching (FFS) technology or a High Transmission Fringe Field Switching (HFS) technology, or by an In-Plane Switching (IPS) technology, or by a Vertical Alignment (VA) technology or a Twisted Nematic (TN) technology, etc. The following embodiments will be described based on the array substrate 10 being driven by a High Transmission Fringe Field Switching (HFS) technology.

[0053] Reference Figures 1 to 4 As shown, according to a first aspect of this application, an array substrate 10 is provided, comprising:

[0054] Multiple scan lines 100 and multiple data line groups 200 are arranged along a first direction. The scan lines 100 extend along the first direction (positive x-axis direction in the figure). The multiple scan lines 100 are arranged along a second direction (positive y-axis direction in the figure) that intersects with the first direction. The multiple scan lines 100 and multiple data line groups 200 are intersected to form multiple pixel regions 10a. In some embodiments of this application, each pixel region 10a is a dual-pixel domain region, and the first type of pixel electrode 311 and the second type of pixel electrode 312 each correspond to a pixel domain region.

[0055] Multiple pixel electrode groups 300 are provided, each pixel electrode group 300 is disposed in a pixel region 10a, and the multiple pixel electrode groups 300 are arranged along a first direction to form a pixel row. The pixel row includes a first type of pixel row 300a and a second type of pixel row 300b. The first type of pixel row 300a and the second type of pixel row 300b are arranged alternately along a second direction. In the second direction, the pixel electrode groups 300 of the first type of pixel row 300a are disposed between two adjacent pixel electrode groups 300 of the second type of pixel row 300b.

[0056] The pixel electrode group 300 includes a first type of pixel electrode 311 and a second type of pixel electrode 312, and the first type of pixel electrode 311 and the second type of pixel electrode 312 are arranged alternately in a first direction.

[0057] The data line group 200 includes a first type of data line 210 and a second type of data line 220, which are arranged alternately in a first direction. The first type of data line 210 connects to the second type of pixel electrode 312 of the first type of pixel row 300a and the first type of pixel electrode 311 of the second type of pixel row 300b, and the second type of data line 220 connects to the first type of pixel electrode 311 of the first type of pixel row 300a and the second type of pixel electrode 312 of the second type of pixel row.

[0058] The array substrate 10 of this application adopts a data line group 200 layout, so that there is no data line between the first type of pixel electrode and the second type of pixel electrode in the pixel electrode group 300, which greatly reduces the distance between the first type of pixel electrode and the second type of pixel electrode in the pixel electrode group 300. Although a data line is added between the pixel electrode groups 300, in the first direction, the distance between two data lines in the same data line group 200 is smaller than the distance from the data line to its nearest pixel electrode. That is, the distance between the first data line and the second data line is smaller, thereby reducing the wiring area in the first direction and improving the aperture ratio.

[0059] In some embodiments, the first data line and the second data line may also be configured in different layers. In the first direction, the first data line and the second data line may be smaller, and even the first data line and the second data line may at least partially overlap, in order to further reduce the distance between the first data line and the second data line in the first direction F1 and improve the aperture ratio.

[0060] Reference Figure 1 and Figure 3In some more specific embodiments, the first type of data line 210 includes a first routing section 211, a second routing section 212, a third routing section 213, a fourth routing section 214, a fifth routing section 215, and a sixth routing section 216. The first routing section 211 and the second routing section 212 are disposed in the first type of pixel row 300a, the fourth routing section 214 and the fifth routing section 215 are disposed in the second type of pixel row 300b, and the third routing section 213 and the sixth routing section 216 are disposed between the first type of pixel row 300a and the second type of pixel row 300b. The third routing section 213 is connected from one end of the second routing section 212 to the fourth routing section 214 in the opposite direction of the first direction, and the sixth routing section 216 is connected from one end of the fifth routing section 215 to the first routing section 211 in the first direction. The arrangement of the third routing section 213 and the sixth routing section 216 can reduce their layout area in the second direction and improve the aperture ratio.

[0061] The second type of data line 220 includes a seventh routing section 221, an eighth routing section 222, a ninth routing section 223, a tenth routing section 224, an eleventh routing section 225, and a twelfth routing section 226. The seventh routing section 221 and the eighth routing section 222 are located in the first type of pixel row 300a. The tenth routing section 224 and the eleventh routing section 225 are located in the second type of pixel row 300b. The ninth routing section 223 and the twelfth routing section 226 are located between the first type of pixel row 300a and the second type of pixel row 300b. The ninth routing section 223 connects to the eighth routing section 222 and the tenth routing section 224, and the twelfth routing section 226 connects to the eleventh routing section 225 and the seventh routing section 221. The sixth routing section 216 and the twelfth routing section 226 are arranged in the same way, and will not be described further here.

[0062] The first routing section 211 and the second routing section 212 are connected to the second type pixel electrode 312 of the first type pixel row 300a. The fourth routing section 214 and the fifth routing section 215 are connected to the first type pixel electrode 311 of the second type pixel row 300b. The seventh routing section 221 and the eighth routing section 222 are connected to the first type pixel electrode 311 of the first type pixel row 300a. The ninth routing section 223 and the tenth routing section 224 are connected to the second type pixel electrode 312 of the second type pixel row 300b.

[0063] Specifically, the first routing section 211 and the seventh routing section 221 are parallel to each other, the second routing section 212 and the eighth routing section 222 are parallel to each other, the fourth routing section 214 and the tenth routing section 224 are parallel to each other, and the fifth routing section 215 and the eleventh routing section 225 are parallel to each other; the first routing section 211 and the second routing section 212 have a first included angle, and the fourth routing section 214 and the fifth routing section 215 have a second included angle. It should be noted that due to the parallel relationship between some routing sections, the corresponding routing sections also have included angles, which will not be elaborated here.

[0064] In some embodiments of this application, the array substrate 10 further includes a plurality of thin-film transistor groups 400. The thin-film transistor groups 400 are disposed between two adjacent pixel electrode groups 300 and located in the corner region of the pixel electrode groups 300. Each thin-film transistor group 400 includes a first thin-film transistor 410 and a second thin-film transistor 420. The control terminals of the first thin-film transistor 410 and the second thin-film transistor 420 are connected to the scan line 100. The input terminal of the first thin-film transistor 410 is connected to a first type data line 210, and the input terminal of the second thin-film transistor 420 is connected to a second type data line 220. In the first pixel row, the output terminal of the first thin-film transistor 410 is connected to a second type pixel electrode 312, and the output terminal of the second thin-film transistor 420 is connected to a first type pixel electrode 311. In the second pixel row, the output terminal of the first thin-film transistor 410 is connected to the first type pixel electrode 311, and the output terminal of the second thin-film transistor 420 is connected to the second type pixel electrode 312.

[0065] It is understandable that in the same thin-film transistor group 400, a first thin-film transistor 410 and a second thin-film transistor 420 share a gate. That is, a first thin-film transistor 410 and a second thin-film transistor 420 are arranged side by side to form a thin-film transistor group 400 by sharing a gate, which reduces the overall layout area of ​​the thin-film transistors and thus increases the aperture ratio.

[0066] Secondly, in the first direction, the side-by-side arrangement of the first thin-film transistor 410 and the second thin-film transistor 420 further reduces the layout area in the second direction and increases the aperture ratio.

[0067] Optionally, in some embodiments of this application, the first thin-film transistor 410 and the second thin-film transistor 420 are alternately arranged in a row along a first direction; in each thin-film transistor group 400, the first thin-film transistor 410 is disposed on the side of the first type of data line 210 away from the second type of data line 220, and the second thin-film transistor 420 is disposed on the side of the second type of data line 220 away from the first type of data line 210. It is understood that by placing the data line group 200 between two thin-film transistors in the thin-film transistor group 400, the distance between the first data line and the second data line in the data line group 200 is reduced, thereby increasing the aperture ratio.

[0068] In some embodiments of this application, the array substrate 10 further includes a common trace 500, which extends along a first direction and is disposed between two adjacent pixel domains in a second direction in the display panel 1 from a top view.

[0069] Reference Figure 1 and Figure 2As shown, in some specific embodiments of this application, multiple pixel electrode groups 300 are co-located on the pixel electrode layer. The array substrate 10 also includes a first common electrode layer 600 connected to a common trace 500. The pixel electrode layer and the first common electrode layer 600 are co-located. The first common electrode layer 600 includes multiple first common electrodes 610, and a first common electrode 610 is correspondingly disposed within a pixel region 10a. In the array substrate 10 viewed from above, a first common electrode 610 simultaneously overlaps with a first type pixel electrode 311 and a second type pixel electrode 312 of the same pixel electrode group 300. The first common electrode layer 600 is provided with a slit.

[0070] Reference Figure 3 and Figure 4 As shown, in some specific embodiments of this application, multiple pixel electrode groups 300 are co-formed on the pixel electrode layer. The array substrate 10 also includes a first common electrode layer 600 and a second common electrode layer 700 connected to the common trace 500. The pixel electrode layer and the first common electrode layer 600 are co-formed, while the pixel electrode layer and the second common electrode layer 700 are co-formed. The first common electrode layer 600 includes multiple first common electrodes 610, each first common electrode 610 being disposed within a pixel region 10a. In the array substrate 10 viewed from above, a first common electrode 610 simultaneously overlaps with the first type of pixel electrode 311 and the second type of pixel electrode 312 of the same pixel electrode group 300. The second common electrode layer 700 includes multiple second common electrodes 710. In the array substrate 10 viewed from above, a second common electrode 710 partially overlaps with the data line group 200. The second common electrode 710 has at least one through-hole 700a, which is used as follows: Figure 7 (a) and Figure 7 As shown in (b), it can have various shapes, which are not limited herein; the pixel electrode layer has slits. In this embodiment, by setting a top-layer pixel electrode and a double-layer common electrode structure, it is beneficial to reduce the capacitance between the pixel and the data line. It should be noted that this capacitance can cause vertical crosstalk caused by the coupling of the pixel signal due to fluctuations in the data signal.

[0071] In some embodiments of this application, in the second direction, the first type of pixel electrode 311 and the second type of pixel electrode 312 are alternately arranged to form pixel columns, and multiple pixel columns are arranged along the first direction. In the same frame, the voltage polarity of the first type of data line 210 and the voltage polarity of the second type of data line 220 are opposite. For example, the first data line is connected to a positive voltage, and the second data line is connected to a negative voltage; or, the first data line is connected to a negative voltage, and the second data line is connected to a positive voltage.

[0072] It should be noted that, since the first data line connects the second type of pixel electrode in the first pixel row and the first type of pixel electrode in the second pixel row, and the second data line connects the first type of pixel electrode in the first pixel row and the second type of pixel electrode in the second pixel row, the voltage polarity of the first type of pixel electrode and the second type of pixel electrode is the same in the same pixel column, and the voltage polarity of the first type of pixel electrode and the second type of pixel electrode is opposite in the same pixel row, thereby achieving the column flipping effect, reducing horizontal crosstalk, and improving the display effect.

[0073] Reference Figure 5 As shown, according to a second aspect of this application, a display panel 1 is provided, including an array substrate 10 and an opposing substrate disposed opposite each other. The array substrate 10 is configured as the array substrate 10 of any of the above embodiments, meaning that the display panel 1 possesses all the technical features of all embodiments of the array substrate 10, and thus all the beneficial effects brought by all these technical features, which will not be elaborated further here.

[0074] Reference Figure 6 As shown, in some embodiments of this application, the opposing substrate includes a black matrix layer 20, which includes a first light-shielding strip 21 and a second light-shielding strip 22. The first light-shielding strip 21 extends along a first direction, and the second light-shielding strip 22 extends along a second direction. Multiple first light-shielding strips 21 and multiple second light-shielding strips 22 are intersected to form multiple openings. Part of the multiple openings faces a first type of pixel electrode, and another part of the multiple openings faces a second type of pixel electrode. The second light-shielding strip 22 includes a first light-shielding portion 22a and a second light-shielding portion 22b. In the first direction, the width of the first light-shielding portion 22a is greater than the width of the second light-shielding portion 22b. In the first direction, the first light-shielding portion 22a and the second light-shielding portion 22b are alternately arranged. In the second direction, the first light-shielding portion 22a and the second light-shielding portion 22b are alternately connected. The wider first light-shielding portion 22a and the narrower second light-shielding portion 22b are alternately connected in the second direction, so that the edge of the second light-shielding strip 22 in the second direction is non-linear, reducing the risk of vertical lines appearing on the display panel 1. Optionally, the second light-shielding strip 22 has non-linear edges on both sides in the second direction to further reduce the risk of vertical lines appearing on the display panel 1. In addition, the wider first light-shielding portion 22a and the narrower second light-shielding portion 22b are alternately arranged in the first and second directions to improve the uniformity of the display.

[0075] In the display panel 1 viewed from above, the first light-shielding strip 21 covers the scan line 100, the second wiring portion 212, and the fifth wiring portion 215. The first light-shielding portion 22a covers the portion of the data line group 200 located between two adjacent pixel electrode groups 300 in the first direction. The second light-shielding portion 22b covers the area between the first type of pixel electrode and the second type of pixel electrode in the pixel electrode group 300. Because the data line group 200 is located between two adjacent pixel electrode groups 300 in the first direction, the distance between adjacent pixel electrode groups 300 is relatively large, while the distance between two pixel electrodes in the same pixel electrode group 300 is relatively small. Therefore, based on the consideration of maximum aperture ratio, the width of the first light-shielding portion 22a is greater than the width of the second light-shielding portion 22b. Furthermore, because the width of the first light-shielding portion 22a is greater than the width of the second light-shielding portion 22b, the edge of the second light-shielding strip 22 in the second direction is non-linear, reducing the risk of vertical lines appearing on the display panel 1 and improving the uniformity of the display.

[0076] Correspondingly, the display panel 1 also includes a plurality of spacers 30, which are disposed between the first type of pixel row 300a and the second type of pixel row 300b; see reference Figure 1 and Figure 3 As shown, in the display panel 1 viewed from above, at least one of the scan line 100 and the data line group 200 partially overlaps with the spacer 30, which is disposed at the intersection of the first light-shielding strip 21 and the second light-shielding strip 22. In some embodiments, a third light-shielding portion 22c is connected to both sides of the intersection of the first light-shielding strip 21 and the second light-shielding strip 22; in the display panel 1 viewed from above, the third light-shielding portion 22c and portions of the first light-shielding strip 21 and the second light-shielding strip 22 connected to the third light-shielding portion 22c respectively cover the spacer 30 as a whole. It can be understood that the first light-shielding portion 22a covers the middle area of ​​the spacer 30, and the third light-shielding portion 22c covers the two side areas of the spacer 30, such that the first light-shielding portion 22a and the third light-shielding portion 22c cover the entire spacer 30. Secondly, since the third light-shielding part 22c is connected to both sides of the first light-shielding part 22a, the edge of the second light-shielding strip 22 in the second direction is more uneven, reducing the risk of vertical lines appearing on the display panel 1.

[0077] In summary, although the present application has disclosed the preferred embodiments as described above, the above preferred embodiments are not intended to limit the present application. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be determined by the scope defined in the claims.

Claims

1. An array substrate, characterized in that, include: Multiple scan lines and multiple data line groups are provided, with the multiple data line groups arranged along a first direction, the scan lines extending along the first direction, and the multiple scan lines arranged along a second direction intersecting the first direction; the multiple scan lines and multiple data line groups are arranged to intersect to form multiple pixel regions; as well as Multiple pixel electrode groups are provided, with one pixel electrode group correspondingly disposed in one pixel region. The multiple pixel electrode groups are arranged along the first direction to form a pixel row. The pixel row includes a first type of pixel row and a second type of pixel row. The first type of pixel row and the second type of pixel row are arranged alternately along the second direction. In the second direction, the pixel electrode groups of the first type of pixel row are correspondingly disposed between two adjacent pixel electrode groups of the second type of pixel row. The pixel electrode group includes a first type of pixel electrode and a second type of pixel electrode, which are arranged alternately in the first direction.

2. The array substrate according to claim 1, characterized in that, The data line group includes a first type of data line and a second type of data line, which are arranged alternately in a first direction; the first type of data line connects the second type of pixel electrode of the first type of pixel row and the first type of pixel electrode of the second type of pixel row, and the second type of data line connects the first type of pixel electrode of the first type of pixel row and the second type of pixel electrode of the second type of pixel row.

3. The array substrate according to claim 2, characterized in that, The first type of data line includes a first routing section, a second routing section, a third routing section, a fourth routing section, a fifth routing section, and a sixth routing section. The first routing section and the second routing section are arranged in the first type of pixel row, the fourth routing section and the fifth routing section are arranged in the second type of pixel row, and the third routing section and the sixth routing section are arranged between the first type of pixel row and the second type of pixel row. The third routing section is connected from one end of the second routing section to the fourth routing section in the opposite direction of the first direction, and the sixth routing section is connected from one end of the fifth routing section to the first routing section in the first direction. The second type of data line includes a seventh routing section, an eighth routing section, a ninth routing section, a tenth routing section, an eleventh routing section, and a twelfth routing section. The seventh routing section and the eighth routing section are arranged in the first type of pixel row, the tenth routing section and the eleventh routing section are arranged in the second type of pixel row, and the ninth routing section and the twelfth routing section are arranged between the first type of pixel row and the second type of pixel row. The ninth routing section connects the eighth routing section and the tenth routing section, and the twelfth routing section connects the eleventh routing section and the seventh routing section. The first and second routing portions are connected to the second type of pixel electrodes of the first type of pixel row, the fourth and fifth routing portions are connected to the first type of pixel electrodes of the second type of pixel row, the seventh and eighth routing portions are connected to the first type of pixel electrodes of the first type of pixel row, and the ninth and tenth routing portions are connected to the second type of pixel electrodes of the second type of pixel row.

4. The array substrate according to claim 3, characterized in that, The first routing section and the seventh routing section are parallel to each other, the second routing section and the eighth routing section are parallel to each other, the fourth routing section and the tenth routing section are parallel to each other, and the fifth routing section and the eleventh routing section are parallel to each other; The first wiring section and the second wiring section have a first included angle, and the fourth wiring section and the fifth wiring section have a second included angle.

5. The array substrate according to claim 4, characterized in that, The array substrate further includes multiple thin-film transistor groups, which are disposed between two adjacent pixel electrode groups and located in the corner region of the pixel electrode groups. Each thin-film transistor group includes a first thin-film transistor and a second thin-film transistor. The control terminals of the first thin-film transistor and the second thin-film transistor are connected to the scan line. The input terminal of the first thin-film transistor is connected to the first type of data line, and the input terminal of the second thin-film transistor is connected to the second type of data line. In the first pixel row, the output terminal of the first thin-film transistor is connected to the second type of pixel electrode, and the output terminal of the second thin-film transistor is connected to the first type of pixel electrode. In the second pixel row, the output terminal of the first thin-film transistor is connected to the first type of pixel electrode, and the output terminal of the second thin-film transistor is connected to the second type of pixel electrode; The first thin-film transistor and the second thin-film transistor are arranged alternately in a row along the first direction; in each group of thin-film transistors, the first thin-film transistor is disposed on the side of the first type of data line away from the second type of data line, and the second thin-film transistor is disposed on the side of the second type of data line away from the first type of data line.

6. The array substrate according to claim 5, characterized in that, Each pixel region is a dual-pixel domain region, with the first type of pixel electrode and the second type of pixel electrode each corresponding to a pixel domain region.

7. The array substrate according to claim 6, characterized in that, The array substrate also includes a common trace that extends along the first direction. In the array substrate viewed from above, the common trace is disposed between two adjacent pixel domains in the second direction.

8. The array substrate according to claim 7, characterized in that, Multiple pixel electrode groups are co-located and formed on the pixel electrode layer. The array substrate also includes a first common electrode layer connected to the common trace. The pixel electrode layer and the first common electrode layer are co-located on different layers. The first common electrode layer includes multiple first common electrodes, and one first common electrode is correspondingly disposed in one pixel region. In the array substrate viewed from above, a first common electrode simultaneously overlaps with a first type of pixel electrode and a second type of pixel electrode in the same pixel electrode group. The first common electrode layer has a slit.

9. The array substrate according to claim 7, characterized in that, Multiple pixel electrode groups are co-located on the pixel electrode layer. The array substrate also includes a first common electrode layer and a second common electrode layer connected to the common trace. The pixel electrode layer and the first common electrode layer are disposed on different layers, and the pixel electrode layer and the second common electrode layer are co-located. The first common electrode layer includes a plurality of first common electrodes, and each first common electrode is disposed in a pixel region. In the array substrate viewed from above, each first common electrode overlaps with a first type of pixel electrode and a second type of pixel electrode in the same pixel electrode group. The second common electrode layer includes a plurality of second common electrodes, and in the array substrate viewed from above, one of the second common electrodes partially overlaps with the data line group; The second common electrode has at least one through hole; The pixel electrode layer has slits.

10. The array substrate according to claim 8 or 9, characterized in that, In the second direction, the first type of pixel electrode and the second type of pixel electrode are alternately arranged in a pixel column, and a plurality of the pixel columns are arranged along the first direction, wherein, in the same frame, the voltage polarity of the first type of data line and the voltage polarity of the second type of data line are opposite.

11. A display panel, characterized in that, It includes the array substrate as described in any one of claims 1 to 10 and the opposing substrate disposed opposite to the array substrate.

12. The display panel according to claim 11, characterized in that, The opposing substrate includes a black matrix layer, the black matrix layer includes a first light-shielding strip and a second light-shielding strip, the first light-shielding strip extends along a first direction, the second light-shielding strip extends along a second direction, a plurality of the first light-shielding strips and a plurality of the second light-shielding strips are cross-connected to form a plurality of openings, a portion of the plurality of openings faces the first type of pixel electrode, and another portion of the plurality of openings faces the second type of pixel electrode; The second light-shielding strip includes a first light-shielding part and a second light-shielding part. In the first direction, the width of the first light-shielding part is greater than the width of the second light-shielding part. In the first direction, the first light-shielding part and the second light-shielding part are arranged alternately. In the second direction, the first light-shielding part and the second light-shielding part are connected alternately. In the display panel viewed from above, the first light-shielding strip covers the scan line, the second trace portion, and the fifth trace portion. The first light-shielding portion covers the portion of the data line group located between two adjacent groups of pixel electrode groups in the first direction. The second light-shielding portion covers the area between the first type of pixel electrode and the second type of pixel electrode in the pixel electrode group.

13. The display panel according to claim 12, characterized in that, The display panel also includes a plurality of spacers disposed between the first type of pixel rows and the second type of pixel rows; In the display panel viewed from above, at least one of the scan lines and the data line group is partially overlapped with the spacer, which is located at the intersection of the first light-shielding strip and the second light-shielding strip.

14. The display panel according to claim 13, characterized in that, A third light-shielding part is connected to both sides of the intersection of the first light-shielding strip and the second light-shielding strip; in the display panel viewed from above, the third light-shielding part and the portions of the first light-shielding strip and the second light-shielding strip connected to the third light-shielding part respectively cover the pad as a whole.

Images