Micro light-emitting diode and display device thereof

Abstract

The invention discloses a micro light-emitting diode and a display device thereof, the micro light-emitting diode is provided with a semiconductor layer sequence, the semiconductor layer sequence comprises a back side and a front side, a first type semiconductor layer and a second type semiconductor layer are sequentially arranged from the front side, an active layer is arranged between the first type semiconductor layer and the second type semiconductor layer, and the back side of the semiconductor layer sequence is provided with an exposed part. The exposed part penetrates through the second type semiconductor layer and the active layer, the first type semiconductor layer is exposed, and the back side of the semiconductor layer sequence comprises a first mesa in the exposed part, a second mesa on the second type semiconductor layer and a mesa side wall located between the first mesa and the second mesa; the back side of the semiconductor layer sequence is provided with a first metal electrode electrically connected with the first type of semiconductor layer, a second metal electrode electrically connected with the second type of semiconductor layer, and a passivation layer covering the upper part and / or the side wall of the semiconductor layer sequence; the passivation layer is provided with a first opening used for arranging the first metal electrode on the first table top, the first opening comprises a first angle close to the side wall of the table top and a second angle away from the side wall of the table top, and the second angle is smaller than the first angle and used for improving the continuity of the first metal electrode.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor manufacturing, and in particular relates to a micro light emitting diode and a display device. Background Art

[0002] Micro LED (mLED) is a hotly researched next-generation display light source. It has the advantages of low power consumption, high brightness, ultra-high resolution and color saturation, fast response speed, low energy consumption, and long life. In addition, its power consumption is about 10% of LCD and 50% of OLED. Compared with OLED, which is also self-luminous, the brightness is many times higher, and the resolution can reach a high pixel density. These obvious advantages of mLED make it likely to replace the current OLED and LCD and become the light source for the next generation of displays. mLED cannot be mass-produced at present because there are still many technical difficulties to be overcome. One of the important technical difficulties is how to improve the yield of micron-level core particles. Summary of the invention

[0003] In order to improve the yield of micron-sized core particles, the present invention provides a micro light-emitting diode, which has a semiconductor layer sequence, the semiconductor layer sequence includes a back side and a front side, and includes a first type semiconductor layer and a second type semiconductor layer in sequence from the front side, with an active layer located between the two, the back side of the semiconductor layer sequence has an exposed portion, the exposed portion penetrates the second type semiconductor layer and the active layer, and at least exposes the first type semiconductor layer, the back side of the semiconductor layer sequence includes a first table in the exposed portion, a second table on the second type semiconductor layer, and a table sidewall located between the two, the back side of the semiconductor layer sequence is provided with a first metal electrode electrically connected to the first type semiconductor layer and a second metal electrode electrically connected to the second type semiconductor layer, and also includes a passivation layer covering the semiconductor layer sequence above and / or on the sidewall, the passivation layer is partially provided on the first table, the passivation layer has a first opening for providing the first metal electrode, and the first opening includes a first angle α close to the table sidewall relative to a horizontal plane 1 and a second angle α away from the side wall of the table 2 , the second angle α 2 Smaller than the first angle α 1 .

[0004] The present invention also provides a micro light emitting diode, comprising a semiconductor layer sequence, wherein the semiconductor layer sequence comprises a back side and a front side, and comprises a first type semiconductor layer and a second type semiconductor layer in sequence from the front side, with an active layer located therebetween, the back side of the semiconductor layer sequence comprising an exposed portion, the exposed portion penetrating the second type semiconductor layer and the active layer, exposing at least the first type semiconductor layer, the back side of the semiconductor layer sequence comprising a first table in the exposed portion, a second table on the second type semiconductor layer, and a table sidewall located therebetween, the exposed portion being a non-closed step, the exposed portion being composed of N side surfaces, N being an integer not less than 2, wherein at least one side surface is a table sidewall, and at least one side surface is exposed, a first metal electrode electrically connected to the first type semiconductor layer and a second metal electrode electrically connected to the second type semiconductor layer are arranged on the back side of the semiconductor layer sequence, and a passivation layer covering the semiconductor layer sequence above and / or on the sidewalls, the passivation layer being partially arranged on the first table, the passivation layer having a first opening for arranging the first metal electrode, and the first opening comprising a first angle α close to the table sidewall relative to a horizontal plane 1 and a second angle α near the exposed side 2 , the second angle α 2 Smaller than the first angle α 1 .

[0005] The present invention also provides a display device, comprising a plurality of micro-light-emitting diodes and a substrate, wherein the micro-light-emitting diodes are arranged on the substrate and have a semiconductor layer sequence, wherein the semiconductor layer sequence comprises a back side and a front side, and comprises a first type semiconductor layer and a second type semiconductor layer in sequence from the front side, with an active layer located therebetween, wherein the back side of the semiconductor layer sequence comprises an exposed portion, wherein the exposed portion penetrates the second type semiconductor layer and the active layer to expose the first type semiconductor layer, wherein the back side of the semiconductor layer sequence comprises a first table in the exposed portion, a second table on the second type semiconductor layer, and a table sidewall located therebetween, wherein a first metal electrode electrically connected to the first type semiconductor layer and a second metal electrode electrically connected to the second type semiconductor layer are arranged on the back side of the semiconductor layer sequence, and further comprises a passivation layer covering the semiconductor layer sequence above and / or on the sidewalls, wherein the passivation layer comprises a first opening on the first table for arranging the first metal electrode, wherein the first opening comprises a first angle α close to the table sidewall relative to a horizontal plane 1 and a second angle α away from the side wall of the table 2 , the second angle α 2 Smaller than the first angle α 1 .

[0006] The present invention improves both product performance and yield through differentiated design of the passivation layer opening.

[0007] Other beneficial effects of the present invention will be gradually described through embodiments and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, some of the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0009] Figure 1 and Figure 2 They are respectively a cross-sectional schematic diagram and a top view schematic diagram of a micro light emitting diode chip in the prior art; Figure 3 and Figure 4 They are respectively a cross-sectional schematic diagram and a top schematic diagram of a first embodiment of the present invention; Figure 5 is a schematic top view of a second embodiment of the present invention; Figure 6 is a top view schematically showing a third embodiment of the present invention; Figure 7 is a cross-sectional schematic diagram of a fourth embodiment of the present invention; Figure 8 is a cross-sectional schematic diagram of a fifth embodiment of the present invention; Fig. 9 is a cross-sectional schematic diagram of a sixth embodiment of the present invention; Fig.10 It is a cross-sectional schematic diagram of the seventh embodiment of the present invention.

[0010] Symbols in the figure: 110, semiconductor layer sequence; 111, first type semiconductor layer; 112, second type semiconductor layer; 113, active layer; 210, first metal electrode; 211, 221, first layer; 212, 222, second layer; 220, second metal electrode; 300, passivation layer; 400, transparent conductive layer; 500, substrate; CR, crack; G1, exposed part; K1, first opening; K2, second opening; K11, first electrode hole; K12, second electrode hole; M1, first table; M2, second table; S1, side wall; α1, first angle; α2, second angle; α3, third angle; α4, fourth angle; d1, distance; h, height; L1, L2, length; C1, micro light-emitting diode; P1: epoxy resin. DETAILED DESCRIPTION

[0011] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments; the technical features designed in different implementation modes of the present invention described below can be combined with each other as long as they do not conflict with each other; based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0012] In some embodiments, a micro-light emitting diode is provided, which has a semiconductor layer sequence, the semiconductor layer sequence includes a back side and a front side, and includes a first type semiconductor layer and a second type semiconductor layer in sequence from the front side, with an active layer located therebetween, the back side of the semiconductor layer sequence has an exposed portion, the exposed portion penetrates the second type semiconductor layer and the active layer, and at least exposes the first type semiconductor layer, the back side of the semiconductor layer sequence includes a first table in the exposed portion, a second table on the second type semiconductor layer, and a table sidewall located therebetween, the back side of the semiconductor layer sequence is provided with a first metal electrode electrically connected to the first type semiconductor layer and a second metal electrode electrically connected to the second type semiconductor layer, and also includes a passivation layer covering the semiconductor layer sequence above and / or on the sidewall, the passivation layer is partially provided on the first table, the passivation layer has a first opening for providing the first metal electrode, and the first opening includes a first angle α close to the table sidewall relative to a horizontal plane 1 and a second angle α away from the side wall of the table 2 , the second angle α 2 Smaller than the first angle α 1 Here, the opening of the passivation layer refers to the opening formed by removing a portion of the passivation layer by etching, and the exposed portion is, for example, a groove or a step.

[0013] In some embodiments, the first angle α 1 The second angle α 2 1.05 times to 5 times, the angle here mainly refers to the angle between the side of the passivation layer and the horizontal plane. When the relevant multiple is less than 1.05 times, the yield of the first metal electrode is limited. When the passivation layer is a distributed Bragg reflector DBR with a multi-layer structure, the relevant multiple exceeds 5 times and the reflection effect will be significantly reduced.

[0014] In some embodiments, the second angle α 2 is 15° to 75°, the second angle α 2 When it is less than 15°, the passivation layer will be too thin, reducing the process yield. If the passivation layer is a DBR, the reflection efficiency may be reduced.

[0015] In some embodiments, the length of the first metal electrode and / or the second metal electrode is 5 μm to 30 μm. When the length is less than 5 μm, especially when the length of the first metal electrode is less than 5 μm, the stability and symmetry of the bonding will be significantly affected by the exposed portion.

[0016] In some embodiments, the distance between the first opening and the sidewall of the mesa is 0.5 μm to 5 μm. The closer the first opening is to the sidewall of the mesa, the more difficult it is to control the first angle in terms of process.

[0017] In some embodiments, in the vertical direction, the height between the first table and the second table is 0.2 μm to 2 μm. The greater the height difference is, the more difficult it is to control the first angle in terms of process.

[0018] In some embodiments, the exposed portion is a non-closed step; three of the four side surfaces of the exposed portion are mesa side walls, and the other side surface is exposed to reserve more light-emitting area.

[0019] In some embodiments, the exposed portion is a non-closed step; the exposed portion is composed of N side surfaces, N is an integer not less than 2, at least one side surface is a table side wall, and at least one side surface is exposed.

[0020] In some embodiments, the first metal electrode covers the second mesa from the exposed portion, and a height h from the first mesa to the upper surface of the passivation layer on the second mesa is 0.5 μm to 3 μm, where the height is a vertical height.

[0021] In some embodiments, the projected area of ​​the back surface of the first metal electrode and / or the second metal electrode is 25 μm 2 Up to 200 μm 2 The smaller the projection area, especially the smaller the projection area of ​​the first metal electrode, the higher the bonding difficulty.

[0022] In some embodiments, the passivation layer covers at least from the first table to the second table, and the passivation layer has a second opening on the second table. The first metal electrode is electrically connected to the first type semiconductor layer through the first opening, and the second metal electrode is electrically connected to the second type semiconductor layer through the second opening. The opening of the passivation layer here refers to a portion of the passivation layer formed by etching away, and a transparent conductive layer is arranged between the second metal electrode and the second type semiconductor layer.

[0023] In some embodiments, the second opening includes a third angle α relative to the horizontal plane. 3 , that is, the inclination angle formed by the passivation layer of the second opening sidewall and the horizontal plane, wherein the third angle α 3 Smaller than the first angle α 1 , where α 3 =(1±30%)*α 2 .

[0024] In some embodiments, α 3 =(1±20%)*α 2 , α 2 Design and α 3 The angle is close, and α is as low as possible 2 angle to achieve better metal electrode production yield.

[0025] In some embodiments, the passivation layer is partially disposed between the second metal electrode and the second type semiconductor layer, the second metal electrode is connected from the second opening to the upper surface of the back side of the passivation layer, the second metal electrode is not disposed between the passivation layer and the second type semiconductor layer, that is, the passivation layer is directly disposed on the second type semiconductor layer, and the second type semiconductor layer, the passivation layer, and the second metal electrode are stacked in sequence, or the second metal electrode is not disposed between the passivation layer and the transparent conductive layer, that is, the passivation layer is directly disposed on the transparent conductive layer, and the second type semiconductor layer, the transparent conductive layer, the passivation layer, and the second metal electrode are stacked in sequence.

[0026] In some embodiments, the thickness of the passivation layer is 0.1 μm to 3 μm. The thicker the passivation layer is, the more difficult it is to form the second opening and the second metal electrode.

[0027] In some embodiments, the first metal electrode is an N-type electrode, and the second metal electrode is a P-type electrode.

[0028] In some embodiments, the exposed portion is in a triangle, rectangle, trapezoid, semi-ellipse, or quasi-semi-ellipse shape, including cases where individual acute angles or obtuse angles are chamfered.

[0029] In some embodiments, when the passivation layer is designed as a DBR, the angle between the sidewall of the mesa and the horizontal plane is a fourth angle α 4 , α 4 When the angle is 30° to 70°, or the passivation layer is a single or double dielectric layer, α 4 70° to 90°.

[0030] In some embodiments, a display device is provided, including a plurality of micro-LEDs and a substrate, wherein the micro-LEDs are arranged on the substrate and have a semiconductor layer sequence, wherein the semiconductor layer sequence includes a back side and a front side, and includes, in sequence from the front side, a first type semiconductor layer and a second type semiconductor layer, with an active layer located therebetween, wherein the back side of the semiconductor layer sequence has an exposed portion, wherein the exposed portion penetrates the second type semiconductor layer and the active layer to expose the first type semiconductor layer, wherein the back side of the semiconductor layer sequence includes a first table within the exposed portion, a second table on the second type semiconductor layer, and a table sidewall located therebetween, wherein a first metal electrode electrically connected to the first type semiconductor layer and a second metal electrode electrically connected to the second type semiconductor layer are arranged on the back side of the semiconductor layer sequence, and further includes a passivation layer covering the semiconductor layer sequence above and / or on the sidewalls, wherein the passivation layer has a first opening on the first table for setting a first metal electrode, wherein the first opening includes a first angle close to the table sidewall and a second angle away from the table sidewall relative to a horizontal plane, and the second angle is smaller than the first angle. In some embodiments, the chromium content of the first metal electrode is set to be greater than that of the second metal electrode, and the length of the second metal electrode is 2μm to 30μm. Metal migration depends on high temperature and high humidity conditions. Under the catalysis of water vapor, ions carrying chromium migrate, and there is a high electric field on the second metal electrode. The chromium of the second metal electrode is more easily migrated than the chromium of the first metal electrode. As the size of the second metal electrode continues to shrink, the metal coating decreases, and chromium leakage is prone to occur. Reducing the chromium of the second metal electrode helps reduce the risk of chromium leakage.

[0031] In some embodiments, the first metal electrode contacts the first type semiconductor layer through chromium, and the second metal electrode does not contain chromium, that is, is not connected to the second type semiconductor layer through chromium, or is not connected to the transparent conductive layer through chromium.

[0032] In some embodiments, the length of the second metal electrode is 5 μm to 30 μm. Increasing the minimum length of the second metal electrode compensates for the loss of adhesion due to the reduction of chromium content and reduces the risk of the second metal electrode falling off.

[0033] In some embodiments, the first metal electrode is completely disposed in the exposed portion, and the exposed portion is a non-closed step; three of the four side surfaces of the exposed portion are exposed, and the other side surface is a mesa sidewall, or two of the four side surfaces of the exposed portion are exposed, and the other two side surfaces are mesa sidewalls.

[0034] In some embodiments, the projected area of ​​the back surface of the first metal electrode and / or the second metal electrode is 25 μm 2 Up to 100 μm 2 The projected area of ​​the back surface of the first layer of the second metal electrode is 30 μm 2 Up to 100 μm2 The area of ​​the first layer of the second metal electrode is increased as much as possible to increase the electrode adhesion.

[0035] In some embodiments, a distance between the first metal electrode and the second metal electrode is 4 μm to 10 μm.

[0036] In some embodiments, the maximum pore size of the first opening is 2 μm to 20 μm, and the maximum pore size of the second opening is 2 μm to 20 μm, where the pore size refers to the diameter of the bottom of the opening, ensuring that the second metal electrode and the second type semiconductor layer have sufficient connection strength to compensate for the loss of adhesion due to the reduction or elimination of chromium content.

[0037] In some embodiments, the passivation layer is disposed between the second metal electrode and the second type semiconductor layer, and the second metal electrode is connected from the second opening to the upper surface of the back side of the passivation layer. The thickness of the passivation layer is 0.1 μm to 3 μm.

[0038] In some embodiments, the back surface of the first metal electrode corresponding to the first opening has a first electrode hole, and the back surface of the second metal electrode corresponding to the second opening has a second electrode hole, wherein the opening area of ​​the first electrode hole is smaller than the opening area of ​​the second electrode hole, thereby increasing the opening area of ​​the second electrode hole. Since the first metal electrode extends from the exposed portion to the second table, the effective area for contact is limited. This embodiment increases the contact area between the second metal electrode and the second type semiconductor layer or the transparent conductive layer on its positive side, and at the same time increases the bonding area when the first metal electrode is bonded to the outside, thereby reducing the risk of bonding detachment.

[0039] In some embodiments, the opening area of ​​the first electrode hole accounts for 10% to 40% of the back surface area of ​​the first metal electrode, and the opening area of ​​the second electrode hole accounts for 15% to 50% of the back surface area of ​​the second metal electrode, thereby increasing the bonding area when the first metal electrode is bonded to the outside and reducing the risk of bonding detachment.

[0040] In some embodiments, the first metal electrode and the second metal electrode have n metal stack layers, n is an integer greater than or equal to 2, the first layer of the first metal electrode is close to the first table side and contains chromium, and is used to connect to the first type semiconductor layer; the first layer of the second metal electrode is close to the second table side and does not contain chromium, and is in contact with a transparent conductive layer, and the transparent conductive layer is electrically connected to the second type semiconductor layer.

[0041] In some embodiments, the length of the first layer of the second metal electrode is greater than 2 μm to 25 μm. The first layer of the second metal electrode serves as a contact layer with the second type semiconductor layer or the transparent conductive layer. The material includes, for example, nickel, aluminum, titanium, platinum, gold or any alloy of the above. The adhesion to the second type semiconductor layer and the transparent conductive layer is lower than that of chromium. Therefore, increasing the length is beneficial to improving the overall adhesion of the second metal electrode.

[0042] In some embodiments, the first layer of the second metal electrode includes titanium, which has relatively high adhesion and is not easy to migrate under an electric field, that is, the second type semiconductor layer, the transparent conductive layer, and the first layer of the second metal electrode are stacked in sequence.

[0043] In some embodiments, the micro-LED is sealed by epoxy resin, and the micro-LED has a semiconductor layer sequence, the semiconductor layer sequence includes a back side and a front side, and includes a first type semiconductor layer and a second type semiconductor layer in sequence from the front side, and an active layer is located between the two. The back side of the semiconductor layer sequence has an exposed portion, and the exposed portion penetrates the second type semiconductor layer and the active layer to expose the first type semiconductor layer. The back side of the semiconductor layer sequence includes a first mesa in the exposed portion, a second mesa on the second type semiconductor layer, and a mesa sidewall located between the two. The back side of the semiconductor layer sequence is provided with a first metal electrode electrically connected to the first type semiconductor layer and a second metal electrode electrically connected to the second type semiconductor layer. The chromium content of the first metal electrode is greater than that of the second metal electrode, and the length of the second metal electrode is 2μm to 30μm. Since the stress of the epoxy resin is large, chromium leakage in the second metal electrode is likely to occur, so reducing or eliminating the chromium content of the first electrode is conducive to improving the product yield.

[0044] In some embodiments, the first metal electrode contacts the first type semiconductor layer through chromium, and the second metal electrode does not contain chromium.

[0045] See also Figure 1 and Figure 2 In the prior art, silicone is usually used as a packaging material. Silicone has a technical effect of low stress. The micro light-emitting diode includes: a semiconductor layer sequence 110, the semiconductor layer sequence 110 has a first type semiconductor layer 111, a first type semiconductor layer 112, an active layer 113 is located therebetween, a first metal electrode 210 is electrically connected to the first type semiconductor layer 111, and a second metal electrode 220 is electrically connected to the first type semiconductor layer 112.

[0046] On the one hand, the passivation layer 300 has a first opening K1 on the first table M1, and the first metal electrode 210 is connected to the passivation layer 300 from the first table M1. Since the distance from the side wall of the exposed portion G1 is too close and the aperture of the first opening K1 is limited, the angle between the first opening K1 and the horizontal plane is too large, the manufacturing difficulty of the first metal electrode 210 increases, and cracks CR are prone to occur.

[0047] On the one hand, in order to replace the existing technology, when the client uses epoxy resin as the packaging material, the stress of the packaging glue increases, causing the chromium in the first layer 221 of the second metal electrode 220 to leak more easily. On the other hand, since the size of the micro-LED chip is micron-level and significantly smaller than the traditional LED chip, the size of the second metal electrode 220 also needs to be continuously reduced. The first layer 221 of the second metal electrode 220 is usually used as a contact layer to provide adhesion. The second layer or above of the second metal electrode 220 is used as a protective layer to cover the first layer 221 of the second metal electrode 220 to prevent the first layer 221 of the second metal electrode 220 from leaking. As the size of the second metal electrode 220 continues to shrink, the coating effect of the second layer 222 of the second metal electrode 220 is reduced, and the first layer 221 of the second metal electrode 220 is more likely to leak.

[0048] See also Figure 3 and Figure 4 In the first embodiment of the present invention, a micro-LED is provided. The micro-LED is rectangular, the short side length of the micro-LED is 10μm to 30μm, and the long side length of the micro-LED is 15μm to 40μm. For example, the size of the micro-LED is 10μm*25μm, and it has a semiconductor layer sequence 110. The semiconductor layer sequence 110 includes a back side and a front side. Starting from the front side, it includes a first type semiconductor layer 111 and a second type semiconductor layer 112 in sequence. The active layer 113 is located between the two. The first type semiconductor layer 111 of the micro-LED is at least partially removed from the front side, for example, after substrate stripping and epitaxial thinning process. In order to improve the light extraction efficiency of the flip chip, the light extraction surface (N-GaN surface) needs to be roughened or patterned. After the COW process is completed, the chip is bonded and laser stripped. Laser stripping is to use a high-photon energy laser to decompose the gallium nitride at the interface between the chip and the sapphire, thereby separating the chip from the substrate. The parameters of the laser light source (spot, power, scanning path) in the laser lift-off process have an important influence on the chip lift-off effect.

[0049] In this embodiment, the first type semiconductor layer 111 is further roughened with a periodic or non-periodic pattern from the front side, and the front side is used as a light-emitting surface to improve light extraction efficiency. The semiconductor layer sequence 110 is based on gallium nitride. The back side of the semiconductor layer sequence 110 has an exposed portion G1, which serves as a Mesa groove and provides a window for making an electrode. The exposed portion G1 penetrates the second type semiconductor layer 112 and the active layer 113, exposing at least the first type semiconductor layer 111, or removing a portion of the first type semiconductor layer 111. The back side of the semiconductor layer sequence 110 includes a first mesa M1 in the exposed portion G1, a second mesa M2 on the second type semiconductor layer 112, and a mesa sidewall S1 located therebetween. The back side of the semiconductor layer sequence 110 is provided with a first mesa M1 connected to the first type semiconductor layer 111. The semiconductor layer sequence 110 includes a first metal electrode 210 connected to the semiconductor layer 110 and a second metal electrode 220 electrically connected to the second type semiconductor layer 112, and further includes a passivation layer 300 covering the semiconductor layer sequence 110 and / or the sidewall thereof, wherein the passivation layer 300 is partially disposed on the first table M1, and the passivation layer M1 has a first opening K1 for arranging the first metal electrode 210, and the first metal electrode 210 is connected to the passivation layer 300 along the sidewall of the first opening K1, and further connected from the passivation layer 300 to the second table M2, and the first opening K1 includes a first angle α close to the table sidewall S1 relative to the horizontal plane. 1 and a second angle α away from the mesa sidewall S1 2 , the second angle α 2 The angle α1 is smaller than the first angle α1 . Here, the opening of the passivation layer 300 is formed by removing a portion of the passivation layer 300 by etching. The exposed portion G1 is, for example, a groove or a step with an exposed side.

[0050] In some implementations of this embodiment, the length L1 of the first metal electrode 210 and the length L2 of the second metal electrode 220 are 5 μm to 30 μm.

[0051] In some implementations of this embodiment, the projection area of ​​the back surface of the first metal electrode 210 and / or the second metal electrode 220 is 25 μm 2 Up to 100 μm 2 .

[0052] In some implementations of this embodiment, the exposed portion G1 is a non-closed step; three of the four side surfaces of the exposed portion are mesa side walls, and the three surfaces are composed of an arc surface relative to the middle and side surfaces arranged on both sides of the arc surface. The side surfaces on both sides can be planes or arc surfaces, and the other side surface is exposed to retain more light-emitting area. In this embodiment, the exposed portion G1 is semi-elliptical or semi-elliptical, and the area of ​​the active layer 113 is retained as much as possible. The opening direction of the semi-elliptical or semi-elliptical shape is parallel to the long side direction of the chip rectangle. In this embodiment, the symmetric central axis of the exposed portion G1 is parallel to the symmetric central axis of the long side direction of the chip rectangle, so as to improve the symmetry of the bonding surface of the first metal electrode 210 and improve the reliability of bonding with the external circuit.

[0053] In some implementations of this embodiment, in the vertical direction, the height of the first mesa M1 from the second mesa M2 is 0.2 μm to 2 μm. The first metal electrode 210 covers the second mesa M2 from the exposed portion G1, and the height h from the first mesa M1 to the upper surface of the passivation layer 300 on the second mesa M2 is 0.5 μm to 3 μm. For the sake of clarity, the height h from the first mesa M1 to the upper surface of the passivation layer 300 on the second mesa M2 is the vertical height.

[0054] In some implementations of the present embodiment, the passivation layer 300 is partially disposed between the second metal electrode 220 and the second type semiconductor layer 112, the second metal electrode 220 is connected from the second opening K2 to the upper surface of the back side of the passivation layer 300, and the second metal electrode 220 is not disposed between the passivation layer 300 and the second type semiconductor layer 112, that is, the passivation layer 300 is directly disposed on the second type semiconductor layer 112, and the second type semiconductor layer 112, the passivation layer 300, and the second metal electrode 220 are stacked in sequence, or the second metal electrode 220 is not disposed between the passivation layer 300 and the transparent conductive layer 400, that is, the passivation layer 300 is directly disposed on the transparent conductive layer 400, and the second type semiconductor layer 112, the transparent conductive layer 400, the passivation layer 300 and the second metal electrode 220 are stacked in sequence.

[0055] In some implementations of this embodiment, when viewed in the vertical projection direction, the first platform M1 and the second platform M2 are combined into a rectangle, and the single side size of the second platform M2 is 5 μm to 35 μm. Experiments have shown that the rectangle helps to improve the current density of the product at a small size, thereby improving the brightness of the product.

[0056] In this embodiment, the second mesa M2 is located on a side of the first type semiconductor layer 112 away from the active layer 113, a passivation layer 300 is provided on the second mesa M2, the passivation layer 300 covers at least from the second mesa M2 to the first mesa M1, the passivation layer 300 has a first opening K1 on the first mesa M1, the passivation layer 300 has a second opening K2 on the second mesa M2, the first metal electrode 210 is electrically connected to the first type semiconductor layer 111 through the first opening K1, the second metal electrode 220 is electrically connected to the first type semiconductor layer 112 through the second opening K2, and the maximum aperture of the second opening K2 is 2 μm to 20 μm. A transparent conductive layer 400 is provided between the second metal electrode 220 and the first type semiconductor layer 112.

[0057] The material of the passivation layer 300 includes: silicon dioxide, silicon nitride, aluminum oxide or titanium oxide, and the passivation layer 300 is composed of a single layer, a double layer or a multilayer. The passivation layer 300 mainly serves the purpose of electrical insulation. In some cases, a DBR structure can also be used to increase the reflected light. The passivation layer 300 is arranged between the second metal electrode 220 and the first type semiconductor layer 112, and the second metal electrode 220 is connected from the second opening K2 to the upper surface of the back side of the passivation layer 300. The thickness of the passivation layer 300 is 0.1μm to 3μm. For example, when the thickness of the passivation layer 300 is 0.5μm to 3μm, the difficulty of controlling the angle of the first opening K1 increases significantly. In this embodiment, the second metal electrode 220 is not arranged between the passivation layer 300 and the first type semiconductor layer 112, or the second metal electrode 220 is not arranged between the passivation layer 300 and the transparent conductive layer 400.

[0058] In this embodiment, the distance d1 between the first opening K1 and the mesa sidewall S1 is 0.5 μm to 5 μm, where the distance refers to the minimum distance between the bottom of the first opening K1 and the bottom of the mesa sidewall S1. The closer the distance is, the more difficult it is to make the first opening K1 in the passivation layer 300. 2 Far away from the side wall S1 of the table, it will not be restricted by the side wall S1 of the table, and the difficulty of adjusting the angle size is low. By reducing the second angle α on the side away from the side wall S1 of the table 2 , reducing the probability of abnormality of the first metal electrode 210, the first angle α 1 The second angle α 2 1.05 to 5 times of the first angle α. The angle here mainly refers to the angle between the side of the passivation layer 300 and the horizontal plane. When the relevant multiple is less than 1.05 times, the yield of the first metal electrode 210 is limited. 1 is 60° to 90°, the second angle α 2 15° to 75°.

[0059] As much as possible, the second angle α 2 Designed to be equal to the first angle α 1 To improve the process consistency, the second opening K2 includes a third angle α relative to the horizontal plane. 3 , that is, the inclination angle formed by the passivation layer on the side wall of the second opening K2 and the horizontal plane, wherein the third angle α 3 Smaller than the first angle α 1 , where α 3 =(1±30%)*α 2 , further, α 3 =(1±20%)*α 2 .

[0060] See also Figure 5In the second embodiment of the present invention, a micro-light-emitting diode is provided. The main difference from the first embodiment is that the exposed side of the exposed portion G1 is rotated from the side close to the short side of the chip to the side close to the long side of the chip. In this embodiment, the first opening K1 deviates from the central axis of the long side direction, and is close to the long side of the exposed side relative to the central axis of the long side direction. Correspondingly, in order to ensure the reliability of bonding, the second opening K2 deviates from the central axis of the long side direction, and is far away from the long side of the exposed side relative to the central axis of the long side direction. The first opening K1 and the second opening K2 are symmetrically arranged relative to the central axis of the short side direction of the chip rectangle.

[0061] See also Figure 6 In the third embodiment of the present invention, a micro-LED is provided. The main difference from the first embodiment is that the exposed portion G1 is a non-closed step; the exposed portion G1 is composed of N side surfaces, N is an integer not less than 2, at least one side surface is a mesa side wall, and at least one side surface is exposed. Taking this embodiment as an example, the exposed portion G1 is composed of four side surfaces, two of which are mesa side walls. In this embodiment, the exposed portion G1 is a rectangle or a quasi-rectangle with chamfers.

[0062] In some implementations of this embodiment, the exposed portion G1 may also be designed to be a triangle, a rectangle, or a trapezoid.

[0063] See also Figure 7 In the fourth embodiment of the present invention, a micro light emitting diode is provided. The main difference from the first embodiment is that in the first embodiment, when the passivation layer 300 can be a single-layer or double-layer dielectric layer, α 4 In this embodiment, when the passivation layer 300 is designed as a DBR, in order to improve the reflection efficiency and the DBR coating quality, the angle between the mesa side wall S1 and the horizontal plane is set to a fourth angle α 4 , relative to the designed gentle slope, α 4 is between 30° and 70°, if α 4 Less than 30° will also result in loss of luminous area. 4 If the angle is greater than 70°, the DBR reflection effect decreases.

[0064] See also Figure 8In the fifth embodiment of the present invention, a first metal electrode 210 electrically connected to the first type semiconductor layer 111 and a second metal electrode 220 electrically connected to the first type semiconductor layer 112 are provided on the back side of the semiconductor layer sequence 110, and the chromium content of the first metal electrode 210 is greater than that of the second metal electrode 220. The first metal electrode 210 and the second metal electrode 220 are used for bonding with an external power source, and the length of the second metal electrode 220 is 2μm to 30μm. In this embodiment, the first type semiconductor layer 111 is an N-type semiconductor layer, the first type semiconductor layer 112 is a P-type semiconductor layer, the first metal electrode 210 is an N-type electrode, and the second metal electrode 220 is a P-type electrode. The difference from the first embodiment is that the second metal electrode 220 is not plated with chromium metal in the process, for example, the chromium content of the second metal electrode 220 is zero. The spacing between the first metal electrode 210 and the second metal electrode 220 is 4μm to 10μm.

[0065] In this embodiment, the first metal electrode 210 extends from the exposed portion G1 to the second mesa M2 on the first type semiconductor layer 112. Two of the four side surfaces of the exposed portion G1 are exposed, and the other two side surfaces are the side walls S1 of the exposed portion G1. The height of the side walls S1 of the exposed portion G1 is 0.5 μm to 2 μm.

[0066] In some implementations of this embodiment, the first metal electrode 210 is completely disposed in the exposed portion G1, and the exposed portion G1 is a non-closed step; three of the four side surfaces of the exposed portion G1 are exposed, and the other side surface is the side wall S1 of the exposed portion G1. The second mesa M2 is located on the side of the first type semiconductor layer 112 away from the active layer 113, and a passivation layer 300 is disposed on the second mesa M2. The passivation layer 300 covers at least from the first mesa M1 to the second mesa M2. The passivation layer 300 has a first opening K1 on the first mesa M1, and the passivation layer 300 has a second opening K2 on the second mesa M2. The first metal electrode 210 is electrically connected to the first type semiconductor layer 111 through the first opening K1, and the second metal electrode 220 is electrically connected to the first type semiconductor layer 112 through the second opening K2. The maximum aperture of the second opening K2 is 2 μm to 20 μm. A transparent conductive layer 400 is disposed between the second metal electrode 220 and the first type semiconductor layer 112.

[0067] In this embodiment, the back surface of the first metal electrode 210 corresponding to the first opening K1 has a first electrode hole K11, and the back surface of the second metal electrode 220 corresponding to the second opening K2 has a second electrode hole K12, wherein the opening area of ​​the first electrode hole K11 is smaller than the opening area of ​​the second electrode hole K12. The opening area of ​​the first electrode hole K11 accounts for 10% to 40% of the back surface area of ​​the first metal electrode 210, and the opening area of ​​the second electrode hole K12 accounts for 15% to 50% of the back surface area of ​​the second metal electrode 220. It should be noted that, due to the different shapes of the exposed portion G1, the first electrode hole K11 is caused by the first opening K2 and the exposed portion G1, and there may be no completely closed boundary, and sufficient bonding area is required, which does not affect the implementation of this embodiment.

[0068] See also Fig. 9 In the sixth embodiment of the present invention, the difference from the fifth embodiment is that the first metal electrode 210 and the second metal electrode 220 have n metal stacks, n is an integer greater than or equal to 2, the first layer 211 of the first metal electrode 210 is close to the first mesa M1 side and contains chromium, and is used to connect with the first type semiconductor layer 111; the first layer 221 of the second metal electrode 220 is close to the second mesa M2 side and does not contain chromium, and is in contact with a transparent conductive layer 400, and the transparent conductive layer 400 is electrically connected to the first type semiconductor layer 112. In this embodiment, the first type semiconductor layer 111 is an N-type semiconductor layer, the first type semiconductor layer 112 is a P-type semiconductor layer, the first metal electrode 210 is an N-type electrode, and the second metal electrode 220 is a P-type electrode.

[0069] The length L21 of the first layer 221 of the second metal electrode 220 is greater than 2 μm to 25 μm. The first layer 221 of the second metal electrode 220 serves as a contact layer with the first type semiconductor layer 112 or the transparent conductive layer 400. The material includes, for example, nickel, aluminum, titanium, platinum, gold or any alloy of the above. The adhesion to the first type semiconductor layer 112 and the transparent conductive layer 400 is lower than that of chromium. Therefore, increasing the length is beneficial to improving the overall adhesion of the second metal electrode 220. In this embodiment, titanium is preferably used for the first layer 221 of the second metal electrode 220. The transparent conductive layer 400 is, for example, ITO. In this embodiment, the length of the first layer 221 of the second metal electrode 220 refers to the longest dimension.

[0070] In some implementations of this embodiment, the projection area of ​​the back surface of the first layer 221 of the second metal electrode 220 is 30 μm 2 Up to 100 μm 2 The area of ​​the first layer 221 of the second metal electrode 220 is increased as much as possible to increase the electrode adhesion.

[0071] See also Fig.10 In a seventh embodiment of the present invention, a display device is provided, which is sealed by the micro-LED of the fifth embodiment or the sixth embodiment, wherein the micro-LED C1 is sealed by an epoxy resin P1, and the micro-LED C1 is bonded and fixed on a substrate 500, and has a semiconductor layer sequence 110, wherein the semiconductor layer sequence 110 includes a back side and a front side, and includes a first type semiconductor layer 111 and a first type semiconductor layer 112 in sequence from the front side, and an active layer 113 is located therebetween, and the back side of the semiconductor layer sequence 110 has an exposed portion G1, and the exposed portion G1 penetrates the first type semiconductor layer 112. , an active layer 113, exposing the first type semiconductor layer 111, the back side of the semiconductor layer sequence 110 includes a first table M1 in the exposed portion G1, a second table M2 on the first type semiconductor layer 112 and a side wall S1 of the exposed portion G1 located therebetween, and a first metal electrode 210 electrically connected to the first type semiconductor layer 111 and a second metal electrode 220 electrically connected to the first type semiconductor layer 112 are disposed on the back side of the semiconductor layer sequence 110, the chromium content of the first metal electrode 210 is greater than that of the second metal electrode 220, and the length of the second metal electrode 220 is 2μm to 30μm. Since the stress of the epoxy resin P1 is relatively large, the chromium leakage in the second metal electrode 220 is likely to occur, so reducing or eliminating the chromium content of the first electrode is conducive to improving the product yield, and effectively improving the performance and yield of the overall display device.

[0072] In the eighth embodiment of the present invention, a display device is provided, which is different from the sixth embodiment in that the micro-LED chip of the second embodiment is used, the first metal electrode 210 contacts the first type semiconductor layer 111 through the first layer 211 of the first metal electrode, and the first layer 221 of the second metal electrode 220 does not contain chromium. Thus, the performance and yield of the overall display device are improved.

[0073] In the ninth embodiment of the present invention, the difference from the seventh embodiment is that a display device is provided, which adopts the micro-LED chips of the first to fourth embodiments.

[0074] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A micro light emitting diode, comprising a semiconductor layer sequence, the semiconductor layer sequence comprising a back side and a front side, and comprising a first type semiconductor layer and a second type semiconductor layer in sequence from the front side, with an active layer located therebetween, the back side of the semiconductor layer sequence having an exposed portion, the exposed portion penetrating the second type semiconductor layer and the active layer, exposing at least the first type semiconductor layer, the back side of the semiconductor layer sequence comprising a first mesa in the exposed portion, a second mesa on the second type semiconductor layer, and a mesa sidewall located therebetween, the back side of the semiconductor layer sequence being provided with a first metal electrode electrically connected to the first type semiconductor layer and a second metal electrode electrically connected to the second type semiconductor layer, and further comprising a passivation layer covering the semiconductor layer sequence and / or the sidewalls, characterized in that: The passivation layer is partially disposed on the first table, and has a first opening for disposing a first metal electrode. The first opening comprises a first angle α1 close to the table sidewall and a second angle α2 away from the table sidewall relative to a horizontal plane, and the second angle α2 is smaller than the first angle α1.

2. A micro light emitting diode according to claim 1, characterized in that: The first angle α1 is 1.05 to 5 times the second angle α2.

3. The micro light emitting diode according to claim 1, characterized in that: The first angle α1 is 60° to 90°, and the second angle α2 is 15° to 75°.

4. The micro light emitting diode according to claim 1, characterized in that: The length of the first metal electrode and / or the second metal electrode is 5 μm to 30 μm.

5. The micro light emitting diode according to claim 1, characterized in that: The first opening is at a distance of 0.5 μm to 5 μm from the side wall of the mesa.

6. The micro light emitting diode according to claim 1, characterized in that: In the vertical direction, the height between the first mesa and the second mesa is 0.2 μm to 2 μm.

7. The micro light emitting diode according to claim 1, characterized in that: The exposed portion is a non-closed step; the exposed portion is composed of N side surfaces, N is an integer not less than 2, at least one side surface is a table side wall, and at least one side surface is exposed.

8. The micro light emitting diode according to claim 1, characterized in that: The exposed portion is in the shape of a triangle, a rectangle, a trapezoid, a semi-ellipse or a quasi-semi-ellipse.

9. The micro light emitting diode according to claim 1, characterized in that: The exposed part is an unclosed step; three of the four sides of the exposed part are table side walls, and the other side is bare.

10. The micro light emitting diode according to claim 1, characterized in that: The first metal electrode covers the second mesa from the exposed portion, and a height h from the first mesa to the upper surface of the passivation layer on the second mesa is 0.5 μm to 3 μm.

11. The micro light emitting diode according to claim 1, characterized in that: The projected area of ​​the back surface of the first metal electrode and / or the second metal electrode is 25 μm 2 Up to 200 μm 2 .

12. The micro light emitting diode according to claim 1, characterized in that: The passivation layer covers at least from the first table to the second table, and the passivation layer has a second opening on the second table. The first metal electrode is electrically connected to the first type semiconductor layer through the first opening, and the second metal electrode is electrically connected to the second type semiconductor layer through the second opening. A transparent conductive layer is arranged between the second metal electrode and the second type semiconductor layer.

13. The micro light emitting diode according to claim 12, characterized in that: The second opening includes a third angle α3 relative to the horizontal plane, and the third angle α3 is smaller than the first angle α1, wherein α3 is (1±30%)*α2.

14. The micro light emitting diode according to claim 12, characterized in that: The maximum pore size of the first opening is 2 μm to 20 μm, and the maximum pore size of the second opening is 2 μm to 20 μm.

15. The micro light emitting diode according to claim 12, characterized in that: The passivation layer is partially arranged between the second metal electrode and the second type semiconductor layer, the second metal electrode is connected from the second opening to the upper surface of the back side of the passivation layer, the second metal electrode is not arranged between the passivation layer and the second type semiconductor layer, or the second metal electrode is not arranged between the passivation layer and the transparent conductive layer.

16. The micro light emitting diode according to claim 1, characterized in that: The thickness of the passivation layer is 0.1 μm to 3 μm.

17. The micro light emitting diode according to claim 1, characterized in that: The passivation layer is a distributed Bragg reflection layer with a multi-layer structure.

18. The micro light emitting diode according to claim 1, characterized in that: The first metal electrode is an N-type electrode, and the second metal electrode is a P-type electrode.

19. The micro light emitting diode according to claim 1, characterized in that: The angle between the side wall of the table top and the horizontal plane is a fourth angle α4, and α4 is 30° to 70° or α4 is 70° to 90°.

20. A display device, comprising a plurality of micro-LEDs and a substrate, wherein the micro-LEDs are arranged on the substrate and have a semiconductor layer sequence, wherein the semiconductor layer sequence comprises a back side and a front side, and comprises a first type semiconductor layer and a second type semiconductor layer in sequence from the front side, with an active layer located therebetween, wherein the back side of the semiconductor layer sequence comprises an exposed portion, wherein the exposed portion penetrates the second type semiconductor layer and the active layer to expose the first type semiconductor layer, wherein the back side of the semiconductor layer sequence comprises a first table in the exposed portion, a second table on the second type semiconductor layer and a table side wall located therebetween, wherein a first metal electrode electrically connected to the first type semiconductor layer and a second metal electrode electrically connected to the second type semiconductor layer are arranged on the back side of the semiconductor layer sequence, and further comprises a passivation layer covering the semiconductor layer sequence and / or the side wall, wherein the device is characterized in that: The passivation layer has a first opening on the first table for arranging a first metal electrode. The first opening comprises a first angle α1 close to the table sidewall and a second angle α2 away from the table sidewall relative to a horizontal plane. The second angle α2 is smaller than the first angle α1.

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