Display panel and display device

Abstract

The display panel and the display device are used for avoiding poor display of bright stripes. The display panel comprises a substrate which comprises a hole area and a display area; the hole region comprises a light-transmitting region and a wiring region; a plurality of data lines including a first data line; the first data line and the light-transmitting area are not overlapped, the first data line comprises a first wiring part, the first wiring part of at least part of the first data line penetrates through the wiring area, and the first wiring part of at least part of the first data line extends non-linearly; a part of the first wiring part comprises a first sub-wiring, and a part of the first wiring part comprises a second sub-wiring; the first sub-wires and the second sub-wires are alternately arranged, the shielding structure is overlapped with the first sub-wires and / or the second sub-wires, and the shielding structure is located on a film layer between the first sub-wires and the second sub-wires; or at least partial areas of the orthographic projections of the plurality of first sub-wires on the substrate are located on the sides, facing or far away from the light-transmitting area, of at least partial areas of the orthographic projections of the plurality of second sub-wires on the substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In recent years, as people pursue higher and higher screen-to-body ratios, full-screen technology has developed rapidly. At present, the mainstream solution for under-screen cameras in full-screen technology is to dig a hole in the display area to place the camera. However, when the display area is opened, some data lines need to be bent and wound around the hole, which increases the length of the data line and the parasitic capacitance, and easily causes poor display of bright stripes, affecting the user experience. Summary of the invention

[0003] Embodiments of the present disclosure provide a display panel and a display device to avoid poor display due to bright stripes.

[0004] An embodiment of the present disclosure provides a display panel, the display panel comprising:

[0005] The substrate comprises: at least one hole area, a display area surrounding the at least one hole area, and a peripheral area surrounding the display area; the hole area comprises: a light-transmitting area and a wiring area located between the display area and the light-transmitting area;

[0006] A plurality of data lines, at least located in the display area; the plurality of data lines: including a plurality of first data lines; the orthographic projections of the plurality of first data lines on the base substrate do not overlap with the light-transmitting area, the first data lines include first routing portions, the orthographic projections of at least some of the first routing portions of the first data lines on the base substrate pass through the wiring area, and at least some of the first routing portions of the first data lines extend non-linearly; some of the first routing portions of the plurality of first data lines include first sub-routings, and some of the first routing portions of the plurality of first data lines include second sub-routings located on a different layer from the first sub-routings;

[0007] Among them, the orthographic projections of the first sub-routes and the second sub-routes on the substrate are arranged alternately, and the display panel also includes multiple shielding structures, the orthographic projections of the shielding structures on the substrate overlap with the orthographic projections of the first sub-routes and / or the second sub-routes on the substrate, and the shielding structures are located in the film layer between the first sub-routes and the second sub-routes; or, at least part of the orthographic projections of the multiple first sub-routes on the substrate are located on the side of at least part of the orthographic projections of the multiple second sub-routes on the substrate facing or away from the light-transmitting area.

[0008] In some embodiments, a plurality of shielding structures are disposed on the same layer, and an orthographic projection of the shielding structure on the substrate covers an orthographic projection of the first sub-line or the second sub-line on the substrate.

[0009] In some embodiments, the plurality of shielding structures include: a plurality of first shielding structures disposed on the same layer, a plurality of second shielding structures disposed on the same layer and located on different layers from the first shielding structures;

[0010] The orthographic projection of the first shielding structure on the substrate covers the orthographic projection of the first sub-line on the substrate, and the orthographic projection of the second shielding structure on the substrate covers the orthographic projection of the second sub-line on the substrate.

[0011] In some embodiments, the second sub-route is located on a side of the first sub-route away from the substrate, and the first shielding structure is located on a side of the second shielding structure away from the substrate.

[0012] In some embodiments, the minimum distance between the surface of at least part of the shielding structure close to the substrate substrate and the substrate substrate is smaller than the distance between the surface of the first sub-route away from the substrate substrate and the substrate substrate; and the surface of at least part of the shielding structure close to the substrate substrate has a groove that is recessed toward the side away from the substrate substrate, and the orthographic projection of the first sub-route on the substrate substrate is located within the orthographic projection of the groove on the substrate substrate.

[0013] In some embodiments, the display panel further includes a plurality of pixel driving units; the pixel driving unit includes: at least one thin film transistor, at least one capacitor, and a switching electrode located on a side of the thin film transistor away from the substrate and electrically connected to the thin film transistor; the display panel specifically includes:

[0014] A first conductive layer, including a gate of a thin film transistor, a first electrode of a capacitor, and at least a portion of a first sub-wire;

[0015] A second conductive layer is located on a side of the first conductive layer away from the substrate; the second conductive layer includes a second electrode of the capacitor;

[0016] A third conductive layer is located on a side of the second conductive layer away from the substrate; the third conductive layer includes at least one of a source electrode and a drain electrode of the thin film transistor;

[0017] The fourth conductive layer is located on a side of the third conductive layer away from the base substrate; the fourth conductive layer includes a portion of the data line located in the display area and at least a portion of the second sub-line.

[0018] In some embodiments, the plurality of first sub-routes are all located in the first conductive layer, the plurality of second sub-routes are all located in the fourth conductive layer, and the second conductive layer and / or the third conductive layer further include a shielding structure.

[0019] In some embodiments, the display panel further includes: a light emitting device electrically connected to the pixel driving unit, a power supply voltage signal line, an initialization signal line, and a first level signal line; the light emitting device includes a stacked anode, a light emitting functional layer, and a cathode, the anode is electrically connected to the drain through the switching electrode, the power supply voltage signal line and the initialization signal line are electrically connected to the pixel driving unit, and the cathode is electrically connected to the first level signal line;

[0020] The plurality of shielding structures are electrically connected to at least one of the first level signal line, the power supply voltage signal line, and the initialization signal line.

[0021] In some embodiments, at least a portion of the orthographic projections of the plurality of first sub-routes on the substrate substrate are located on a side of at least a portion of the orthographic projections of the plurality of second sub-routes on the substrate substrate that faces toward or away from the light-transmitting region;

[0022] The plurality of first sub-routes are located in different layers, and the first sub-routes located in different layers are arranged alternately in orthographic projection on the substrate;

[0023] The plurality of second sub-routes are located in different layers, and the second sub-routes located in different layers are arranged alternately in the orthographic projection of the substrate.

[0024] In some embodiments, the display panel further comprises:

[0025] The third shielding structure is located in at least one of the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer; at least a partial area of ​​the orthographic projection of the third shielding structure on the substrate is located in the wiring area between the orthographic projection of the plurality of first sub-routes on the substrate and the orthographic projection of the plurality of second sub-routes on the substrate.

[0026] In some embodiments, the display panel includes multiple sub-pixel columns, each sub-pixel column includes multiple sub-pixels; each sub-pixel column is electrically connected to at least one data line; among the two adjacent sub-pixel columns electrically connected to the first data line, one column of the sub-pixel columns is electrically connected to the first data line including the first sub-route, and the other column of the sub-pixel columns is electrically connected to the first data line including the second sub-route.

[0027] In some embodiments, the display panel further comprises:

[0028] A multi-way selection circuit is electrically connected to a plurality of data lines; the multi-way selection circuit comprises: a plurality of data input lines, a plurality of multi-way selection units and m multi-way selection control lines; each multi-way selection unit comprises m switch units; the control ends of the m switch units are electrically connected to the m multi-way selection control lines in a one-to-one correspondence, the input ends of the m switch units are electrically connected to the n data input lines, and the output ends of the switch units are electrically connected to the data lines; wherein m is an integer greater than 1, and n is a positive integer; the first sub-routing and the second sub-routing are electrically connected to different multi-way selection control lines.

[0029] In some embodiments, m=2, n=1; or, m=4, n=1.

[0030] In some embodiments, the plurality of data lines further include: a plurality of second data lines, the orthographic projections of the plurality of second data lines on the base substrate do not overlap with at least one hole area, and the length of the first data line is greater than that of the second data line.

[0031] A display device provided by an embodiment of the present disclosure includes a display panel provided by an embodiment of the present disclosure.

[0032] In the display panel and display device provided by the embodiments of the present disclosure, when the first sub-routing and the second sub-routing are arranged alternately, a shielding structure of the film layer between the first sub-routing and the second sub-routing is provided, and the orthographic projection of the shielding structure on the substrate substrate overlaps with the orthographic projection of at least one of the first sub-routing and the second sub-routing on the substrate substrate, thereby reducing the parasitic capacitance between the first sub-routing and the second sub-routing. Alternatively, at least part of the orthographic projection of the plurality of first sub-routing on the substrate substrate is located on the side of at least part of the orthographic projection of the plurality of second sub-routing on the substrate substrate facing or away from the light-transmitting area, so that the first sub-routing and the second sub-routing are no longer arranged alternately, and the parasitic capacitance between the first sub-routing and the second sub-routing can be reduced. Since the parasitic capacitance between the first sub-routing and the second sub-routing is reduced, the voltage jump on the first data line can be reduced, and the poor display of bright stripes caused by uneven brightness can be avoided, thereby improving the display effect and user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present disclosure;

[0035] Figure 2 A method provided in the embodiment of the present disclosure includes Figure 1 Schematic diagram of the enlarged structure of the E1 region;

[0036] Figure 3 Another embodiment provided by the present disclosure includes Figure 1 Schematic diagram of the enlarged structure of the E1 region;

[0037] Figure 4 A schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure;

[0038] Figure 5 A timing diagram of a display panel provided in an embodiment of the present disclosure;

[0039] Figure 6 A timing diagram of another display panel provided in an embodiment of the present disclosure;

[0040] Figure 7 A schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure;

[0041] Figure 8 A schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure;

[0042] Fig. 9 A schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure;

[0043] Fig.10 A schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure;

[0044] Fig.11 A schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure;

[0045] Fig.12 A schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure;

[0046] Fig.13 A schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure;

[0047] Fig.14 A schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure;

[0048] Fig.15 A schematic diagram of the structure of another display panel provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present disclosure.

[0050] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0051] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, and are only intended to illustrate the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0052] In the related art, a hole is dug in the display area of ​​the display panel to place the camera. However, when the opening is set in the display area, some data lines need to be bent and wound around the opening, which increases the length of the data line and the parasitic capacitance. The voltage loaded on the data line is divided into a data writing stage and a floating stage. The voltage on the data line in the floating stage lasts until the next data writing stage starts. The voltage on the data line in the floating stage is easily interfered by other jumping signals. If the parasitic capacitance on the adjacent data lines is too large, the voltage jump on any data line will cause the voltage jump on the adjacent data line. If the data line is coupled while the row scan signal is at a low level, the sub-pixel will also be affected by the coupling, resulting in uneven brightness of the sub-pixel, and poor display of bright stripes is likely to occur, affecting the user experience.

[0053] The present disclosure provides a display panel. Figure 1 , Figure 2 , Figure 3 As shown, the display panel includes:

[0054] The base substrate 1 comprises: at least one hole area HL, a display area AA surrounding the at least one hole area HL, and a peripheral area NA surrounding the display area AA; the hole area HL comprises: a light-transmitting area HL1 and a wiring area HL2 located between the display area AA and the light-transmitting area HL1;

[0055] A plurality of data lines 2, at least located in the display area AA; the plurality of data lines 2: including a plurality of first data lines 201; the orthographic projections of the plurality of first data lines 201 on the substrate 1 do not overlap with the light-transmitting area HL1, the first data lines 201 include a first routing portion 3, the orthographic projections of at least a portion of the first routing portion 3 of the first data lines 201 on the substrate 1 pass through the wiring area HL2, and at least a portion of the first routing portion 3 of the first data lines 201 extend non-linearly; that is, the first data lines 201 are data lines 2 located near the light-transmitting area HL1, and at least a portion of the first data lines 201 need to be provided with a non-linearly extending first routing portion 3 to avoid the light-transmitting area HL1 of the hole area HL; a portion of the first routing portion 3 in the plurality of first data lines 201 includes a first sub-routing 301, and a portion of the first routing portion 3 in the plurality of first data lines 201 includes a second sub-routing 302 located at a different layer from the first sub-routing 301;

[0056] Among them, Figure 2 As shown, the orthographic projections of the first sub-routing 301 and the second sub-routing 302 on the base substrate 1 are alternately arranged, and the display panel further includes a plurality of shielding structures 4, the orthographic projections of the shielding structures 4 on the base substrate 1 overlap with the orthographic projections of the first sub-routing 301 and / or the second sub-routing 302 on the base substrate 1, and the shielding structures 4 are located in the film layer between the first sub-routing 301 and the second sub-routing 302; or, as Figure 3 As shown, at least a portion of the orthographic projections of the plurality of first sub-routes 301 on the substrate 1 are located on a side of at least a portion of the orthographic projections of the plurality of second sub-routes 302 on the substrate 1 that faces toward or away from the light-transmitting area HL1 .

[0057] It should be noted that Figure 1 In the description, the hole area HL is rectangular and the light-transmitting area HL1 is circular, and the center of the rectangle coincides with the center of the circle. In a specific implementation, the hole area HL and the light-transmitting area HL1 may both be circular, and the centers of the two circles coincide. Figure 2 For a Figure 1 A magnified schematic diagram of the E1 region in the middle. Figure 3 For another including Figure 1 Schematic diagram of the enlarged E1 region. Figure 2 For example, the first wiring portion 3 located in the wiring area HL2 closest to the display area AA extends in a straight line, and the other first wiring portions 3 extend in a non-straight line. Figure 3 The following description is made by taking the example that the first wiring portions 3 located in the wiring area HL2 all extend in a non-linear manner.

[0058] In the display panel provided by the embodiment of the present disclosure, when the first sub-route and the second sub-route are arranged alternately, a shielding structure of the film layer between the first sub-route and the second sub-route is provided, and the orthographic projection of the shielding structure on the substrate substrate overlaps with the orthographic projection of at least one of the first sub-route and the second sub-route on the substrate substrate, thereby reducing the parasitic capacitance between the first sub-route and the second sub-route. Alternatively, at least part of the orthographic projection of the plurality of first sub-routes on the substrate substrate is located on the side of at least part of the orthographic projection of the plurality of second sub-routes on the substrate substrate facing or away from the light-transmitting area, so that the first sub-route and the second sub-route are no longer arranged alternately, and the parasitic capacitance between the first sub-route and the second sub-route can be reduced. Since the parasitic capacitance between the first sub-route and the second sub-route is reduced, the voltage jump on the first data line can be reduced, and the poor display of bright stripes caused by uneven brightness can be avoided, thereby improving the display effect and user experience.

[0059] In addition, in the display panel provided by the embodiment of the present disclosure, since the wiring space in the wiring area is small, the multiple first data lines include parts located in different layers. When the first sub-routes and the second sub-routes located in different layers are arranged alternately, it is beneficial to reduce the distance between adjacent first data lines while avoiding short circuits between adjacent first data lines, thereby saving wiring space.

[0060] In some embodiments, Figure 2 , Figure 3 As shown, the first sub-route 301 or the second sub-route 302 of the non-linearly extending first routing portion 3 is arc-shaped, and the non-linearly extending first routing portion 3 also includes a straight or zigzag portion electrically connected to the arc-shaped first sub-route 301 or the second sub-route 302. In some embodiments, the first sub-route 301 or the second sub-route 302 may also be a pattern composed of zigzag segments with an outline approximating an arc shape.

[0061] In some embodiments, Figure 2 , Figure 3 As shown, the plurality of data lines 2 further include: a plurality of second data lines 202, the orthographic projections of the second data lines 202 on the substrate 1 do not overlap with at least one hole area HL, that is, the second data lines 202 do not pass through the wiring area HL2, and the length of the first data line 201 is greater than the length of the second data line 202;

[0062] The display panel includes a plurality of sub-pixel columns 6 , each of which includes a plurality of sub-pixel columns 7 ; the plurality of sub-pixel columns 6 are arranged along a first direction X, and the plurality of sub-pixel columns 7 are arranged along a second direction Y; and each sub-pixel column 6 is electrically connected to at least one data line 2 .

[0063] In some embodiments, Figure 2 , Figure 3As shown, the plurality of sub-pixel columns 6 include a plurality of first sub-pixel columns 601 and a plurality of second sub-pixel columns 602;

[0064] In the second direction Y, at least part of the sub-pixels 7 in the second sub-pixel column 602 are located on one side of the hole area HL; the number of sub-pixels 7 included in the second sub-pixel column 602 is greater than the number of sub-pixels 7 included in the first sub-pixel column 601; that is, the first sub-pixel column 601 is the sub-pixel column 6 corresponding to the hole area HL, and the existence of the hole area HL makes it necessary for the data line 2 electrically connected to at least part of the first sub-pixel column 601 corresponding to the hole area HL, that is, the first data line 201, to be wound (that is, a non-linear extension portion needs to be provided) to avoid the light-transmitting area HL1 of the hole area HL;

[0065] The first sub-pixel column 601 is electrically connected to the first data line 201 , and the second sub-pixel column 602 is electrically connected to the second data line 202 .

[0066] In some embodiments, Figure 2 , Figure 3 As shown, the display panel includes a plurality of sub-pixels 7 including: a plurality of first sub-pixels 701, a plurality of second sub-pixels 702 and a plurality of third sub-pixels 703; one of the odd-numbered sub-pixel columns 6 and the even-numbered sub-pixel columns 6 includes the first sub-pixels 701 and the second sub-pixels 702 arranged alternately, and the other of the odd-numbered sub-pixel columns 6 and the even-numbered sub-pixel columns 6 includes only the third sub-pixel 703.

[0067] In some embodiments, Figure 2 , Figure 3 As shown, the first sub-pixel 701 is a red sub-pixel R, the second sub-pixel 702 is a blue sub-pixel B, and the third sub-pixel 703 is a green sub-pixel G.

[0068] In some embodiments, Figure 2 As shown, a plurality of sub-pixels 7 in each sub-pixel column 6 are electrically connected to the same data line 2 .

[0069] Or, in some embodiments, Figure 3 As shown, a plurality of sub-pixels 7 in each sub-pixel column 6 are electrically connected to two data lines 2;

[0070] In a sub-pixel column 7 including first sub-pixels 701 and second sub-pixels 702 arranged alternately, the first sub-pixels 701 and the second sub-pixels 702 are electrically connected to different data lines 2, that is, all the first sub-pixels 701, i.e., red sub-pixels R, are electrically connected to the same data line 2, and all the second sub-pixels 702, i.e., blue sub-pixels B, are electrically connected to the same data line 2;

[0071] In the sub-pixel column 7 including only the third sub-pixels 703 , two adjacent third sub-pixels 703 are electrically connected to different data lines 2 .

[0072] In some embodiments, Figure 2 , Figure 3 As shown, each sub-pixel column 6 is electrically connected to at least one data line 2; among the two adjacent columns of sub-pixel columns 6 electrically connected to the first data line 201, one column of sub-pixel columns 6 is electrically connected to the first data line 201 including the first sub-route 301, and the other column of sub-pixel columns 6 is electrically connected to the first data line 201 including the second sub-route 302.

[0073] In some embodiments, Figure 4 As shown, the display panel also includes a plurality of pixel driving units 9 and a plurality of scanning lines (not shown); the pixel driving unit 9 includes: at least one thin film transistor 901, at least one capacitor 902, and a switching electrode 10 located on the side of the thin film transistor 901 away from the substrate 1 and electrically connected to the thin film transistor 901; the thin film transistor 901 includes: an active layer 9014, a gate 9011, a source 9012 and a drain 9013; the capacitor 902 includes a first electrode 9021 and a second electrode 9022.

[0074] In some embodiments, Figure 4 As shown, the display panel specifically includes:

[0075] A first conductive layer 11;

[0076] The second conductive layer 12 is located on a side of the first conductive layer 11 away from the substrate 1;

[0077] The third conductive layer 13 is located on a side of the second conductive layer 12 away from the substrate 1;

[0078] The fourth conductive layer 14 is located on a side of the third conductive layer 13 facing away from the substrate 1 .

[0079] In some embodiments, Figure 4 As shown, the first conductive layer 11 includes a scan line (not shown), a gate 9011 of a thin film transistor 901, a first electrode 9021 of a capacitor 902, and at least a portion of a first sub-line (not shown);

[0080] The second conductive layer 12 includes a second electrode 9022 of the capacitor 902;

[0081] The third conductive layer 13 includes at least one of the source electrode 9012 and the drain electrode 9013 of the thin film transistor 901;

[0082] The fourth conductive layer 14 includes a portion (not shown) of the data line (not shown) located in the display area and at least a portion of the second sub-line (not shown).

[0083] In some embodiments, the display panel is an electroluminescent display panel, and the display panel further includes a light emitting device 15 electrically connected to the pixel driving unit 9; Figure 4 As shown, the light emitting device 15 is located on the side of the thin film transistor 901 away from the substrate 1; the light emitting device 15 includes an anode 1501, a light emitting functional layer 1502, and a cathode 1503 arranged in layers;

[0084] The anode 1501 is electrically connected to the drain 9013 .

[0085] In some embodiments, the source and drain of the thin film transistor may be arranged in the same layer, that is, the third conductive layer includes the source and the drain, and the portion of the data line located in the display area is located in a different layer from the source.

[0086] Or, in some embodiments, Figure 4 As shown, the source electrode 9012 and the drain electrode 9013 are located in different layers, and the fourth conductive layer 14 includes the source electrode 9012. The source electrode 9012 and a portion (not shown) of a data line (not shown) located in the display area are arranged in the same layer and are electrically connected.

[0087] In the display panel provided by the embodiment of the present disclosure, since the source and drain are located in different layers, the distance between the source and drain can be reduced without causing a short circuit between the two, and the space occupied by the thin film transistor can be reduced, which is beneficial to improving the sub-pixel aperture ratio.

[0088] Or, in some embodiments, it can also be. The first conductive layer includes a scan line, a gate of a thin film transistor, a first electrode of a capacitor, and at least a portion of the first sub-line, the second conductive layer includes a second electrode of the capacitor, the third conductive layer includes a source and a drain of the thin film transistor and a portion of the data line located in the display area, and the fourth conductive layer includes at least a portion of the second sub-line and a switching electrode; the anode is electrically connected to the drain through the switching electrode. The first routing portion located in the first conductive layer and / or the fourth conductive layer in the wiring area needs to be electrically connected to the portion of the data line located in the third conductive layer.

[0089] Alternatively, in some embodiments, the first conductive layer includes a scan line, a gate of a thin film transistor, a first electrode of a capacitor, and at least a portion of a first sub-line, the second conductive layer includes a second electrode of the capacitor, the third conductive layer includes a source electrode of the thin film transistor and a portion of the data line located in the display area, and the fourth conductive layer includes at least a portion of the second sub-line and a drain. The first line portion located in the first conductive layer and / or the fourth conductive layer in the wiring area needs to be electrically connected to a portion of the data line located in the third conductive layer.

[0090] In some embodiments, Figure 4As shown, the display panel further includes: a buffer layer 16 located between the base substrate 1 and the active layer 9014, a first gate insulating layer 17 located between the first conductive layer 11 and the active layer 9014, a second gate insulating layer 18 located between the first conductive layer 11 and the second conductive layer 12, an interlayer insulating layer 19 located between the second conductive layer 12 and the third conductive layer 13, a first planarization layer 20 located between the third conductive layer 13 and the fourth conductive layer 14, a second planarization layer 21 located between the fourth conductive layer 14 and the anode 1501, a pixel definition layer 22, and an encapsulation layer 23 located on the side of the pixel definition layer 22 and the cathode 1503 away from the base substrate 1. It should be noted that Figure 4 The thin film transistor 901 is taken as an example of a top gate structure, that is, the gate 9011 is located on the side of the active layer 9014 away from the substrate 1 .

[0091] Of course, in a specific implementation, the thin film transistor may also be a bottom gate structure, that is, the active layer is located on the side of the gate electrode facing away from the substrate.

[0092] In some embodiments, Figure 4 As shown, the pixel definition layer 22 is located on the side of the anode 1501 away from the substrate 1, and the cathode is located on the side of the pixel definition layer 22 away from the substrate 1. The pixel definition layer 22 has an opening exposing the anode 1501. The anode 1501, the light-emitting functional layer 1502, and the cathode 1503 are stacked in the opening of the pixel definition layer 22 to form a light-emitting device 15. The area corresponding to the opening of the pixel definition layer 22 is the light-emitting area of ​​the light-emitting device 15.

[0093] In some embodiments, the light-emitting functional layer includes at least an organic light-emitting layer, and may further include at least one of an electron transport layer, a hole transport layer, an electron injection layer, a hole injection layer, an electron blocking layer, and the like.

[0094] In some embodiments, the encapsulation layer includes an inorganic encapsulation layer, an organic encapsulation layer, and an inorganic encapsulation layer that are stacked.

[0095] In some embodiments, Figure 2 , Figure 3 As shown, the display panel also includes:

[0096] A multiplexer circuit 8 is electrically connected to a plurality of data lines 2; the multiplexer circuit 8 comprises: a plurality of data input lines 801, a plurality of multiplexer units 802 and m multiplexer control lines MUX / MUXm; each multiplexer unit 802 comprises m switch units 8021; control ends of the m switch units 8021 are electrically connected to the m multiplexer control lines MUX / MUXm in a one-to-one correspondence, input ends of the m switch units 8021 are electrically connected to the n data input lines 801, and output ends of the switch units 8021 are electrically connected to the data lines 2; wherein m is an integer greater than 1, and n is a positive integer; a first sub-route 301 and a second sub-route 302 are electrically connected to different multiplexer control lines MUX / MUXm.

[0097] In some embodiments, m=2, n=1; or, m=4, n=1.

[0098] Specifically, Figure 2 Take m=4, n=1 as an example, the timing diagram is as follows Figure 5 As shown, GAP1~GAP6 represent scanning signals of different 6 rows of scanning lines, MUX1~MUX4 represent multiplex selection control signals of different multiplex selection control lines, S1 and S2 represent data signals input by different data input lines, RO represents the signal of the data line electrically connected to the red sub-pixels in a column of sub-pixels, BE represents the signal of the data line electrically connected to the blue sub-pixels in a column of sub-pixels, and GO and GE respectively represent the signals of two data lines electrically connected to the green sub-pixels in a column of sub-pixels. Figure 3 Take m=2, n=1 as an example, the timing diagram is as follows Figure 6 As shown, GAP1~GAP6 represent scanning signals of different 6 rows of scanning lines, MUX1~MUX2 represent multiplexer selection control signals of different multiplexer selection control lines, S1 and S2 represent data signals input by different data input lines, daRB represents the signal of the data line electrically connected to a column of sub-pixels including red sub-pixels and blue sub-pixels, daRB' represents the signal of the data line electrically connected to the next column of sub-pixels including red sub-pixels and blue sub-pixels, daG represents the signal of the data line electrically connected to a column of sub-pixels including green sub-pixels, and daG' represents the signal of the data line electrically connected to the next column of sub-pixels including green sub-pixels.

[0099] Next, an embodiment of setting a shielding structure is described in detail.

[0100] In some embodiments, Figure 7 to Figure 9 As shown, a plurality of shielding structures 4 are arranged on the same layer, and the orthographic projection of the shielding structure 4 on the substrate 1 covers the orthographic projection of the first sub-line 301 or the second sub-line 302 on the substrate 1 .

[0101] It should be noted that Figure 7 to Figure 9 For different Figure 2 Schematic diagram of the cross-sectional structure of FF'. Figure 7 , Figure 8 In the embodiment, the orthographic projections of the plurality of shielding structures 4 on the substrate 1 cover the orthographic projections of the second sub-line 302 on the substrate 1. Fig. 9 In the embodiment, the orthographic projections of the plurality of shielding structures 4 on the substrate 1 cover the orthographic projections of the first sub-routing 301 on the substrate 1 .

[0102] Or, in some embodiments, Fig.10 , Fig.11 As shown, the multiple shielding structures 4 include: multiple first shielding structures 401 arranged in the same layer, and multiple second shielding structures 402 arranged in the same layer and located in different layers from the first shielding structures 401;

[0103] The orthographic projection of the first shielding structure 401 on the substrate 1 covers the orthographic projection of the first sub-line 301 on the substrate 1 , and the orthographic projection of the second shielding structure 402 on the substrate 1 covers the orthographic projection of the second sub-line 302 on the substrate 1 .

[0104] It should be noted that Figure 10-11 Also for different species Figure 2 Schematic diagram of the cross-sectional structure of FF'.

[0105] In the display panel provided by the embodiment of the present disclosure, the orthographic projections of the first sub-route and the second sub-route on the base substrate are covered by the orthographic projection of the shielding structure on the base substrate, which can improve the shielding effect of the shielding structure on the first sub-route and the second sub-route, and can further reduce the parasitic capacitance between adjacent data lines.

[0106] In some embodiments, Fig.10 As shown, the second sub-line 302 is located on a side of the first sub-line 301 away from the substrate 1 , and the first shielding structure 401 is located on a side of the second shielding structure 402 away from the substrate 1 .

[0107] Or, in some embodiments, Fig.11 As shown, the second sub-line 302 is located on a side of the first sub-line 301 away from the substrate 1 , and the second shielding structure 402 is located on a side of the first shielding structure 401 away from the substrate 1 .

[0108] In some embodiments, Figure 7 to Figure 11 As shown, the plurality of first sub-routes 301 are all located in the first conductive layer 11, the plurality of second sub-routes 302 are all located in the fourth conductive layer 14, and the second conductive layer 12 and / or the third conductive layer 13 further include a shielding structure 4. Figure 7 The middle shielding structures 4 are all located in the third conductive layer 13; Figure 8 , Fig. 9 The middle shielding structures 4 are all located in the second conductive layer 12; Fig.10 In the embodiment, the first shielding structure 401 is located in the third conductive layer 13, and the second shielding structure 402 is located in the second conductive layer 12; Fig.11 In the embodiment, the second shielding structure 402 is located in the third conductive layer 13 , and the first shielding structure 401 is located in the second conductive layer 12 .

[0109] In some embodiments, when the portion of the data line located in the display area is located in the fourth conductive layer, that is, the first sub-line of the data line located in the first conductive layer needs to be electrically connected to the portion of the data line located in the fourth conductive layer. Figure 2 In the figure, for the first routing portion 3 located in the wiring area HL2, the thick line represents the portion of the first routing portion 3 located in the first conductive layer (not shown), the thin line represents the portion of the first routing portion 3 located in the fourth conductive layer (not shown), and the straight or broken line portions electrically connected at both ends of the arc-shaped portion of the first routing portion 3 that extends non-straight or has an arc-like contour are located in the fourth conductive layer (not shown) and / or the first conductive layer (not shown). In the wiring area HL2, in the orthographic projection of the substrate 1, there are two first routing portions 3 that overlap, and in the overlapping area, one of the two first routing portions 3 is located in the fourth conductive layer (not shown) and the other is located in the first conductive layer (not shown). Specifically, as Figure 2 As shown, the first routing portion 3 also includes a third sub-routing 303 and a fourth sub-routing 304 which are electrically connected to both ends of the first sub-routing 301 or the second sub-routing 302 respectively; the third sub-routing 303 is located in the fourth conductive layer (not shown) and / or the first conductive layer (not shown), and the fourth sub-routing 304 is located in the fourth conductive layer (not shown) and / or the first conductive layer (not shown).

[0110] In some embodiments, Fig. 9 As shown, the minimum distance h1 between the surface 25 of at least part of the shielding structure 4 on the side close to the substrate substrate 1 and the substrate substrate 1 is smaller than the distance h2 between the surface 26 of the first sub-route 301 on the side away from the substrate substrate 1 and the substrate substrate 1; and the surface 25 of at least part of the shielding structure 4 on the side close to the substrate substrate 1 has a groove 24 that is recessed toward the side away from the substrate substrate 1, and the orthographic projection of the first sub-route 301 on the substrate substrate 1 is located within the orthographic projection of the groove 24 on the substrate substrate 1.

[0111] That is, in the display panel provided by the embodiment of the present disclosure, at least part of the shielding structure covers part of the side surface of the first sub-line, thereby further improving the shielding effect of the shielding structure and reducing the parasitic capacitance between adjacent data lines.

[0112] It should be noted that Fig. 9In the specific implementation, when the shielding structure includes a first shielding structure and a second shielding structure, the first shielding structure covers the first sub-line and the first shielding structure is located in the second conductive layer. Fig. 9 How to set it up.

[0113] It should be noted that if m=4, n=1, and the first sub-route and the second sub-route are alternately arranged in the wiring area, the voltage jump of the data line electrically connected to the red sub-pixel will couple the data line electrically connected to the green sub-pixel. When the driving order of MUX is MUX2, MUX1, MUX4, and MUX3, the data line electrically connected to the green sub-pixel is coupled the most times, and green vertical stripes will appear in the display area below the hole area. The display panel provided by the embodiment of the present disclosure can reduce the parasitic capacitance between the data lines by setting a shielding structure, which can alleviate the poor display of green vertical stripes.

[0114] It should be noted that although Figure 2 Taking m=4 and n=1 as an example, for a multiplexer circuit with m=2 and n=1, the first sub-routing and the second sub-routing can still be alternately arranged in the wiring area, and a shielding structure can be arranged. The setting method of the shielding structure is the same as the above. Figure 7 to Figure 11 The setting method is the same and will not be repeated here.

[0115] Next, Figure 7 to Figure 10 Taking the structure shown in FIG. 1 as an example, the parasitic capacitance between the data lines provided by the embodiment of the present disclosure is described. The capacitance data per unit length (100 μm) is shown in Table 1, where N1 is a display panel without a shielding layer and having bright streaks, and N2, N3, N4, and N5 are respectively Figure 7 to Figure 10 In the structure shown, c1 represents the parasitic capacitance between the closest second sub-routing 302 located in the same layer, c2 represents the parasitic capacitance between the closest first sub-routing 301 located in the same layer, c3 represents the parasitic capacitance between the adjacent first sub-routing 301 and the second sub-routing 302, the total capacitance 1 represents the capacitance of the portion of the data line located in the fourth conductive layer, and the total capacitance 2 represents the capacitance of the portion of the data line located in the first conductive layer. The units of the above capacitances are all femtofarads (fF) / 100 micrometers (μm). It can be seen from Table 1 that the parasitic capacitances of c1, c2, and c3 of N2, N3, N4, and N5 are all reduced compared to N1. It is known that the display panel corresponding to N2 is already a qualified product without bright streak defects, and the parasitic capacitances of c1, c2, and c3 of the display panel corresponding to N5 are the most reduced compared to N2, that is, setting a double-layer shielding structure can better improve the parasitic capacitance between data lines.

[0116] Table 1

[0117]

[0118] In some embodiments, the plurality of shielding structures input a constant voltage signal.

[0119] In some embodiments, the display panel further includes: a power supply voltage signal line, an initialization signal line, and a first level signal line; the power supply voltage signal line and the initialization signal line are electrically connected to the pixel driving unit, and the cathode is electrically connected to the first level signal line;

[0120] The plurality of shielding structures are electrically connected to at least one of the first level signal line, the power supply voltage signal line, and the initialization signal line.

[0121] It should be noted that the power supply voltage signal line, the initialization signal line, and the first level signal line all carry constant voltage signals, and multiple shielding structures are electrically connected to at least one of the first level signal line, the power supply voltage signal line, and the initialization signal line, so that multiple shielding structures input constant voltage signals.

[0122] In some embodiments, the pixel driving unit includes a plurality of thin film transistors, the power supply voltage signal line is electrically connected to a source of one of the thin film transistors in the pixel driving unit, and the initialization signal line is electrically connected to a source of another thin film transistor.

[0123] In some embodiments, a circuit diagram in which the first level signal line VSS, the power supply voltage signal line VDD, the initialization signal line VINT are electrically connected to the pixel driving unit 901 and the light emitting device 15 is as shown in FIG. Fig.12 As shown, the pixel driving unit 901 includes 7 thin film transistors 9011 and 2 capacitors 9012. For the sake of distinction, the 7 thin film transistors 9011 are represented by M0 to M6, and the 2 capacitors 9012 are represented by C1 and C2. The display panel also includes: a first light emitting control line EM1, a second light emitting control line EM2, a first reset control signal line RE1, a second reset control signal line RE2, a third reset control signal line RE3, and a reference signal line VREF; the initialization signal line VINT includes a first initialization signal line VINT1 and a second initialization signal line VINT2. The gate of M1 is electrically connected to the scan line through the scan signal terminal GA; the source of M1 is electrically connected to the data line through the data signal terminal DA; the source of M2 and one of the electrodes of C2 are electrically connected to the power supply voltage signal line VDD; the gate of M2 is electrically connected to the first light-emitting control line EM1; the gate of M3 is electrically connected to the second light-emitting control line EM2; the gate of M4 is electrically connected to the first reset control signal line RE1, and the source of M4 is electrically connected to the reference signal line VREF; the gate of M5 is electrically connected to the second reset control signal line RE2, and the source of M5 is electrically connected to the first initialization signal line VINT1; the gate of M6 is electrically connected to the third reset control signal line RE3, and the source of M6 is electrically connected to the second initialization signal line VINT2.

[0124] Alternatively, in some embodiments, the pixel driving unit may also be a low temperature polysilicon (LTPS) circuit structure, that is, the thin film transistors included in the pixel driving unit are all LTPS thin film transistors, so as to reduce costs and achieve low-frequency driving. Another circuit diagram in which the first level signal line VSS, the power supply voltage signal line VDD, and the initialization signal line VINT are electrically connected to the pixel driving unit 901 and the light emitting device 15 is shown in FIG. Fig.13 As shown, the pixel driving unit 901 includes eight thin film transistors 9011 and one capacitor 9012. Fig.12 To distinguish, eight thin-film transistors 9011 are represented by T1 to T8 respectively, and one capacitor 9012 is represented by Cst. The display panel also includes: a first light-emitting control line EM1, a second light-emitting control line EM2, a reset control signal line RE, and a reference signal line VREF; the initialization signal line VINT includes a first initialization signal line VINT1 and a second initialization signal line VINT2. The gate of M1 is electrically connected to the scan line through the scan signal terminal GA; the gate of T1 is electrically connected to the reset control signal line RE, and the first electrode of T1 is electrically connected to the first initialization signal line VINT1; the second electrode of T1 is electrically connected to one of the electrodes of Cst, the gate of T3, and the second electrode of T2; the other electrode of Cst is electrically connected to the power supply voltage signal line VDD; the gate of T2 is electrically connected to the scan line through the scan signal terminal GA, and the gate of T4 is electrically connected to the scan line through the scan signal terminal GA; the first electrode of T4 is electrically connected to the data line through the data signal terminal DA; the second electrode of T4 is electrically connected to the first electrode of T3; the gate of T5 is electrically connected to the first light-emitting control line The gate of T6 is electrically connected to the first light-emitting control line EM1, the first electrode of T5 is electrically connected to the power supply voltage signal line VDD, and the second electrode of T5 is electrically connected to the first electrode of T3; the gate of T6 is electrically connected to the first light-emitting control line EM1, the first electrode of T6 is electrically connected to the anode of the light-emitting device 15 and the second electrode of T7, the second electrode of T6 is electrically connected to the first electrode of T2 and the second electrode of T3; the gate of T7 is electrically connected to the second light-emitting control line EM2, the first electrode of T7 is electrically connected to the second initialization signal line VINT2; the gate of T8 is electrically connected to the second light-emitting control line EM2, the first electrode of T8 is electrically connected to the reference signal line VREF, and the second electrode of T8 is electrically connected to the second electrode of T4.

[0125] It should be noted that Fig.12 , Fig.13The circuit structure of the pixel unit of the present disclosure is merely an example. In a specific implementation, the pixel unit may also include other numbers of thin film transistors and capacitors. The circuit structure of the pixel unit may also be applicable to low temperature polycrystalline oxide (LTPO) circuits, etc. The number of thin film transistors and capacitors, the device type of thin film transistors, the connection relationship, etc. are not limited here.

[0126] Next, an embodiment in which at least a portion of the orthographic projections of the plurality of first sub-routes on the substrate are located on a side of at least a portion of the orthographic projections of the plurality of second sub-routes on the substrate facing toward or away from the light-transmitting region is described in detail.

[0127] In some embodiments, Figure 3 As shown, the wiring area HL2 includes: a first wiring area HL201 surrounding the light-transmitting area HL1, and a second wiring area HL202 surrounding the first wiring area HL201 on a side of the first wiring area HL201 away from the light-transmitting area HL1.

[0128] In some embodiments, Figure 3 As shown, at least part of the orthographic projection of the plurality of first sub-routes 301 on the substrate 1 is located in the first wiring area HL201 , and at least part of the orthographic projection of the plurality of second sub-routes 302 on the substrate 1 is located in the second wiring area HL202 .

[0129] Alternatively, in some embodiments, at least part of the orthographic projection of the plurality of first sub-routes 301 on the substrate 1 is located in the first wiring area HL201 , and at least part of the orthographic projection of the plurality of second sub-routes 302 on the substrate 1 is located in the second wiring area HL202 .

[0130] In some embodiments, Figure 3 As shown, among the first data lines 201 electrically connected to any two adjacent sub-pixel columns 7 , one of the first data lines 201 includes a first sub-wire 301 , and the other first data line 201 includes a second sub-wire 302 .

[0131] In some embodiments, Figure 3 As shown, among any two adjacent first data lines 201 in the display area AA, one of the first data lines 201 includes a first sub-routing line 301, and the other first data line 201 includes a second sub-routing line 302. Therefore, the first routing portions 3 corresponding to any two adjacent first data lines 201 in the display area AA are respectively located in the first wiring area HL201 and the second wiring area HL202, and the distance between the two is relatively far, which can avoid mutual interference between the first sub-routing lines 301 and the second sub-routing lines 302 corresponding to the two, resulting in excessive parasitic capacitance and causing poor bright lines.

[0132] In some embodiments, Fig.14 As shown, a plurality of first sub-routes 301 are located in different layers, and any two adjacent first sub-routes 301 are located in different layers; that is, the first sub-routes 301 located in different layers are arranged alternately in the orthographic projection of the substrate, and even if the distance between the first sub-routes 301 is reduced, there will be no short circuit problem between the two, which can save wiring space;

[0133] Multiple second sub-routes 302 are located in different layers, and any two adjacent second sub-routes 302 are located in different layers; that is, the second sub-routes 302 located in different layers are arranged alternately in the orthographic projection of the substrate. Even if the distance between the second sub-routes 302 is reduced, there will be no short circuit problem between the two, which can save wiring space.

[0134] It should be noted that Fig.14 For along Figure 3 Cross-sectional view of HH'.

[0135] In some embodiments, when part of the first sub-routing is located in the first conductive layer, the rest of the first sub-routing may be located in one of the second conductive layer, the third conductive layer, and the fourth conductive layer;

[0136] When part of the second sub-routing is located in the fourth conductive layer, the rest of the second sub-routing may be located in one of the second conductive layer, the third conductive layer and the first conductive layer.

[0137] In some embodiments, Fig.15 As shown, some of the first sub-routes 301 among the plurality of first sub-routes 301 are also located in the second conductive layer 12;

[0138] Some of the second sub-routes 302 among the plurality of second sub-routes 302 are also located in the third conductive layer 13 .

[0139] In some embodiments, Figure 3 As shown, the first routing portion 3 further includes a third sub-routing 303 and a fourth sub-routing 304 which are electrically connected to both ends of the first sub-routing 301 or the second sub-routing 302 respectively;

[0140] For the first routing portion 3 including the first sub-routing 301, the third sub-routing 303 and the fourth sub-routing 304 are arranged in the same layer as the first sub-routing 301, that is, the first sub-routing 301, the third sub-routing 303, and the fourth sub-routing 304 are all located in the first conductive layer (not shown) or the second conductive layer (not shown);

[0141] For the first routing section 3 including the second sub-routing 302, the third sub-routing 303 and the fourth sub-routing 304 are arranged on the same layer as the second sub-routing 302, and the second sub-routing 302, the third sub-routing 303, and the fourth sub-routing 304 are all located in the third conductive layer (not shown) or the fourth conductive layer (not shown).

[0142] In some embodiments, Fig.15 As shown, the display panel also includes:

[0143] The third shielding structure 5 is located at least one of the first conductive layer (not shown), the second conductive layer (not shown), the third conductive layer 13, and the fourth conductive layer (not shown); at least a partial area of ​​the orthographic projection of the third shielding structure 5 on the substrate substrate 1 is located in the wiring area HL2 between the orthographic projection of multiple first sub-routes 301 on the substrate substrate 1 and the orthographic projection of multiple second sub-routes 302 on the substrate substrate 1.

[0144] The display panel provided by the embodiment of the present disclosure further provides a third shielding structure between the plurality of first sub-routes and the plurality of second sub-routes, so as to avoid mutual interference between the two most adjacent first sub-routes and the second sub-routes.

[0145] In some embodiments, Fig.15 The third shielding structure 5 is located in the third conductive layer 13 as an example for illustration.

[0146] In some embodiments, Fig.15 As shown, when the first sub-route 301 is located in the first wiring area HL201, the third sub-route 303 electrically connected to the first sub-route 301 extends from the first wiring area HL201 to the second wiring area HL202, and the orthographic projection of the third sub-route 303 electrically connected to the first sub-route 301 on the substrate substrate 1 overlaps with the orthographic projection of the third shielding structure 5 on the substrate substrate 1, therefore, the third shielding structure 5 needs to be located in a different layer from the third sub-route 303 electrically connected to the first sub-route 301. Similarly, if the second sub-route is located in the first wiring area, the third sub-route electrically connected to the second sub-route extends from the first wiring area to the second wiring area, and the orthographic projection of the third sub-route electrically connected to the second sub-route on the substrate substrate overlaps with the orthographic projection of the third shielding structure on the substrate substrate, the third shielding structure needs to be located in a different layer from the third sub-route electrically connected to the second sub-route.

[0147] In some embodiments, a line width of the third shielding structure is greater than a line width of the data line.

[0148] In some embodiments, the third shielding structure inputs a constant voltage signal.

[0149] In some embodiments, Fig.12The third shielding structure can be electrically connected to one of the first level signal line VSS, the power supply voltage signal line VDD, and the initialization signal line VINT.

[0150] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, including the display panel provided by the embodiment of the present disclosure.

[0151] The display device provided in the embodiment of the present disclosure is any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device should be understood by a person skilled in the art, and will not be described in detail here, nor should they be used as a limitation of the present disclosure. The implementation of the display device can refer to the embodiment of the display panel above, and the repeated parts will not be described in detail.

[0152] In summary, in the display panel and display device provided by the embodiments of the present disclosure, when the first sub-routing and the second sub-routing are arranged alternately, a shielding structure of the film layer between the first sub-routing and the second sub-routing is provided, and the orthographic projection of the shielding structure on the substrate substrate overlaps with the orthographic projection of at least one of the first sub-routing and the second sub-routing on the substrate substrate, thereby reducing the parasitic capacitance between the first sub-routing and the second sub-routing. Alternatively, at least a portion of the orthographic projection of the plurality of first sub-routing on the substrate substrate is located on the side of at least a portion of the orthographic projection of the plurality of second sub-routing on the substrate substrate facing or away from the light-transmitting area, so that the first sub-routing and the second sub-routing are no longer arranged alternately, and the parasitic capacitance between the first sub-routing and the second sub-routing can be reduced. Since the parasitic capacitance between the first sub-routing and the second sub-routing is reduced, the voltage jump on the first data line can be reduced, and the poor display of bright stripes caused by uneven brightness can be avoided, thereby improving the display effect and user experience.

[0153] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0154] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A display panel, wherein: The display panel comprises: A substrate, comprising: at least one hole area, a display area surrounding the at least one hole area, and a peripheral area surrounding the display area; the hole area comprises: a light-transmitting area and a wiring area located between the display area and the light-transmitting area; A plurality of data lines, at least located in the display area; the plurality of data lines: include a plurality of first data lines; the orthographic projections of the plurality of first data lines on the base substrate do not overlap with the light-transmitting area, the first data lines include first routing portions, the orthographic projections of at least some of the first data lines on the base substrate pass through the wiring area, and the first routing portions of at least some of the first data lines extend non-linearly; some of the first routing portions in the plurality of first data lines include first sub-routes, and some of the first routing portions in the plurality of first data lines include second sub-routes located in a different layer from the first sub-routes; Among them, the first sub-routes and the second sub-routes are alternately arranged on the orthographic projection of the substrate, and the display panel also includes a plurality of shielding structures, the orthographic projection of the shielding structure on the substrate overlaps with the orthographic projection of the first sub-routes and / or the second sub-routes on the substrate, and the shielding structure is located in the film layer between the first sub-routes and the second sub-routes; or, at least a portion of the orthographic projection of the plurality of first sub-routes on the substrate is located on a side of at least a portion of the orthographic projection of the plurality of second sub-routes on the substrate toward or away from the light-transmitting area.

2. The display panel according to claim 1, wherein: The multiple shielding structures are arranged in the same layer, and the orthographic projection of the shielding structure on the base substrate covers the orthographic projection of the first sub-line or the second sub-line on the base substrate.

3. The display panel according to claim 1, wherein: The multiple shielding structures include: multiple first shielding structures arranged in the same layer, and multiple second shielding structures arranged in the same layer and located in different layers from the first shielding structures; The orthographic projection of the first shielding structure on the base substrate covers the orthographic projection of the first sub-line on the base substrate, and the orthographic projection of the second shielding structure on the base substrate covers the orthographic projection of the second sub-line on the base substrate.

4. The display panel according to claim 3, wherein: The second sub-route is located at a side of the first sub-route away from the substrate, and the first shielding structure is located at a side of the second shielding structure away from the substrate.

5. The display panel according to any one of claims 2 to 4, wherein: The minimum distance between the surface of at least part of the shielding structure close to the substrate substrate and the substrate substrate is smaller than the distance between the surface of the first sub-route away from the substrate substrate and the substrate substrate; and the surface of at least part of the shielding structure close to the substrate substrate has a groove that is recessed toward the side away from the substrate substrate, and the orthographic projection of the first sub-route on the substrate substrate is located within the orthographic projection of the groove on the substrate substrate.

6. The display panel according to any one of claims 1 to 4, wherein: The display panel also includes a plurality of pixel driving units; The pixel driving unit includes: at least one thin film transistor, at least one capacitor, and a switching electrode located on a side of the thin film transistor away from the substrate and electrically connected to the thin film transistor; the display panel specifically includes: A first conductive layer, including a gate of the thin film transistor, a first electrode of the capacitor, and at least a portion of the first sub-wire; A second conductive layer is located on a side of the first conductive layer away from the substrate; the second conductive layer includes a second electrode of the capacitor; A third conductive layer is located on a side of the second conductive layer away from the substrate; the third conductive layer includes at least one of a source electrode and a drain electrode of the thin film transistor; The fourth conductive layer is located on a side of the third conductive layer away from the base substrate; the fourth conductive layer includes a portion of the data line located in the display area and at least a portion of the second sub-line.

7. The display panel according to claim 6, wherein: The plurality of first sub-routes are all located in the first conductive layer, the plurality of second sub-routes are all located in the fourth conductive layer, and the second conductive layer and / or the third conductive layer further include the shielding structure.

8. The display panel according to claim 6, wherein: The display panel further comprises: a light emitting device electrically connected to the pixel driving unit, a power supply voltage signal line, an initialization signal line, and a first level signal line; the light emitting device comprises a stacked anode, a light emitting functional layer, and a cathode, the anode is electrically connected to the drain via the switching electrode, the power supply voltage signal line and the initialization signal line are electrically connected to the pixel driving unit, and the cathode is electrically connected to the first level signal line; The plurality of shielding structures are electrically connected to at least one of the first level signal line, the power supply voltage signal line, and the initialization signal line.

9. The display panel according to claim 6, wherein: At least a portion of the orthographic projections of the plurality of first sub-routes on the substrate are located on a side of at least a portion of the orthographic projections of the plurality of second sub-routes on the substrate facing toward or away from the light-transmitting area; The plurality of first sub-routes are located in different layers, and the first sub-routes located in different layers are arranged alternately in the orthographic projection of the substrate; The plurality of second sub-routes are located in different layers, and the second sub-routes located in different layers are alternately arranged in the orthographic projection of the substrate.

10. The display panel according to claim 6, wherein: The display panel further includes: A third shielding structure is located in at least one of the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer; at least a partial area of ​​the orthographic projection of the third shielding structure on the substrate is located in the wiring area between the orthographic projections of the plurality of first sub-routes on the substrate and the orthographic projections of the plurality of second sub-routes on the substrate.

11. The display panel according to any one of claims 1 to 4 and 7 to 9, wherein: The display panel includes a plurality of sub-pixel columns, each of which includes a plurality of sub-pixels; each of the sub-pixel columns is electrically connected to at least one of the data lines; among two adjacent sub-pixel columns electrically connected to the first data line, one of the sub-pixel columns is electrically connected to the first data line including the first sub-route, and the other of the sub-pixel columns is electrically connected to the first data line including the second sub-route.

12. The display panel according to any one of claims 1 to 4 and 7 to 9, wherein: The display panel further includes: A multi-way selection circuit is electrically connected to the plurality of data lines; the multi-way selection circuit comprises: a plurality of data input lines, a plurality of multi-way selection units and m multi-way selection control lines; each of the multi-way selection units comprises m switch units; the control ends of the m switch units are electrically connected to the m multi-way selection control lines in a one-to-one correspondence, the input ends of the m switch units are electrically connected to n of the data input lines, and the output ends of the switch units are electrically connected to the data lines; wherein m is an integer greater than 1, and n is a positive integer; the first sub-route and the second sub-route are electrically connected to different multi-route selection control lines.

13. The display panel according to claim 1, wherein: m=2, n=1; Alternatively, m=4, n=1.

14. The display panel according to any one of claims 1 to 4 and 7 to 9, wherein: The plurality of data lines further include: a plurality of second data lines, the orthographic projections of the plurality of second data lines on the base substrate do not overlap with the at least one hole area, and the length of the first data line is greater than the length of the second data line.

15. A display device, wherein: The invention comprises a display panel according to any one of claims 1 to 14.

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