Display device and head mounted display device including the same

Abstract

The invention provides a display device and a head-mounted display device including the same. The display device includes: a semiconductor substrate including a transistor; a conductive layer over the semiconductor substrate; a reflective electrode layer over the conductive layer; an optical auxiliary layer over the reflective electrode layer; a plurality of light emitting elements over the optical auxiliary layer and each including a first electrode, a light emitting stack, and a second electrode; a pixel defining film over the first electrode to separate a plurality of light emitting regions of the plurality of light emitting elements; a first sub-pad conductive layer over the conductive layer; and a second sub-pad conductive layer over the first pad conductive layer, wherein the sum of the thickness of the first sub-pad conductive layer and the thickness of the second sub-pad conductive layer is greater than the thickness of the reflective electrode layer.

Description

Technical Field

[0001] One or more embodiments of the present disclosure relate to a display device and a head-mounted display device including the display device. Background Art

[0002] A head mounted display (HMD) device is an image display device that is worn on the user's head in the form of glasses or a helmet to form a focused image at a close distance in front of the user's eyes. The head mounted display device can realize virtual reality (VR) or augmented reality (AR).

[0003] The head-mounted display device magnifies the image displayed on the small display device by using a plurality of lenses and displays the magnified image. Therefore, a display device suitable for the head-mounted display device can appropriately provide a high-resolution image, for example, an image with a resolution of 3000PPI (pixels per inch) or more. For this reason, an organic light-emitting diode on silicon (OLEDoS), which is a high-resolution small organic light-emitting display device, is used as a display device applied to the head-mounted display device. OLEDoS is an image display device in which an organic light-emitting diode (OLED) is positioned on a semiconductor wafer substrate including a complementary metal oxide semiconductor (CMOS). Summary of the invention

[0004] Aspects of embodiments of the present disclosure provide a display device capable of providing a high-resolution image.

[0005] Aspects of the embodiments of the present disclosure also provide a head-mounted display device capable of providing high-resolution images.

[0006] However, the embodiments of the present disclosure are not limited to those set forth herein. The above and other embodiments of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0007] According to one or more embodiments of the present disclosure, a display device is provided, which includes: a semiconductor substrate including a transistor; a conductive layer above the semiconductor substrate; a reflective electrode layer above the conductive layer; an optical auxiliary layer above the reflective electrode layer; a plurality of light-emitting elements above the optical auxiliary layer and each including a first electrode, a light-emitting stack, and a second electrode; a pixel-defining film above the first electrode to separate a plurality of light-emitting regions of the plurality of light-emitting elements; a first sub-pad conductive layer above the conductive layer; and a second sub-pad conductive layer above the first sub-pad conductive layer, wherein the thickness of the first sub-pad conductive layer and the thickness of the second sub-pad conductive layer are greater than the thickness of the reflective electrode layer.

[0008] The first sub-pad conductive layer and the second sub-pad conductive layer may include a first sub-pad and a second sub-pad separated by the optical auxiliary layer.

[0009] An area of ​​the first sub pad may be greater than an area of ​​the second sub pad.

[0010] The first sub-pad conductive layer and the second sub-pad conductive layer may further include a third sub-pad separated by the optical auxiliary layer.

[0011] An area of ​​the first sub pad may be greater than an area of ​​the second sub pad, wherein an area of ​​the first sub pad is greater than an area of ​​the third sub pad.

[0012] The display device may further include a groove penetrating the pixel defining film and a portion of the optical auxiliary layer.

[0013] The light emitting stack may include a first stack layer for emitting light of a first color in the groove, and a second stack layer for emitting light of a second color in the groove and spaced apart from the first stack layer.

[0014] The light emitting stack may further include a first charge generation layer between the first stack layer and the second stack layer and separated at the groove.

[0015] The pixel defining film may include a first pixel defining film covering at least a portion of the first electrode, a second pixel defining film above the first pixel defining film and exposing a portion of the top surface of the first pixel defining film, and a third pixel defining film above the second pixel defining film and exposing a portion of the top surface of the second pixel defining film.

[0016] The groove may penetrate the first pixel defining film, the second pixel defining film, and the third pixel defining film.

[0017] The reflective electrode layer may include a first reflective electrode, a second reflective electrode over the first reflective electrode, and a step layer between the first reflective electrode and the second reflective electrode.

[0018] The display device may also include a first power connection electrode above the conductive layer, a pad via that penetrates the optical auxiliary layer covering the first power connection electrode to connect to the first power connection electrode, and a second power connection electrode above the optical auxiliary layer, connected to the pad via and connected to the second electrode.

[0019] A pixel defining film may be over at least a portion of the second power connection electrode.

[0020] The reflective electrode layer may include a first reflective electrode, a second reflective electrode above the first reflective electrode, and a step layer between the first reflective electrode and the second reflective electrode, wherein the first power connection electrode includes a first sub-power connection electrode and a second sub-power connection electrode, the first sub-power connection electrode includes the same material as the first reflective electrode, and the second sub-power connection electrode includes the same material as the second reflective electrode.

[0021] The display device may further include a dam penetrating the pixel defining film and a portion of the optical auxiliary layer.

[0022] The depth of the dam may be substantially equal to the depth of the trench.

[0023] The display device may further include an encapsulation layer over the plurality of light emitting elements and the pixel defining film and including a first encapsulation inorganic layer and an encapsulation organic layer in the dam.

[0024] The encapsulating organic layer may be over the first encapsulating inorganic layer in the dam.

[0025] The thickness of the first sub-pad conductive layer is greater than the thickness of the second sub-pad conductive layer, wherein the display device also includes a permeation reducing electrode above the conductive layer, and wherein the permeation reducing electrode includes a first sub-permeation reducing electrode comprising the same material as the first sub-pad conductive layer, and a second sub-permeation reducing electrode comprising the same material as the second sub-pad conductive layer.

[0026] According to one or more embodiments of the present disclosure, a display device is provided, which includes: a display area including pixels; a power connection area outside the display area; a dam area outside the power connection area; a first distribution circuit at a first side of the display area in a first direction; a data driver outside the first distribution circuit in the first direction; a pad area outside the data driver in the first direction; an electrostatic protection area outside the pad area in the first direction; a penetration reduction area outside the electrostatic protection area in the first direction, and a crack reduction area outside the penetration reduction area in the first direction.

[0027] The power connection area may surround the display area in the plan view, wherein the dam area surrounds the power connection area in the plan view, wherein the pad area is outside the dam area, wherein the electrostatic protection area surrounds the dam area in the plan view, wherein the penetration reduction area surrounds the electrostatic protection area in the plan view, and wherein the crack reduction area surrounds the penetration reduction area in the plan view.

[0028] According to one or more embodiments of the present disclosure, a head-mounted display device is provided, which includes a display device housing configured to accommodate at least one display device, and an optical component configured to magnify a display image of the at least one display device or change an optical path, wherein the at least one display device includes: a semiconductor substrate including a transistor; a conductive layer above the semiconductor substrate; a reflective electrode layer above the conductive layer; an interlayer insulating layer above the reflective electrode layer; a plurality of light-emitting elements above the interlayer insulating layer and each including a first electrode, a light-emitting stack, and a second electrode; a pixel defining film above the first electrode to separate a plurality of light-emitting regions in which the plurality of light-emitting elements are respectively positioned; a first sub-pad conductive layer above the conductive layer; and a second sub-pad conductive layer above the first sub-pad conductive layer, the thickness of the first sub-pad conductive layer and the thickness of the second sub-pad conductive layer being greater than the thickness of the reflective electrode layer.

[0029] According to the above and other embodiments of the present disclosure, by forming a light emitting element backplane and a light emitting element layer on a semiconductor substrate on which a plurality of transistors are formed, the size of a plurality of pixels can be greatly reduced so that a display device displaying high-resolution images can be provided.

[0030] In addition, according to the above and other embodiments of the present disclosure, the first pad conductive layer of the first sub-pad and the second pad conductive layer of the second sub-pad are separated or distinguished from each other, so that although the second pad conductive layer of the second sub-pad may be damaged or destroyed by a fixture or a probe during the inspection process, the first pad conductive layer of the first sub-pad may not be damaged or destroyed. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other embodiments of the present disclosure will become more apparent by describing the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0032] Figure 1 is an exploded perspective view showing a display device according to one or more embodiments;

[0033] Figure 2 is a block diagram showing a display device according to one or more embodiments;

[0034] Figure 3 is an equivalent circuit diagram of a first sub-pixel according to one or more embodiments;

[0035] Figure 4 is a layout diagram showing a display panel according to one or more embodiments;

[0036] Figure 5 It is shown Figure 4 A layout diagram of a first electrode, a light emitting area, and a pixel defining film of each sub-pixel in a display area;

[0037] Figure 6 is a layout diagram showing a first electrode, a light emitting region, and a pixel defining film of each of a plurality of sub-pixels according to yet one or more other embodiments;

[0038] Figure 7 is shown along Figure 5 A cross-sectional view of the display device taken along line AA';

[0039] Figure 8 It is shown Figure 4 a layout diagram of a first pad of a first pad portion;

[0040] Fig. 9 is shown along Figure 8 A cross-sectional view of the display panel taken along line BB';

[0041] Fig.10 It is shown Figure 4 A layout diagram of yet another example of a first pad of a first pad portion;

[0042] Fig.11 is shown along Fig.10 A cross-sectional view of the display panel taken along line CC';

[0043] Fig.12 It is shown Figure 4 A layout diagram of yet another example of a first pad of a first pad portion;

[0044] Fig.13 is along Fig.12 A cross-sectional view of the display panel taken along line D-D';

[0045] Fig.14 It is shown in detail Figure 4 A layout diagram of area X;

[0046] Fig.15 is along Fig.14 A cross-sectional view of the display panel taken along line EE';

[0047] Fig.16 is along Fig.14 A cross-sectional view of the display panel taken along line FF';

[0048] Fig.17 It is shown in detail Figure 4 A layout diagram of area Y;

[0049] Fig.18 is along Fig.17 A cross-sectional view of the display panel taken along line G-G';

[0050] Fig.19 It is shown in detail Figure 4A layout diagram of area Z;

[0051] Fig. 20 is shown along Fig.19 A cross-sectional view of the display panel taken along line H-H' and line II';

[0052] Fig.21 is a perspective view showing a head mounted display device according to one or more embodiments;

[0053] Fig. 22 It is shown Fig.21 An exploded perspective view of a head mounted display device; and

[0054] Fig.23 is a perspective view showing a head mounted display device according to one or more embodiments. DETAILED DESCRIPTION

[0055] By referring to the detailed description and the accompanying drawings of the embodiments, it is easier to understand the various aspects of the embodiments of the present disclosure and the methods for realizing them. Hereinafter, the embodiments will be described in more detail with reference to the accompanying drawings. However, the described embodiments can be implemented in various forms and should not be interpreted as being limited only to the embodiments shown in this article. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the various aspects of the present disclosure to those skilled in the art. Accordingly, the processes, elements and techniques that are not necessary for a person of ordinary skill in the art to fully understand the various aspects of the present disclosure may not be described.

[0056] Unless otherwise specified, in the entire drawings and written description, the same reference numerals, characters or combinations thereof represent the same elements, and therefore their description will not be repeated. In addition, in order to make the description clear, parts that are not related to the description of one or more embodiments may not be shown.

[0057] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity. Accordingly, the use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements.

[0058] Various embodiments are described herein with reference to cross-sectional views that are schematic illustrations of embodiments and / or intermediate structures. Thus, variations in the shapes of the illustrations resulting from, for example, manufacturing techniques and / or tolerances are contemplated. In addition, for purposes of describing embodiments according to the present disclosure, the specific structural or functional descriptions disclosed herein are merely illustrative. Therefore, the embodiments disclosed herein should not be construed as being limited to the shapes of the specific illustrated regions, but rather include deviations in shape resulting from, for example, manufacturing.

[0059] For example, an implanted region shown as a rectangle may have rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may produce some implantation in the region between the buried region and the surface for implantation. Therefore, the regions shown in the accompanying drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to be limiting. Additionally, those skilled in the art will appreciate that the described embodiments may be modified in a variety of different ways without departing from the scope of the present disclosure.

[0060] In the detailed description, for the purpose of explanation, numerous specific details are set forth to provide a thorough understanding of the various embodiments. However, it is apparent that the various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid unnecessary confusion of the various embodiments.

[0061] Spatially relative terms such as "beneath", "below", "lower", "under", "above", "upper" and similar may be used herein for convenience of explanation to describe the relationship between one element or feature and another (or some) element or feature as shown in the figures. It should be understood that, in addition to the orientations depicted in the figures, spatially relative terms are intended to also include different orientations of the device in use or in operation. For example, if the device in the figures is flipped, the element described as being "below" or "beneath" or "under" other elements or features will then be oriented to be "above" other elements or features. Therefore, the example terms "below" and "under" can include both the orientations of above and below. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. Similarly, when the first portion is described as being disposed “on” the second portion, this indicates that the first portion is disposed at the upper side or lower side of the second portion, without being limited to the upper side thereof based on the gravity direction.

[0062] Furthermore, in this specification, the phrase "on a plane" or "in a plan view" means observing a target portion from the top, and the phrase "in section" means observing a section formed by vertically cutting the target portion from the side.

[0063] It should be understood that when an element, layer, region, or component is referred to as being "formed" "on," "on," "connected to," or "coupled to" another element, layer, region, or component, it can be directly formed on, directly on, directly connected to, or directly coupled to, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to, such that there may be one or more intervening elements, layers, regions, or components. For example, when a layer, region, or component is referred to as being "electrically connected to" or "electrically coupled to" another layer, region, or component, it can be directly electrically connected or coupled to, or there may be intervening layers, regions, or components. However, "directly connected / directly coupled" means that one component is directly connected or coupled to another component without intermediate components. At the same time, other expressions describing the relationship between components such as "between", "immediately adjacent" or "adjacent" and "directly adjacent" may be similarly interpreted. In addition, it should be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0064] For the purposes of the present disclosure, expressions such as "at least one of," "one of," and "selected from," when following a list of elements, modify the entire list of elements without modifying the individual elements in the list. For example, "at least one of X, Y, and Z" and "at least one selected from the cluster consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as XYZ, XYY, XZ, YZ, and ZZ), or any variation thereof. Similarly, expressions such as "at least one of A and B" may include A, B, or A and B. As used herein, the term "and / or" includes any or all combinations of one or more of the relevant listed items. For example, expressions such as "A and / or B" may include A, B, or A and B. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0065] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed below may be referred to as a second element, component, region, layer or part without departing from the scope of the present disclosure.

[0066] In the example, the x-axis, y-axis and / or z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction and / or the third direction.

[0067] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. Unless otherwise clearly indicated in the context, the singular forms "a" and "an" as used herein are also intended to include the plural forms. It should also be understood that when the terms "comprise", "comprising", "have", "having", "include" and "including" are used in this specification, the existence of the stated features, wholes, steps, operations, elements and / or parts is specified, but the existence or addition of one or more other features, wholes, steps, operations, elements, parts and / or clusters thereof is not excluded.

[0068] As used herein, the terms "substantially," "about," "approximately," and the like are used as terms of approximation rather than terms of degree, and are intended to take into account the inherent deviations in measured or calculated values ​​that one of ordinary skill in the art would recognize. Taking into account the errors associated with the measurements and with the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximately" as used herein are inclusive of the stated value and mean within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value.

[0069] When one or more embodiments can be implemented in different ways, the specific process order may be performed differently from the described order. For example, two processes described in succession may be performed substantially simultaneously or in the reverse order of the described order.

[0070] In addition, any numerical range disclosed and / or listed herein is intended to include all sub-ranges of the same numerical precision included in the listed range. For example, the range of "1.0 to 10.0" is intended to include all sub-ranges between the minimum value of 1.0 listed and the maximum value of 10.0 listed (and including the minimum value of 1.0 listed and the maximum value of 10.0 listed), for example, all sub-ranges with a minimum value greater than or equal to 1.0 and a maximum value less than or equal to 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limit listed herein is intended to include all lower numerical limits included therein, and any minimum numerical limit listed in this specification is intended to include all greater numerical limits included therein. Therefore, the applicant reserves the right to modify this specification (including claims) to explicitly list any sub-ranges included in the scope explicitly listed herein.

[0071] The electronic or electrical devices and / or any other related devices or components described herein according to one or more embodiments of the present disclosure may be implemented using any suitable hardware, firmware (e.g., an application specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices may be formed on an integrated circuit (IC) chip or on separate IC chips. In addition, the various components of these devices may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate.

[0072] In addition, the various components of these devices may be processes or threads that run on one or more processors in one or more computing devices to execute computer program instructions and interact with other system components to perform the various functions described herein. Computer program instructions are stored in a memory, which can be implemented in a computing device using a standard memory device (e.g., such as a random access memory (RAM)). Computer program instructions may also be stored in other non-transitory computer-readable media (such as, for example, a CD-ROM, a flash drive, or the like). Moreover, those skilled in the art should recognize that the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed on one or more other computing devices without departing from the scope of the present disclosure.

[0073] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that, unless explicitly defined as such herein, terms such as those defined in commonly used dictionaries should be interpreted as having, for example, the meaning consistent with their meaning in the context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal sense.

[0074] Figure 1 is an exploded perspective view showing a display device according to one or more embodiments. Figure 2 is a block diagram illustrating a display device according to one or more embodiments.

[0075] Reference Figure 1 and Figure 2 , the display device 10 according to one or more embodiments is a device for displaying a moving image or a still image. The display device 10 according to one or more embodiments may be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation systems, ultra-mobile PCs (UMPCs), or the like. For example, the display device 10 according to one or more embodiments may be applied as a display of a television, a notebook computer, a monitor, a billboard, or an Internet of Things (IoT) terminal. Alternatively, the display device 10 according to one or more embodiments may be applied to smart watches, watch phones, head-mounted display (HMD) devices for realizing virtual reality and augmented reality, and the like.

[0076] The display device 10 according to one or more embodiments includes a display panel 100 , a heat dissipation layer 200 , a circuit board 300 , a timing control circuit 400 , and a power supply circuit 500 .

[0077] The display panel 100 may have a planar shape similar to a quadrilateral shape. For example, the display panel 100 may have a planar shape similar to a quadrilateral shape having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. In the display panel 100, an angle at which the short sides in the first direction DR1 and the long sides in the second direction DR2 intersect may be a right angle or a rounded angle having a curvature (e.g., a predetermined curvature). The planar shape of the display panel 100 is not limited to a quadrilateral shape, and may be a shape similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display device 10 may be consistent with the planar shape of the display panel 100, but the present disclosure is not limited thereto.

[0078] like Figure 2As shown in FIG. 1 , the display panel 100 includes a display area DAA for displaying an image, and a non-display area NDA where no image is displayed.

[0079] The display area DAA includes a plurality of pixels PX, a plurality of scan lines, a plurality of emission control lines EL, and a plurality of data lines DL.

[0080] A plurality of pixels PX may be arranged in a matrix in the first direction DR1 and the second direction DR2. A plurality of scan lines and a plurality of emission control lines EL may extend in the first direction DR1 while being arranged in the second direction DR2. A plurality of data lines DL may extend in the second direction DR2 while being arranged in the first direction DR1.

[0081] The plurality of scan lines include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines EBL. The plurality of emission control lines EL include a plurality of first emission control lines EL1 and a plurality of second emission control lines EL2.

[0082] The plurality of pixels PX include a plurality of sub-pixels SP1, SP2, and SP3. The plurality of sub-pixels SP1, SP2, and SP3 may include Figure 3 The plurality of pixel transistors shown in FIG. 1 and FIG. 2 may be formed by a semiconductor process and positioned on a semiconductor substrate SSUB (see FIG. 2 ). Figure 7 ). For example, a plurality of pixel transistors may be formed by a complementary metal oxide semiconductor (CMOS).

[0083] Each of the plurality of sub-pixels SP1, SP2, and SP3 may be connected to any one of the plurality of write scan lines GWL, any one of the plurality of control scan lines GCL, any one of the plurality of bias scan lines EBL, any one of the plurality of first emission control lines EL1, any one of the plurality of second emission control lines EL2, and any one of the plurality of data lines DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 may receive a data voltage of the data line DL in response to a write scan signal of the write scan line GWL, and emit light from the light emitting element according to the data voltage.

[0084] The non-display area NDA includes a scan driver 610 , an emission driver 620 , and a data driver 700 .

[0085] The scan driver 610 includes a plurality of scan transistors, and the emission driver 620 includes a plurality of emission transistors. The plurality of scan transistors and the plurality of emission transistors may be formed on a semiconductor substrate SSUB (see Figure 7). For example, a plurality of scanning transistors and a plurality of emission transistors may be formed by CMOS. Figure 2 , the scan driver 610 is shown to be positioned on the left side of the display area DAA, and the emission driver 620 is positioned on the right side of the display area DAA, but the present disclosure is not limited thereto. For example, the scan driver 610 and the emission driver 620 may be positioned on both the left and right sides of the display area DAA.

[0086] The scan driver 610 may include a write scan signal output 611, a control scan signal output 612, and a bias scan signal output 613. Each of the write scan signal output 611, the control scan signal output 612, and the bias scan signal output 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output 611 may generate a write scan signal according to the scan timing control signal SCS of the timing control circuit 400, and sequentially output them to the write scan line GWL. The control scan signal output 612 may generate a control scan signal in response to the scan timing control signal SCS, and sequentially output them to the control scan line GCL. The bias scan signal output 613 may generate a bias scan signal according to the scan timing control signal SCS, and sequentially output them to the bias scan line EBL.

[0087] The emission driver 620 includes a first emission control driver 621 and a second emission control driver 622. Each of the first emission control driver 621 and the second emission control driver 622 may receive an emission timing control signal ECS from the timing control circuit 400. The first emission control driver 621 may generate first emission control signals according to the emission timing control signal ECS and sequentially output them to the first emission control line EL1. The second emission control driver 622 may generate second emission control signals according to the emission timing control signal ECS and sequentially output them to the second emission control line EL2.

[0088] The data driver 700 may include a plurality of data transistors, and the plurality of data transistors may be formed on a semiconductor substrate SSUB (see Figure 7 For example, a plurality of data transistors of the data driver 700 may be formed of CMOS.

[0089] The data driver 700 may receive the digital video data DATA and the data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS, and outputs the analog data voltage to the data line DL. In this case, the sub-pixels SP1, SP2, and SP3 are selected by the write scan signal of the scan driver 610, and the data voltage may be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0090] The heat dissipation layer 200 may overlap the display panel 100 in the third direction DR3 which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be positioned on one surface of the display panel 100, for example, on the rear surface thereof. The heat dissipation layer 200 serves to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a conductive layer having high thermal conductivity, such as graphite, silver (Ag), copper (Cu), or aluminum (Al).

[0091] The circuit board 300 may be electrically connected to the first pad portion PDA1 of the display panel 100 by using a conductive adhesive such as an anisotropic conductive film (see Figure 4 ) of a plurality of first pads PD1 (see Figure 4 ). The circuit board 300 may be a flexible printed circuit board having a flexible material, or a flexible film. Figure 1 , the circuit board 300 is shown to be unfolded, but the circuit board 300 may be bent. In this case, one end of the circuit board 300 may be positioned on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. One end of the circuit board 300 may be the first pad portion PDA1 of the circuit board 300 connected to the display panel 100 by using a conductive adhesive (see Figure 4 ) of a plurality of first pads PD1 (see Figure 4 ) at the opposite end of the other end.

[0092] The timing control circuit 400 may receive digital video data DATA and a timing signal input from the outside. The timing control circuit 400 may generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100 in response to the timing signal. The timing control circuit 400 may output the scan timing control signal SCS to the scan driver 610 and the emission timing control signal ECS to the emission driver 620. The timing control circuit 400 may output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0093] The power supply circuit 500 may generate a plurality of panel driving voltages according to a power supply voltage from the outside. For example, the power supply circuit 500 may generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply them to the display panel 100. Figure 3 A first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT are described.

[0094] Each of the timing control circuit 400 and the power supply circuit 500 may be formed as an integrated circuit (IC) and attached to one surface of the circuit board 300. In this case, the scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 may be supplied to the display panel 100 through the circuit board 300. In addition, the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 may be supplied to the display panel 100 through the circuit board 300.

[0095] Alternatively, similar to the scan driver 610, the emission driver 620, and the data driver 700, each of the timing control circuit 400 and the power supply circuit 500 may be positioned in the non-display area NDA of the display panel 100. In this case, the timing control circuit 400 may include a plurality of timing transistors, and the power supply circuit 500 may include a plurality of power supply transistors. The plurality of timing transistors and the plurality of power supply transistors may be formed on the semiconductor substrate SSUB by a semiconductor process (see Figure 7 ). For example, the plurality of timing transistors and the plurality of power supply transistors may be formed of CMOS. Each of the timing control circuit 400 and the power supply circuit 500 may be positioned between the data driver 700 and the first pad portion PDA1 (see Figure 4 )between.

[0096] Figure 3 is an equivalent circuit diagram of a first subpixel according to one or more embodiments.

[0097] Reference Figure 3, the first sub-pixel SP1 may be connected to the write scan line GWL, the control scan line GCL, the bias scan line EBL, the first emission control line EL1, the second emission control line EL2, and the data line DL. In addition, the first sub-pixel SP1 may be connected to a first drive voltage line VSL to which a first drive voltage VSS corresponding to a low potential voltage is applied, a second drive voltage line VDL to which a second drive voltage VDD corresponding to a high potential voltage is applied, and a third drive voltage line VIL to which a third drive voltage VINT corresponding to an initialization voltage is applied. That is, the first drive voltage line VSL may be a low potential voltage line, the second drive voltage line VDL may be a high potential voltage line, and the third drive voltage line VIL may be an initialization voltage line. In this case, the first drive voltage VSS may be lower than the third drive voltage VINT. The second drive voltage VDD may be higher than the third drive voltage VINT.

[0098] The first subpixel SP1 includes a plurality of transistors T1 , T2 , T3 , T4 , T5 , and T6 , a light emitting element LE, a first capacitor C1 , and a second capacitor C2 .

[0099] The light emitting element LE emits light in response to a driving current flowing through the channel of the first transistor T1. The emission amount of the light emitting element LE may be proportional to the driving current. The light emitting element LE may be positioned between the fourth transistor T4 and the first driving voltage line VSL. The first electrode of the light emitting element ED may be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light emitting element ED may be connected to the first driving voltage line VSL. The first electrode of the light emitting element LE may be an anode electrode, and the second electrode of the light emitting element LE may be a cathode electrode. The light emitting element LE may be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer positioned between the first electrode and the second electrode, but the present disclosure is not limited thereto. For example, the light emitting element LE may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor positioned between the first electrode and the second electrode, in which case the light emitting element LE may be a micro light emitting diode.

[0100] The first transistor T1 may be a driving transistor that controls a source-drain current (hereinafter referred to as a "driving current") flowing between its source electrode and drain electrode according to a voltage applied to its gate electrode. The first transistor T1 includes a gate electrode connected to the first node N1, a source electrode connected to the drain electrode of the sixth transistor T6, and a drain electrode connected to the second node N2.

[0101] The second transistor T2 may be positioned between one electrode of the first capacitor C1 and the data line DL. The second transistor T2 is turned on by a write scan signal of the write scan line GWL to connect one electrode of the first capacitor C1 to the data line DL. Accordingly, a data voltage of the data line DL may be applied to one electrode of the first capacitor C1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor C1.

[0102] The third transistor T3 may be positioned between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal of the control scan line GCL to connect the first node N1 to the second node N2. To this end, since the gate electrode and the drain electrode of the first transistor T1 are connected, the first transistor T1 may operate like a diode. The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0103] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emission control signal of the first emission control line EL1 to connect the second node N2 to the third node N3. Accordingly, the driving current of the first transistor T1 may be supplied to the light emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0104] The fifth transistor T5 may be positioned between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line EBL to connect the third node N3 to the third driving voltage line VIL. Accordingly, the third driving voltage VINT of the third driving voltage line VIL may be applied to the first electrode of the light emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line EBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0105] The sixth transistor T6 may be positioned between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 is turned on by the second emission control signal of the second emission control line EL2 to connect the source electrode of the first transistor T1 to the second driving voltage line VDL. Accordingly, the second driving voltage VDD of the second driving voltage line VDL may be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emission control line EL2, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0106] The first capacitor C1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor C1 includes one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0107] The second capacitor C2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor C2 includes one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second driving voltage line VDL.

[0108] The first node N1 is a junction point between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor C1, and one electrode of the second capacitor C2. The second node N2 is a junction point between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a junction point between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light emitting element LE.

[0109] Each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be a P-type MOSFET, but the present disclosure is not limited thereto. Each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be an N-type MOSFET. Alternatively, one or more of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be a P-type MOSFET, and the remaining transistors may be N-type MOSFETs.

[0110] Although in Figure 3 FIG. 4 shows that the first sub-pixel SP1 includes six transistors T1, T2, T3, T4, T5 and T6 and two capacitors C1 and C2, but it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to Figure 3 For example, the number of transistors and the number of capacitors of the first sub-pixel SP1 are not limited to Figure 3 Those shown in .

[0111] In addition, the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 can be combined with Figure 3The equivalent circuit diagram of the first sub-pixel SP1 described is substantially the same. Therefore, the description of the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 is omitted in the present disclosure.

[0112] Figure 4 is a layout diagram showing a display panel according to one or more embodiments.

[0113] Reference Figure 4 According to one or more embodiments, the display area DAA of the display panel 100 includes a plurality of pixels PX arranged in a matrix form. According to one or more embodiments, the non-display area NDA of the display panel 100 includes a scan driver 610, an emission driver 620, a data driver 700, a first distribution circuit 710 and a second distribution circuit 720, a first pad portion (or a first pad area) PDA1, a second pad portion (or a second pad area) PDA2, a power connection portion (or a power connection area) PCA, a dam portion (or a dam area) DMA, an electrostatic protection area ESA, a permeation reduction area (e.g., an anti-permeation portion) MPA, and a crack reduction area (e.g., an anti-crack portion) CPA.

[0114] The scan driver 610 may be positioned on a first side of the display area DAA, and the emission driver 620 may be positioned on a second side of the display area DAA. For example, the scan driver 610 may be positioned on one side of the display area DAA in the first direction DR1, and the emission driver 620 may be positioned on the other side of the display area DAA in the first direction DR1. That is, the scan driver 610 may be positioned on the left side of the display area DAA, and the emission driver 620 may be positioned on the right side of the display area DAA. However, the present disclosure is not limited thereto, and the scan driver 610 and the emission driver 620 may be positioned on both the first side and the second side of the display area DAA.

[0115] The first pad portion PDA1 may include a plurality of first pads PD1 connected to pads or bumps of the circuit board 300 by a conductive adhesive. The first pad portion PDA1 may be positioned on a third side of the display area DAA. For example, the first pad portion PDA1 may be positioned on one side of the display area DAA in the second direction DR2.

[0116] The first pad portion PDA1 may be positioned outside the data driver 700 in the second direction DR2. That is, the first pad portion PDA1 may be closer to the edge of the display panel 100 than the data driver 700.

[0117] The second pad portion PDA2 may be positioned on a fourth side of the display area DAA. For example, the second pad portion PDA2 may be positioned on the other side of the display area DAA in the second direction DR2. The second pad portion PDA2 may include a plurality of second pads PD2 corresponding to inspection pads for testing whether the display panel 100 is functioning properly. The plurality of second pads PD2 may be connected to a fixture or a probe during the inspection process, or may be connected to a circuit board for inspection. The circuit board for inspection may be a rigid printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0118] The first distribution circuit 710 distributes the data voltage applied through the first pad portion PDA1 to the plurality of data lines DL. For example, the first distribution circuit 710 may distribute the data voltage applied through one first pad PD1 in the first pad portion PDA1 to P data lines DL (P is a positive integer of 2 or more), and as a result, the number of the plurality of first pads PD1 may be reduced. The first distribution circuit 710 may be positioned on a third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 may be positioned on one side of the display area DAA in the second direction DR2. That is, the first distribution circuit 710 may be positioned on the lower side of the display area DAA.

[0119] The second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan driver 610, the emission driver 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 may be configured to check the operation of each of the plurality of pixels PX in the display area DAA. The second distribution circuit 720 may be positioned on a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 may be positioned on the other side of the display area DAA in the second direction DR2. That is, the second distribution circuit 720 may be positioned on the upper side of the display area DAA.

[0120] Each of the scan driver 610, the first distribution circuit 710, and the second distribution circuit 720 may include a plurality of data transistors, and the plurality of data transistors may be formed by a semiconductor process and may be formed on a semiconductor substrate SSUB (see Figure 7 For example, a plurality of data transistors of each of the scan driver 610, the first distribution circuit 710, and the second distribution circuit 720 may be formed of CMOS.

[0121] The power connection part PCA refers to the light emitting element LE (see Figure 3 ) is connected to a region where the second electrode of the light emitting element LE is connected to a power connection electrode to which the first driving voltage VSS is applied, so that the first driving voltage VSS can be applied to the light emitting element LE (see Figure 3)'s second electrode.

[0122] The power connection portion PCA may be positioned to surround the display area DAA (as used herein, "surrounding" may mean "surrounding in a plan view"). In addition, the power connection portion PCA may be positioned outside the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720. For example, the power connection portion PCA may be closer to the edge of the display panel 100 than the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720. The power connection portion PCA may be positioned to surround the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720. However, the present disclosure is not limited thereto, and the power connection portion PCA may overlap with at least one of the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720 in the third direction DR3.

[0123] The dam portion DMA may be used to reduce or prevent the light emitting element LE from being packaged (see Figure 3 ) of the encapsulation layer TFE (see Figure 7 ) has an encapsulation organic layer TFE2 that overflows into the first pad portion PDA1 and the second pad portion PDA2.

[0124] The dam portion DMA may be positioned to surround the display area DAA. In addition, the dam portion DMA may be positioned outside the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720. For example, the dam portion DMA may be closer to the edge of the display panel 100 than the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720. The dam portion DMA may be positioned to surround the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720. However, the present disclosure is not limited thereto, and the dam portion DMA may overlap with at least one of the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720 in the third direction DR3.

[0125] In addition, the dam portion DMA may be positioned outside the power connection portion PCA. For example, the dam portion DMA may be closer to the edge of the display panel 100 than the power connection portion PCA. The dam portion DMA may be positioned to surround the power connection portion PCA.

[0126] The electrostatic protection area ESA may be a structure for protecting the plurality of pixels PX, the scan driver 610, the emission driver 620, the first distribution circuit 710, the second distribution circuit 720, the first pad portion PDA1, and the second pad portion PDA2 of the display panel 100 from static electricity applied from the outside. To this end, the first driving voltage VSS may be applied to the electrostatic protection area ESA. The electrostatic protection area ESA may be positioned to surround the display area DAA.

[0127] In addition, the electrostatic protection area ESA may be positioned outside the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720. For example, the electrostatic protection area ESA may be closer to the edge of the display panel 100 than the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720. The electrostatic protection area ESA may be positioned to surround the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720.

[0128] In addition, the electrostatic protection area ESA may be positioned outside the power connection portion PCA. For example, the electrostatic protection area ESA may be closer to the edge of the display panel 100 than the power connection portion PCA. The electrostatic protection area ESA may be positioned to surround the power connection portion PCA.

[0129] In addition, the electrostatic protection area ESA may be positioned outside the dam portion DMA. For example, the electrostatic protection area ESA may be closer to the edge of the display panel 100 than the dam portion DMA. The electrostatic protection area ESA may be positioned to surround the dam portion DMA.

[0130] In addition, the electrostatic protection area ESA may be positioned outside the first pad portion PDA1 and outside the second pad portion PDA2. For example, the electrostatic protection area ESA may be closer to the edge of the display panel 100 than the first pad portion PDA1 and the second pad portion PDA2. The electrostatic protection area ESA may be positioned to surround the first pad portion PDA1 and the second pad portion PDA2.

[0131] The penetration reduction area MPA can be used to protect the semiconductor substrate SSUB (see Figure 7 ) is protected from external moisture or oxygen. The permeation reduction area MPA may be positioned outside the electrostatic protection area ESA. For example, the permeation reduction area MPA may be closer to the edge of the display panel 100 than the electrostatic protection area ESA. The permeation reduction area MPA may be positioned to surround the electrostatic protection area ESA.

[0132] The crack reduction area CPA may be a structure for reducing or preventing the possibility that cracks generated at the edge of the display panel 100 due to an external impact propagate to the center of the display panel 100. The crack reduction area CPA may be positioned outside the permeation reduction area MPA. For example, the crack reduction area CPA may be closer to the edge of the display panel 100 than the permeation reduction area MPA. The crack reduction area CPA may be positioned to surround the permeation reduction area MPA.

[0133] Figure 5 It is shown Figure 4 Layout diagram of the first electrode, light-emitting area and pixel defining film of each sub-pixel in the display area.

[0134] Reference Figure 5 Each of the plurality of pixels PX includes a first emission area EA1 as a emission area of ​​a first subpixel SP1, a second emission area EA2 as a emission area of ​​a second subpixel SP2, and a third emission area EA3 as a emission area of ​​a third subpixel SP3.

[0135] Each of the first, second, and third emission regions EA1, EA2, and EA3 may be a region defined by the pixel defining film PDL. For example, each of the first, second, and third emission regions EA1, EA2, and EA3 may be a region defined by the first pixel defining film PDL1.

[0136] The length of the first light emitting region EA1 in the first direction DR1 may be smaller than the length of the second light emitting region EA2 in the first direction DR1, and may be smaller than the length of the third light emitting region EA3 in the first direction DR1. The length of the first light emitting region EA1 in the first direction DR1 may be substantially the same as the length of the second light emitting region EA2 in the first direction DR1 and the length of the third light emitting region EA3 in the first direction DR1.

[0137] In each of the plurality of pixels PX, the first light emitting area EA1 and the second light emitting area EA2 may be adjacent to each other in the first direction DR1. In addition, the first light emitting area EA1 and the third light emitting area EA3 may be adjacent to each other in the first direction DR1. In addition, the second light emitting area EA2 and the third light emitting area EA3 may be adjacent to each other in the second direction DR2. The area of ​​the first light emitting area EA1, the area of ​​the second light emitting area EA2, and the area of ​​the third light emitting area EA3 may be different.

[0138] The first light emitting area EA1 may emit light of a first color, the second light emitting area EA2 may emit light of a second color, and the third light emitting area EA3 may emit light of a third color. Here, the first color light may be light of a blue wavelength band, the second color light may be light of a green wavelength band, and the third color light may be light of a red wavelength band. For example, the blue wavelength band may be a wavelength band of light whose main peak wavelength is in the range of about 370 nm to about 460 nm, the green wavelength band may be a wavelength band of light whose main peak wavelength is in the range of about 480 nm to about 560 nm, and the red wavelength band may be a wavelength band of light whose main peak wavelength is in the range of about 600 nm to about 750 nm.

[0139] In a plan view, the first electrode AND of the light emitting element LE (see Figure 7 ) may have a rectangular shape. The planar shape of the first electrode AND of the light emitting element LE may be different in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, the first electrode AND of the first sub-pixel SP1 may have a rectangular shape having a short side in the first direction DR1 and a long side in the second direction DR2 in a plan view. The first electrode AND of each of the second sub-pixel SP2 and the third sub-pixel SP3 may have a rectangular shape having a long side in the first direction DR1 and a short side in the second direction DR2 in a plan view. The length of the first electrode AND of the second sub-pixel SP2 in the second direction DR2 may be shorter than the length of the first electrode AND of the third sub-pixel SP3 in the second direction DR2.

[0140] The first electrode AND of the light emitting element LE can be connected to the reflective electrode layer RL through the tenth via hole VA10 (see Figure 7 ). The tenth via hole VA10 may overlap the first pixel defining film PDL1 , the second pixel defining film PDL2 , and the third pixel defining film PDL3 in the third direction DR3 .

[0141] At least one groove TRC may be a structure for cutting off at least one charge generation layer of the light emitting stack IL between adjacent light emitting areas EA1, EA2, and EA3. At least one groove TRC may be positioned between the first light emitting area EA1 and the second light emitting area EA2, between the first light emitting area EA1 and the third light emitting area EA3, and between the second light emitting area EA2 and the third light emitting area EA3. For example, at least one groove TRC may be positioned between the first electrode AND of the first sub-pixel SP1 and the first electrode AND of the second sub-pixel SP2, between the first electrode AND of the first sub-pixel SP1 and the first electrode AND of the third sub-pixel SP3, and between the first electrode AND of the second sub-pixel SP2 and the first electrode AND of the third sub-pixel SP3.

[0142] Figure 6 is a layout diagram illustrating a first electrode, a light emitting region, and a pixel defining film of each of a plurality of sub-pixels according to yet one or more other embodiments.

[0143] Since the plane shapes of the first light emitting area EA1, the second light emitting area EA2 and the third light emitting area EA3 are different from those corresponding to Figure 5 Except for those different from one or more embodiments of Figure 6 One or more embodiments corresponding to Figure 5 One or more embodiments of the present invention are substantially the same, and thus the description corresponding to Figure 5 A description of one or more embodiments is repeated.

[0144] Reference Figure 6 , the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may be positioned in a hexagonal structure having a hexagonal shape in a plan view. In this case, the first light emitting area EA1 and the second light emitting area EA2 may be adjacent to each other in the first direction DR1, but the second light emitting area EA2 and the third light emitting area EA3 may be adjacent to each other in the first oblique direction DD1, and the first light emitting area EA1 and the third light emitting area EA3 may be adjacent to each other in the second oblique direction DD2. The first oblique direction DD1 may be a direction between the first direction DR1 and the second direction DR2, and may refer to a direction inclined 45 degrees relative to the first direction DR1 and the second direction DR2, and the second oblique direction DD2 may be a direction perpendicular to the first oblique direction DD1.

[0145] exist Figure 5 and Figure 6 , each of the plurality of pixels PX includes three emission areas EA1, EA2, and EA3, but the present disclosure is not limited thereto. That is, each of the plurality of pixels PX may include four emission areas.

[0146] In addition, the arrangement of the light emitting areas EA1, EA2, and EA3 of the plurality of pixels PX is not limited to Figure 5 and Figure 6 For example, the light emitting regions of the plurality of pixels PX may be positioned in a stripe structure in which the light emitting regions are arranged in a first direction DR1, a structure in which the light emitting regions are arranged in a diamond shape, or a structure in which the light emitting regions are arranged in a stripe shape. Structure or similar ( and PENTILE TM is a registered trademark of Samsung Display Co., Ltd. of South Korea).

[0147] Figure 7 is shown along Figure 5 A cross-sectional view of the display device taken along line AA'.

[0148] Reference Figure 7 , the display panel 100 includes a semiconductor backplane SBP, a light emitting element backplane EBP, a display element layer EML, an encapsulation layer TFE, an optical layer OPL, a cover layer CVL and a polarizing plate POL.

[0149] The semiconductor backplane SBP includes: a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating layers covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR, respectively. Figure 3 The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are described.

[0150] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a first type of impurity. A plurality of well regions WA may be positioned on the top surface of the semiconductor substrate SSUB. The plurality of well regions WA may be regions doped with a second type of impurity. The second type of impurity may be different from the first type of impurity described above. For example, if the first type of impurity is a p-type impurity, the second type of impurity may be an n-type impurity. Alternatively, if the first type of impurity is an n-type impurity, the second type of impurity may be a p-type impurity.

[0151] Each of the plurality of well regions WA includes a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode of the pixel transistor PTR, and a channel region CH positioned between the source region SA and the drain region DA.

[0152] The lower insulating layer BINS may be positioned between the gate electrode GE and the well area WA. The side insulating layer SINS may be positioned on a side surface of the gate electrode GE. The side insulating layer SINS may be positioned on the lower insulating layer BINS.

[0153] Each of the source region SA and the drain region DA may be a region doped with first type impurities. The gate electrode GE of the pixel transistor PTR may overlap the well region WA in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be positioned on one side of the gate electrode GE (for example, in a plan view), and the drain region DA may be positioned on the other side of the gate electrode GE.

[0154] Each of the plurality of well regions WA further includes a first low-concentration impurity region LDD1 positioned between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 positioned between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region having an impurity concentration lower than that of the source region SA due to the lower insulating layer BINS. The second low-concentration impurity region LDD2 may be a region having an impurity concentration lower than that of the drain region DA due to the lower insulating layer BINS. Due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, the distance between the source region SA and the drain region DA may be increased. Therefore, the length of the channel region CH of each of the plurality of pixel transistors PTR may be increased, thereby reducing or preventing the possibility of breakdown and hot carrier phenomena that may be caused by a short channel.

[0155] The first semiconductor insulating layer SINS1 may be positioned on the semiconductor substrate SSUB (as used herein, “on” may mean “above” or “over”). The first semiconductor insulating layer SINS1 may be made of silicon carbonitride (SiCN) or silicon oxide (SiO x )-based inorganic layer is formed, but the present disclosure is not limited thereto.

[0156] The second semiconductor insulating layer SINS2 may be positioned on the first semiconductor insulating layer SINS1. The second semiconductor insulating layer SINS2 may be made of silicon oxide (SiO x )-based inorganic layer is formed, but the present disclosure is not limited thereto.

[0157] A plurality of contact terminals CTE may be positioned on the second semiconductor insulating layer SINS2. Each of the plurality of contact terminals CTE may be connected to any one of the gate electrode GE, the source area SA, and the drain area DA of each of the plurality of pixel transistors PTR through a hole penetrating the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2. The plurality of contact terminals CTE may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ti), and neodymium (Nd), or an alloy containing any one of them.

[0158] The third semiconductor insulating layer SINS3 may be positioned on a side surface of each of the plurality of contact terminals CTE. A top surface of each of the plurality of contact terminals CTE may be exposed without being covered by the third semiconductor insulating layer SINS3. The third semiconductor insulating layer SINS3 may be made of silicon oxide (SiO x )-based inorganic layer is formed, but the present disclosure is not limited thereto.

[0159] The semiconductor substrate SSUB may be replaced with a glass substrate or a polymer resin substrate (such as polyimide). In this case, the thin film transistor may be positioned on the glass substrate or the polymer resin substrate. The glass substrate may be a rigid substrate that does not bend, and the polymer resin substrate may be a flexible substrate that can be bent or folded.

[0160] The light emitting element backplane EBP includes a first conductive layer ML1, a second conductive layer ML2, a third conductive layer ML3, a fourth conductive layer ML4, a fifth conductive layer ML5, a sixth conductive layer ML6, a seventh conductive layer ML7 and an eighth conductive layer ML8 and a plurality of vias VA1, VA2, VA3, VA4, VA5, VA6, VA7, VA8 and VA9. In addition, the light emitting element backplane EBP includes a plurality of interlayer insulating layers INS1, INS2, INS3, INS4, INS5, INS6, INS7, INS8 and INS9 positioned respectively between the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, the sixth conductive layer ML6, the seventh conductive layer ML7 and the eighth conductive layer ML8.

[0161] The first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, the sixth conductive layer ML6, the seventh conductive layer ML7 and the eighth conductive layer ML8 are used to connect a plurality of contact terminals CTE exposed from the semiconductor backplane SBP, thereby realizing Figure 3 The circuit of the first sub-pixel SP1 shown in FIG. That is, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are formed only on the semiconductor backplane SBP, and the connection between the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 and the first capacitor C1 and the second capacitor C2 is completed through the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, the sixth conductive layer ML6, the seventh conductive layer ML7 and the eighth conductive layer ML8. In addition, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5 and the first electrode of the light emitting element LE is also completed through the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, the sixth conductive layer ML6, the seventh conductive layer ML7 and the eighth conductive layer ML8.

[0162] The first interlayer insulating layer INS1 may be positioned on the semiconductor backplane SBP. Each of the plurality of first vias VA1 may penetrate the first interlayer insulating layer INS1 to be connected to the contact terminal CTE exposed from the semiconductor backplane SBP. Each of the plurality of first conductive layers ML1 may be positioned on the first interlayer insulating layer INS1 and may be connected to the first vias VA1.

[0163] The second interlayer insulating layer INS2 may be positioned on the first interlayer insulating layer INS1 and the plurality of first conductive layers ML1. Each of the plurality of second via holes VA2 may penetrate the second interlayer insulating layer INS2 and may be connected to the exposed first conductive layer ML1. Each of the plurality of second conductive layers ML2 may be positioned on the second interlayer insulating layer INS2 and may be connected to the second via holes VA2.

[0164] The third interlayer insulating layer INS3 may be positioned on the second interlayer insulating layer INS2 and the plurality of second conductive layers ML2. Each of the plurality of third via holes VA3 may penetrate the third interlayer insulating layer INS3 and may be connected to the exposed second conductive layer ML2. Each of the plurality of third conductive layers ML3 may be positioned on the third interlayer insulating layer INS3 and may be connected to the third via holes VA3.

[0165] The fourth interlayer insulating layer INS4 may be positioned on the third interlayer insulating layer INS3 and the plurality of third conductive layers ML3. Each of the plurality of fourth vias VA4 may penetrate the fourth interlayer insulating layer INS4 and may be connected to the exposed third conductive layer ML3. Each of the plurality of fourth conductive layers ML4 may be positioned on the fourth interlayer insulating layer INS4 and may be connected to the fourth via VA4.

[0166] The fifth interlayer insulating layer INS5 may be positioned on the fourth interlayer insulating layer INS4 and the plurality of fourth conductive layers ML4. Each of the plurality of fifth vias VA5 may penetrate the fifth interlayer insulating layer INS5 and may be connected to the exposed fourth conductive layer ML4. Each of the plurality of fifth conductive layers ML5 may be positioned on the fifth interlayer insulating layer INS5 and may be connected to the fifth vias VA5.

[0167] The sixth interlayer insulating layer INS6 may be positioned on the fifth interlayer insulating layer INS5 and the plurality of fifth conductive layers ML5. Each of the plurality of sixth vias VA6 may penetrate the sixth interlayer insulating layer INS6 and may be connected to the exposed fifth conductive layer ML5. Each of the plurality of sixth conductive layers ML6 may be positioned on the sixth interlayer insulating layer INS6 and may be connected to the sixth via VA6.

[0168] The seventh interlayer insulating layer INS7 may be positioned on the sixth interlayer insulating layer INS6 and the plurality of sixth conductive layers ML6. Each of the plurality of seventh vias VA7 may penetrate the seventh interlayer insulating layer INS7 and may be connected to the exposed sixth conductive layer ML6. Each of the plurality of seventh conductive layers ML7 may be positioned on the seventh interlayer insulating layer INS7 and may be connected to the seventh via VA7.

[0169] The eighth interlayer insulating layer INS8 may be positioned on the seventh interlayer insulating layer INS7 and the plurality of seventh conductive layers ML7. Each of the plurality of eighth vias VA8 may penetrate the eighth interlayer insulating layer INS8 and may be connected to the exposed seventh conductive layer ML7. Each of the plurality of eighth conductive layers ML8 may be positioned on the eighth interlayer insulating layer INS8 and may be connected to the eighth vias VA8.

[0170] The first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, the sixth conductive layer ML6, the seventh conductive layer ML7 and the eighth conductive layer ML8 and the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, the seventh via VA7 and the eighth via VA8 may be formed of substantially the same material. The first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, the sixth conductive layer ML6, the seventh conductive layer ML7 and the eighth conductive layer ML8 and the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, the seventh via VA7 and the eighth via VA8 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or an alloy containing any one of them. The first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, the seventh via VA7 and the eighth via VA8 may be made of substantially the same material. The first interlayer insulating layer INS1, the second interlayer insulating layer INS2, the third interlayer insulating layer INS3, the fourth interlayer insulating layer INS4, the fifth interlayer insulating layer INS5, the sixth interlayer insulating layer INS6, the seventh interlayer insulating layer INS7 and the eighth interlayer insulating layer INS8 may be made of silicon oxide (SiO x )-based inorganic layer is formed, but the present disclosure is not limited thereto.

[0171] The thickness of the first conductive layer ML1, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 may be respectively greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be greater than the thickness of the first conductive layer ML1. The thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 may be substantially the same. For example, the thickness of the first conductive layer ML1 may be approximately The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be approximately And the thickness of each of the first via hole VA1, the second via hole VA2, the third via hole VA3, the fourth via hole VA4, the fifth via hole VA5, and the sixth via hole VA6 may be approximately

[0172] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thickness of the first conductive layer ML1, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 may be greater than the thickness of the seventh via VA7 and the thickness of the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 may be greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 may be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be approximately The thickness of each of the seventh via hole VA7 and the eighth via hole VA8 may be approximately

[0173] The ninth interlayer insulating layer INS9 may be positioned on the eighth interlayer insulating layer INS8 and the plurality of eighth conductive layers ML8. The ninth interlayer insulating layer INS9 may be made of silicon oxide (SiO x )-based inorganic layer is formed, but the present disclosure is not limited thereto.

[0174] Each of the plurality of ninth via holes VA9 may penetrate the ninth interlayer insulating layer INS9 and may be connected to the exposed eighth conductive layer ML8. The ninth via hole VA9 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ti), and neodymium (Nd), or an alloy containing any one of them. The thickness of the ninth via hole VA9 may be approximately

[0175] The display element layer EML may be positioned on the light emitting element backplane EBP. The display element layer EML includes a reflective electrode layer RL, a tenth interlayer insulating layer INS10, a plurality of light emitting elements LE, a pixel defining film PDL and a plurality of trenches TRC. Each of the plurality of light emitting elements LE includes a first electrode AND, a light emitting stack IL and a second electrode CAT.

[0176] The reflective electrode layer RL may be positioned on the ninth interlayer insulating layer INS9. The reflective electrode layer RL may include at least one reflective electrode. Figure 7 As shown in , the reflective electrode layer RL may include first, second, third, and fourth reflective electrodes RL1, RL2, RL3, and RL4, and a step layer STPL.

[0177] Each of the plurality of first reflective electrodes RL1 may be positioned on the ninth interlayer insulating layer INS9 and may be connected to the ninth via hole VA9. The first reflective electrode RL1 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ti), and neodymium (Nd), or an alloy containing any one of them. The first reflective electrode RL1 may include titanium nitride (TiN).

[0178] The second reflective electrode RL2 may be positioned on the first reflective electrode RL1. The second reflective electrode RL2 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ti), and neodymium (Nd), or an alloy containing any one of them. For example, the second reflective electrode RL2 may include aluminum.

[0179] In the first sub-pixel SP1, the step layer STPL may be positioned on the second reflective electrode RL2. The step layer STPL may be omitted from the second sub-pixel SP2 and the third sub-pixel SP3. In order to advantageously reflect the light of the first color emitted from the first stacked layer IL1 of the first sub-pixel SP1, the thickness of the step layer STPL may be set in consideration of the wavelength of the light of the first color and the distance from the first stacked layer IL1 to the fourth reflective electrode RL4. The step layer STPL may be made of silicon carbon nitride (SiCN) or silicon oxide (SiO x) is formed as a base inorganic layer, but the present disclosure is not limited thereto. The thickness of the step layer STPL may be about

[0180] In the first sub-pixel SP1, the third reflective electrode RL3 may be positioned on the second reflective electrode RL2 and the step layer STPL. In the second sub-pixel SP2 and the third sub-pixel SP3, the third reflective electrode RL3 may be positioned on the second reflective electrode RL2. The third reflective electrode RL3 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ti), and neodymium (Nd), or an alloy containing any one of them. For example, the third reflective electrode RL3 may include titanium nitride (TiN).

[0181] In one or more embodiments, at least one of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3 may be omitted.

[0182] The fourth reflective electrode RL4 may be positioned on the third reflective electrode RL3, respectively. The fourth reflective electrode RL4 may reflect light from the first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3. The fourth reflective electrode RL4 may include a metal having a high reflectivity to advantageously reflect light. The fourth reflective electrode RL4 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ti), and neodymium (Nd), or an alloy containing any one of them. For example, the fourth reflective electrode RL4 may include titanium (Ti).

[0183] The tenth interlayer insulating layer INS10 may be positioned on the ninth interlayer insulating layer INS9 and the fourth reflective electrode RL4. The tenth interlayer insulating layer INS10 may be an optical auxiliary layer through which light reflected by the reflective electrode layer RL from among the light emitted from the light emitting element LE passes. The tenth interlayer insulating layer INS10 may be made of silicon oxide (SiO x )-based inorganic layer is formed, but the present disclosure is not limited thereto.

[0184] Each of the plurality of tenth via holes VA10 may penetrate the tenth interlayer insulating layer INS10 and may be connected to the exposed fourth reflective electrode RL4. The tenth via hole VA10 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ti), and neodymium (Nd), or an alloy containing any one of them. Due to the presence of the step layer STPL, the thickness of the tenth via hole VA10 in the first sub-pixel SP1 may be less than the thickness of the tenth via hole VA10 in each of the second sub-pixel SP2 and the third sub-pixel SP3. For example, the thickness of the tenth via hole VA10 in the first sub-pixel SP1 may be about 1000 Å. And the thickness of the tenth via hole VA10 in each of the second sub-pixel SP2 and the third sub-pixel SP3 may be about 100 mm.

[0185] In at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, in order to adjust the resonance distance of the light emitted from the light emitting element LE, the step layer STPL may be omitted from at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. Alternatively, the thickness of the step layer STPL may be different in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. Due to the presence or thickness difference of the step layer STPL, the distance between the first electrode AND and the reflective electrode layer RL may be different in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. That is, in order to adjust the distance from the reflective electrode layer RL to the first electrode AND according to the main wavelength of the light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the presence or absence of the step layer STPL or the thickness of the step layer STPL may be determined in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. Figure 7 It is shown that the distance between the first electrode AND and the reflective electrode layer RL in the first subpixel SP1 is smaller than the distance between the first electrode AND and the reflective electrode layer RL in the second subpixel SP2 and smaller than the distance between the first electrode AND and the reflective electrode layer RL in the third subpixel SP3, but the present disclosure is not limited thereto.

[0186] Each of the plurality of tenth via holes VA10 may penetrate the tenth interlayer insulating layer INS10 in the second sub-pixel SP2 and the third sub-pixel SP3, and may be connected to the exposed fourth reflective electrode RL4. The tenth via hole VA10 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ti), and neodymium (Nd), or an alloy including any one of them. The thickness of the tenth via hole VA10 in the second sub-pixel SP2 may be less than the thickness of the tenth via hole VA10 in the third sub-pixel SP3.

[0187] The first electrode AND of each of the plurality of light emitting elements LE may be positioned on the tenth interlayer insulating layer INS10 and may be connected to the tenth via VA10. The first electrode AND of each of the plurality of light emitting elements LE may be connected to the drain area DA or the source area SA of the pixel transistor PTR through the tenth via VA10, the first reflective electrode RL1, the second reflective electrode RL2, the third reflective electrode RL4, and the fourth reflective electrode RL4, the first via VA1 to the ninth via VA9, the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, the sixth conductive layer ML6, the seventh conductive layer ML7, and the eighth conductive layer ML8, and the contact terminal CTE. The first electrode AND of each of the plurality of light emitting elements LE may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ti), and neodymium (Nd), or an alloy containing any one of them. For example, the first electrode AND of each of the plurality of light emitting elements LE may be titanium nitride (TiN).

[0188] The pixel definition film PDL may be positioned on a portion of the first electrode AND of each of the plurality of light emitting elements LE. The pixel definition film PDL may cover an edge of the first electrode AND of each of the plurality of light emitting elements LE. The pixel definition film PDL may be used to separate the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3.

[0189] The first light emitting area EA1 may be defined as an area where the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second light emitting area EA2 may be defined as an area where the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third light emitting area EA3 may be defined as an area where the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0190] The pixel definition film PDL may include a first pixel definition film PDL1, a second pixel definition film PDL2, and a third pixel definition film PDL3. The first pixel definition film PDL1 may be positioned on the edge of the first electrode AND of each of the plurality of light emitting elements LE, the second pixel definition film PDL2 may be positioned on the first pixel definition film PDL1, and the third pixel definition film PDL3 may be positioned on the second pixel definition film PDL2. The first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 may be made of silicon oxide (SiO x)-based inorganic layer, but the present disclosure is not limited thereto. The first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may each have a thickness of about Thickness.

[0191] When the first pixel defining film PDL1, the second pixel defining film PDL2 and the third pixel defining film PDL3 are formed into one pixel defining film, the height of the one pixel defining film increases, so that the first encapsulation inorganic layer TFE1 can be cut off due to step coverage. Step coverage refers to the ratio of the degree of film coating on the inclined portion to the degree of film coating on the flat portion. The lower the step coverage, the greater the possibility that the film will be cut off at the inclined portion.

[0192] Therefore, in order to reduce or prevent the possibility of the first encapsulation inorganic layer TFE1 being cut off due to the step coverage, the first pixel defining film PDL1, the second pixel defining film PDL2 and the third pixel defining film PDL3 may have a cross-sectional structure with a step portion. For example, the width of the first pixel defining film PDL1 may be greater than the width of the second pixel defining film PDL2 and the width of the third pixel defining film PDL3. And for example, the width of the second pixel defining film PDL2 may be greater than the width of the third pixel defining film PDL3. The width of the first pixel defining film PDL1 refers to the horizontal length of the first pixel defining film PDL1 defined in the first direction DR1 and the second direction DR2.

[0193] Each of the plurality of trenches TRC may penetrate the first pixel defining film PDL1 , the second pixel defining film PDL2 , and the third pixel defining film PDL3 . The tenth interlayer insulating layer INS10 may be partially recessed at each of the plurality of trenches TRC.

[0194] At least one trench TRC may be positioned between adjacent sub-pixels SP1, SP2, and SP3. Figure 7 It is shown that two trenches TRC are positioned between adjacent sub-pixels SP1 , SP2 , and SP3 , but the present disclosure is not limited thereto.

[0195] The light emitting stack IL may include a plurality of stacked layers. Figure 7 The light emitting stack IL is shown to have a triple series structure including a first stack layer IL1, a second stack layer IL2, and a third stack layer IL3, but the present disclosure is not limited thereto. For example, the light emitting stack IL may have a double series structure including two stack layers.

[0196] In the three-series structure, the light emitting stack IL may have a series structure including a plurality of stack layers IL1, IL2, and IL3 emitting different lights. For example, the light emitting stack IL may include a first stack layer IL1 emitting light of a first color, a second stack layer IL2 emitting light of a third color, and a third stack layer IL3 emitting light of a second color. The first stack layer IL1, the second stack layer IL2, and the third stack layer IL3 may be sequentially stacked.

[0197] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first organic light emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second organic light emitting layer emitting light of a third color, and a second electron transport layer are sequentially stacked. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third organic light emitting layer emitting light of a second color, and a third electron transport layer are sequentially stacked.

[0198] The first charge generation layer for supplying holes to the second stack layer IL2 and for supplying electrons to the first stack layer IL1 may be positioned between the first stack layer IL1 and the second stack layer IL2. The first charge generation layer may include an N-type charge generation layer for supplying electrons to the first stack layer IL1 and a P-type charge generation layer for supplying holes to the second stack layer IL2. The N-type charge generation layer may include a dopant of a metal material.

[0199] The second charge generation layer for supplying holes to the third stacked layer IL3 and for supplying electrons to the second stacked layer IL2 may be positioned between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an N-type charge generation layer for supplying electrons to the second stacked layer IL2 and a P-type charge generation layer for supplying holes to the third stacked layer IL3.

[0200] The first stacked layer IL1 may be positioned on the first electrode AND and the pixel defining film PDL, and may be positioned on the bottom surface of each groove TRC. Due to the groove TRC, the first stacked layer IL1 may be cut off between adjacent sub-pixels SP1, SP2, and SP3. The second stacked layer IL2 may be positioned on the first stacked layer IL1. Due to the groove TRC, the second stacked layer IL2 may be cut off between adjacent sub-pixels SP1, SP2, and SP3. The cavity ESS or empty space may be positioned between the first stacked layer IL1 and the second stacked layer IL2. The third stacked layer IL3 may be positioned on the second stacked layer IL2. The third stacked layer IL3 is not cut off by the groove TRC, and may be positioned to cover the second stacked layer IL2 in each of the plurality of grooves TRC (for example, to cover the edge of the second stacked layer IL2 in each of the plurality of grooves TRC). That is, in the three-series structure, each of the plurality of grooves TRC may be a structure of the first stacked layer IL1 and the second stacked layer IL2, the first charge generation layer, and the second charge generation layer for cutting off the display element layer EML between the adjacent sub-pixels SP1, SP2, and SP3. In addition, in the dual tandem structure, each of the plurality of trenches TRC may be a structure for cutting off the lower stack layer and the charge generation layer positioned between the lower stack layer and the upper stack layer.

[0201] In order to stably cut off the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent sub-pixels SP1, SP2 and SP3, the height of each of the plurality of grooves TRC may be greater than the height of the pixel defining film PDL. The height of each of the plurality of grooves TRC refers to the length of each of the plurality of grooves TRC in the third direction DR3. The height of the pixel defining film PDL refers to the length of the pixel defining film PDL in the third direction DR3. In order to cut off the first stacked layer IL1, the second stacked layer IL2 and the third stacked layer IL3 of the display element layer EML between adjacent sub-pixels SP1, SP2 and SP3, there may be another structure to replace the groove TRC. For example, instead of the groove TRC, an inverted tapered partition wall may be positioned on the pixel defining film PDL.

[0202] The number of stacked layers emitting different light is not limited to Figure 7 . For example, the light emitting stack IL may include two stack layers. In this case, one of the two stack layers may be substantially the same as the first stack layer IL1, and the other stack layer may include a second hole transport layer, a second organic light emitting layer, a third organic light emitting layer, and a second electron transport layer. In this case, a charge generation layer for supplying electrons to one stack layer and holes to the other stack layer may be positioned between the two stack layers.

[0203] in addition, Figure 7It is shown that the first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 are all positioned in the first light-emitting area EA1, the second light-emitting area EA2, and the third light-emitting area EA3, but the present disclosure is not limited thereto. For example, the first stacked layer IL1 may be positioned in the first light-emitting area EA1, and may be omitted from the second light-emitting area EA2 and the third light-emitting area EA3. In addition, the second stacked layer IL2 may be positioned in the second light-emitting area EA2, and may be omitted from the first light-emitting area EA1 and the third light-emitting area EA3. In addition, the third stacked layer IL3 may be positioned in the third light-emitting area EA3, and may be omitted from the first light-emitting area EA1 and the second light-emitting area EA2. In this case, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL may be omitted.

[0204] The second electrode CAT may be positioned on the third stacked layer IL3. The second electrode CAT may be positioned on the third stacked layer IL3 in each of the plurality of trenches TRC. The second electrode CAT may be formed of a transparent conductive material (TCO) capable of transmitting light, such as ITO or IZO, or of a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. When the second electrode CAT is formed of a semi-transmissive conductive material, light emission efficiency may be improved in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 due to a microcavity effect.

[0205] The encapsulation layer TFE may be positioned on the display element layer EML. The encapsulation layer TFE may include at least one inorganic layer to reduce or prevent oxygen or moisture from penetrating into the display element layer EML. In addition, the encapsulation layer TFE may include at least one organic layer to protect the display element layer EML from foreign matter such as dust. For example, the encapsulation layer TFE may include a first encapsulation inorganic layer TFE1, an encapsulation organic layer TFE2, and a second encapsulation inorganic layer TFE3.

[0206] The first encapsulation inorganic layer TFE1 may be positioned on the second electrode CAT, the encapsulation organic layer TFE2 may be positioned on the first encapsulation inorganic layer TFE1, and the second encapsulation inorganic layer TFE3 may be positioned on the encapsulation organic layer TFE2. The first encapsulation inorganic layer TFE1 and the second encapsulation inorganic layer TFE3 may be composed of silicon nitride (SiN x ) layer, silicon oxynitride (SiON) layer, silicon oxide (SiO x ) layer, titanium oxide (TiO x ) layer or aluminum oxide (AlO x ) layers are alternately stacked. The encapsulating organic layer TFE2 may be a monomer. Alternatively, the encapsulating organic layer TFE2 may be an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin or the like.

[0207] The adhesive layer ADL may be a layer for bonding the encapsulation layer TFE to the optical layer OPL. The adhesive layer ADL may be a double-sided adhesive. In addition, the adhesive layer ADL may be a transparent adhesive, such as a transparent adhesive resin.

[0208] The optical layer OPL includes a plurality of color filters CF1, CF2, and CF3, a plurality of lenses LNS, and a filling layer FIL. The plurality of color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be positioned on the adhesive layer ADL.

[0209] The first color filter CF1 may overlap the first emission area EA1 of the first subpixel SP1. The first color filter CF1 may transmit light of a first color (e.g., light of a blue wavelength band). The blue wavelength band may be about 370 nm to about 460 nm. Therefore, the first color filter CF1 may transmit light of the first color among the light emitted from the first emission area EA1.

[0210] The second color filter CF2 may overlap with the second light emitting area EA2 of the second sub-pixel SP2. The second color filter CF2 may transmit light of a second color (e.g., light of a green wavelength band). The green wavelength band may be about 480 nm to about 560 nm. Therefore, the second color filter CF2 may transmit light of a second color among the light emitted from the second light emitting area EA2.

[0211] The third color filter CF3 may overlap with the third emission area EA3 of the third sub-pixel SP3. The third color filter CF3 may transmit light of a third color (e.g., light of a red wavelength band). The red wavelength band may be about 600 nm to about 750 nm. Therefore, the third color filter CF3 may transmit light of a third color among the light emitted from the third emission area EA3.

[0212] The plurality of lenses LNS may be positioned on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the plurality of lenses LNS may be a structure for increasing the proportion of light guided to the front of the display device 10. Each of the plurality of lenses LNS may have a cross-sectional shape convex in an upward direction.

[0213] The filling layer FIL may be positioned on the plurality of lenses LNS. The filling layer FIL may have a refractive index (e.g., a predetermined refractive index) so that light travels in the third direction DR3 at an interface between the filling layer FIL and the plurality of lenses LNS. In addition, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0214] The cover layer CVL may be positioned on the filling layer FIL. The cover layer CVL may be a glass substrate or a polymer resin. When the cover layer CVL is a glass substrate, it may be attached to the filling layer FIL. In this case, the filling layer FIL may be used to bond the cover layer CVL. When the cover layer CVL is a glass substrate, it may be used as a packaging substrate. When the cover layer CVL is a polymer resin, it may be directly applied to the filling layer FIL.

[0215] The polarizing plate POL may be positioned on one surface of the cover layer CVL. The polarizing plate POL may be a structure for reducing or preventing visibility degradation caused by reflection of external light. The polarizing plate POL may include a linear polarizing plate and a phase delay film. For example, the phase delay film may be a λ / 4 plate (quarter wave plate), but the present disclosure is not limited thereto. However, if the visibility degradation caused by reflection of external light is sufficiently overcome by the first color filter CF1, the second color filter CF2, and the third color filter CF3, the polarizing plate POL may be omitted.

[0216] like Figure 7 As shown in , by forming a light emitting element backplane EBP and a display element layer EML on a semiconductor substrate SSUB on which a plurality of transistors are formed, the size of a plurality of pixels PX can be greatly reduced so that a display device 10 displaying a high-resolution image can be provided.

[0217] Figure 8 It is shown Figure 4 A layout diagram of a first pad of a first pad portion. Fig. 9 is shown along Figure 8 A cross-sectional view of the display panel taken along line BB'.

[0218] Reference Figure 8 and Fig. 9 , each of the plurality of first pads PD1 includes a first sub-pad BPD and a second sub-pad IPD in which the pad conductive layer PML is separated by a tenth interlayer insulating layer INS10. Both the first sub-pad BPD and the second sub-pad IPD may be electrically connected to a pad or a bump of the circuit board 300 through a conductive adhesive. In addition, the second sub-pad IPD may be a pad connected to a jig or a probe during an inspection process, or may be a pad connected to a circuit board for inspection.

[0219] The area of ​​the first sub-pad BPD may be greater than the area of ​​the second sub-pad IPD. The length of the first sub-pad BPD in the first direction DR1 may be substantially the same as the length of the second sub-pad IPD in the first direction DR1. The length of the first sub-pad BPD in the second direction DR2 may be greater than the length of the second sub-pad IPD in the second direction DR2.

[0220] The pad conductive layer PML may include a first sub-pad conductive layer SPML1 and a second sub-pad conductive layer SPML2. The first sub-pad conductive layer SPML1 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or an alloy including any one of them. The second sub-pad conductive layer SPML2 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or an alloy including any one of them. For example, the first sub-pad conductive layer SPML1 may be made of aluminum (Al) and may have an approximate In addition, the second sub-pad conductive layer SPML2 may be made of titanium nitride (TiN) and may have a thickness of approximately The thickness of the pad conductive layer PML may be greater than the thickness of the reflective electrode layer RL. That is, the sum of the thickness of the first sub-pad conductive layer SPML1 and the thickness of the second sub-pad conductive layer SPML2 may be greater than the thickness of the reflective electrode layer RL.

[0221] A portion of a top surface of the second sub-pad conductive layer SPML2 corresponding to the first sub-pad BPD may be exposed without being covered by the tenth interlayer insulating layer INS10. A top surface of the second sub-pad conductive layer SPML2 corresponding to the second sub-pad IPD may be exposed without being covered by the tenth interlayer insulating layer INS10. The first sub-pad conductive layer SPML1 may be connected to a pad via PVA9 penetrating the ninth interlayer insulating layer INS9 to be connected to the eighth conductive layer ML8.

[0222] like Figure 8 and Fig. 9 As shown in , since the pad conductive layer PML of the first sub-pad BPD and the pad conductive layer PML of the second sub-pad IPD are formed integrally, if the pad conductive layer PML of the second sub-pad IPD is damaged or destroyed during the inspection process, the pad conductive layer PML of the first sub-pad BPD may also be damaged or destroyed. Accordingly, it may be appropriate to separate or distinguish the pad conductive layer PML of the second sub-pad IPD and the pad conductive layer PML of the first sub-pad BPD used in the inspection process.

[0223] Fig.10 It is shown Figure 4 FIG. 1 is a layout diagram of yet another example of a first pad of a first pad portion. Fig.11 is shown along Fig.10 A cross-sectional view of the display panel taken along line CC'.

[0224] Reference Fig.10 and Fig.11, each of the plurality of first pads PD1 includes a first sub-pad BPD made of a first pad conductive layer PML1, and a second sub-pad IPD made of a second pad conductive layer PML2. Both the first sub-pad BPD and the second sub-pad IPD may be electrically connected to a pad or a bump of the circuit board 300 through a conductive adhesive. In addition, the second sub-pad IPD may be a pad connected to a jig or a probe during an inspection process, or may be a pad connected to a circuit board for inspection.

[0225] The area of ​​the first sub-pad BPD may be greater than the area of ​​the second sub-pad IPD. The length of the first sub-pad BPD in the first direction DR1 may be substantially the same as the length of the second sub-pad IPD in the first direction DR1. The length of the first sub-pad BPD in the second direction DR2 may be greater than the length of the second sub-pad IPD in the second direction DR2.

[0226] Each of the first pad conductive layer PML1 and the second pad conductive layer PML2 may include a first sub-pad conductive layer SPML1 and a second sub-pad conductive layer SPML2. The first sub-pad conductive layer SPML1 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or an alloy including any one of them. The second sub-pad conductive layer SPML2 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or an alloy including any one of them. For example, the first sub-pad conductive layer SPML1 may be made of aluminum (Al) and may have an approximate In addition, the second sub-pad conductive layer SPML2 may be made of titanium nitride (TiN) and may have a thickness of approximately The thickness of each of the first pad conductive layer PML1 and the second pad conductive layer PML2 may be greater than the thickness of the reflective electrode layer RL.

[0227] A portion of a top surface of a second sub-pad conductive layer SPML2 of the first pad conductive layer PML1 corresponding to the first sub-pad BPD may be exposed without being covered by the tenth interlayer insulating layer INS10. A top surface of a second sub-pad conductive layer SPML2 of a second pad conductive layer PML2 corresponding to the second sub-pad IPD may be exposed without being covered by the tenth interlayer insulating layer INS10. The first sub-pad conductive layer SPML1 may be connected to a pad via PVA9 penetrating the ninth interlayer insulating layer INS9 to be connected to the eighth conductive layer ML8.

[0228] The first pad conductive layer PML1 and the second pad conductive layer PML2 are connected to the same eighth conductive layer ML8 through the pad via PVA9. Accordingly, the first pad conductive layer PML1 and the second pad conductive layer PML2 may have substantially the same potential.

[0229] like Fig.10 and Fig.11 As shown in, since the first pad conductive layer PML1 of the first sub-pad BPD and the second pad conductive layer PML2 of the second sub-pad IPD are separated or distinguished from each other, even if the second pad conductive layer PML2 of the second sub-pad IPD is damaged or destroyed by a fixture or a probe during the inspection process, the first pad conductive layer PML1 of the first sub-pad BPD may not be damaged or destroyed.

[0230] Fig.12 It is shown Figure 4 FIG. 1 is a layout diagram of yet another example of a first pad of a first pad portion. Fig.13 is along Fig.12 A cross-sectional view of the display panel taken along line DD'.

[0231] Reference Fig.12 and Fig.13 , each of the plurality of first pads PD1 includes a first sub-pad BPD formed by a first pad conductive layer PML1, a second sub-pad IPD1 formed by a second pad conductive layer PML2, and a third sub-pad IPD2 formed by a third pad conductive layer PML3. The first sub-pad BPD, the second sub-pad IPD1, and the third sub-pad IPD2 may all be electrically connected to a pad or a bump of the circuit board 300 through a conductive adhesive. In addition, the second sub-pad IPD1 and the third sub-pad IPD2 may be pads connected to a fixture or a probe during an inspection process, or may be pads connected to a circuit board for inspection. The second sub-pad IPD1 may be a pad for inspecting whether the scan driver 610, the emission driver 620, and the data driver 700 are operating normally, and the third sub-pad IPD2 may be a pad for performing a visual inspection of a display image of the display area DAA of the display panel 100.

[0232] The area of ​​the first sub-pad BPD may be greater than the area of ​​the second sub-pad IPD1 and the area of ​​the third sub-pad IPD2. The length of the first sub-pad BPD in the first direction DR1 may be substantially the same as the length of the second sub-pad IPD1 and the length of the third sub-pad IPD2 in the first direction DR1. The length of the first sub-pad BPD in the second direction DR2 may be greater than the length of the second sub-pad IPD1 and the length of the third sub-pad IPD2 in the second direction DR2.

[0233] Each of the first pad conductive layer PML1, the second pad conductive layer PML2 and the third pad conductive layer PML3 may include a first sub-pad conductive layer SPML1 and a second sub-pad conductive layer SPML2. The first sub-pad conductive layer SPML1 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or an alloy including any one of them. The second sub-pad conductive layer SPML2 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or an alloy including any one of them. For example, the first sub-pad conductive layer SPML1 may be made of aluminum (Al) and may have an approximate In addition, the second sub-pad conductive layer SPML2 may be made of titanium nitride (TiN) and may have a thickness of approximately The thickness of each of the first pad conductive layer PML1, the second pad conductive layer PML2, and the third pad conductive layer PML3 may be greater than the thickness of the reflective electrode layer RL.

[0234] A portion of the top surface of the second sub-pad conductive layer SPML2 of the first pad conductive layer PML1 corresponding to the first sub-pad BPD may be exposed without being covered by the tenth interlayer insulating layer INS10. A top surface of the second sub-pad conductive layer SPML2 of the second pad conductive layer PML2 corresponding to the second sub-pad IPD1 may be exposed without being covered by the tenth interlayer insulating layer INS10. A top surface of the second sub-pad conductive layer SPML2 of the third pad conductive layer PML3 corresponding to the third sub-pad IPD2 may be exposed without being covered by the tenth interlayer insulating layer INS10. The first sub-pad conductive layer SPML1 may be connected to the pad via PVA9 penetrating the ninth interlayer insulating layer INS9 to be connected to the eighth conductive layer ML8.

[0235] The first pad conductive layer PML1, the second pad conductive layer PML2 and the third pad conductive layer PML3 are connected to the same eighth conductive layer ML8 through the pad via PVA9. Accordingly, the first pad conductive layer PML1, the second pad conductive layer PML2 and the third pad conductive layer PML3 may have substantially the same potential.

[0236] like Fig.12 and Fig.13As shown in the figure, the first pad conductive layer PML1 of the first sub-pad BPD, the second pad conductive layer PML2 of the second sub-pad IPD1 and the third pad conductive layer PML3 of the third sub-pad IPD2 are separated or distinguished from each other, so that even if the second pad conductive layer PML2 of the second sub-pad IPD1 and / or the third pad conductive layer PML3 of the third sub-pad IPD2 are damaged or destroyed by a fixture or a probe during the inspection process, the first pad conductive layer PML1 of the first sub-pad BPD may not be damaged or destroyed.

[0237] Fig.14 It is shown in detail Figure 4 Layout diagram of area X. Fig.15 is along Fig.14 A cross-sectional view of the display panel taken along line EE'. Fig.16 is along Fig.14 A cross-sectional view of the display panel taken along line FF'.

[0238] Figure 4 The area X in φ may be an area positioned on a third side of the display area DAA. Figures 14 to 16 The first distribution circuit 710, the power connection portion PCA, the dam portion DMA, the data driver 700, the first pad portion PDA1, the electrostatic protection area ESA, the permeation reduction area MPA, and the crack reduction area CPA positioned on the third side of the display area DAA are shown.

[0239] On the third side of the display area DAA, the first distribution circuit 710, the power connection portion PCA, the dam portion DMA, the data driver 700, the first pad portion PDA1, the electrostatic protection area ESA, the permeation reduction area MPA, and the crack reduction area CPA may be sequentially positioned in the second direction DR2. However, the present disclosure is not limited thereto, and the power connection portion PCA may overlap with the first distribution circuit 710 or the data driver 700 in the third direction DR3, and the dam portion DMA may overlap with the first distribution circuit 710 or the data driver 700 in the third direction DR3.

[0240] The first distribution circuit 710 may include a plurality of first distribution transistors DBTR1. Since each of the plurality of first distribution transistors DBTR1 may be formed to be combined with Figure 7The pixel transistors PTR described are substantially the same, so a detailed description of the plurality of first distribution transistors DBTR1 will be omitted. In addition, since the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, the sixth conductive layer ML6, the seventh conductive layer ML7 and the eighth conductive layer ML8 electrically connected to the plurality of first distribution transistors DBTR1 and the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, the seventh via VA7 and the eighth via VA8 are also connected to the first distribution transistors DBTR1. Figure 7 Those described are substantially the same, so description thereof will be omitted.

[0241] The power connection portion PCA includes a first power connection area PCAA1 of the semiconductor substrate SSUB, a first power connection electrode PCE1, and a second power connection electrode PCE2.

[0242] The first driving voltage VSS may be applied to the first power connection area PCAA1 of the semiconductor substrate SSUB.

[0243] The first power connection electrode PCE1 may be positioned on the ninth interlayer insulating layer INS9. The first power connection electrode PCE1 may be connected to the first power connection area PCAA1 of the semiconductor substrate SSUB through the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, the sixth conductive layer ML6, the seventh conductive layer ML7, and the eighth conductive layer ML8 and the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, the seventh via VA7, the eighth via VA8, and the ninth via VA9.

[0244] The first power connection electrode PCE1 may include a first sub-power connection electrode SPCE1, a second sub-power connection electrode SPCE2, a third sub-power connection electrode SPCE3, and a fourth sub-power connection electrode SPCE4. The first sub-power connection electrode SPCE1, the second sub-power connection electrode SPCE2, the third sub-power connection electrode SPCE3, and the fourth sub-power connection electrode SPCE4 of the first power connection electrode PCE1 may be substantially the same as the first reflective electrode RL1, the second reflective electrode RL2, the third reflective electrode RL3, and the fourth reflective electrode RL4 of the reflective electrode layer RL. That is, the first sub-power connection electrode SPCE1 may correspond to the first reflective electrode RL1, the second sub-power connection electrode SPCE2 may correspond to the second reflective electrode RL2, the third sub-power connection electrode SPCE3 may correspond to the third reflective electrode RL3, and the fourth sub-power connection electrode SPCE4 may correspond to the fourth reflective electrode RL4.

[0245] The second power connection electrode PCE2 may be positioned on the tenth interlayer insulating layer INS10. The second power connection electrode PCE2 may be connected to the first power connection electrode PCE1 through the tenth via VA10. The second power connection electrode PCE2 may include a material substantially the same as that of the first electrode AND of the light emitting element LE. The second power connection electrode PCE2 may be separated by the pixel defining film PDL. The second electrode CAT of the light emitting element LE may be connected to the second power connection electrode PCE2 that is exposed and not covered by the pixel defining film PDL.

[0246] The dam portion DMA includes a first dam DM1 and a second dam DM2. The first dam DM1 and the second dam DM2 may be substantially the same as the trench TRC. Each of the first dam DM1 and the second dam DM2 may penetrate the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3. The tenth interlayer insulating layer INS10 may be partially recessed at each of the first dam DM1 and the second dam DM2.

[0247] In each of the first dam DM1 and the second dam DM2, the first encapsulation inorganic layer TFE1 may be positioned on the bottom surface, the encapsulation organic layer TFE2 may be positioned on the first encapsulation inorganic layer TFE1, and the second encapsulation inorganic layer TFE3 may be positioned on the encapsulation organic layer TFE2. The encapsulation organic layer TFE2 may be positioned to fill a portion of each of the first dam DM1 and the second dam DM2. Alternatively, the encapsulation organic layer TFE2 may not be positioned on each of the first dam DM1 and the second dam DM2. That is, the first encapsulation inorganic layer TFE1 and the second encapsulation inorganic layer TFE3 may be positioned in each of the first dam DM1 and the second dam DM2.

[0248] The first and second dams DM1 and DM2 may reduce or prevent the encapsulation organic layer TFE2 from flowing toward the first pad portion PDA1 to avoid covering the first pad PD1. When the encapsulation organic layer TFE2 covers the first pad PD1, the first pad PD1 may not be electrically connected to the circuit board 300.

[0249] The data driver 700 may include a plurality of data transistors DTR. Since each of the plurality of data transistors DTR may be formed to be coupled to Figure 7The pixel transistors PTR described are substantially the same, so a detailed description of the plurality of data transistors DTR will be omitted. In addition, since the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, the sixth conductive layer ML6, the seventh conductive layer ML7 and the eighth conductive layer ML8 electrically connected to the plurality of data transistors DTR and the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, the seventh via VA7 and the eighth via VA8 are also connected to the plurality of data transistors DTR. Figure 7 Those described are substantially the same, so description thereof will be omitted.

[0250] The electrostatic protection area ESA includes a second power connection area PCAA2 of the semiconductor substrate SSUB.

[0251] The first driving voltage VSS may be applied to the second power connection area PCAA2 of the semiconductor substrate SSUB. The second power connection area PCAA2 may be connected to the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, the sixth conductive layer ML6, the seventh conductive layer ML7, and the eighth conductive layer ML8 and the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, the seventh via VA7, and the eighth via VA8. Accordingly, the electrostatic protection area ESA may discharge static electricity applied from the outside to the first driving voltage VSS.

[0252] The permeation reducing area MPA includes the permeation reducing electrode MPE and the third power connection area PCAA3 of the semiconductor substrate SSUB.

[0253] The first driving voltage VSS may be applied to the third power connection area PCAA3 of the semiconductor substrate SSUB. Alternatively, the third power connection area PCAA3 of the semiconductor substrate SSUB may be electrically floating.

[0254] The permeation reduction electrode MPE can be used with Fig. 9 The pad conductive layer PML shown in Fig.11 The first pad conductive layer PML1 and the second pad conductive layer PML2 shown in FIG. Fig.13 The first pad conduction layer PML1, the second pad conduction layer PML2, and the third pad conduction layer PML3 shown in FIG. 1 are substantially the same.

[0255] The permeation reducing electrode MPE may include a first sub-permeation reducing electrode SMPE1 and a second sub-permeation reducing electrode SMPE2. The first sub-permeation reducing electrode SMPE1 and the second sub-permeation reducing electrode SMPE2 of the permeation reducing electrode MPE may be connected to Fig. 9 , Fig.11 and Fig.13 The first sub-pad conductive layer SPML1 and the second sub-pad conductive layer SPML2 shown in FIG. 5 are substantially the same. That is, the first sub-permeation reducing electrode SMPE1 may correspond to the first sub-pad conductive layer SPML1, and the second sub-permeation reducing electrode SMPE2 may correspond to the second sub-pad conductive layer SPML2.

[0256] The crack reduction area CPA includes a fourth power connection area PCAA4 of the semiconductor substrate SSUB.

[0257] The first driving voltage VSS may be applied to the fourth power connection area PCAA4 of the semiconductor substrate SSUB. Alternatively, the fourth power connection area PCAA4 of the semiconductor substrate SSUB may be electrically floating. The fourth power connection area PCAA4 may be connected to the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, the sixth conductive layer ML6, the seventh conductive layer ML7, and the eighth conductive layer ML8 and the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, the seventh via VA7, and the eighth via VA8.

[0258] Fig.17 It is shown in detail Figure 4 Layout diagram of area Y. Fig.18 is along Fig.17 A cross-sectional view of the display panel taken along line G-G'.

[0259] Figure 4 The region Y in φ may be a region positioned on a first side of the display area DAA. Fig.17 and Fig.18 The scan driver 610 , the power connection portion PCA, the dam portion DMA, the electrostatic protection area ESA, the permeation reduction area MPA, and the crack reduction area CPA positioned on a first side of the display area DAA are illustrated.

[0260] On the first side of the display area DAA, the scan driver 610, the power connection portion PCA, the dam portion DMA, the electrostatic protection area ESA, the permeation reduction area MPA, and the crack reduction area CPA may be sequentially positioned in the first direction DR1. However, the present disclosure is not limited thereto, and the power connection portion PCA may overlap the scan driver 610 in the third direction DR3, and the dam portion DMA may overlap the scan driver 610 in the third direction DR3.

[0261] The scan driver 610 may include a plurality of scan transistors STR. Since each of the plurality of scan transistors STR may be formed to be coupled to Figure 7The pixel transistors PTR described are substantially the same, so a detailed description of the plurality of scanning transistors STR will be omitted. In addition, since the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, the sixth conductive layer ML6, the seventh conductive layer ML7 and the eighth conductive layer ML8 electrically connected to the plurality of scanning transistors STR and the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, the seventh via VA7 and the eighth via VA8 are also connected to the plurality of scanning transistors STR. Figure 7 Those described are substantially the same, so description thereof will be omitted.

[0262] Due to the combination of the power connection part PCA, the dam part DMA, the electrostatic protection area ESA, the penetration reduction area MPA and the crack reduction area CPA Figures 14 to 16 are essentially the same as those described, so Fig.17 and Fig.18 Descriptions of the power connection portion PCA, the dam portion DMA, the electrostatic protection area ESA, the permeation reduction area MPA, and the crack reduction area CPA will be omitted.

[0263] In addition, since the area positioned on the second side of the display area DAA is different from the area positioned on the second side of the display area DAA in addition to the scan driver 610 replacing the emission driver 620. Fig.17 and Fig.18 The regions shown in are substantially the same, so description thereof will be omitted.

[0264] Fig.19 It is shown in detail Figure 4 Layout diagram of area Z. Fig. 20 is shown along Fig.19 Cross-sectional views of the display panel taken along lines HH' and II'.

[0265] Figure 4 The region Z in φ may be a region positioned on a fourth side of the display area DAA. Fig.19 and Fig. 20 The second distribution circuit 720 , the power connection portion PCA, the dam portion DMA, the electrostatic protection area ESA, the permeation reduction area MPA, and the crack reduction area CPA positioned on the fourth side of the display area DAA are shown.

[0266] On the fourth side of the display area DAA, the second distribution circuit 720, the power connection portion PCA, the dam portion DMA, the electrostatic protection area ESA, the permeation reduction area MPA, and the crack reduction area CPA may be sequentially positioned in the second direction DR2. However, the present disclosure is not limited thereto, and the power connection portion PCA may overlap with the second distribution circuit 720 in the third direction DR3, and the dam portion DMA may overlap with the second distribution circuit 720 in the third direction DR3.

[0267] The second distribution circuit 720 may include a plurality of second distribution transistors DBTR2. Figure 7 The pixel transistors PTR described are substantially the same, so a detailed description of the plurality of second distribution transistors DBTR2 will be omitted. In addition, since the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, the sixth conductive layer ML6, the seventh conductive layer ML7 and the eighth conductive layer ML8 electrically connected to the plurality of second distribution transistors DBTR2 and the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, the seventh via VA7 and the eighth via VA8 are also connected to the plurality of second distribution transistors DBTR2. Figure 7 Those described are substantially the same, so description thereof will be omitted.

[0268] Due to the combination of the power connection part PCA, the dam part DMA, the electrostatic protection area ESA, the penetration reduction area MPA and the crack reduction area CPA Figures 14 to 16 are essentially the same as those described, so Fig.19 and Fig. 20 Descriptions of the power connection portion PCA, the dam portion DMA, the electrostatic protection area ESA, the permeation reduction area MPA, and the crack reduction area CPA will be omitted.

[0269] Fig.21 is a perspective view showing a head mounted display device according to one or more embodiments. Fig. 22 It is shown Fig.21 An exploded perspective view of a head mounted display device.

[0270] Reference Fig.21 and Fig. 22 According to one or more embodiments, the head-mounted display device 1000 includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted strap 1300, an intermediate frame 1400, a first optical component 1510, a second optical component 1520 and a control circuit board 1600.

[0271] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Figure 1 and Figure 2 The display devices 10 described are substantially the same, and thus descriptions of the first display device 10_1 and the second display device 10_2 will be omitted.

[0272] The first optical member 1510 may be positioned between the first display device 10_1 and the first eyepiece 1210. The second optical member 1520 may be positioned between the second display device 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0273] The middle frame 1400 may be positioned between the first display device 10_1 and the control circuit board 1600 and between the second display device 10_2 and the control circuit board 1600. The middle frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0274] The control circuit board 1600 may be positioned between the middle frame 1400 and the display device housing 1100. The control circuit board 1600 may be connected to the first display device 10_1 and the second display device 10_2 through a connector. The control circuit board 1600 may convert an image source input from the outside into digital video data DATA, and transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 through the connector.

[0275] The control circuit board 1600 may transmit digital video data DATA corresponding to a left-eye image designed or optimized for the left eye of the user to the first display device 10_1, and may transmit digital video data DATA corresponding to a right-eye image designed or optimized for the right eye of the user to the second display device 10_2. Alternatively, the control circuit board 1600 may transmit the same digital video data DATA to the first display device 10_1 and the second display device 10_2.

[0276] The display device housing 1100 is used to accommodate the first display device 10_1, the second display device 10_2, the middle frame 1400, the first optical member 1510, the second optical member 1520, and the control circuit board 1600. The housing cover 1200 is positioned to cover one open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for the user's left eye to be positioned thereat and a second eyepiece 1220 for the user's right eye to be positioned thereat. Fig.21 and Fig. 22It is shown that the first eyepiece 1210 and the second eyepiece 1220 are separately positioned, but the present disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be combined into one.

[0277] The first eyepiece 1210 may be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece 1220 may be aligned with the second display device 10_2 and the second optical member 1520. Therefore, the user may observe the image of the first display device 10_1 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210, and may observe the image of the second display device 10_2 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0278] The head-mounted strap 1300 is used to fix the display device housing 1100 to the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 remain positioned on the user's left eye and right eye, respectively. When the display device housing 1100 is implemented to be lightweight and compact, the head-mounted display device 1000 can provide a user-friendly display device. Fig.23 The eyeglass frame shown in FIG. 1 is used to replace the head-mounted strap 1300.

[0279] In addition, the head mounted display device 1000 may further include a battery for supplying power, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0280] Fig.23 is a perspective view showing a head mounted display device according to one or more embodiments.

[0281] Reference Fig.23 The head mounted display device 1000_1 according to one or more embodiments may be a glasses type display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. The head mounted display device 1000_1 according to one or more embodiments may include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical member 1060, an optical path changing member 1070, and a display device housing 1200_1.

[0282] The display device housing 1200_1 may include the display device 10_3, the optical member 1060, and the optical path changing member 1070. The image displayed on the display device 10_3 may be enlarged by the optical member 1060, and may be provided to the right eye of the user through the right-eye lens 1020 after its optical path is changed by the optical path changing member 1070. As a result, the user may observe, through the right eye, an augmented reality image in which a virtual image displayed on the display device 10_3 and a real image viewed through the right-eye lens 1020 are combined.

[0283] Fig.23 The display device housing 1200_1 is shown to be positioned at the right end of the support frame 1030, but the present disclosure is not limited thereto. For example, the display device housing 1200_1 may be positioned at the left end of the support frame 1030, and in this case, the image of the display device 10_3 may be provided to the left eye of the user. Alternatively, the display device housing 1200_1 may be positioned at both the left and right ends of the support frame 1030, and in this case, the user may observe the image displayed on the display device 10_3 through both the left and right eyes.

[0284] However, it should be understood that the various aspects of the embodiments of the present disclosure are not limited to the contents described herein. The above and other aspects of the present disclosure will become more obvious to ordinary technicians in the technical field of the present disclosure by referring to the claims and their functional equivalents included therein.

Claims

1. A display device, comprising: a semiconductor substrate, the semiconductor substrate comprising a transistor; a conductive layer, the conductive layer being above the semiconductor substrate; a reflective electrode layer, the reflective electrode layer being above the conductive layer; an optical auxiliary layer, the optical auxiliary layer being above the reflective electrode layer; a plurality of light emitting elements, the plurality of light emitting elements being above the optical auxiliary layer and each comprising a first electrode, a light emitting stack, and a second electrode; A pixel defining film, the pixel defining film being above the first electrode to separate a plurality of light emitting regions of the plurality of light emitting elements; a first sub-pad conductive layer, the first sub-pad conductive layer being above the conductive layer; as well as A second sub-pad conductive layer, wherein the second sub-pad conductive layer is above the first sub-pad conductive layer, and the sum of the thickness of the first sub-pad conductive layer and the thickness of the second sub-pad conductive layer is greater than the thickness of the reflective electrode layer.

2. The display device according to claim 1, wherein: The first sub-pad conductive layer and the second sub-pad conductive layer include a first sub-pad and a second sub-pad separated by the optical auxiliary layer.

3. The display device according to claim 2, wherein: An area of ​​the first sub pad is greater than an area of ​​the second sub pad.

4. The display device according to claim 2, wherein: The first sub-pad conductive layer and the second sub-pad conductive layer further include a third sub-pad separated by the optical auxiliary layer.

5. The display device according to claim 4, wherein: The area of ​​the first sub-pad is greater than the area of ​​the second sub-pad, and The area of ​​the first sub-pad is greater than the area of ​​the third sub-pad.

6. The display device according to claim 1, further comprising: A groove penetrates the pixel defining film and a portion of the optical auxiliary layer.

7. The display device according to claim 6, wherein: The light emitting stack comprises: a first stacked layer, the first stacked layer being configured to emit light of a first color in the groove; and A second stacked layer is provided in the groove for emitting light of a second color and is spaced apart from the first stacked layer.

8. The display device according to claim 7, wherein: The light emitting stack further comprises: A first charge generation layer is between the first stacked layer and the second stacked layer and is separated at the groove.

9. The display device according to claim 6, wherein: The pixel definition film comprises: a first pixel defining film, wherein the first pixel defining film covers at least a portion of the first electrode; a second pixel-defining film over the first pixel-defining film and exposing a portion of a top surface of the first pixel-defining film; and A third pixel defining film is above the second pixel defining film and exposes a portion of a top surface of the second pixel defining film.

10. The display device according to claim 9, wherein: The groove penetrates the first pixel defining film, the second pixel defining film, and the third pixel defining film.

11. The display device according to claim 1, wherein: The reflective electrode layer comprises: a first reflective electrode; a second reflective electrode, the second reflective electrode being above the first reflective electrode; and A step layer is provided between the first reflective electrode and the second reflective electrode.

12. The display device according to claim 1, further comprising: a first power connection electrode, the first power connection electrode being above the conductive layer; a pad via hole, the pad via hole penetrating the optical auxiliary layer covering the first power connection electrode to be connected to the first power connection electrode; as well as A second power connection electrode is over the optical auxiliary layer, connected to the pad via and connected to the second electrode.

13. The display device according to claim 12, wherein: The pixel defining film is over at least a portion of the second power connection electrode.

14. The display device according to claim 12, wherein: The reflective electrode layer includes a first reflective electrode, a second reflective electrode above the first reflective electrode, and a step layer between the first reflective electrode and the second reflective electrode, and The first power connection electrode includes a first sub-power connection electrode and a second sub-power connection electrode, the first sub-power connection electrode includes the same material as the first reflective electrode, and the second sub-power connection electrode includes the same material as the second reflective electrode.

15. The display device according to claim 6, further comprising: A dam penetrates the pixel defining film and a portion of the optical auxiliary layer.

16. The display device according to claim 15, wherein: The depth of the dam is equal to the depth of the groove.

17. The display device according to claim 15, further comprising: An encapsulation layer is above the plurality of light emitting elements and the pixel defining film and includes a first encapsulation inorganic layer and an encapsulation organic layer in the dam.

18. The display device according to claim 17, wherein: The encapsulating organic layer is over the first encapsulating inorganic layer in the dam.

19. The display device according to claim 1, wherein: The thickness of the first sub-pad conductive layer is greater than the thickness of the second sub-pad conductive layer, Wherein, the display device further includes: a permeation reducing electrode overlying the conductive layer, and Wherein, the permeation reduction electrode comprises: a first sub-permeability reducing electrode including a same material as that of the first sub-pad conductive layer; and A second sub-permeability reducing electrode, the second sub-permeability reducing electrode includes a same material as that of the second sub-pad conductive layer.

20. A display device, comprising: A display area, the display area comprising pixels; a power connection area, the power connection area being outside the display area; a dam area, the dam area being outside the power connection area; a first distribution circuit at a first side of the display area in a first direction; a data driver external to the first distribution circuit in the first direction; a pad region, the pad region being outside the data driver in the first direction; an electrostatic protection region, the electrostatic protection region being outside the pad region in the first direction; a permeation reduction region, the permeation reduction region being outside the electrostatic protection region in the first direction; as well as A crack reduced region is provided, the crack reduced region being external to the permeation reduced region in the first direction.

21. The display device according to claim 20, wherein: The power connection area surrounds the display area in a plan view, wherein the dam area surrounds the power connection area in a plan view, Wherein, the pad area is outside the dam area, Wherein, in a plan view, the electrostatic protection area surrounds the dam area, wherein the permeation reduction region surrounds the electrostatic protection region in a plan view, and Wherein, the crack reduction region surrounds the permeation reduction region in a plan view.

22. A head mounted display device, comprising: a display device housing configured to accommodate at least one display device; as well as an optical member configured to magnify a display image of the at least one display device or change an optical path, Wherein, the at least one display device comprises: a semiconductor substrate, the semiconductor substrate comprising a transistor; a conductive layer, the conductive layer being above the semiconductor substrate; a reflective electrode layer, the reflective electrode layer being above the conductive layer; an interlayer insulating layer, the interlayer insulating layer being above the reflective electrode layer; a plurality of light emitting elements, the plurality of light emitting elements being above the interlayer insulating layer and each including a first electrode, a light emitting stack, and a second electrode; A pixel defining film, the pixel defining film is above the first electrode to separate a plurality of light emitting regions where the plurality of light emitting elements are respectively positioned; a first sub-pad conductive layer over the conductive layer; and A second sub-pad conductive layer, wherein the second sub-pad conductive layer is above the first sub-pad conductive layer, and the sum of the thickness of the first sub-pad conductive layer and the thickness of the second sub-pad conductive layer is greater than the thickness of the reflective electrode layer.

Images