Display panel and display device

Abstract

The embodiment of the invention discloses a display panel and a display device. The display panel comprises a substrate; the active layer is positioned on one side of the substrate; the multiple conductive layers are stacked on the side, away from the substrate, of the active layer; the at least one pixel circuit comprises a driving transistor and a switch module, and a grid electrode of the driving transistor is connected with a control end of the switch module; the grid electrode of the driving transistor and the control end of the switch module are located on one of the multiple conductive layers. The active layer comprises a first active layer and a second active layer which are connected, a channel region of the driving transistor is located on the first active layer, and a channel region of the switch module is located on the second active layer; the second active layer comprises at least one bending part, and the bending part is bent towards one side close to the first active layer. According to the display panel provided by the embodiment of the invention, the problem of easy short circuit caused by insufficient wiring space of the pixel circuit of the display panel is solved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, people have higher and higher requirements on display panels. The pixel circuits of existing display panels have the problem of insufficient wiring space and easy short circuit, which affects the display effect of the display panel. Summary of the invention

[0003] Embodiments of the present invention provide a display panel and a display device to solve the problem that a pixel circuit of a display panel has insufficient wiring space and is prone to short circuit.

[0004] In order to achieve the above technical problems, the present invention adopts the following technical solutions:

[0005] An embodiment of the present invention provides a display panel, including:

[0006] substrate;

[0007] An active layer, the active layer is located on one side of the substrate;

[0008] A plurality of conductive layers stacked on a side of the active layer away from the substrate;

[0009] at least one pixel circuit, the pixel circuit comprising a driving transistor and a switch module, the gate of the driving transistor is connected to the control end of the switch module; the gate of the driving transistor and the control end of the switch module are located in one of the multiple conductive layers;

[0010] The active layer comprises a first active layer and a second active layer which are connected, the channel region of the driving transistor is located in the first active layer, and the channel region of the switch module is located in the second active layer;

[0011] The second active layer includes at least one bending portion, and the bending portion bends toward a side close to the first active layer.

[0012] Optionally, the multi-layer conductive layer includes a first conductive layer, and the first conductive layer is located on a side of the active layer away from the substrate; the gate of the driving transistor and the control end of the switch module are both located on the first conductive layer;

[0013] At least part of the first active layer extends along a first direction, at least part of the second active layer extends along a second direction, and the first direction and the second direction intersect; the first active layer and the second active layer are arranged in the same layer;

[0014] The bending portion includes a first straight line segment, a second straight line segment and a third straight line segment connected in sequence; the first straight line segment and the third straight line segment extend along the first direction, and the second straight line segment extends along the second direction;

[0015] The first end of the first straight line segment is connected to the first end of the second straight line segment, and the second end of the second straight line segment is connected to the first end of the third straight line segment;

[0016] The straight line where the second end of the first straight line segment and the second end of the third straight line segment are connected is staggered with the second straight line segment;

[0017] Preferably, the orthographic projection of the gate of the driving transistor on the substrate covers the orthographic projection of the channel region of the driving transistor on the substrate;

[0018] The orthographic projection of the control terminal of the switch module on the substrate covers the orthographic projection of the channel region of the switch module on the substrate;

[0019] Preferably, the gate of the driving transistor is multiplexed as the control terminal of the switch module;

[0020] Preferably, the first direction and the second direction are perpendicular to each other.

[0021] Optionally, the width of the second active layer is greater than or equal to the width of the first active layer.

[0022] Optionally, the second active layer has a first boundary away from the first active layer;

[0023] The control end of the switch module has a second boundary away from the first active layer;

[0024] A distance from an orthographic projection of the first boundary on the substrate to an orthographic projection of the second boundary on the substrate is greater than or equal to 2.5 μm and less than or equal to 5 μm.

[0025] Optionally, a distance between active layers of two adjacent pixel circuits is greater than or equal to 2 μm;

[0026] The minimum distance between the orthographic projection of the second boundary on the substrate and the orthographic projection of the active layer of the adjacent pixel circuit on the substrate is greater than or equal to 1 μm;

[0027] The minimum distance from the orthographic projection of the first boundary on the substrate to the orthographic projection of the active layer of the adjacent pixel circuit on the substrate is greater than or equal to 2 μm.

[0028] Optionally, the switch module includes a first transistor and a second transistor; the second active layer includes a first active structure and a second active structure; the channel region of the first transistor is located in the first active structure, and the channel region of the second transistor is located in the second active structure; the second active layer includes a first bending portion, and the first active structure is located in a second straight line segment of the first bending portion; the second active structure is located in the second straight line segment of the first bending portion;

[0029] The orthographic projection of the gate of the first transistor on the substrate covers the orthographic projection of the channel region of the first transistor on the substrate; the orthographic projection of the gate of the second transistor on the substrate covers the orthographic projection of the channel region of the second transistor on the substrate; the gate of the first transistor is connected to the gate of the second transistor and the gate of the driving transistor;

[0030] At least part of the first active structure extends along the second direction, and at least part of the second active structure extends along the second direction; both the first active structure and the second active structure are connected to the first end of the first active layer;

[0031] Preferably, the first active structure extending along the first direction and the second active structure extending along the first direction are reused.

[0032] Optionally, the width of the first active structure is greater than or equal to the width of the first active layer; and / or the width of the second active structure is greater than or equal to the width of the first active layer;

[0033] Preferably, the length of the first active structure is the same as the length of the second active structure; and / or, the width of the first active structure is the same as the width of the second active structure;

[0034] Preferably, with a straight line connecting the first end of the first active layer and the second end of the first active layer being a symmetry axis, the first active structure and the second active structure are symmetrical to each other.

[0035] Optionally, the switch module further includes a third transistor and a fourth transistor; the second active layer further includes a third active structure and a fourth active structure;

[0036] The channel region of the third transistor is located in the third active structure, and the channel region of the fourth transistor is located in the fourth active structure; the second active layer includes a second bending portion, and the third active structure is located in the second straight line segment of the second bending portion; the fourth active structure is located in the second straight line segment of the second bending portion;

[0037] At least part of the third active structure extends along the second direction, and at least part of the fourth active structure extends along the second direction; the third active structure and the fourth active structure are both connected to the second end of the first active layer;

[0038] The orthographic projection of the gate of the third transistor on the substrate covers the orthographic projection of the channel region of the third transistor on the substrate; the orthographic projection of the gate of the fourth transistor on the substrate covers the orthographic projection of the channel region of the fourth transistor on the substrate; the gate of the third transistor is connected to the gate of the fourth transistor and the gate of the driving transistor;

[0039] Preferably, the third active structure extending along the first direction and the fourth active structure extending along the first direction are reused.

[0040] Optionally, the width of the third active structure is greater than or equal to the width of the first active layer; and / or the width of the fourth active structure is greater than or equal to the width of the first active layer;

[0041] Preferably, the length of the third active structure is the same as the length of the fourth active structure; and / or, the width of the third active structure is the same as the width of the fourth active structure;

[0042] Preferably, with the straight line connecting the first end of the first active layer and the second end of the first active layer as the symmetry axis, the third active structure and the fourth active structure are symmetrical to each other;

[0043] Preferably, with a perpendicular line connecting the first end of the first active layer and the second end of the first active layer as a symmetry axis, the third active structure and the first active structure are symmetrical to each other;

[0044] Preferably, with a perpendicular line connecting the first end of the first active layer and the second end of the first active layer as a symmetry axis, the fourth active structure and the second active structure are symmetrical to each other.

[0045] Optionally, the display panel further includes a data line, the pixel circuit further includes a fifth transistor, the active layer further includes a third active layer, and the third active layer is arranged in the same layer as the first active layer and the second active layer; the third active layer further includes a fifth active structure, and the gate of the fifth transistor is located in the first conductive layer; and the channel region of the fifth transistor is located in the fifth active structure;

[0046] The fifth active structure extends along the second direction, and the straight line where the fifth active structure is located is not collinear with the straight line where the first active structure of the first transistor is located;

[0047] Preferably, the width of the first active structure is greater than or equal to the width of the fifth active structure; and / or the width of the second active structure is greater than or equal to the width of the fifth active structure;

[0048] Preferably, the channel region of the fifth transistor is located at the positive projection position of the gate of the fifth transistor on the fifth active structure, the multi-layer conductive layer further comprises a second conductive layer and a third conductive layer sequentially arranged on the first conductive layer away from the substrate, the display panel comprises a first via hole, the first electrode of the fifth transistor is connected to the data line via the first via hole, the second electrode of the fifth transistor is connected to the first electrode of the first transistor via the fifth active structure; the second electrode of the first transistor is connected to the first electrode of the driving transistor via the first active structure; the fifth transistor is used to transmit a data voltage to the gate of the driving transistor via the turned-on first transistor;

[0049] Preferably, the display panel further includes a first scan line, the gate of the fifth transistor is connected to the first scan line, the first scan line extends along a first direction, and an orthographic projection of the first scan line on the substrate covers an orthographic projection of the channel region of the fifth transistor on the substrate.

[0050] Optionally, the display panel further includes a first power line, the pixel circuit further includes a sixth transistor, the third active layer further includes a sixth active structure, the gate of the sixth transistor is located in the first conductive layer; and the channel region of the sixth transistor is located in the sixth active structure;

[0051] The sixth active structure extends along the second direction, and the straight line where the sixth active structure is located is not collinear with the straight line where the second active structure of the second transistor is located;

[0052] Preferably, the width of the first active structure is greater than or equal to the width of the sixth active structure; and / or the width of the second active structure is greater than or equal to the width of the sixth active structure;

[0053] Preferably, the channel region of the sixth transistor is located at the positive projection position of the gate of the sixth transistor on the sixth active structure, the display panel includes a second via hole, the first electrode of the sixth transistor is connected to the first power line through the second via hole, the second electrode of the sixth transistor is connected to the first electrode of the second transistor through the sixth active structure; the second electrode of the second transistor is connected to the first electrode of the driving transistor through the second active structure; the sixth transistor is used to transmit the driving voltage to the anode of the light-emitting module through the turned-on second transistor and the turned-on driving transistor;

[0054] Preferably, the display panel further includes a light emitting control line, the gate of the sixth transistor is connected to the light emitting control line, the light emitting control line extends along the first direction, and the orthographic projection of the light emitting control line on the substrate covers the orthographic projection of the channel region of the sixth transistor on the substrate.

[0055] Optionally, the pixel circuit further includes a seventh transistor, the third active layer further includes a seventh active structure, the gate of the seventh transistor is located in the first conductive layer; and the channel region of the seventh transistor is located in the seventh active structure;

[0056] At least a portion of the seventh active structure extends along the second direction, and along the second direction, a straight line where the seventh active structure is located is not collinear with a straight line where the third active structure of the third transistor is located;

[0057] Preferably, the width of the third active structure is greater than or equal to the width of the seventh active structure; and / or the width of the fourth active structure is greater than or equal to the width of the seventh active structure;

[0058] Preferably, the channel region of the seventh transistor is located at the positive projection position of the gate of the seventh transistor on the seventh active structure, the third conductive layer includes a first connecting line, a third via hole and a fourth via hole, the first electrode of the seventh transistor is connected to the gate of the driving transistor through the third via hole, the first connecting line and the fourth via hole, the second electrode of the seventh transistor is connected to the first electrode of the third transistor through the seventh active structure; the second electrode of the third transistor is connected to the second electrode of the driving transistor through the third active structure; the seventh transistor is used to transmit a data voltage to the gate of the driving transistor through the turned-on fifth transistor, the first transistor and the driving transistor;

[0059] Preferably, the gate of the seventh transistor is connected to the first scan line, and the orthographic projection of the first scan line on the substrate covers the orthographic projection of the channel region of the seventh transistor on the substrate;

[0060] Preferably, the gate of the seventh transistor includes a first conductive portion and a second conductive portion, the first conductive portion extends along the first direction, and the second conductive portion extends along the second direction; the first conductive portion and the second conductive portion are both connected to the first scan line;

[0061] Preferably, the seventh active structure includes a first bending portion and a second bending portion, the first bending portion extends along the second direction, and the second bending portion extends along the first direction; the orthographic projection of the first conductive portion on the substrate covers the orthographic projection of the first bending portion on the substrate; the orthographic projection of the second conductive portion on the substrate covers the orthographic projection of the second bending portion on the substrate.

[0062] Optionally, the pixel circuit further includes an eighth transistor, the third active layer further includes an eighth active structure, the gate of the eighth transistor is located in the first conductive layer; and the channel region of the eighth transistor is located in the eighth active structure;

[0063] At least a portion of the eighth active structure extends along the second direction, and along the second direction, a straight line where the eighth active structure is located is not collinear with a straight line where the fourth active structure of the fourth transistor is located;

[0064] Preferably, the width of the third active structure is greater than or equal to the width of the eighth active structure; and / or the width of the fourth active structure is greater than or equal to the width of the eighth active structure;

[0065] Preferably, the channel region of the eighth transistor is located at the positive projection position of the gate of the eighth transistor on the eighth active structure, the display panel includes a fifth via hole, the first electrode of the eighth transistor is connected to the anode of the light-emitting module through the fifth via hole, the second electrode of the eighth transistor is connected to the first electrode of the fourth transistor through the eighth active structure; the second electrode of the fourth transistor is connected to the second electrode of the driving transistor through the fourth active structure; the eighth transistor is used to transmit the driving voltage to the anode of the light-emitting module through the turned-on sixth transistor, the second transistor, the driving transistor and the fourth transistor;

[0066] Preferably, the gate of the eighth transistor is connected to the light emitting control line, and the orthographic projection of the light emitting control line on the substrate covers the orthographic projection of the channel region of the eighth transistor on the substrate.

[0067] Optionally, the pixel circuit further includes a capacitor, wherein a first electrode plate of the capacitor is located in the first conductive layer, a second electrode plate of the capacitor is located in the second conductive layer, the first electrode plate of the capacitor is connected to the gate of the driving transistor; the second electrode plate of the capacitor is connected to the first power line of the display panel; the orthographic projection of the first electrode plate of the capacitor on the substrate at least partially covers the orthographic projection of the channel region of the driving transistor on the substrate;

[0068] Preferably, the orthographic projection of the first plate of the capacitor on the substrate at least partially overlaps with the orthographic projection of the second plate of the capacitor on the substrate;

[0069] Preferably, the first electrode plate of the capacitor includes a hole area, and the overlapping position of the orthographic projection of the first electrode plate of the capacitor on the substrate and the orthographic projection of the second electrode plate of the capacitor on the substrate at least partially covers the orthographic projection of the hole area on the substrate.

[0070] Optionally, the display panel further includes a first initialization line, which is located in the second conductive layer; the first initialization line extends along the first direction;

[0071] The pixel circuit further includes a ninth transistor, and the third active layer further includes a ninth active structure; the gate of the ninth transistor is located in the first conductive layer, and the channel region of the ninth transistor is located in the ninth active structure; the width of the first active structure is greater than or equal to the width of the ninth active structure; and / or the width of the second active structure is greater than or equal to the width of the ninth active structure; and / or the width of the third active structure is greater than or equal to the width of the ninth active structure; and / or the width of the fourth active structure is greater than or equal to the width of the ninth active structure;

[0072] Preferably, the channel region of the ninth transistor is located at the positive projection position of the gate of the ninth transistor on the ninth active structure, and the display panel includes a sixth via hole and a seventh via hole; the first electrode of the ninth transistor is connected to the first initialization line through the seventh via hole, and the second electrode of the ninth transistor is connected to the gate of the driving transistor through the ninth active structure, the sixth via hole, the first connection line and the fourth via hole; the ninth transistor is used to transmit the first initialization voltage to the gate of the driving transistor;

[0073] Preferably, the display panel further comprises a second scan line, the second scan line extends along the first direction, the gate of the ninth transistor is connected to the second scan line, and the orthographic projection of the second scan line on the substrate covers the orthographic projection of the channel region of the ninth transistor on the substrate;

[0074] Preferably, the gate of the ninth transistor includes a third conductive portion and a fourth conductive portion, the third conductive portion and the fourth conductive portion both extend along the first direction; the first conductive portion and the second conductive portion are both connected to the second scan line;

[0075] Preferably, the ninth active structure includes a third bending portion and a fourth bending portion arranged at intervals, the third bending portion and the fourth bending portion both extend along the second direction, and the first bending portion is connected to the second bending portion; the orthographic projection of the third conductive portion on the substrate covers the orthographic projection of the third bending portion on the substrate; the orthographic projection of the fourth conductive portion on the substrate covers the orthographic projection of the fourth bending portion on the substrate.

[0076] Optionally, the display panel further includes a second initialization line, which is located in the second conductive layer; and the second initialization line extends along the first direction;

[0077] The pixel circuit further includes a tenth transistor, and the third active layer further includes a tenth active structure; the gate of the tenth transistor is located in the first conductive layer, and the channel region of the tenth transistor is located in the tenth active structure;

[0078] The width of the first active structure is greater than or equal to the width of the tenth active structure; and / or, the width of the second active structure is greater than or equal to the width of the tenth active structure; and / or, the width of the third active structure is greater than or equal to the width of the tenth active structure; and / or, the width of the fourth active structure is greater than or equal to the width of the tenth active structure;

[0079] Preferably, the channel region of the tenth transistor is located at the positive projection position of the gate of the tenth transistor on the tenth active structure, and the display panel includes an eighth via hole; the first electrode of the tenth transistor is connected to the second initialization line through the eighth via hole, and the second electrode of the tenth transistor is connected to the anode of the light-emitting module through the tenth active structure and the fifth via hole; the tenth transistor is used to transmit the second initialization voltage to the anode of the light-emitting module;

[0080] Preferably, the display panel further includes a third scan line extending along the first direction, the gate of the tenth transistor is connected to the third scan line, and the orthographic projection of the third scan line on the substrate covers the orthographic projection of the channel region of the tenth transistor on the substrate.

[0081] Optionally, the display panel further includes a third initialization line, which is located in the third conductive layer; the third initialization line extends along the first direction;

[0082] The pixel circuit further includes an eleventh transistor, and the third active layer further includes an eleventh active structure; the gate of the eleventh transistor is located in the first conductive layer, and the channel region of the eleventh transistor is located in the eleventh active structure;

[0083] The width of the first active structure is greater than or equal to the width of the eleventh active structure; and / or, the width of the second active structure is greater than or equal to the width of the eleventh active structure; and / or, the width of the third active structure is greater than or equal to the width of the eleventh active structure; and / or, the width of the fourth active structure is greater than or equal to the width of the eleventh active structure;

[0084] Preferably, the channel region of the eleventh transistor is located at the positive projection position of the gate of the eleventh transistor on the eleventh active structure, the display panel includes a ninth via hole and a tenth via hole; the third conductive layer also includes a second connecting line; the first electrode of the eleventh transistor is connected to the third initialization line via the ninth via hole, and the second electrode of the eleventh transistor is connected to the first electrode of the driving transistor through the eleventh active structure, the tenth via hole and the second connecting line; the eleventh transistor is used to transmit the third initialization voltage to the first electrode of the driving transistor;

[0085] Preferably, the gate of the eleventh transistor is connected to the third scan line, and the orthographic projection of the third scan line on the substrate covers the orthographic projection of the channel region of the eleventh transistor on the substrate.

[0086] Optionally, the material of the active layer includes low temperature polysilicon.

[0087] According to another aspect of the present invention, this embodiment provides a display device, including the display panel proposed in any item of the first aspect.

[0088] The technical solution provided by the embodiment of the present invention is to arrange the channel region of the driving transistor to be located in the first active layer, the channel region of the switch module to be located in the second active layer, and the first active layer and the second active layer to be connected to each other, so that the second active layer extends the length of the channel region of the first active layer, thereby making the device size of the driving transistor larger, thereby increasing the step length of the driving voltage corresponding to the grayscale, and thereby obtaining a better grayscale expansion effect. On the other hand, by arranging the second active layer to include at least one bending portion, the bending portion is bent toward the side close to the first active layer, so that the active layer can have sufficient space to arrange the second active layer, without increasing the layout size occupied by the pixel circuit, thereby improving the resolution of the display panel, facilitating the flexible setting of the width of the second active layer of the switch module, thereby optimizing the wiring space between adjacent pixel circuits, and reducing the short circuit risk of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0089] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the contents of the embodiments of the present invention and these drawings without paying any creative work.

[0090] Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0091] Figure 2 The embodiment of the present invention provides a display panel along the Figure 1 Schematic diagram of the cross section along the AA' direction;

[0092] Figure 3 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0093] Figure 4 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0094] Figure 5 is a circuit schematic diagram of a pixel circuit of a display panel provided by an embodiment of the present invention;

[0095] Figure 6 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0096] Figure 7 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0097] Figure 8 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0098] Fig. 9 is a circuit schematic diagram of another pixel circuit of a display panel provided by an embodiment of the present invention;

[0099] Fig.10 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0100] Fig.11 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0101] Fig.12 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0102] Fig.13 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0103] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0104] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0105] Based on the above technical problems, this embodiment proposes the following solutions:

[0106] Figure 1 It is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention. Figure 2 The embodiment of the present invention provides a display panel along the Figure 1 Schematic diagram of the cross section along the AA' direction. Figure 1 and Figure 2 A display panel 100 includes: a substrate 1; an active layer 2, the active layer 2 is located on one side of the substrate 1; a plurality of conductive layers stacked on the side of the active layer 2 away from the substrate 1; at least one pixel circuit 10, the pixel circuit 10 includes a driving transistor T1 and a switch module 20, the gate of the driving transistor T1 is connected to the control end of the switch module 20; the gate of the driving transistor T1 and the control end of the switch module 20 are located in one of the plurality of conductive layers; the substrate 1 active layer 2 includes a first active layer 21 and a second active layer 22 connected, the channel region of the driving transistor T1 is located in the first active layer 21, and the channel region of the switch module 20 is located in the second active layer 22; the second active layer 22 includes at least one bending portion 60, and the bending portion 60 is bent toward a side close to the first active layer 21.

[0107] Specifically, the substrate 1 is used to provide protection and support for the display panel, wherein the substrate 1 can be a flexible substrate formed of materials such as polyimide (PI), polyethylene naphthalate (PEN) or polyethylene terephthalate (PET), or a hard substrate formed of materials such as glass. A plurality of conductive layers are arranged on one side of the substrate 1, and the plurality of conductive layers are isolated from each other by insulating layers. A plurality of pixel circuits 10 are formed in the display panel, and the pixel circuit 10 is used to drive the light-emitting element to emit light. Among them, the pixel circuit 10 includes a driving transistor T1 and a switch module 20, and the gate of the switch module 20 is connected to the gate of the driving transistor T1. Since the gate of the driving transistor and the gate of the switch module 20 share a node, the first active layer 21 of the driving transistor T1 and the second active layer 22 of the switch module 20 can be arranged in the same layer and connected to each other.

[0108] The first active layer 21 of the driving transistor T1 and the second active layer 22 of the switch module 20 are in the same layer and are connected to each other, so that the channel region of the driving transistor T1 effectively increases the equivalent length of the driving transistor T1 through the first active layer 21 and the second active layer 22, thereby increasing the width-to-length ratio of the channel region of the driving transistor T1. By increasing the length of the channel region of the driving transistor T1, the voltage step corresponding to two adjacent gray scales of the driving transistor T1 is increased, so that the voltage difference between the gray scales is larger. Since the driving voltage corresponding to the gray scale is output by the driving module, by increasing the length of the channel region of the driving transistor T1, the voltage fluctuation of the driving module will not affect the gray scale expansion of the display panel, thereby improving the display effect of the display panel.

[0109] The second active layer 22 is provided to include at least one bending portion 60, and the bending portion 60 is bent toward a side close to the first active layer 21, so that the active layer 2 can have sufficient space to set the second active layer 22, thereby forming a switch module, which effectively improves the grayscale expansion of the display panel and improves the display effect of the display panel without increasing the layout size occupied by the pixel circuit, which is convenient for optimizing the wiring space of the pixel circuit and supporting the pixel display of the high-resolution display panel. On the other hand, by providing the bending portion 60, the width of the second active layer 22 of the switch module can be flexibly set, which is convenient for optimizing the wiring space between adjacent pixel circuits and reducing the risk of short circuit of the display panel.

[0110] The technical solution provided in this embodiment is to arrange the channel region of the driving transistor T1 to be located in the first active layer 21, the channel region of the switch module 20 to be located in the second active layer 22, and the first active layer 21 and the second active layer 22 to be connected to each other, so that the second active layer 22 extends the length of the channel region of the first active layer 21, and the first active layer 21 further makes the device size of the driving transistor T1 larger, thereby increasing the step length of the driving voltage corresponding to the grayscale, and thus obtaining a better grayscale expansion effect. On the other hand, by arranging the second active layer 22 to include at least one bending portion 60, the bending portion 60 is bent toward the side close to the first active layer 21, so that the active layer 2 can have sufficient space to arrange the second active layer 22, without increasing the layout size occupied by the pixel circuit, thereby improving the resolution of the display panel, facilitating the flexible setting of the width of the second active layer 22 of the switch module 20, thereby optimizing the wiring space between adjacent pixel circuits, and reducing the short circuit risk of the display panel.

[0111] Optional, Figure 3 FIG. 1 is a schematic diagram of another display panel structure provided by an embodiment of the present invention. Figure 1 and Figure 3 The multi-layer conductive layer includes a first conductive layer M1, which is located on a side of the active layer 2 away from the substrate 1; the gate of the driving transistor T1 and the control end of the switch module 20 are both located in the first conductive layer M1; at least part of the first active layer 21 extends along the first direction X, and at least part of the second active layer 22 extends along the second direction Y, and the first direction X and the second direction Y intersect; the first active layer 21 and the second active layer 22 are arranged in the same layer. The bending portion 60 includes a first straight line segment K1, a second straight line segment K2 and a third straight line segment K3 connected in sequence; the first straight line segment K1 and the third straight line segment K3 extend along the first direction X, and the second straight line segment K2 extends along the second direction Y; the first end of the first straight line segment K1 is connected to the first end of the second straight line segment K2, and the second end of the second straight line segment K2 is connected to the first end of the third straight line segment K3; the straight line where the second end of the first straight line segment K1 and the second end of the third straight line segment K3 are connected is staggered from the second straight line segment K2.

[0112] Specifically, such a configuration can better save the space of the active layer 2 of the switch module located at the bent portion 60, facilitate optimization of the wiring space of the pixel circuit, and support the pixel display of the high-resolution display panel. The straight line where the second end of the first straight line segment K1 and the second end of the third straight line segment K3 are connected is set to be staggered with the second straight line segment K2, so that the width of the second active layer 22 of the switch module can be flexibly set, which is convenient for optimizing the wiring space between adjacent pixel circuits and reducing the short circuit risk of the display panel.

[0113] Optionally, based on the above embodiment, Figure 1 and Figure 3, the orthographic projection of the gate of the driving transistor T1 on the substrate 1 covers the orthographic projection of the channel region of the driving transistor T1 on the substrate 1; the orthographic projection of the control terminal of the switch module 20 on the substrate 1 covers the orthographic projection of the channel region of the switch module 20 on the substrate 1. Optionally, the gate of the driving transistor T1 is reused as the control terminal of the switch module 20. Optionally, the first direction X and the second direction Y are perpendicular to each other.

[0114] Specifically, this configuration is convenient for optimizing the circuit layout, saving space, and improving the space utilization of the layout. Since the gate of the driving transistor T1 is connected to the gate of the switch module 20, the gate of the driving transistor T1 is reused as the gate of the switch module 20, which is conducive to saving space.

[0115] Optionally, based on the above embodiment, Figure 1 and Figure 3 , the width of the second active layer 22 is greater than or equal to the width of the first active layer 21 .

[0116] Specifically, since the second active layer 22 includes a bent portion, the width of the second active layer 22 can be flexibly set as needed. The width of the second active layer 22 is set to be greater than or equal to the width of the first active layer 21. Since the second active layer 22 is connected to the first active layer 21, the equivalent size of the first active layer 21 is increased, which is equivalent to increasing the size of the channel region of the driving transistor, thereby effectively improving the grayscale expansion effect.

[0117] Optional, Figure 4 FIG. 1 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Figures 1 to 4 The second active layer 22 has a first boundary B1 away from the first active layer 21; the control end of the switch module has a second boundary B2 away from the first active layer 21; the distance D1 from the orthographic projection of the first boundary B1 on the substrate 1 to the orthographic projection of the second boundary B2 on the substrate 1 is greater than or equal to 2.5 μm and less than or equal to 5 μm.

[0118] Specifically, such an arrangement can ensure a safe distance between the signal lines of the pixel circuit and better avoid the risk of short circuit.

[0119] Optionally, based on the above embodiment, Figures 1 to 4 , the distance D2 between the active layers of two adjacent pixel circuits is greater than or equal to 2μm; the minimum distance D3 from the orthographic projection of the second boundary B2 on the substrate 1 to the orthographic projection of the active layer of the adjacent pixel circuit on the substrate 1 is greater than or equal to 1μm; the minimum distance D4 from the orthographic projection of the first boundary B1 on the substrate 1 to the orthographic projection of the active layer of the adjacent pixel circuit on the substrate 1 is greater than or equal to 2μm.

[0120] Specifically, such an arrangement can ensure a safe distance between signal lines between adjacent pixel circuits, and further avoid the risk of short circuits between pixel circuits of the display panel.

[0121] Optionally, based on the above embodiments, Figure 5 It is a circuit principle diagram of a pixel circuit of a display panel provided by an embodiment of the present invention. Figure 6 FIG. 1 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Figures 4 to 6 The switch module 20 includes a first transistor T9 and a second transistor T10; the second active layer 22 includes a first active structure 221 and a second active structure 222; the channel region of the first transistor T9 is located in the first active structure 221, and the channel region of the second transistor T10 is located in the second active structure 222; the second active layer 22 includes a first bending portion 61, and the first active structure 221 is located in the second straight line segment K2 of the first bending portion 61; the second active structure 222 is located in the second straight line segment K2 of the first bending portion 61.

[0122] Specifically, since the second active layer 22 includes the first bend 61, the first active structure 221 of the first transistor T9 is located at the second straight line segment K2 of the first bend 61. The second active structure 222 of the second transistor T10 is located at the second straight line segment K2 of the first bend 61. In this way, the widths of the first active structure 221 of the first transistor T9 and the second active structure 222 of the second transistor T10 can be flexibly set as needed. Since the second active layer 22 is connected to the first active layer 21, the equivalent size of the first active layer 21 is increased, which is equivalent to increasing the size of the channel region of the driving transistor, thereby effectively improving the grayscale expansion effect, thereby improving the display effect of the display panel, and increasing the pixel resolution of the display panel.

[0123] Optionally, the orthographic projection of the gate of the first transistor T9 on the substrate 1 covers the orthographic projection of the channel region of the first transistor T9 on the substrate 1; the orthographic projection of the gate of the second transistor T10 on the substrate 1 covers the orthographic projection of the channel region of the second transistor T10 on the substrate 1; the gate of the first transistor T9 is connected to the gate of the second transistor T10 and the gate of the driving transistor T1; at least part of the first active structure 221 extends along the second direction Y, and at least part of the second active structure 222 extends along the second direction Y; the first active structure 221 and the second active structure 222 are both connected to the first end of the first active layer 21. Optionally, the first active structure 221 extending along the first direction X and the second active structure 222 extending along the first direction X are reused.

[0124] Specifically, since the gate of the first transistor T9, the gate of the second transistor T10 and the gate of the driving transistor T1 are connected as a whole, the first active structure 221 of the first transistor T9 and the second active structure 222 of the second transistor T10 are connected to the first end of the first active layer 21 of the driving transistor T1, so that the first active structure 221 and the second active structure 222 extend the length of the channel region of the driving transistor T1, thereby equivalently obtaining a longer device size of the driving transistor T1, so that the display panel obtains a better grayscale expansion effect.

[0125] Optionally, based on the above embodiments, Figures 4 to 6 , the width of the first active structure 221 is greater than or equal to the width of the first active layer 21 ; and / or, the width of the second active structure 222 is greater than or equal to the width of the first active layer 21 .

[0126] Optionally, the length of the first active structure 221 is the same as the length of the second active structure 222; and / or, the width of the first active structure 221 is the same as the width of the second active structure 222. Optionally, with the straight line l1 where the first end of the first active layer 21 and the second end of the first active layer 21 are connected as the symmetry axis, the first active structure 221 and the second active structure 222 are symmetrical to each other.

[0127] Specifically, the configuration is such that the first active structure 221 of the first transistor T9 and the second active structure 222 of the second transistor T10 are identical, so that the device sizes of the first transistor T9 and the second transistor T10 are consistent, which can ensure that during the data writing stage and the light emitting stage, the channel lengths of the first transistor T9 and the second transistor T10 are consistent, and the two compensate for each other to obtain a better display effect.

[0128] Optionally, based on the above embodiments, Figure 7 FIG. 1 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Figure 7 The switch module 20 also includes a third transistor T11 and a fourth transistor T12; the second active layer 22 also includes a third active structure 223 and a fourth active structure 224; the channel region of the third transistor T11 is located in the third active structure 223, and the channel region of the fourth transistor T12 is located in the fourth active structure 224; the second active layer 22 includes a second bending portion 62, and the third active structure 223 is located in the second straight line segment K2 of the second bending portion 62; the fourth active structure 224 is located in the second straight line segment K2 of the second bending portion 62.

[0129] Specifically, since the second active layer 22 includes the second bend 62, the third active structure 223 of the third transistor T11 is located at the second straight line segment K2 of the second bend 62. The fourth active structure 224 of the fourth transistor T12 is located at the second straight line segment K2 of the second bend 62. In this way, the widths of the third active structure 223 of the third transistor T11 and the fourth active structure 224 of the fourth transistor T12 can be flexibly set as needed. Since the second active layer 22 is connected to the first active layer 21, the equivalent size of the first active layer 21 is increased, and the size of the channel region of the driving transistor is further equivalently increased, so that the grayscale expansion effect can be effectively improved, and then the display effect of the display panel is further improved, and the pixel resolution of the display panel is increased.

[0130] At least part of the third active structure 223 extends along the second direction Y, and at least part of the fourth active structure 224 extends along the second direction Y; the third active structure 223 and the fourth active structure 224 are both connected to the second end of the first active layer 21; the orthographic projection of the gate of the third transistor T11 on the substrate 1 covers the orthographic projection of the channel region of the third transistor T11 on the substrate 1; the orthographic projection of the gate of the fourth transistor T12 on the substrate 1 covers the orthographic projection of the channel region of the fourth transistor T12 on the substrate 1; the gate of the third transistor T11 is connected to the gate of the fourth transistor T12 and the gate of the driving transistor T1; preferably, the third active structure 223 extending along the first direction X and the fourth active structure 224 extending along the first direction X are reused.

[0131] Specifically, the third active structure 223 and the fourth active structure 224 are both connected to the second end of the first active layer 21, so that the third active structure 223 and the fourth active structure 224 are equivalent to extending the length of the first active layer 21 of the driving transistor T1 at the second end of the driving transistor T1. In this way, the length of the channel region of the first active layer 21 is further extended, and the width-to-length ratio of the channel region of the driving transistor T1 is further increased when the width of the first active layer 21 remains unchanged, so that the device size of the driving transistor T1 can be made larger, thereby increasing the step length of the driving voltage corresponding to the gray scale, and thus obtaining a better gray scale expansion effect.

[0132] Optional, Figure 8 It is a structural schematic diagram of another display panel provided by an embodiment of the present invention. Fig. 9 FIG. 1 is a circuit diagram of another pixel circuit of a display panel provided by an embodiment of the present invention. Figure 8 and Fig. 9 , a width of the third active structure 223 is greater than or equal to a width of the first active layer 21 ; and / or a width of the fourth active structure 224 is greater than or equal to a width of the first active layer 21 .

[0133] Optionally, based on the above embodiments, Figure 8 and Fig. 9 , the length of the third active structure 223 is the same as the length of the fourth active structure 224; and / or, the width of the third active structure 223 is the same as the width of the fourth active structure 224; preferably, with the straight line l1 where the first end of the first active layer 21 and the second end of the first active layer 21 are connected as the axis of symmetry, the third active structure 223 and the fourth active structure 224 are symmetrical to each other.

[0134] Specifically, the third active structure 223 of the third transistor T11 and the fourth active structure 224 of the fourth transistor T12 are configured the same, so that the device sizes of the third transistor T11 and the fourth transistor T12 are consistent, which can ensure that during the data writing stage and the light emitting stage, the channel lengths of the third transistor T11 and the fourth transistor T12 are consistent, and the two compensate for each other to obtain a better display effect.

[0135] Optionally, based on the above embodiments, Figure 8 and Fig. 9 , with the perpendicular line l2 connecting the first end of the first active layer 21 and the second end of the first active layer 21 as the symmetry axis, the third active structure 223 and the first active structure 221 are symmetrical to each other; with the perpendicular line l2 connecting the first end of the first active layer 21 and the second end of the first active layer 21 as the symmetry axis, the fourth active structure 224 and the second active structure 222 are symmetrical to each other.

[0136] Specifically, such a setting, on the one hand, is conducive to optimizing the circuit layout, so as to facilitate wiring, thereby improving the layout space utilization rate. On the other hand, such a setting, the first active structure 221 of the first transistor T9, the second active structure 222 of the second transistor T10, the third active structure 223 of the third transistor T11 and the fourth active structure 224 of the fourth transistor T12 are all the same, so that the device sizes of the first transistor T9, the second transistor T10, the third transistor T11 and the fourth transistor T12 are consistent, which can ensure that in the data writing stage and the light emitting stage, the channel lengths of the first transistor T9, the second transistor T10, the third transistor T11 and the fourth transistor T12 are consistent, the first transistor T9 and the second transistor T10 compensate each other, and the third transistor T11 and the fourth transistor T12 compensate each other, further improving the display effect of the display panel.

[0137] Optional, Fig.10 It is a structural schematic diagram of another display panel provided by an embodiment of the present invention. Fig.11 FIG. 1 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Figures 4 to 11, the display panel 100 further includes a data line Data, the pixel circuit 10 further includes a fifth transistor T2, the active layer 2 further includes a third active layer, and the third active layer is arranged in the same layer as the first active layer 21 and the second active layer 22; the third active layer further includes a fifth active structure 231, and the gate of the fifth transistor T2 is located in the first conductive layer M1; the channel region of the fifth transistor T2 is located in the fifth active structure 231. The fifth active structure 231 extends along the second direction Y, and the straight line where the fifth active structure 231 is located is not collinear with the straight line where the first active structure 221 of the first transistor T9 is located.

[0138] Specifically, such a configuration can effectively save the space of the first active structure 221 of the first transistor T9 located in the first bending portion 61, thereby optimizing the wiring space of the pixel circuit and reducing the short circuit risk of the display panel.

[0139] Optionally, the width of the first active structure 221 is greater than or equal to the width of the fifth active structure 231 ; and / or the width of the second active structure 222 is greater than or equal to the width of the fifth active structure 231 .

[0140] Specifically, in the data writing phase, the fifth transistor T2 is turned on, the first transistor T9 is turned on, the driving transistor T1 is turned on, and the data voltage transmitted by the data line Data is transmitted to the gate of the driving transistor T1.

[0141] The widths of the first active structure 221 and the second active structure 222 are set to be wider. Since the first active structure 221 and the second active structure 222 are both connected to the first active layer 21, the equivalent size of the first active layer 21 is increased, which is equivalent to increasing the size of the channel region of the driving transistor, thereby effectively improving the grayscale expansion effect, and further improving the display effect of the display panel.

[0142] Optional, Fig.12 FIG. 1 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Figures 4 to 12 , the channel region of the fifth transistor T2 is located at the positive projection position of the gate of the fifth transistor T2 on the fifth active structure 231, the multi-layer conductive layer also includes a second conductive layer M2 and a third conductive layer M3 which are sequentially arranged on the first conductive layer M1 away from the substrate 1, the display panel 100 also includes a first via hole N1, the first electrode of the fifth transistor T2 is connected to the data line Data through the first via hole N1, the second electrode of the fifth transistor T2 is connected to the first electrode of the first transistor T9 through the fifth active structure 231; the second electrode of the first transistor T9 is connected to the first electrode of the driving transistor T1 through the first active structure 221; the fifth transistor T2 is used to transmit the data voltage to the gate of the driving transistor T1 through the turned-on first transistor T9.

[0143] Specifically, since the gate of the first transistor T9 is connected to the gate of the driving transistor T1, the first electrode of the first transistor T9 is connected to the second electrode of the fifth transistor T2, and the second electrode of the first transistor T9 is connected to the first electrode of the driving transistor T1 through the first active structure 221. In this way, in the data writing stage, the first active structure 221 of the first transistor T9 is equivalent to increasing the channel length of the driving transistor T1, thereby improving the expansion of the grayscale voltage in the data writing stage, thereby improving the display effect of the display panel.

[0144] Optionally, based on the above embodiments, Figures 4 to 12 The display panel 100 further includes a first scan line S2, a gate of the fifth transistor T2 is connected to the first scan line S2, the first scan line S2 extends along the first direction X, and an orthographic projection of the first scan line S2 on the substrate 1 covers an orthographic projection of a channel region of the fifth transistor T2 on the substrate 1.

[0145] Specifically, in the data writing stage, the first scanning signal transmitted by the first scanning line S2 controls the fifth transistor T2 to be turned on.

[0146] Optionally, based on the above embodiments, Figures 4 to 12 , the display panel 100 further includes a first power line ELVDD, the pixel circuit 10 further includes a sixth transistor T5, the third active layer further includes a sixth active structure 232, the gate of the sixth transistor T5 is located in the first conductive layer M1; the channel region of the sixth transistor T5 is located in the sixth active structure 232. The sixth active structure 232 extends along the second direction Y, and the straight line where the sixth active structure 232 is located is not collinear with the straight line where the second active structure 222 of the second transistor T10 is located.

[0147] Specifically, such a configuration can effectively save the space of the second active structure 222 of the second transistor T10 located in the first bending portion 61, thereby optimizing the wiring space of the pixel circuit and reducing the short circuit risk of the display panel.

[0148] Optionally, the width of the first active structure 221 is greater than or equal to the width of the sixth active structure 232 ; and / or the width of the second active structure 222 is greater than or equal to the width of the sixth active structure 232 .

[0149] Specifically, in the light emitting stage, the sixth transistor T5 is turned on, the second transistor T10 is turned on, and the driving transistor T1 is turned on under the driving of the data voltage to drive the light emitting module to emit light.

[0150] The width of the first active structure 221 and the second active structure 222 is set to be wider than the width of the sixth active structure 232, so that the first active structure 221 and the second active structure 222 both connected to the first active layer 21 are equivalent to increasing the size of the first active layer 21, and equivalently increasing the size of the channel region of the driving transistor, thereby effectively improving the grayscale expansion effect, and further improving the display effect of the display panel.

[0151] Optionally, based on the above embodiments, Figures 4 to 12 , the channel region of the sixth transistor T5 is located at the positive projection position of the gate of the sixth transistor T5 on the sixth active structure 232, the display panel 100 also includes a second via hole N2, the first electrode of the sixth transistor T5 is connected to the first power line through the second via hole N2, the second electrode of the sixth transistor T5 is connected to the first electrode of the second transistor T10 through the sixth active structure 232; the second electrode of the second transistor T10 is connected to the first electrode of the driving transistor T1 through the second active structure 222; the sixth transistor T5 is used to transmit the driving voltage to the anode of the light-emitting module through the turned-on second transistor T10 and the turned-on driving transistor T1.

[0152] Specifically, since the gate of the second transistor T10 is connected to the gate of the driving transistor T1, the first electrode of the second transistor T10 is connected to the second electrode of the sixth transistor T5, and the second electrode of the second transistor T10 is connected to the first electrode of the driving transistor T1 through the second active structure 222. In this way, in the light-emitting stage, the second active structure 222 of the second transistor T10 is equivalent to increasing the channel length of the driving transistor T1, thereby improving the development of the grayscale voltage in the data light-emitting stage, thereby improving the display effect of the display panel.

[0153] Optionally, based on the above embodiments, Figures 4 to 12 The display panel 100 further includes a light emitting control line EM, a gate of the sixth transistor T5 is connected to the light emitting control line EM, the light emitting control line EM extends along the first direction X, and an orthographic projection of the light emitting control line EM on the substrate 1 covers an orthographic projection of a channel region of the sixth transistor T5 on the substrate 1 .

[0154] Specifically, in the light emitting stage, the light emitting control signal transmitted by the light emitting control line EM controls the sixth transistor T5 to be turned on.

[0155] Optionally, based on the above embodiments, Fig. 9 , Fig.10 and Fig.12The pixel circuit 10 further includes a seventh transistor T3, the third active layer further includes a seventh active structure 233, the gate of the seventh transistor T3 is located in the first conductive layer M1, and the channel region of the seventh transistor T3 is located in the seventh active structure 233. At least part of the seventh active structure 233 extends along the second direction Y, and along the second direction Y, the straight line where the seventh active structure 233 is located is not collinear with the straight line where the third active structure 223 of the third transistor T11 is located.

[0156] Specifically, such a configuration can effectively save the space of the third active structure 223 of the third transistor T11 located at the second bending portion 62, thereby optimizing the wiring space of the pixel circuit and reducing the short circuit risk of the display panel.

[0157] Optionally, based on the above embodiments, Fig. 9 , Fig.10 and Fig.12 , a width of the third active structure 223 is greater than or equal to a width of the seventh active structure 233 ; and / or a width of the fourth active structure 224 is greater than or equal to a width of the seventh active structure 233 .

[0158] Specifically, the seventh transistor T3 is used to compensate for the threshold voltage of the driving transistor T1. The widths of the third active structure 223 and the fourth active structure 224 are set to be wider than the width of the seventh active structure 233, so that the third active structure 223 and the fourth active structure 224 connected to the first active layer 21 are equivalent to increasing the size of the first active layer 21, and the size of the channel region of the driving transistor is equivalent to increasing, so that the grayscale expansion effect can be effectively improved, and then the display effect of the display panel is further improved.

[0159] Optionally, based on the above embodiments, Fig. 9 , Fig.10 and Fig.12 , the channel region of the seventh transistor T3 is located at the positive projection position of the gate of the seventh transistor T3 on the seventh active structure 233, the third conductive layer M3 includes a first connecting line 40, and the display panel 100 also includes a third via N3 and a fourth via N4. The first electrode of the seventh transistor T3 is connected to the gate of the driving transistor T1 through the third via N3, the first connecting line 40 and the fourth via N4, and the second electrode of the seventh transistor T3 is connected to the first electrode of the third transistor T11 through the seventh active structure 233; the second electrode of the third transistor T11 is connected to the second electrode of the driving transistor T1 through the third active structure 223; the seventh transistor T3 is used to transmit a data voltage to the gate of the driving transistor T1 through the turned-on fifth transistor T2, the first transistor T9 and the driving transistor T1.

[0160] Specifically, since the gate of the third transistor T11 is connected to the gate of the driving transistor T1, the first electrode of the third transistor T11 is connected to the second electrode of the seventh transistor T3, and the second electrode of the third transistor T11 is connected to the second electrode of the driving transistor T1 through the third active structure 223. In this way, in the data writing stage, the third active structure 223 of the third transistor T11 is equivalent to increasing the channel length of the driving transistor T1, thereby improving the development of the grayscale voltage in the data writing stage, thereby improving the display effect of the display panel.

[0161] Optionally, based on the above embodiments, Figures 4 to 12 The gate of the seventh transistor T3 is connected to the first scan line S2 , and the orthographic projection of the first scan line S2 on the substrate 1 covers the orthographic projection of the channel region of the seventh transistor T3 on the substrate 1 .

[0162] Optionally, based on the above embodiments, Figures 4 to 12 The gate of the seventh transistor T3 includes a first conductive portion and a second conductive portion, the first conductive portion extends along the first direction X, and the second conductive portion extends along the second direction Y; the first conductive portion and the second conductive portion are both connected to the first scan line S2.

[0163] Optionally, based on the above embodiments, Figures 4 to 12 The seventh active structure 233 includes a first bending portion 61 and a second bending portion 62, the first bending portion 61 extends along the second direction Y, and the first bending portion 61 extends along the first direction X; the orthographic projection of the first conductive portion on the substrate 1 covers the orthographic projection of the first bending portion 61 on the substrate 1; the orthographic projection of the second conductive portion on the substrate 1 covers the orthographic projection of the second bending portion 62 on the substrate 1.

[0164] Specifically, setting the seventh transistor T3 as a dual-gate transistor can effectively reduce the leakage of the seventh transistor T3 and further improve the display effect of the display panel.

[0165] Optionally, based on the above embodiments, Figures 4 to 12 The pixel circuit 10 further includes an eighth transistor T6, the third active layer further includes an eighth active structure 234, the gate of the eighth transistor T6 is located in the first conductive layer M1, and the channel region of the eighth transistor T6 is located in the eighth active structure 234. At least part of the eighth active structure 234 extends along the second direction Y, and along the second direction Y, the straight line where the eighth active structure 234 is located is not collinear with the straight line where the fourth active structure 224 of the fourth transistor T12 is located.

[0166] Specifically, such a configuration can effectively save the space of the fourth active structure 224 of the fourth transistor T12 located at the second bending portion 62, thereby optimizing the wiring space of the pixel circuit and further reducing the short circuit risk of the display panel.

[0167] Optionally, the width of the third active structure 223 is greater than or equal to the width of the eighth active structure 234 ; and / or the width of the fourth active structure 224 is greater than or equal to the width of the eighth active structure 234 .

[0168] Specifically, the width of the third active structure 223 and the fourth active structure 224 is set to be wider than the width of the eighth active structure 234, so that the third active structure 223 and the fourth active structure 224 connected to the first active layer 21 are equivalent to increasing the size of the first active layer 21, and equivalently increasing the size of the channel region of the driving transistor, thereby effectively improving the grayscale expansion effect, and further improving the display effect of the display panel.

[0169] Optionally, based on the above embodiments, Figures 4 to 12 , the channel region of the eighth transistor T6 is located at the positive projection position of the gate of the eighth transistor T6 on the eighth active structure 234, the display panel 100 also includes a fifth via hole N5, the first electrode of the eighth transistor T6 is connected to the anode of the light-emitting module through the fifth via hole N5, the second electrode of the eighth transistor T6 is connected to the first electrode of the fourth transistor T12 through the eighth active structure 234; the second electrode of the fourth transistor T12 is connected to the second electrode of the driving transistor T1 through the fourth active structure 224; the eighth transistor T6 is used to transmit the driving voltage to the anode of the light-emitting module through the turned-on sixth transistor T5, the second transistor T10, the driving transistor T1 and the fourth transistor T12.

[0170] Specifically, since the gate of the fourth transistor T12 is connected to the gate of the driving transistor T1, the first electrode of the fourth transistor T12 is connected to the second electrode of the eighth transistor T6, and the second electrode of the fourth transistor T12 is connected to the second electrode of the driving transistor T1 through the fourth active structure 224. In this way, in the light-emitting stage, the fourth active structure 224 of the fourth transistor T12 is equivalent to increasing the channel length of the driving transistor T1, thereby further improving the development of the grayscale voltage in the data light-emitting stage, thereby improving the display effect of the display panel.

[0171] Optionally, based on the above embodiments, Figures 4 to 12 The gate of the eighth transistor T6 is connected to the light emitting control line EM, and the orthographic projection of the light emitting control line EM on the substrate 1 covers the orthographic projection of the channel region of the eighth transistor T6 on the substrate 1 .

[0172] Optionally, based on the above embodiments, Figures 4 to 12The pixel circuit 10 also includes a capacitor Cst, a first plate of the capacitor is located on the first conductive layer M1, a second plate of the capacitor is located on the second conductive layer M2, the first plate of the capacitor is connected to the gate of the driving transistor T1; the second plate of the capacitor is connected to the first power line of the display panel; the first plate of the first capacitor is projected on the substrate 1 so as to at least partially cover the projected channel region of the driving transistor T1 on the substrate 1.

[0173] Specifically, such a configuration is conducive to optimizing the circuit layout and reducing the parasitic capacitance in the circuit, so as to facilitate wiring and improve the layout space utilization.

[0174] Optionally, based on the above embodiments, Figures 4 to 12 , the orthographic projection of the first plate of the capacitor on the substrate 1 at least partially overlaps with the orthographic projection of the second plate of the capacitor on the substrate 1 .

[0175] Optionally, based on the above embodiments, Figures 4 to 12 The first plate of the capacitor includes a hole area, and the overlapping position of the orthographic projection of the first plate of the capacitor on the substrate 1 and the orthographic projection of the second plate of the capacitor on the substrate 1 at least partially covers the orthographic projection of the hole area on the substrate 1.

[0176] Specifically, such an arrangement eliminates the need for setting a crossover line, which helps reduce the number of vias.

[0177] Optionally, based on the above embodiments, Figures 4 to 12 The display panel further includes a first initialization line Vrefn1, which is located in the second conductive layer M2; the first initialization line Vrefn1 extends along the first direction X; the pixel circuit 10 further includes a ninth transistor T4, the third active layer further includes a ninth active structure 235; the gate of the ninth transistor T4 is located in the first conductive layer M1, and the channel region of the ninth transistor T4 is located in the ninth active structure 235. The width of the first active structure 221 is greater than or equal to the width of the ninth active structure 235; and / or the width of the second active structure 222 is greater than or equal to the width of the ninth active structure 235; and / or the width of the third active structure 223 is greater than or equal to the width of the ninth active structure 235; and / or the width of the fourth active structure 224 is greater than or equal to the width of the ninth active structure 235.

[0178] Specifically, the ninth transistor T4 plays an initialization role, and is used to initialize the gate of the driving transistor T1.

[0179] Optionally, based on the above embodiments, Figures 4 to 12, the channel region of the ninth transistor T4 is located at the positive projection position of the gate of the ninth transistor T4 on the ninth active structure 235, and the display panel 100 also includes a sixth via N6 and a seventh via N7; the first electrode of the ninth transistor T4 is connected to the first initialization line Vrefn1 through the seventh via N7, and the second electrode of the ninth transistor T4 is connected to the gate of the driving transistor T1 through the ninth active structure 235, the sixth via N6, the first connecting line 40 and the fourth via N4; the ninth transistor T4 is used to transmit the first initialization voltage to the gate of the driving transistor T1.

[0180] Specifically, such a setting is conducive to optimizing the circuit layout and further improving the utilization rate of the layout space.

[0181] Optionally, based on the above embodiments, Figures 4 to 12 The display panel further includes a second scan line S1, which extends along the first direction X. The gate of the ninth transistor T4 is connected to the second scan line S1, and the orthographic projection of the second scan line S1 on the substrate 1 covers the orthographic projection of the channel region of the ninth transistor T4 on the substrate 1.

[0182] Optionally, based on the above embodiments, Figures 4 to 12 The gate of the ninth transistor T4 includes a third conductive portion and a fourth conductive portion, both of which extend along the first direction X; and both of the first conductive portion and the second conductive portion are connected to the second scan line S1.

[0183] Optionally, based on the above embodiments, Figures 4 to 12 The ninth active structure 235 includes a third bending portion 60 and a fourth bending portion 60 that are spaced apart, the third bending portion 60 and the fourth bending portion 60 both extend along the second direction Y, the first bending portion 61 is connected to the second bending portion 62; the orthographic projection of the third conductive portion on the substrate 1 covers the orthographic projection of the third bending portion 60 on the substrate 1; the orthographic projection of the fourth conductive portion on the substrate 1 covers the orthographic projection of the fourth bending portion 60 on the substrate 1.

[0184] Specifically, setting the ninth transistor T4 as a dual-gate transistor can effectively reduce the leakage of the ninth transistor T4 and further improve the display effect of the display panel.

[0185] Optionally, based on the above embodiments, Figures 4 to 12, the display panel further includes a second initialization line Vrefn2, the second initialization line Vrefn2 is located in the second conductive layer M2; the second initialization line Vrefn2 extends along the first direction X; the pixel circuit 10 further includes a tenth transistor T7, the third active layer further includes a tenth active structure 236; the gate of the tenth transistor T7 is located in the first conductive layer M1, and the channel region of the tenth transistor T7 is located in the tenth active structure 236. The width of the first active structure 221 is greater than or equal to the width of the tenth active structure 236; and / or, the width of the second active structure 222 is greater than or equal to the width of the tenth active structure 236; and / or, the width of the third active structure 223 is greater than or equal to the width of the tenth active structure 236; and / or, the width of the fourth active structure 224 is greater than or equal to the width of the tenth active structure 236.

[0186] Specifically, the tenth transistor T7 is used to initialize the anode of the light emitting module, so as to improve the display uniformity of the display panel.

[0187] Optionally, based on the above embodiments, Figures 4 to 12 , the channel region of the tenth transistor T7 is located at the positive projection position of the gate of the tenth transistor T7 on the tenth active structure 236, and the display panel 100 also includes an eighth via N8; the first electrode of the tenth transistor T7 is connected to the second initialization line Vrefn2 through the eighth via N8, and the second electrode of the tenth transistor T7 is connected to the anode of the light-emitting module through the tenth active structure 236 and the fifth via N5; the tenth transistor T7 is used to transmit the second initialization voltage to the anode of the light-emitting module.

[0188] Optionally, based on the above embodiments, Figures 4 to 12 The display panel further includes a third scan line S3, which extends along the first direction X. The gate of the tenth transistor T7 is connected to the third scan line S3, and the orthographic projection of the third scan line S3 on the substrate 1 covers the orthographic projection of the channel region of the tenth transistor T7 on the substrate 1.

[0189] Specifically, such a setting is conducive to optimizing the circuit layout and further improving the utilization rate of the layout space.

[0190] Optionally, based on the above embodiments, Figures 4 to 12, the display panel further includes a third initialization line Vrefp, the third initialization line Vrefp is located in the third conductive layer M3; the third initialization line Vrefp extends along the first direction X; the pixel circuit 10 further includes an eleventh transistor T8, the third active layer further includes an eleventh active structure 237; the gate of the eleventh transistor T8 is located in the first conductive layer M1, and the channel region of the eleventh transistor T8 is located in the eleventh active structure 237. The width of the first active structure 221 is greater than or equal to the width of the eleventh active structure 237; and / or, the width of the second active structure 222 is greater than or equal to the width of the eleventh active structure 237; and / or, the width of the third active structure 223 is greater than or equal to the width of the eleventh active structure 237; and / or, the width of the fourth active structure 224 is greater than or equal to the width of the eleventh active structure 237.

[0191] Specifically, such an arrangement enables the first active structure 221, the second active structure 222, the third active structure 223 and the fourth active structure 224, which are all connected to the first active layer 21, to equivalently increase the size of the first active layer 21 and equivalently increase the size of the channel region of the driving transistor, thereby effectively improving the grayscale expansion effect and further improving the display effect of the display panel.

[0192] Optionally, based on the above embodiments, Figures 4 to 12 , the channel region of the eleventh transistor T8 is located at the positive projection position of the gate of the eleventh transistor T8 on the eleventh active structure 237, the display panel 100 also includes a ninth via hole N9 and a tenth via hole N10; the third conductive layer M3 also includes a second connecting line 50; the first electrode of the eleventh transistor T8 is connected to the third initialization line Vrefp via the ninth via hole N9, and the second electrode of the eleventh transistor T8 is connected to the first electrode of the driving transistor T1 through the eleventh active structure 237, the tenth via hole N10 and the second connecting line; the eleventh transistor T8 is used to transmit the third initialization voltage to the first electrode of the driving transistor T1.

[0193] Specifically, the eleventh transistor T8 is used to initialize the first electrode of the driving transistor T1 to further optimize the display uniformity of the display panel.

[0194] Optionally, based on the above embodiments, Figures 4 to 12 The gate of the eleventh transistor T8 is connected to the third scan line S3 , and the orthographic projection of the third scan line S3 on the substrate 1 covers the orthographic projection of the channel region of the eleventh transistor T8 on the substrate 1 .

[0195] Optionally, based on the above embodiments, Figures 4 to 12 , the material of the active layer 2 includes low temperature polysilicon.

[0196] Specifically, such an arrangement enables the driving transistor T1 and the first transistor T9 to the eleventh transistor T8 to be made thinner and smaller, with lower power consumption, which is conducive to the lightweight arrangement of the display panel.

[0197] It should be noted that the first to tenth vias proposed in the above embodiments refer to conductive structures, and the material thereof is metal. An interlayer insulating layer is provided between the active layer and the multi-layer conductive layer, and a through hole is provided on the interlayer insulating layer. The through hole is the first to tenth vias shown in the above embodiments and the accompanying drawings, and no limitation is made here.

[0198] Optionally, the specific working principle of the pixel circuit 10 provided in the above embodiments may refer to the description in the related art, which will not be repeated here.

[0199] Optionally, an embodiment of the present invention further provides a display device. Fig.13 A schematic diagram of the structure of a display device provided by an embodiment of the present invention. Fig.13 , the display device 200 includes the display panel 100 provided by any embodiment of the present invention, so the display device 200 also has the beneficial effects described in any of the above embodiments. In this embodiment, the display device 200 can be a mobile phone, or any electronic product with a display function, including but not limited to the following categories: display panels in products such as televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, and touch interactive terminals, and the embodiment of the present invention does not specifically limit this.

[0200] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: include: substrate; an active layer, the active layer being located on one side of the substrate; A plurality of conductive layers stacked on a side of the active layer away from the substrate; at least one pixel circuit, the pixel circuit comprising a driving transistor and a switch module, the gate of the driving transistor being connected to the control end of the switch module; the gate of the driving transistor and the control end of the switch module being located in one layer of the multiple conductive layers; The active layer includes a first active layer and a second active layer connected to each other, the channel region of the driving transistor is located in the first active layer, and the channel region of the switch module is located in the second active layer; The second active layer includes at least one bending portion, and the bending portion is bent toward a side close to the first active layer.

2. The display panel according to claim 1, characterized in that: The multi-layer conductive layer comprises a first conductive layer, which is located on a side of the active layer away from the substrate; the gate of the driving transistor and the control end of the switch module are both located on the first conductive layer; At least a portion of the first active layer extends along a first direction, and at least a portion of the second active layer extends along a second direction, and the first direction intersects the second direction; The first active layer and the second active layer are arranged in the same layer; The bending portion includes a first straight line segment, a second straight line segment and a third straight line segment connected in sequence; the first straight line segment and the third straight line segment extend along the first direction, and the second straight line segment extends along the second direction; The first end of the first straight line segment is connected to the first end of the second straight line segment, and the second end of the second straight line segment is connected to the first end of the third straight line segment; The straight line where the second end of the first straight line segment and the second end of the third straight line segment are connected is staggered with the second straight line segment; Preferably, the orthographic projection of the gate of the driving transistor on the substrate covers the orthographic projection of the channel region of the driving transistor on the substrate; The orthographic projection of the control end of the switch module on the substrate covers the orthographic projection of the channel region of the switch module on the substrate; Preferably, the gate of the driving transistor is multiplexed as the control terminal of the switch module; Preferably, the first direction and the second direction are perpendicular to each other.

3. The display panel according to claim 1, characterized in that: The width of the second active layer is greater than or equal to the width of the first active layer.

4. The display panel according to claim 1, characterized in that: The second active layer has a first boundary away from the first active layer; The control end of the switch module has a second boundary away from the first active layer; A distance from an orthographic projection of the first boundary on the substrate to an orthographic projection of the second boundary on the substrate is greater than or equal to 2.5 μm and less than or equal to 5 μm; Preferably, the distance between the active layers of two adjacent pixel circuits is greater than or equal to 2 μm; The minimum distance from the orthographic projection of the second boundary on the substrate to the orthographic projection of the active layer of the adjacent pixel circuit on the substrate is greater than or equal to 1 μm; The minimum distance from the orthographic projection of the first boundary on the substrate to the orthographic projection of the active layer of the adjacent pixel circuit on the substrate is greater than or equal to 2 μm.

5. The display panel according to claim 2, characterized in that: The switch module includes a first transistor and a second transistor; the second active layer includes a first active structure and a second active structure; the channel region of the first transistor is located in the first active structure, and the channel region of the second transistor is located in the second active structure; the second active layer includes a first bending portion, and the first active structure is located in a second straight line segment of the first bending portion; The second active structure is located on the second straight line segment of the first bending portion; The orthographic projection of the gate of the first transistor on the substrate covers the orthographic projection of the channel region of the first transistor on the substrate; The orthographic projection of the gate of the second transistor on the substrate covers the orthographic projection of the channel region of the second transistor on the substrate; the gate of the first transistor is connected to the gate of the second transistor and the gate of the driving transistor; At least part of the first active structure extends along the second direction, and at least part of the second active structure extends along the second direction; The first active structure and the second active structure are both connected to the first end of the first active layer; Preferably, the first active structure extending along the first direction and the second active structure extending along the first direction are reused; Preferably, the width of the first active structure is greater than or equal to the width of the first active layer; and / or, the width of the second active structure is greater than or equal to the width of the first active layer; Preferably, the length of the first active structure is the same as the length of the second active structure; and / or, the width of the first active structure is the same as the width of the second active structure; Preferably, with a straight line connecting the first end of the first active layer and the second end of the first active layer as a symmetry axis, the first active structure and the second active structure are symmetrical to each other; Preferably, the switch module further includes a third transistor and a fourth transistor; the second active layer further includes a third active structure and a fourth active structure; The channel region of the third transistor is located in the third active structure, and the channel region of the fourth transistor is located in the fourth active structure; the second active layer includes a second bending portion, and the third active structure is located in a second straight line segment of the second bending portion; the fourth active structure is located in a second straight line segment of the second bending portion; At least part of the third active structure extends along the second direction, and at least part of the fourth active structure extends along the second direction; the third active structure and the fourth active structure are both connected to the second end of the first active layer; The orthographic projection of the gate of the third transistor on the substrate covers the orthographic projection of the channel region of the third transistor on the substrate; the orthographic projection of the gate of the fourth transistor on the substrate covers the orthographic projection of the channel region of the fourth transistor on the substrate; the gate of the third transistor is connected to the gate of the fourth transistor and the gate of the driving transistor; Preferably, the third active structure extending along the first direction and the fourth active structure extending along the first direction are reused; Preferably, the width of the third active structure is greater than or equal to the width of the first active layer; and / or, the width of the fourth active structure is greater than or equal to the width of the first active layer; Preferably, the length of the third active structure is the same as the length of the fourth active structure; and / or, the width of the third active structure is the same as the width of the fourth active structure; Preferably, with a straight line connecting the first end of the first active layer and the second end of the first active layer as a symmetry axis, the third active structure and the fourth active structure are symmetrical to each other; Preferably, with a perpendicular line connecting the first end of the first active layer and the second end of the first active layer as a symmetry axis, the third active structure and the first active structure are symmetrical to each other; Preferably, with a perpendicular line connecting the first end of the first active layer and the second end of the first active layer as a symmetry axis, the fourth active structure and the second active structure are symmetrical to each other; Preferably, the display panel further includes a data line, the pixel circuit further includes a fifth transistor, the active layer further includes a third active layer, and the third active layer is disposed in the same layer as the first active layer and the second active layer; The third active layer further includes a fifth active structure, the gate of the fifth transistor is located in the first conductive layer; the channel region of the fifth transistor is located in the fifth active structure; The fifth active structure extends along the second direction, and the straight line where the fifth active structure is located is not collinear with the straight line where the first active structure of the first transistor is located; Preferably, the width of the first active structure is greater than or equal to the width of the fifth active structure; and / or the width of the second active structure is greater than or equal to the width of the fifth active structure; Preferably, the channel region of the fifth transistor is located at the positive projection position of the gate of the fifth transistor at the fifth active structure, the multi-layer conductive layer further comprises a second conductive layer and a third conductive layer sequentially arranged on the first conductive layer away from the substrate, the display panel comprises a first via hole, the first electrode of the fifth transistor is connected to the data line via the first via hole, the second electrode of the fifth transistor is connected to the first electrode of the first transistor via the fifth active structure; the second electrode of the first transistor is connected to the first electrode of the driving transistor via the first active structure; the fifth transistor is used to transmit a data voltage to the gate of the driving transistor through the turned-on first transistor; Preferably, the display panel further comprises a first scan line, the gate of the fifth transistor is connected to the first scan line, the first scan line extends along the first direction, and the orthographic projection of the first scan line on the substrate covers the orthographic projection of the channel region of the fifth transistor on the substrate; Preferably, the display panel further includes a first power line, the pixel circuit further includes a sixth transistor, the third active layer further includes a sixth active structure, the gate of the sixth transistor is located in the first conductive layer; and the channel region of the sixth transistor is located in the sixth active structure; The sixth active structure extends along the second direction, and the straight line where the sixth active structure is located is not collinear with the straight line where the second active structure of the second transistor is located; Preferably, the width of the first active structure is greater than or equal to the width of the sixth active structure; and / or the width of the second active structure is greater than or equal to the width of the sixth active structure; Preferably, the channel region of the sixth transistor is located at the positive projection position of the gate of the sixth transistor on the sixth active structure, the display panel includes a second via hole, the first electrode of the sixth transistor is connected to the first power line through the second via hole, the second electrode of the sixth transistor is connected to the first electrode of the second transistor through the sixth active structure; the second electrode of the second transistor is connected to the first electrode of the driving transistor through the second active structure; the sixth transistor is used to transmit the driving voltage to the anode of the light-emitting module through the turned-on second transistor and the turned-on driving transistor; Preferably, the display panel further comprises a light emitting control line, the gate of the sixth transistor is connected to the light emitting control line, the light emitting control line extends along the first direction, and the orthographic projection of the light emitting control line on the substrate covers the orthographic projection of the channel region of the sixth transistor on the substrate; Preferably, the pixel circuit further includes a seventh transistor, the third active layer further includes a seventh active structure, the gate of the seventh transistor is located in the first conductive layer; and the channel region of the seventh transistor is located in the seventh active structure; At least part of the seventh active structure extends along the second direction, and along the second direction, a straight line where the seventh active structure is located is not collinear with a straight line where the third active structure of the third transistor is located; Preferably, the width of the third active structure is greater than or equal to the width of the seventh active structure; and / or, the width of the fourth active structure is greater than or equal to the width of the seventh active structure; Preferably, the channel region of the seventh transistor is located at the positive projection position of the gate of the seventh transistor on the seventh active structure, the third conductive layer includes a first connecting line, the display panel includes a third via hole and a fourth via hole, the first electrode of the seventh transistor is connected to the gate of the driving transistor through the third via hole, the first connecting line and the fourth via hole, the second electrode of the seventh transistor is connected to the first electrode of the third transistor through the seventh active structure; the second electrode of the third transistor is connected to the second electrode of the driving transistor through the third active structure; The seventh transistor is used for transmitting a data voltage to a gate of the driving transistor through the turned-on fifth transistor, the first transistor and the driving transistor; Preferably, the gate of the seventh transistor is connected to the first scan line, and the orthographic projection of the first scan line on the substrate covers the orthographic projection of the channel region of the seventh transistor on the substrate; Preferably, the gate of the seventh transistor comprises a first conductive portion and a second conductive portion, the first conductive portion extends along the first direction, and the second conductive portion extends along the second direction; the first conductive portion and the second conductive portion are both connected to the first scan line; Preferably, the seventh active structure includes a first bending portion and a second bending portion, the first bending portion extends along the second direction, and the first bending portion extends along the first direction; the orthographic projection of the first conductive portion on the substrate covers the orthographic projection of the first bending portion on the substrate; the orthographic projection of the second conductive portion on the substrate covers the orthographic projection of the second bending portion on the substrate; Preferably, the pixel circuit further includes an eighth transistor, the third active layer further includes an eighth active structure, the gate of the eighth transistor is located in the first conductive layer; and the channel region of the eighth transistor is located in the eighth active structure; At least part of the eighth active structure extends along the second direction, and along the second direction, a straight line where the eighth active structure is located is not collinear with a straight line where the fourth active structure of the fourth transistor is located; Preferably, the width of the third active structure is greater than or equal to the width of the eighth active structure; and / or the width of the fourth active structure is greater than or equal to the width of the eighth active structure; Preferably, the channel region of the eighth transistor is located at the positive projection position of the gate of the eighth transistor on the eighth active structure, the display panel includes a fifth via hole, the first electrode of the eighth transistor is connected to the anode of the light-emitting module through the fifth via hole, the second electrode of the eighth transistor is connected to the first electrode of the fourth transistor through the eighth active structure; the second electrode of the fourth transistor is connected to the second electrode of the driving transistor through the fourth active structure; the eighth transistor is used to transmit the driving voltage to the anode of the light-emitting module through the turned-on sixth transistor, the second transistor, the driving transistor and the fourth transistor; Preferably, the gate of the eighth transistor is connected to the light-emitting control line, and the orthographic projection of the light-emitting control line on the substrate covers the orthographic projection of the channel region of the eighth transistor on the substrate.

6. The display panel according to claim 5, characterized in that: The pixel circuit further comprises a capacitor, wherein a first electrode plate of the capacitor is located in the first conductive layer, a second electrode plate of the capacitor is located in the second conductive layer, the first electrode plate of the capacitor is connected to the gate of the driving transistor; the second electrode plate of the capacitor is connected to the first power line of the display panel; the orthographic projection of the first electrode plate of the capacitor on the substrate at least partially covers the orthographic projection of the channel region of the driving transistor on the substrate; Preferably, the orthographic projection of the first electrode plate of the capacitor on the substrate at least partially overlaps with the orthographic projection of the second electrode plate of the capacitor on the substrate; Preferably, the first electrode plate of the capacitor includes a hole area, and the overlapping position of the orthographic projection of the first electrode plate of the capacitor on the substrate and the orthographic projection of the second electrode plate of the capacitor on the substrate at least partially covers the orthographic projection of the hole area on the substrate.

7. The display panel according to claim 5, characterized in that: The display panel further includes a first initialization line, which is located in the second conductive layer; the first initialization line extends along the first direction; The pixel circuit further includes a ninth transistor, and the third active layer further includes a ninth active structure; the gate of the ninth transistor is located in the first conductive layer, and the channel region of the ninth transistor is located in the ninth active structure; the width of the first active structure is greater than or equal to the width of the ninth active structure; and / or the width of the second active structure is greater than or equal to the width of the ninth active structure; and / or, the width of the third active structure is greater than or equal to the width of the ninth active structure; and / or, the width of the fourth active structure is greater than or equal to the width of the ninth active structure; Preferably, the channel region of the ninth transistor is located at the positive projection position of the gate of the ninth transistor on the ninth active structure, and the display panel includes a sixth via hole and a seventh via hole; the first electrode of the ninth transistor is connected to the first initialization line through the seventh via hole, and the second electrode of the ninth transistor is connected to the gate of the driving transistor through the ninth active structure, the sixth via hole, the first connection line and the fourth via hole; the ninth transistor is used to transmit a first initialization voltage to the gate of the driving transistor; Preferably, the display panel further includes a second scan line, the second scan line extends along the first direction, the gate of the ninth transistor is connected to the second scan line, and the orthographic projection of the second scan line on the substrate covers the orthographic projection of the channel region of the ninth transistor on the substrate; Preferably, the gate of the ninth transistor comprises a third conductive portion and a fourth conductive portion, the third conductive portion and the fourth conductive portion both extend along the first direction; the first conductive portion and the second conductive portion are both connected to the second scan line; Preferably, the ninth active structure includes a third bending portion and a fourth bending portion arranged at intervals, the third bending portion and the fourth bending portion both extend along the second direction, and the first bending portion and the second bending portion are connected; the orthographic projection of the third conductive portion on the substrate covers the orthographic projection of the third bending portion on the substrate; the orthographic projection of the fourth conductive portion on the substrate covers the orthographic projection of the fourth bending portion on the substrate.

8. The display panel according to claim 5, characterized in that: The display panel further includes a second initialization line, which is located in the second conductive layer; the second initialization line extends along the first direction; The pixel circuit further includes a tenth transistor, and the third active layer further includes a tenth active structure; a gate of the tenth transistor is located in the first conductive layer, and a channel region of the tenth transistor is located in the tenth active structure; The width of the first active structure is greater than or equal to the width of the tenth active structure; and / or the width of the second active structure is greater than or equal to the width of the tenth active structure; and / or, the width of the third active structure is greater than or equal to the width of the tenth active structure; and / or, the width of the fourth active structure is greater than or equal to the width of the tenth active structure; Preferably, the channel region of the tenth transistor is located at the positive projection position of the gate of the tenth transistor on the tenth active structure, and the display panel includes an eighth via hole; the first electrode of the tenth transistor is connected to the second initialization line through the eighth via hole, and the second electrode of the tenth transistor is connected to the anode of the light-emitting module through the tenth active structure and the fifth via hole; the tenth transistor is used to transmit the second initialization voltage to the anode of the light-emitting module; Preferably, the display panel further comprises a third scan line, the third scan line extends along the first direction, the gate of the tenth transistor is connected to the third scan line, and the orthographic projection of the third scan line on the substrate covers the orthographic projection of the channel region of the tenth transistor on the substrate; Preferably, the display panel further includes a third initialization line, the third initialization line is located in the third conductive layer; the third initialization line extends along the first direction; The pixel circuit further includes an eleventh transistor, and the third active layer further includes an eleventh active structure; the gate of the eleventh transistor is located in the first conductive layer, and the channel region of the eleventh transistor is located in the eleventh active structure; The width of the first active structure is greater than or equal to the width of the eleventh active structure; and / or, the width of the second active structure is greater than or equal to the width of the eleventh active structure; and / or, the width of the third active structure is greater than or equal to the width of the eleventh active structure; and / or, the width of the fourth active structure is greater than or equal to the width of the eleventh active structure; Preferably, the channel region of the eleventh transistor is located at the positive projection position of the gate of the eleventh transistor on the eleventh active structure, the display panel includes a ninth via hole and a tenth via hole; the third conductive layer also includes a second connecting line; the first electrode of the eleventh transistor is connected to the third initialization line via the ninth via hole, and the second electrode of the eleventh transistor is connected to the first electrode of the driving transistor through the eleventh active structure, the tenth via hole and the second connecting line; the eleventh transistor is used to transmit a third initialization voltage to the first electrode of the driving transistor; Preferably, the gate of the eleventh transistor is connected to the third scan line, and the orthographic projection of the third scan line on the substrate covers the orthographic projection of the channel region of the eleventh transistor on the substrate.

9. The display panel according to claim 1, characterized in that: The material of the active layer includes low temperature polysilicon.

10. A display device, characterized in that: A display panel comprising any one of claims 1 to 9.

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