Display panel and display device

Abstract

The invention discloses a display panel and a display device, and belongs to the technical field of display. The display panel comprises a first active layer and a plurality of conductive layers which are arranged on one side of a substrate in a stacked mode and used for forming a pixel unit, and the pixel unit comprises two pixel circuits which are in mirror symmetry in the first direction; the pixel circuit comprises a driving transistor and an auxiliary transistor; the first active layer comprises a first active region, and comprises a first active part and a second active part which are arranged along a first direction and respectively comprise a channel region of the driving transistor and a channel region of the auxiliary transistor; the two second active parts in the same pixel unit are adjacent to each other and are arranged at an interval; the plurality of conductive layers includes a first conductive layer including a first gate structure; the orthographic projection of the first gate structure on the substrate covers the orthographic projection of the corresponding first active region on the substrate; the distance between the two first gate structures in the same pixel unit in the first direction is larger than or equal to 1.5 micrometers. The layout space utilization rate of the display panel can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light Emitting Display (OLED) and flat display devices based on technologies such as light emitting diodes (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops and desktop computers due to their advantages of high image quality, power saving, thin body and wide application range, becoming the mainstream of display devices. However, the current layout space utilization rate of display panels is low. Summary of the invention

[0003] The present invention provides a display panel and a display device to improve the layout space utilization of the display panel.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, including:

[0005] substrate;

[0006] A first active layer and a plurality of conductive layers are stacked on one side of the substrate; wherein the first active layer and the plurality of conductive layers are used to form a plurality of pixel units, and the pixel units include two pixel circuits that are mirror-symmetrical along a first direction;

[0007] The pixel circuit includes: a driving transistor and at least one auxiliary transistor; the first active layer includes a plurality of first active areas belonging to each of the pixel circuits, the first active area includes a first active portion and a second active portion arranged along a first direction, the first active portion includes a channel region of the driving transistor, and the second active portion includes a channel region of the auxiliary transistor; in the same pixel unit, two of the second active portions are adjacent and spaced apart;

[0008] The multiple conductive layers include: a first conductive layer, which is arranged on a side of the first active layer away from the substrate; the first conductive layer includes multiple first gate structures belonging to each pixel circuit; the orthographic projection of each first gate structure on the substrate respectively covers the orthographic projection of each first active area on the substrate; wherein the spacing between two first gate structures in the same pixel unit in the first direction is greater than or equal to 1.5 microns.

[0009] Optionally, an orthographic projection area of ​​the first gate structure on the substrate is larger than an orthographic projection area of ​​the first active region on the substrate;

[0010] Preferably, an outer contour of an orthographic projection of the first gate structure on the substrate surrounds an outer contour of an orthographic projection of the first active region on the substrate;

[0011] The outer contour of the positive projection of the first gate structure on the substrate includes: a first edge extending along the second direction and close to the center line of the pixel unit where the first gate structure is located; the outer contour of the positive projection of the first active area on the substrate includes: a second edge extending along the second direction and close to the center line of the pixel unit where the first active area is located; wherein the second direction is perpendicular to the first direction; the center line extends along the second direction, and the two pixel circuits in the pixel unit are mirror-symmetric along the center line; the spacing between the first edge and the second edge in the same pixel circuit is greater than or equal to 1 micron.

[0012] Optionally, in the first active area, the channel region of the driving transistor is connected to the channel region of each of the auxiliary transistors;

[0013] Preferably, the first active portion includes a first rectangular area, a C-shaped area and a second rectangular area sequentially connected along the first direction; the second active portion is connected to a side of the second rectangular area away from the C-shaped area;

[0014] Preferably, a channel width of the driving transistor is greater than or equal to a channel width of the auxiliary transistor.

[0015] Optionally, the pixel circuit includes two auxiliary transistors, namely a first transistor and a second transistor; the second active portion includes a channel region of the first transistor and a channel region of the second transistor arranged along the second direction;

[0016] Preferably, the channel width of the first transistor is equal to the channel width of the second transistor, and the channel length of the first transistor is equal to the channel length of the second transistor;

[0017] Preferably, in the second active portion, the channel region of the first transistor is connected to the channel region of the second transistor;

[0018] Preferably, in the second active portion, the channel region of the first transistor partially overlaps with the channel region of the second transistor;

[0019] Preferably, the second active portion is rectangular;

[0020] An extension line of a first symmetry axis extending along the first direction in the second rectangular area overlaps with a second symmetry axis extending along the first direction in the second active portion; in the second active portion, a channel region of the first transistor and a channel region of the second transistor are symmetrical along the second symmetry axis;

[0021] Preferably, the width of the second active portion along the first direction is greater than or equal to 2 micrometers;

[0022] A length of the second active portion along the second direction is greater than a width of the second active portion along the first direction.

[0023] Optionally, the pixel circuit further includes a storage capacitor; the multiple conductive layers further include: a second conductive layer, arranged on a side of the first conductive layer away from the substrate;

[0024] Wherein, the first gate structure is reused as the first electrode of the storage capacitor; the second electrode of the storage capacitor is arranged on the second conductive layer; in the same storage capacitor, the orthographic projection of the first electrode on the substrate and the orthographic projection of the second electrode on the substrate at least partially overlap;

[0025] Preferably, in the same pixel unit, the second electrodes of two storage capacitors are connected.

[0026] Optionally, the pixel circuit includes two auxiliary transistors, namely a first transistor and a second transistor; the channel region of the driving transistor is connected to the channel region of the first transistor and the channel region of the second transistor respectively; the second electrode of the driving transistor is located in the first active layer and connected to a side of the first active portion away from the second active portion; the first electrode of the first transistor is located in the first active layer and connected to the channel region of the first transistor; the first electrode of the second transistor is located in the first active layer and connected to the channel region of the second transistor;

[0027] The pixel circuit further includes: a plurality of first-type switch transistors, wherein a first electrode, a channel region, and a second electrode of the first-type switch transistors are connected in sequence and are all located on the first active layer; a gate of the first-type switch transistor is located on the first conductive layer, and an orthographic projection of the gate of the first-type switch transistor on the substrate at least partially overlaps with an orthographic projection of the channel region of the first-type switch transistor on the substrate;

[0028] Preferably, the plurality of first-type switch transistors include: a third transistor, a fourth transistor, a fifth transistor and a sixth transistor; the first electrode of the third transistor is connected to the data line, the second electrode of the third transistor is connected to the first electrode of the first transistor; the first electrode of the fourth transistor is connected to the second electrode of the storage capacitor through the first connecting line, the second electrode of the storage capacitor is connected to the first power line; the second electrode of the fourth transistor is connected to the first electrode of the second transistor; the first electrode of the fifth transistor is connected to the second electrode of the driving transistor, the second electrode of the fifth transistor is connected to the second electrode of the sixth transistor, and the first electrode of the sixth transistor is connected to the first initialization signal line through the second connecting line;

[0029] The multiple conductive layers further include: a third conductive layer and a fourth conductive layer stacked in sequence on a side of the second conductive layer away from the substrate; the data line and the first power line are both located in the fourth conductive layer; the first initialization signal line, the first connection line and the second connection line are all located in the third conductive layer; the first initialization signal line extends along the first direction;

[0030] Preferably, each of the pixel units is arranged in an array in the display panel; the first conductive layer further comprises: a plurality of first scan lines, a plurality of second scan lines and a plurality of light emitting control signal lines; each of the first scan lines, each of the second scan lines and each of the light emitting control signal lines extends along the first direction and is arranged along the second direction; the first direction is perpendicular to the second direction;

[0031] Wherein, the gates of the third transistors in the pixel circuits in the same row are all located on the same first scanning line; the gates of the fourth transistors and the gates of the fifth transistors in the pixel circuits in the same row are all located on the same light emitting control signal line; the gates of the sixth transistors in the pixel circuits in the same row are all located on the same second scanning line; the first electrodes of the sixth transistors in the pixel circuits in the same row are connected to the same first initialization signal line;

[0032] Preferably, two pixel circuits in the same pixel unit share the same first connecting line.

[0033] Optionally, the pixel circuit further includes: a plurality of second type switch transistors; the plurality of conductive layers further include a fifth conductive layer disposed between the second conductive layer and the third conductive layer; the display panel further includes a second active layer disposed between the second conductive layer and the fifth conductive layer;

[0034] The first electrode, the channel region, and the second electrode of the second type switch transistor are connected in sequence and are all located in the second active layer; the gate of the second type switch transistor is located in the fifth conductive layer, and the orthographic projection of the gate of the second type switch transistor on the substrate at least partially overlaps with the orthographic projection of the channel region of the second type switch transistor on the substrate;

[0035] Preferably, the plurality of second-type switch transistors include: a seventh transistor and an eighth transistor; the first electrode of the seventh transistor is connected to the second electrode of the driving transistor through a third connecting line, and the second electrode of the seventh transistor is connected to the first gate structure through a fourth connecting line; the second electrode of the seventh transistor is multiplexed as the second electrode of the eighth transistor, and the first electrode of the eighth transistor is connected to the second initialization signal line through a fifth connecting line;

[0036] The third connection line, the fourth connection line and the fifth connection line are all located in the third conductive layer; the second initialization signal line is located in the fifth conductive layer, and the second initialization signal line extends along the first direction;

[0037] The display panel further includes: a plurality of third scan lines and a plurality of fourth scan lines; each of the third scan lines and each of the fourth scan lines extends along the first direction;

[0038] The third scan line includes a first sub-line located in the fifth conductive layer; the fourth scan line includes a second sub-line located in the fifth conductive layer; the gates of the seventh transistors in the pixel circuits in the same row are all located on the same second sub-line, and the gates of the eighth transistors in the pixel circuits in the same row are all located on the same first sub-line;

[0039] Preferably, the third scanning line further comprises a third sub-line located in the second conductive layer, an orthographic projection of the first sub-line on the substrate at least partially overlaps with an orthographic projection of the third sub-line on the substrate, and the first sub-line is electrically connected to the third sub-line;

[0040] And / or, the fourth scan line also includes a fourth sub-line located in the second conductive layer, the orthographic projection of the second sub-line on the substrate at least partially overlaps with the orthographic projection of the fourth sub-line on the substrate, and the second sub-line is electrically connected to the fourth sub-line.

[0041] Optionally, in the same row of the pixel circuits, the second initialization signal line, the third scan line, the first scan line, the fourth scan line, the first gate structure, the light emitting control signal line, the second scan line and the first initialization signal line are arranged in sequence along the second direction;

[0042] Preferably, an orthographic projection of the third scanning line in the pixel circuits in this row on the substrate overlaps with an orthographic projection of the first initialization signal line in the pixel circuits in the previous row on the substrate;

[0043] And / or, the orthographic projection of the second scanning line in the pixel circuits in the current row on the substrate overlaps with the orthographic projection of the second initialization signal line in the pixel circuits in the next row on the substrate.

[0044] Optionally, the plurality of first-type switch transistors further include: a ninth transistor; the gate of the ninth transistor is located on the second scan line; the first electrode of the ninth transistor is connected to the third initialization signal line, and the second electrode of the ninth transistor is connected to the second electrode of the fourth transistor through a sixth connection line;

[0045] Wherein, the third initialization signal line and the sixth connection line are both located in the third conductive layer; the third initialization signal line extends along the first direction;

[0046] Preferably, the gates of the ninth transistors in the pixel circuits in the same row are all located on the same second scanning line; the first electrodes of the ninth transistors in the pixel circuits in the same row are all connected to the same third initialization signal line;

[0047] Preferably, in the same row of pixel circuits, an orthographic projection of the third initialization signal line on the substrate overlaps with an orthographic projection of the second scanning line on the substrate.

[0048] In a second aspect, an embodiment of the present invention provides a display device, including: a display panel provided by any embodiment of the present invention.

[0049] In the display panel provided by the embodiment of the present invention, a plurality of pixel units are formed by stacking a first active layer and a plurality of conductive layers, and the pixel unit includes two pixel circuits that are mirror-symmetrical along a first direction. The first active layer is provided with a first active region of each pixel circuit, and the first active region includes a first active portion for providing a channel region of a driving transistor, and a second active portion for providing a channel region of an auxiliary transistor; the first conductive layer is provided with a first gate structure of each pixel circuit. By providing the orthographic projection of the first gate structure on the substrate to cover the orthographic projection of the first active region on the substrate, the connection between the gate of the driving transistor and the gate of each auxiliary transistor can be achieved, and the device size of the driving transistor and each auxiliary transistor can be stabilized. Among them, based on the second active portion, the length of the channel region of the driving transistor can be extended, which is conducive to increasing the driving capability of the driving transistor in a limited layout space; and by providing the spacing between the two first gate structures in the same pixel unit in the first direction to be greater than or equal to 1.5 microns, it can be ensured that there is no short circuit between the two first gate structures, and the two pixel circuits can work normally, and at the same time, it can also be ensured that the spacing between the first active layer structures of the two pixel circuits meets the process requirements. Therefore, the embodiments of the present invention can effectively improve the layout space utilization of the display panel.

[0050] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0052] Figure 1 It is a schematic diagram of a layout of a display panel in the related art;

[0053] Figure 2 is a schematic diagram of a layout structure of a display panel provided by an embodiment of the present invention;

[0054] Figure 3 is a schematic structural diagram of a first active layer provided by an embodiment of the present invention;

[0055] Figure 4 is a schematic structural diagram of a first active region provided by an embodiment of the present invention;

[0056] Figure 5is a schematic diagram of a connection relationship between a driving transistor and a channel region of a first transistor provided by an embodiment of the present invention;

[0057] Figure 6 is a schematic diagram of the connection relationship between a channel region of a driving transistor and a second transistor provided by an embodiment of the present invention;

[0058] Figure 7 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0059] Figure 8 is a schematic diagram of a film layer structure of a display panel provided by an embodiment of the present invention;

[0060] Fig. 9 is a schematic diagram of the layout structure of another display panel provided by an embodiment of the present invention;

[0061] Fig.10 is a schematic diagram of a layout structure of another display panel provided by an embodiment of the present invention;

[0062] Fig.11 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0063] Fig.12 is a schematic diagram of a layout structure of another display panel provided by an embodiment of the present invention;

[0064] Fig.13 It is a schematic diagram of the layout structure of another display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0065] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0066] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0067] As mentioned in the background art, the space utilization rate of the display panel in the related art is low. The reasons for this problem are briefly described below. Figure 1 It is a schematic diagram of a display panel layout in the related art. Figure 1 , a pixel unit may include two pixel circuits that are mirror-symmetrical along a first direction X, Figure 1 The structure related to the driving transistor DTFT of two pixel circuits in a pixel unit is given in FIG. The display panel includes a first active layer PSI and a first conductive layer M1 which are stacked. The first active layer PSI includes an active region of each driving transistor DTFT, and the active region includes a drain region D01, a channel region G01 and a source region S01 which are sequentially connected along a first direction X; the first conductive layer M1 includes a gate G of each driving transistor DTFT.

[0068] According to the requirements and limitations of the current process capability, the following size limitations are imposed on the layout structure:

[0069] 1. The spacing d04 between the gate G of the driving transistor DTFT and the drain region D01 of the driving transistor DTFT in the first direction X, and the spacing d01 between the gate G of the driving transistor DTFT and the source region S01 of the driving transistor DTFT in the first direction X are generally designed to be ≥1um. The reason is that the gate G overlaps with the first active layer PSI to form a TFT (thin film transistor) device. The above size limitation of ≥1um is mainly considered to prevent the gate G from overlapping with the source region S01 and the drain region D01 when the wiring and the related via size fluctuate, so as to avoid forming a new TFT device.

[0070] 2. Since the potentials of the first active layer structures belonging to the two pixel circuits in the same pixel unit are different, a certain distance needs to be maintained between the two. Usually, due to the limitations of current equipment and process capabilities, the spacing d02 between the first active layer structures of the two pixel circuits needs to be ≥ 2um.

[0071] 3. The width of the wiring in the first active layer PSI is usually ≥ 2 um, and the width of the source region S01 in the first direction X is usually around 2 um.

[0072] In summary, due to the above requirements for the spacings d01, d02, and d03, in the same pixel unit, the spacing between the gates G of the driving transistors DTFT of the two pixel circuits in the first direction X is: 2*d01+d02+2*d03≥2*1+2+2*2 (um), that is, the minimum spacing between the gates G of the driving transistors DTFT of the two pixel circuits in the first direction X is about 8um. Therefore, in the related art, the size of the gate G of the driving transistor DTFT and the length of the channel region G01 are limited, and the layout space utilization of the display panel is limited.

[0073] To solve the above technical problems, an embodiment of the present invention provides a display panel. The display panel includes a substrate, and a first active layer and a plurality of conductive layers stacked on one side of the substrate. The first active layer and the plurality of conductive layers are used to form a plurality of pixel units, and the pixel unit includes two pixel circuits that are mirror-symmetrical along a first direction; the pixel circuit includes: a driving transistor and at least one auxiliary transistor. The gate of the auxiliary transistor is connected to the gate of the driving transistor, and the channel region of the auxiliary transistor can also be connected to the channel region of the driving transistor. The auxiliary transistor is used to extend the channel region of the driving transistor to improve the width-to-length ratio of the driving transistor and enhance the driving capability of the driving transistor.

[0074] Figure 2 is a schematic diagram of a layout structure of a display panel provided by an embodiment of the present invention, Figure 3 is a schematic diagram of the structure of a first active layer provided by an embodiment of the present invention. Figure 2 A layout structure related to a driving transistor DTFT and an auxiliary transistor ATFT in a pixel unit is given, wherein two pixel circuits in a pixel unit are, for example, mirror-symmetric about a center line LC of the pixel unit in a first direction X; the center line LC extends along a second direction Y, and the second direction Y is perpendicular to the first direction X. Figure 3 It is given in Figure 2 The structure of the first active layer of the pixel circuit on the left. Figure 2 and Figure 3 The first active layer PSI includes a plurality of first active regions 10 belonging to each pixel circuit. The first active region 10 includes a first active portion 11 and a second active portion 12 arranged along a first direction X. The first active portion 11 includes a channel region of a driving transistor DTFT, and the second active portion 12 includes a channel region of an auxiliary transistor ATFT. In the first active region 10, the first active portion 11 and the second active portion 12 can be connected to each other, for example. In the same pixel unit, two second active portions 12 are adjacent and spaced apart. In other words, for the first active region 10 of any pixel circuit in the pixel unit, the second active portion 12 is arranged on the side of the first active portion 11 close to the center line LC.

[0075] The multiple conductive layers include: a first conductive layer M1; the first conductive layer M1 is arranged on the side of the first active layer PSI away from the substrate. The first conductive layer M1 includes multiple first gate structures G1 belonging to each pixel circuit. The orthographic projections of each first gate structure G1 on the substrate respectively cover the orthographic projections of each first active area 10 on the substrate; wherein the orthographic projection position of the first active part 11 on the first gate structure G1 can be used as the gate of the driving transistor DTFT, and the orthographic projection position of the second active part on the first gate structure G1 can be used as the gate of each auxiliary transistor ATFT. The first gate structure G1 is an integrated structure, that is, the gate of the driving transistor DTFT is connected to the gate of each auxiliary transistor ATFT.

[0076] Among them, the spacing d1 between the two first gate structures G1 in the same pixel unit in the first direction X is greater than or equal to 1.5 microns. It can be understood that the spacing d1 between the two first gate structures G1 in the first direction X is the distance between the edges of the two first gate structures G1 closest to the center line LC. Since the orthographic projection of the first gate structure G1 on the substrate covers the orthographic projection of the first active area 10 on the substrate, the spacing d2 between the two second active parts 12 in the same pixel unit is greater than the spacing d1 between the two first gate structures G1 in the first direction X, that is, the spacing d2 between the two second active parts 12 in the same pixel unit can be greater than 1.5 microns, meeting the spacing requirements of the first active layer structures belonging to the two pixel circuits in the same pixel unit under the current equipment and process capabilities.

[0077] In the display panel provided by the embodiment of the present invention, a plurality of pixel units are formed by stacking a first active layer PSI and a plurality of conductive layers, and the pixel units are provided with two pixel circuits that are mirror-symmetric along a first direction X. A first active region 10 of each pixel circuit is provided in the first active layer PSI, and the first active region 10 includes a first active portion 11 for providing a channel region of a driving transistor DTFT, and a second active portion 12 for providing a channel region of an auxiliary transistor ATFT; a first gate structure G1 of each pixel circuit is provided in the first conductive layer M1. By providing the orthographic projection of the first gate structure G1 on the substrate to cover the orthographic projection of the first active region 10 on the substrate, the connection between the gate of the driving transistor DTFT and the gate of each auxiliary transistor ATFT can be achieved, and the device sizes of the driving transistor DTFT and each auxiliary transistor ATFT are stabilized. Among them, the second active portion 12 can extend the length of the channel region of the driving transistor DTFT, which is beneficial to increase the driving capability of the driving transistor DTFT in a limited layout space; and by setting the spacing d1 of the two first gate structures G1 in the same pixel unit in the first direction X to be greater than or equal to 1.5 microns, it can be ensured that there is no short circuit between the two first gate structures G1, and that both pixel circuits can work normally, and at the same time, it can also be ensured that the spacing between the first active layer structures of the two pixel circuits meets the process requirements. Therefore, the embodiment of the present invention can effectively improve the layout space utilization of the display panel.

[0078] On the basis of the above-mentioned embodiments, optionally, each pixel unit can be arranged in an array in a display area of ​​the display panel; each pixel unit has the same structure, and adjacent pixel units are connected.

[0079] The substrate is used to provide protection and support for other film layers of the display panel. The substrate can be a flexible substrate formed of materials such as polyimide (PI), polyethylene naphthalate (PEN) or polyethylene terephthalate (PET), or a hard substrate formed of materials such as glass. Each conductive layer can be composed of any conductive material, such as a metal, alloy, metal oxide or non-metallic conductive material, and specific materials may include silver, molybdenum, titanium, aluminum and copper. The first active layer PSI can be composed of polycrystalline silicon material. It can be understood that at least one insulating layer is provided between each two adjacent conductive layers, and at least one insulating layer is also provided between the first active layer PSI and the conductive layer adjacent thereto; the material of the insulating layer can be set to an inorganic material or an organic material according to requirements, and is not specifically limited here. Two structures located in two different film layers can be directly connected through vias, or can be bridged through connecting wires located in other conductive layers (that is, both structures are connected to the same connecting wire through vias to achieve electrical connection).

[0080] On the basis of the above-mentioned embodiments, optionally, the orthographic projection area of ​​the first gate structure G1 on the substrate is larger than the orthographic projection area of ​​the first active area 10 on the substrate, so as to ensure that the orthographic projection of the first gate structure G1 on the substrate completely covers the orthographic projection of the first active area 10 on the substrate, so that the device size of each auxiliary transistor ATFT is stable.

[0081] Furthermore, the outer contour of the orthographic projection of the first gate structure G1 on the substrate surrounds the outer contour of the orthographic projection of the first active area 10 on the substrate. The outer contour of the orthographic projection of the first gate structure G on the substrate includes: a first edge extending along the second direction Y and close to the center line LC of the pixel unit where the first gate structure G1 is located. The outer contour of the orthographic projection of the first active area 10 on the substrate includes: a second edge extending along the second direction Y and close to the center line LC of the pixel unit where the first active area 10 is located. The second direction Y is perpendicular to the first direction X; the center line LC extends along the second direction Y, and the two pixel circuits in the pixel unit are mirror-symmetrical along the center line LC. The spacing between the first edge and the second edge in the same pixel circuit (corresponding to Figure 2 The spacing d3) is greater than or equal to 1 micron.

[0082] In the embodiment of the present invention, the first gate structure G1 is set to extend in the first direction X by a distance ≥1um relative to the first active area 10 in the direction of the center line LC, so as to ensure that the TFT device size of the auxiliary transistor ATFT formed by the first gate structure G1 extending to overlap with the second active portion 12 is stable and not affected by process fluctuations.

[0083] On the basis of the above embodiments, optionally, in the first active area 10, the channel area of ​​the driving transistor DTFT is connected to the channel area of ​​each auxiliary transistor ATFT, that is, the first active portion 11 is directly connected to the second active portion 12, which is equivalent to extending the gate of the driving transistor DTFT to cover the second active portion 12 to form a first gate structure G1; the second active portion 12 may correspond to Figure 1 In this embodiment, the auxiliary transistors ATFT are formed by overlapping the first gate structure G1 and the second active portion 12, which is equivalent to using the source region S01 position of the driving transistor DTFT to form the channel region of each auxiliary transistor ATFT. On the basis of not increasing the layout area, the channel region of the driving transistor DTFT can be extended. Since the channel region of the driving transistor DTFT is directly connected to the channel region of each auxiliary transistor ATFT, the space occupied by the source region of the driving transistor DTFT and the drain region of the auxiliary transistor ATFT can be saved, thereby maximizing the use of the layout space.

[0084] Figure 4 is a schematic diagram of the structure of a first active region provided by an embodiment of the present invention. Figure 4 On the basis of the above embodiments, optionally, the first active portion 11 includes a first rectangular area 111, a C-type area 112 and a second rectangular area 113 connected in sequence along the first direction X; the second active portion 12 is connected to a side of the second rectangular area 113 away from the C-type area 112.

[0085] On the basis of the above embodiments, optionally, the channel width of the driving transistor DTFT may be set equal to the channel width of the auxiliary transistor ATFT. Such a setting is conducive to quantitatively determining the channel extension effect of the auxiliary transistor ATFT on the driving transistor DTFT. Specifically, when the channel width of the driving transistor DTFT is consistent with the channel width of the auxiliary transistor ATFT, the actual length of the channel region of the driving transistor DTFT can be obtained by directly adding the channel length of the auxiliary transistor ATFT and the channel length of the driving transistor DTFT.

[0086] Alternatively, the channel width of the driving transistor DTFT may be set to be greater than the channel width of the auxiliary transistor ATFT. Figure 5 and Figure 6 , the width of the channel region DG of the driving transistor is, for example, the length WD of the second rectangular region 113 along the second direction Y; see Figure 4 The channel width of the auxiliary transistor ATFT is, for example, the width d4 of the second active portion 12 along the first direction X. By setting the channel width of the auxiliary transistor ATFT to be smaller than the channel width of the driving transistor DTFT, the layout space can be effectively saved.

[0087] The length of the channel region DG of the driving transistor is, for example, Figure 5 and Figure 6 The center line LD of the channel region DG of the driving transistor shown in FIG. Figure 5 and Figure 6 For example, the width of the channel region DG of the driving transistor DTFT may be set to be smaller than the length, and the width and length may be 3 um and 18 um, respectively.

[0088] The length of the channel region of the auxiliary transistor ATFT is, for example, related to the length d5 ​​of the second active portion 12 in the second direction Y. The length of the channel region of the auxiliary transistor ATFT can be arbitrarily set according to actual needs and wiring space. As long as the length of the channel region of the auxiliary transistor ATFT is greater than zero, the extension of the channel region of the driving transistor DTFT can be achieved. Exemplarily, the width of the channel region of the auxiliary transistor ATFT can be set to be smaller than the length, and the width and length are 2um and 3.5um respectively.

[0089] Based on the above embodiments, the pixel circuit may optionally include two auxiliary transistors, namely a first transistor and a second transistor; the second active portion 12 may include a channel region of the first transistor and a channel region of the second transistor arranged along the second direction Y. Figure 7 , exemplarily, one end of the channel region of the first transistor T1 can be connected to the channel region of the driving transistor DTFT, and the other end of the channel region of the first transistor T1 can be connected to the first electrode of the first transistor T1, and then connected to the third transistor T3; the third transistor T3 is used to respond to the first scan signal SP1, and transmit the data voltage Vdata to the driving transistor DTFT in the data writing stage. Then, the first transistor T1 can be used to extend the channel region of the driving transistor DTFT in the data writing stage. One end of the channel region of the second transistor T2 can be connected to the channel region of the driving transistor DTFT, and the other end of the channel region of the second transistor T2 can be connected to the first electrode of the second transistor T2, and then connected to the fourth transistor T4; the fourth transistor T4 and the fifth transistor T5 are used to respond to the light emitting control signal EM, and are turned on in the light emitting stage, so that the driving transistor DTFT generates a driving current to drive the light emitting device OLED to emit light. Then, the second transistor T2 can be used to extend the channel region of the driving transistor DTFT in the light emitting stage.

[0090] In summary, in this embodiment, by providing two auxiliary transistors, the channel region of the driving transistor DTFT can be extended in different driving stages of the pixel circuit, so as to improve the driving capability of the driving transistor DTFT as much as possible.

[0091] On the basis of the above-mentioned embodiments, optionally, the channel region sizes of the first transistor T1 and the second transistor T2 can be arbitrarily set according to actual needs and wiring space, for example, set to the same size or different sizes. Preferably, the width WT1 of the channel region T1G of the first transistor T1 can be set equal to the width WT2 of the channel region T2G of the second transistor T2, and the length of the channel region T1G of the first transistor T1 can be set equal to the length of the channel region T2G of the second transistor T2. In this embodiment, the size parameters of the first transistor T1 and the second transistor T2 are set to be completely consistent, and the channel region sizes are consistent, so that in the data writing stage and the light emitting stage, the auxiliary transistor has the same channel extension effect on the driving transistor DTFT, so that the threshold voltage of the driving transistor DTFT in the data writing stage and the light emitting stage is consistent, thereby ensuring the optimal display effect.

[0092] Specifically, in the second active portion 12, the channel region of the first transistor T1 is connected to the channel region of the second transistor T2, that is, the channel region of the driving transistor DTFT (i.e., the first active portion 11) is connected to the channel region of the first transistor T1 and the channel region of the second transistor T2, forming an integrally connected first active region 10. Figure 5 and Figure 6 In the second active portion 12 , the channel region T1G of the first transistor T1 and the channel region T2G of the second transistor T2 may partially overlap, so as to further reduce the area occupied by the pixel circuit layout.

[0093] Exemplarily, the second active portion 12 is rectangular. Figure 4 , the second rectangular area 113 includes a first symmetry axis LZ1 extending along the first direction X, the second active portion 12 includes a second symmetry axis LZ2 extending along the first direction X, and the extension line of the first symmetry axis LZ1 in the first direction X overlaps with the second symmetry axis LZ2. Also, in the second active portion 12, the channel region T1G of the first transistor T1 and the channel region T2G of the second transistor T2 are symmetrical along the second symmetry axis LZ2. In this way, it can be ensured that the first transistor T1 is completely symmetrical with the second transistor, and the extension effect on the channel region DG of the driving transistor DTFT is completely consistent. Specifically, see Figure 5 The width WT1 of the channel region T1G of the first transistor T1 is, for example, the width of the second active portion 12 in the first direction X; the length of the channel region T1G of the first transistor T1 is, for example, Figure 5 The center line LT1 of the channel region T1G of the first transistor T1 shown in FIG. Figure 5 The length of the black dotted line in Figure 6 The width WT2 of the channel region T2G of the second transistor T2 is, for example, the width of the second active portion 12 in the first direction X; the length of the channel region T2G of the second transistor T2 is, for example, Figure 6 The center line LT2 of the channel region T2G of the second transistor T2 shown in FIG. Figure 6 The length of the black dotted line in the figure.

[0094] Based on the above embodiments, optionally, the width d4 of the second active portion 12 along the first direction X is greater than or equal to 2 microns; the length d5 ​​of the second active portion 12 along the second direction Y is greater than the width of the second active portion 12 along the first direction X, and specifically may be greater than or equal to 3.5 microns.

[0095] In the above-mentioned embodiments, the structure and size information related to the driving transistor DTFT and the auxiliary transistor ATFT are described in detail. The specific layout structure of the pixel circuit is described below, but it is not intended to limit the present invention.

[0096] Continue to see Figure 7 , based on the above embodiments, optionally, the pixel circuit further includes a storage capacitor Cst. Figure 8 Schematic diagram of a film structure of a display panel provided by an embodiment of the present invention. Figure 8 The multiple conductive layers also include: a second conductive layer M2, which is arranged on a side of the first conductive layer M1 away from the substrate 200.

[0097] Fig. 9 It is a schematic diagram of the layout structure of another display panel provided by an embodiment of the present invention. Fig. 9 4 shows a complete structure of a pixel unit 400, with the center line LC as the dividing line, and the left and right sides along the first direction X are respectively two pixel circuit structures in the pixel unit 400, and the two pixel circuit structures are mirror-symmetrical about the center line LC. Fig. 9 The first gate structure G1 can be reused as the first electrode C1 of the storage capacitor Cst, which is equivalent to the first electrode C1 of the storage capacitor Cst being connected to the gate of the driving transistor DTFT; the second electrode C2 of the storage capacitor Cst is disposed on the second conductive layer M2. In the same storage capacitor Cst, the orthographic projection of the first electrode C1 on the substrate 200 and the orthographic projection of the second electrode C2 on the substrate 200 at least partially overlap.

[0098] Furthermore, in the same pixel unit 400, the second electrodes C2 of the two storage capacitors Cst can be connected into an integral structure. Figure 7 It can be seen that the second electrode C2 of the storage capacitor Cst is connected to the first power line and is connected to the first power signal VDD. Therefore, the signals connected to the second electrodes C2 of the two storage capacitors Cst in the same pixel unit 400 are consistent and can be connected together and connected to the same first power line through a via located on the center line LC to reduce the via structure in the display panel.

[0099] On the basis of the above embodiments, optionally, the pixel circuit includes two auxiliary transistors, namely, a first transistor T1 and a second transistor T2; the channel region of the driving transistor DTFT is connected to the channel region of the first transistor T1 and the channel region of the second transistor T2 respectively; the second electrode (drain region) of the driving transistor DTFT is located in the first active layer PSI and connected to the side of the first active portion 11 away from the second active portion 12. The first electrode of the first transistor T1 is located in the first active layer PSI and connected to the channel region of the first transistor T1, for example, connected to the side of the channel region of the first transistor T1 away from the channel region of the second transistor T2 along the second direction Y. The first electrode of the second transistor T2 is located in the first active layer PSI and connected to the channel region of the second transistor, for example, connected to the side of the channel region of the second transistor T2 away from the channel region of the first transistor T1 along the second direction Y. It can be understood that the structure of the transistors in the display panel is symmetrical, the first electrode of each transistor may include the source region (or drain region) of the transistor, and the second electrode may include the drain region (or source region) of the transistor, and the source and drain of each transistor are not distinguished here.

[0100] On this basis, see Figure 7 , the pixel circuit further includes: a plurality of first-type switch transistors. The first electrode, the channel region, and the second electrode of the first-type switch transistor are connected in sequence and are all located on the first active layer PSI; the gate of the first-type switch transistor is located on the first conductive layer M1, and the positive projection of the gate M1 of the first-type switch transistor on the substrate 200 at least partially overlaps with the positive projection of the channel region of the first-type switch transistor on the substrate 200. For example, the first-type switch transistor is a transistor of the same channel type as the drive transistor DTFT and the auxiliary transistor ATFT, for example, both are P-type LTPS transistors.

[0101] Specifically, the plurality of first type switch transistors include: a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6. Figure 7 , Fig. 9 and Fig.10 , the first electrode of the third transistor T3 is connected to the data line (not shown in the figure), and is connected to the data voltage Vdata; the second electrode of the third transistor T3 is connected to the first electrode of the first transistor T1. The first electrode of the fourth transistor T4 is connected to the second electrode C2 of the storage capacitor Cst through the first connection line L1, and the second electrode C2 of the storage capacitor Cst is connected to the first power line (not shown in the figure); the second electrode of the fourth transistor T4 is connected to the first electrode of the second transistor T2. The first electrode of the fifth transistor T5 is connected to the second electrode of the driving transistor DTFT, and the second electrode of the fifth transistor T5 is connected to the second electrode of the sixth transistor T6; the first electrode of the sixth transistor T6 is connected to the first initialization signal line LREF1 through the second connection line L2, and is connected to the first initialization voltage Vrefn2.

[0102] Among them, see Figure 8 The multiple conductive layers also include: a third conductive layer M3 and a fourth conductive layer M4 stacked in sequence on the side of the second conductive layer M2 away from the substrate 200. The data line and the first power line are both located in the fourth conductive layer M4, for example, both extend along the second direction Y. The first initialization signal line LREF1, the first connection line L1, and the second connection line L2 are all located in the third conductive layer M3. The first initialization signal line LREF1 extends along the first direction X.

[0103] On the basis of the above embodiments, optionally, each pixel unit 400 is arranged in an array in the display panel. The first conductive layer M1 further includes: a plurality of first scan lines LS1 for providing a first scan signal SP1; a plurality of second scan lines LS2 for providing a second scan signal SP2; and a plurality of light emitting control signal lines LEM for providing a light emitting control signal EM. Each of the first scan lines LS1, each of the second scan lines LS2, and each of the light emitting control signal lines LEM extends along a first direction X and is arranged along a second direction Y; the first direction X is perpendicular to the second direction Y.

[0104] Among them, the gates of the third transistors T3 in each pixel circuit in the same row are all located on the same first scan line LS1; in other words, the orthographic projections of each first scan line LS1 on the substrate 200 overlap with the orthographic projections of the channel regions of each third transistor T3 on the substrate 200, and the orthographic projection position of the channel region of the third transistor T3 on the first scan line LS1 constitutes the gate of the third transistor T3. The gates of the fourth transistor T4 and the fifth transistor T5 in each pixel circuit in the same row are all located on the same light-emitting control signal line LEM. The gates of the sixth transistors T6 in each pixel circuit in the same row are all located on the same second scan line LS2. The first electrodes of the sixth transistors T6 in each pixel circuit in the same row are connected to the same first initialization signal line LREF1. Among them, the relationship between each signal line and the gate of the corresponding transistor can refer to the corresponding relationship between the gate of the third transistor T3 and the first scan line LS1, and no further description is given.

[0105] Based on the above embodiments, two pixel circuits in the same pixel unit 400 may share the same first connection line L1. The first connection line L1 may extend along the second direction Y and be symmetrical about the center line LC in the first direction X with the center line LC as the axis of symmetry.

[0106] Based on the above embodiments, optionally, the pixel circuit further includes: a plurality of second type switch transistors. Figure 8The multiple conductive layers also include a fifth conductive layer GATO arranged between the second conductive layer M2 and the third conductive layer M3; the display panel also includes a second active layer IGZO arranged between the second conductive layer M2 and the fifth conductive layer GATO; the second active layer IGZO includes, for example, indium gallium zinc oxide material.

[0107] The first electrode, the channel region, and the second electrode of the second type switch transistor are connected in sequence and are all located in the second active layer IGZO; the gate of the second type switch transistor is located in the fifth conductive layer GATO, and the orthographic projection of the gate of the second type switch transistor on the substrate 200 at least partially overlaps with the orthographic projection of the channel region of the second type switch transistor on the substrate 200. For example, the second type switch transistor is a transistor of a channel type different from that of the drive transistor DTFT and the auxiliary transistor ATFT, for example, both are N-type IGZO transistors.

[0108] Specifically, the plurality of second type switch transistors include: a seventh transistor T7 and an eighth transistor T8. Figure 7 , Fig. 9 and Fig.10 The first electrode of the seventh transistor T7 is connected to the second electrode of the driving transistor DTFT through the third connecting line L3, and the second electrode of the seventh transistor T7 is connected to the first gate structure G1 through the fourth connecting line L4; the second electrode of the seventh transistor T7 is multiplexed as the second electrode of the eighth transistor T8, or connected to the second electrode of the eighth transistor T8, and the first electrode of the eighth transistor T8 is connected to the second initialization signal line LREF2 through the fifth connecting line L5, and is connected to the second initialization signal Vrefn1.

[0109] The third connection line L3 , the fourth connection line L4 and the fifth connection line L5 are all located in the third conductive layer M3 ; the second initialization signal line LREF2 is located in the fifth conductive layer GAT0 , and the second initialization signal line LREF2 extends along the first direction X.

[0110] The display panel further includes: a plurality of third scan lines LS3 for providing a third scan signal SN1; and a plurality of fourth scan lines LS4 for providing a fourth scan signal SN2. Each of the third scan lines LS3 and each of the fourth scan lines LS4 extends along the first direction X.

[0111] Specifically, the third scan line LS3 may include a first sub-line LS31 located in the fifth conductive layer GATO; the fourth scan line LS4 may include a second sub-line LS41 located in the fifth conductive layer GATO. The first sub-line LS31 and the second sub-line LS41 both extend along the first direction X. The gates of the seventh transistors T7 in each pixel circuit in the same row are all located on the same second sub-line LS41, and the gates of the eighth transistors T8 in each pixel circuit in the same row are all located on the same first sub-line LS31.

[0112] Further, the third scanning line LS3 may also include a third sub-line LS32 located on the second conductive layer M2, the orthographic projection of the first sub-line LS31 on the substrate 200 and the orthographic projection of the third sub-line LS32 on the substrate 200 at least partially overlap, and the first sub-line LS31 is electrically connected to the third sub-line LS32. Among them, the orthographic projection of the channel region of the seventh transistor T7 on the third sub-line LS32 can be used as the bottom gate of the seventh transistor T7, and the gate of the seventh transistor T7 located on the first sub-line LS31 can be used as the top gate of the seventh transistor T7, so that a seventh transistor T7 with a double-gate structure can be formed, and the top gate and the bottom gate of the seventh transistor T7 are connected to the same signal. In this way, during the driving process, current can flow through the upper and lower surfaces of the channel of the seventh transistor T7, thereby increasing the driving current, which is conducive to quickly realizing the on-off control of the seventh transistor T7, and the use of a double-gate structure can effectively reduce the size of the transistor compared to a single-gate structure.

[0113] The fourth scanning line LS4 may further include a fourth sub-line LS42 located on the second conductive layer M2, the orthographic projection of the second sub-line LS41 on the substrate 200 overlaps at least partially with the orthographic projection of the fourth sub-line LS42 on the substrate 200, and the second sub-line LS41 is electrically connected to the fourth sub-line LS42. Among them, the orthographic projection of the channel region of the eighth transistor T8 on the fourth sub-line LS42 can be used as the bottom gate of the eighth transistor T8, and the gate of the eighth transistor T8 located on the second sub-line LS41 can be used as the top gate of the eighth transistor T8, so that the eighth transistor T8 with a double-gate structure can be formed, and the top gate and the bottom gate of the eighth transistor T8 are connected to the same signal. Such a setting is conducive to quickly realizing the on-off control of the eighth transistor T8, and the use of a double-gate structure can effectively reduce the size of the transistor compared to a single-gate structure.

[0114] On the basis of the above embodiments, optionally, for the same row of pixel circuits, the second initialization signal line LREF2, the third scan line LS3, the first scan line LS1, the fourth scan line LS4, the first gate structure G1, the light emitting control signal line LEM, the second scan line LS2 and the first initialization signal line LREF1 are arranged in sequence along the second direction Y, for example, from top to bottom.

[0115] On this basis, in order to save layout space, the orthographic projection of the third scan line LS3 in the pixel circuit of this row on the substrate 200 can be set to overlap with the orthographic projection of the first initialization signal line LREF1' in the pixel circuit of the previous row on the substrate 200. And / or, the orthographic projection of the second scan line LS2 in the pixel circuit of this row on the substrate 200 can be set to overlap with the orthographic projection of the second initialization signal line LREF2' in the pixel circuit of the next row on the substrate 200.

[0116] Fig.11 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention. Fig.11 , based on the above embodiments, optionally, the plurality of first type switch transistors further include: a ninth transistor T9. Fig.12 is a schematic diagram of a layout structure of another display panel provided by an embodiment of the present invention; Fig.13 FIG. 1 is a schematic diagram of a layout structure of another display panel provided by an embodiment of the present invention. Figure 11-13 The gate of the ninth transistor T9 is located on the second scanning line LS2 and is connected to the second scanning signal SP2; the first electrode of the ninth transistor T9 is connected to the third initialization signal line LREF3 and is connected to the third initialization signal Vrefp; the second electrode of the ninth transistor T9 is connected to the second electrode of the fourth transistor T4 through the sixth connecting line L6.

[0117] The third initialization signal line LREF3 and the sixth connection line L6 are both located in the third conductive layer M3. The third initialization signal line LREF3 extends along the first direction X. Exemplarily, for the same row of pixel circuits, the orthographic projection of the third initialization signal line LREF3 on the substrate 200 overlaps with the orthographic projection of the second scanning line LS2 on the substrate 200. By setting signal lines of different layers to overlap, the layout size can be saved.

[0118] Exemplarily, the gates of the ninth transistors T9 in each pixel circuit in the same row are all located on the same second scan line LS2; the first electrodes of the ninth transistors T9 in each pixel circuit in the same row are all connected to the same third initialization signal line LREF3.

[0119] It should be noted that the extension direction of each signal line mentioned in the embodiment of the present invention is the overall extension direction of the signal line on the display panel. When it is refined to the structure in a pixel circuit, in order to avoid the wiring positions of each signal line and related structures, the signal line may have some bending and step areas.

[0120] It should also be noted that the drawings of the embodiments of the present invention provide the general morphology of the wiring of each film layer, but this is not intended to limit the present invention. In particular, for the locations where there are right angles in the wiring of each film layer, due to the influence of the optical proximity effect, the shape of the mask can be appropriately adjusted during the patterning process, such as removing a pattern or adding a pattern, so that the wiring pattern finally formed in the display panel after considering the optical proximity effect can present a right angle.

[0121] On the basis of the above embodiments, optionally, the display panel also includes an anode layer, a light-emitting material layer and a cathode layer stacked on a side of the fourth conductive layer M4 away from the substrate 200; the anode layer includes an anode of each light-emitting device OLED, which is connected to the second electrode of the fifth transistor T5 in the corresponding pixel circuit; the light-emitting material layer includes a light-emitting layer of each light-emitting device OLED, and the cathode layer includes a cathode of each light-emitting device OLED, and each cathode is connected to a second power line and connected to a second power signal VSS.

[0122] Based on the above embodiments, optionally, see Figure 8 A first gate insulating layer 31 may be provided between the first active layer PSI and the first conductive layer M1, a capacitor insulating layer 32 may be provided between the first conductive layer M1 and the second conductive layer M2, a second gate insulating layer 33 may be provided between the second conductive layer M2 and the second active layer IGZO, a third gate insulating layer 34 may be provided between the second active layer IGZO and the fifth conductive layer GATO, a first interlayer insulating layer 35 may be provided between the fifth conductive layer GATO and the third conductive layer M3, a second interlayer insulating layer 36 may be provided between the third conductive layer M3 and the fourth conductive layer M4, and a planarizing layer 37 may be provided between the fourth conductive layer M4 and the anode layer. Among them, each insulating layer may be provided to include inorganic materials and / or organic materials according to requirements, and any of the above insulating layers may be a single-layer structure or a stacked structure consisting of multiple sub-insulating layers.

[0123] Figure 8 and Fig. 9 The various types of vias required in the pixel circuit are also shown. Figure 8 and Fig. 9 On the basis of the above embodiments, optionally, the first active layer PSI is connected to the third conductive layer M3 through a first type via K11, the first conductive layer M1 is connected to the third conductive layer M3 through a second type via K12, the second conductive layer M2 is connected to the third conductive layer M3 through a third type via K13, the second active layer IGZO is connected to the third conductive layer M3 through a fourth type via K21, and the fifth conductive layer GATO is connected to the third conductive layer M3 through a fifth type via K22.

[0124] For example, the first type via K11, the second type via K12 and the third type via K13 can be prepared in the same mask process. Fig. 9 The fourth type via K21 and the fifth type via K22 can be prepared in the same mask process. For details, please refer to Fig. 9 The red vias in the middle.

[0125] The embodiment of the present invention further provides a display device, including the display panel provided by any embodiment of the present invention, having corresponding beneficial effects. Exemplarily, the display device can be a mobile phone, a television, a laptop computer, a desktop computer, etc.

[0126] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0127] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: substrate; A first active layer and a plurality of conductive layers are stacked on one side of the substrate; wherein the first active layer and the plurality of conductive layers are used to form a plurality of pixel units, and the pixel units include two pixel circuits that are mirror-symmetrical along a first direction; The pixel circuit includes: a driving transistor and at least one auxiliary transistor; the first active layer includes a plurality of first active areas belonging to each of the pixel circuits, the first active area includes a first active portion and a second active portion arranged along a first direction, the first active portion includes a channel region of the driving transistor, and the second active portion includes a channel region of the auxiliary transistor; in the same pixel unit, two of the second active portions are adjacent and spaced apart; The multiple conductive layers include: a first conductive layer, which is arranged on a side of the first active layer away from the substrate; the first conductive layer includes multiple first gate structures belonging to each pixel circuit; the orthographic projection of each first gate structure on the substrate respectively covers the orthographic projection of each first active area on the substrate; wherein the spacing between two first gate structures in the same pixel unit in the first direction is greater than or equal to 1.5 microns.

2. The display panel according to claim 1, characterized in that: The orthographic projection area of ​​the first gate structure on the substrate is larger than the orthographic projection area of ​​the first active region on the substrate; Preferably, an outer contour of an orthographic projection of the first gate structure on the substrate surrounds an outer contour of an orthographic projection of the first active region on the substrate; The outer contour of the positive projection of the first gate structure on the substrate includes: a first edge extending along the second direction and close to the center line of the pixel unit where the first gate structure is located; the outer contour of the positive projection of the first active area on the substrate includes: a second edge extending along the second direction and close to the center line of the pixel unit where the first active area is located; wherein the second direction is perpendicular to the first direction; the center line extends along the second direction, and the two pixel circuits in the pixel unit are mirror-symmetric along the center line; the spacing between the first edge and the second edge in the same pixel circuit is greater than or equal to 1 micron.

3. The display panel according to claim 1, characterized in that: In the first active area, the channel region of the driving transistor is connected to the channel regions of the auxiliary transistors; Preferably, the first active portion includes a first rectangular area, a C-shaped area and a second rectangular area sequentially connected along the first direction; the second active portion is connected to a side of the second rectangular area away from the C-shaped area; Preferably, a channel width of the driving transistor is greater than or equal to a channel width of the auxiliary transistor.

4. The display panel according to claim 3, characterized in that: The pixel circuit includes two auxiliary transistors, namely a first transistor and a second transistor; the second active portion includes a channel region of the first transistor and a channel region of the second transistor arranged along the second direction; Preferably, the channel width of the first transistor is equal to the channel width of the second transistor, and the channel length of the first transistor is equal to the channel length of the second transistor; Preferably, in the second active portion, the channel region of the first transistor is connected to the channel region of the second transistor; Preferably, in the second active portion, the channel region of the first transistor partially overlaps with the channel region of the second transistor; Preferably, the second active portion is rectangular; An extension line of a first symmetry axis extending along the first direction in the second rectangular area overlaps with a second symmetry axis extending along the first direction in the second active portion; in the second active portion, a channel region of the first transistor and a channel region of the second transistor are symmetrical along the second symmetry axis; Preferably, the width of the second active portion along the first direction is greater than or equal to 2 micrometers; A length of the second active portion along the second direction is greater than a width of the second active portion along the first direction.

5. The display panel according to any one of claims 1 to 4, characterized in that: The pixel circuit further includes a storage capacitor; the plurality of conductive layers further include: a second conductive layer, disposed on a side of the first conductive layer away from the substrate; Wherein, the first gate structure is reused as the first electrode of the storage capacitor; the second electrode of the storage capacitor is arranged on the second conductive layer; in the same storage capacitor, the orthographic projection of the first electrode on the substrate and the orthographic projection of the second electrode on the substrate at least partially overlap; Preferably, in the same pixel unit, the second electrodes of two storage capacitors are connected.

6. The display panel according to claim 5, characterized in that: The pixel circuit includes two auxiliary transistors, which are a first transistor and a second transistor; the channel region of the driving transistor is connected to the channel region of the first transistor and the channel region of the second transistor respectively; the second electrode of the driving transistor is located in the first active layer and connected to a side of the first active portion away from the second active portion; the first electrode of the first transistor is located in the first active layer and connected to the channel region of the first transistor; the first electrode of the second transistor is located in the first active layer and connected to the channel region of the second transistor; The pixel circuit further includes: a plurality of first-type switch transistors, wherein a first electrode, a channel region, and a second electrode of the first-type switch transistors are connected in sequence and are all located on the first active layer; a gate of the first-type switch transistor is located on the first conductive layer, and an orthographic projection of the gate of the first-type switch transistor on the substrate at least partially overlaps with an orthographic projection of the channel region of the first-type switch transistor on the substrate; Preferably, the plurality of first-type switch transistors include: a third transistor, a fourth transistor, a fifth transistor and a sixth transistor; the first electrode of the third transistor is connected to the data line, the second electrode of the third transistor is connected to the first electrode of the first transistor; the first electrode of the fourth transistor is connected to the second electrode of the storage capacitor through the first connecting line, the second electrode of the storage capacitor is connected to the first power line; the second electrode of the fourth transistor is connected to the first electrode of the second transistor; the first electrode of the fifth transistor is connected to the second electrode of the driving transistor, the second electrode of the fifth transistor is connected to the second electrode of the sixth transistor, and the first electrode of the sixth transistor is connected to the first initialization signal line through the second connecting line; The multiple conductive layers further include: a third conductive layer and a fourth conductive layer stacked in sequence on a side of the second conductive layer away from the substrate; the data line and the first power line are both located in the fourth conductive layer; the first initialization signal line, the first connection line and the second connection line are all located in the third conductive layer; the first initialization signal line extends along the first direction; Preferably, each of the pixel units is arranged in an array in the display panel; the first conductive layer further comprises: a plurality of first scan lines, a plurality of second scan lines and a plurality of light emitting control signal lines; each of the first scan lines, each of the second scan lines and each of the light emitting control signal lines extends along the first direction and is arranged along the second direction; the first direction is perpendicular to the second direction; Wherein, the gates of the third transistors in the pixel circuits in the same row are all located on the same first scanning line; the gates of the fourth transistors and the gates of the fifth transistors in the pixel circuits in the same row are all located on the same light emitting control signal line; the gates of the sixth transistors in the pixel circuits in the same row are all located on the same second scanning line; the first electrodes of the sixth transistors in the pixel circuits in the same row are connected to the same first initialization signal line; Preferably, two pixel circuits in the same pixel unit share the same first connecting line.

7. The display panel according to claim 6, characterized in that: The pixel circuit further includes: a plurality of second type switch transistors; the plurality of conductive layers further include a fifth conductive layer disposed between the second conductive layer and the third conductive layer; the display panel further includes a second active layer disposed between the second conductive layer and the fifth conductive layer; The first electrode, the channel region, and the second electrode of the second type switch transistor are connected in sequence and are all located in the second active layer; the gate of the second type switch transistor is located in the fifth conductive layer, and the orthographic projection of the gate of the second type switch transistor on the substrate at least partially overlaps with the orthographic projection of the channel region of the second type switch transistor on the substrate; Preferably, the plurality of second-type switch transistors include: a seventh transistor and an eighth transistor; the first electrode of the seventh transistor is connected to the second electrode of the driving transistor through a third connecting line, and the second electrode of the seventh transistor is connected to the first gate structure through a fourth connecting line; the second electrode of the seventh transistor is multiplexed as the second electrode of the eighth transistor, and the first electrode of the eighth transistor is connected to the second initialization signal line through a fifth connecting line; The third connection line, the fourth connection line and the fifth connection line are all located in the third conductive layer; the second initialization signal line is located in the fifth conductive layer, and the second initialization signal line extends along the first direction; The display panel further includes: a plurality of third scan lines and a plurality of fourth scan lines; each of the third scan lines and each of the fourth scan lines extends along the first direction; The third scan line includes a first sub-line located in the fifth conductive layer; the fourth scan line includes a second sub-line located in the fifth conductive layer; the gates of the seventh transistors in the pixel circuits in the same row are all located on the same second sub-line, and the gates of the eighth transistors in the pixel circuits in the same row are all located on the same first sub-line; Preferably, the third scanning line further comprises a third sub-line located in the second conductive layer, an orthographic projection of the first sub-line on the substrate at least partially overlaps with an orthographic projection of the third sub-line on the substrate, and the first sub-line is electrically connected to the third sub-line; And / or, the fourth scan line also includes a fourth sub-line located in the second conductive layer, the orthographic projection of the second sub-line on the substrate at least partially overlaps with the orthographic projection of the fourth sub-line on the substrate, and the second sub-line is electrically connected to the fourth sub-line.

8. The display panel according to claim 7, characterized in that: In the pixel circuits of the same row, the second initialization signal line, the third scan line, the first scan line, the fourth scan line, the first gate structure, the light emitting control signal line, the second scan line and the first initialization signal line are arranged in sequence along the second direction; Preferably, an orthographic projection of the third scanning line in the pixel circuits in this row on the substrate overlaps with an orthographic projection of the first initialization signal line in the pixel circuits in the previous row on the substrate; And / or, the orthographic projection of the second scanning line in the pixel circuits in the current row on the substrate overlaps with the orthographic projection of the second initialization signal line in the pixel circuits in the next row on the substrate.

9. The display panel according to claim 6, characterized in that: The plurality of first-type switch transistors further include: a ninth transistor; the gate of the ninth transistor is located on the second scan line; the first electrode of the ninth transistor is connected to the third initialization signal line, and the second electrode of the ninth transistor is connected to the second electrode of the fourth transistor through a sixth connection line; Wherein, the third initialization signal line and the sixth connection line are both located in the third conductive layer; the third initialization signal line extends along the first direction; Preferably, the gates of the ninth transistors in the pixel circuits in the same row are all located on the same second scanning line; the first electrodes of the ninth transistors in the pixel circuits in the same row are all connected to the same third initialization signal line; Preferably, in the same row of pixel circuits, an orthographic projection of the third initialization signal line on the substrate overlaps with an orthographic projection of the second scanning line on the substrate.

10. A display device, characterized in that: include: The display panel according to any one of claims 1 to 9.

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