Display device and mother substrate

Abstract

The invention provides a display device and a mother substrate. A display device includes: a substrate; an organic insulating layer disposed within the entire range of a display region in which an image is displayed and a peripheral region outside the display region; a lower electrode disposed on the organic insulating layer in the display region; an inorganic insulating layer disposed on the organic insulating layer and covering a peripheral portion of the lower electrode; an organic layer disposed on the lower electrode and including a light emitting layer; an upper electrode disposed on the organic layer; and a plurality of peripheral partition walls disposed in the peripheral region, each of the plurality of peripheral partition walls having: a first lower portion located on the inorganic insulating layer; and a first upper portion located on the first lower portion and protruding from a side surface of the first lower portion, the organic insulating layer has a missing portion along an outer edge of the substrate in the peripheral region, the inorganic insulating layer has an annular groove surrounding the display region in the peripheral region, and the plurality of peripheral partition walls include a pair of first partition walls facing each other across the groove.

Description

[0001] Cross-references of related applications

[0002] This application claims priority based on Japanese Patent Application No. 2023-179398 filed on October 18, 2023, and cites all the contents described in the Japanese Patent Application. Technical Field

[0003] Embodiments of the present invention relate to a display device and a mother substrate. Background Art

[0004] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put into practical use. The display element includes a pixel circuit including a thin film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. In addition to the light-emitting layer, the organic layer also includes functional layers such as a hole transport layer and an electron transport layer.

[0005] In the process of manufacturing such display elements, a technology to suppress the reduction of reliability is required. Summary of the invention

[0006] An object of the embodiment is to provide a display device and a mother substrate capable of suppressing a decrease in reliability.

[0007] According to one embodiment, a display device comprises: a substrate; an organic insulating layer, which is arranged above the substrate in the entire range of a display area displaying an image and a peripheral area outside the display area; a lower electrode, which is arranged on the organic insulating layer in the display area; an inorganic insulating layer, which is arranged on the organic insulating layer and covers the peripheral portion of the lower electrode; an organic layer, which is arranged on the lower electrode and includes a light-emitting layer; an upper electrode, which is arranged on the organic layer; and a plurality of peripheral partition walls, which are arranged in the peripheral area, each of the plurality of peripheral partition walls having: a first lower portion located on the inorganic insulating layer; and a first upper portion located on the first lower portion and protruding from the side of the first lower portion, the organic insulating layer having a missing portion along the outer edge of the substrate in the peripheral area, the inorganic insulating layer having an annular groove surrounding the display area in the peripheral area, and the plurality of peripheral partition walls including a pair of first partition walls opposite to each other with the groove separated therefrom.

[0008] According to one embodiment, a display device comprises: a substrate; an organic insulating layer, which is arranged above the substrate in the entire range of a display area for displaying an image and a peripheral area outside the display area; a lower electrode, which is arranged on the organic insulating layer in the display area; an inorganic insulating layer, which is arranged on the organic insulating layer and covers the peripheral portion of the lower electrode; an organic layer, which is arranged on the lower electrode and includes a light-emitting layer; an upper electrode, which is arranged on the organic layer; and a plurality of peripheral partition walls, which are arranged in the peripheral area, each of the plurality of peripheral partition walls having: a first lower portion; and a first upper portion located above the first lower portion and protruding from the side of the first lower portion, the organic insulating layer having a missing portion along the outer edge of the substrate in the peripheral area, the plurality of peripheral partition walls including a second partition wall arranged in the missing portion, the second partition wall being arranged along a corner portion in the outer edge of the organic insulating layer and forming an L shape when viewed from above.

[0009] According to one embodiment, a display device comprises: a substrate; an organic insulating layer, which is arranged above the substrate in the entire range of a display area for displaying an image and a peripheral area outside the display area; a lower electrode, which is arranged on the organic insulating layer in the display area; an inorganic insulating layer, which is arranged on the organic insulating layer and covers the peripheral portion of the lower electrode; an organic layer, which is arranged on the lower electrode and includes a light-emitting layer; an upper electrode, which is arranged on the organic layer; and a plurality of peripheral partition walls, which are arranged in the peripheral area, each of the plurality of peripheral partition walls having: a first lower portion; and a first upper portion located above the first lower portion and protruding from the side of the first lower portion, the organic insulating layer having a missing portion along the outer edge of the substrate in the peripheral area, the outer edge of the organic insulating layer including a rounded corner portion, and the radius of curvature of the rounded corner portion is greater than or equal to the width of the missing portion.

[0010] According to one embodiment, a mother substrate comprises: a panel portion having a display area for displaying an image and a peripheral area on the outside of the display area; a blank portion on the outside of the panel portion; an organic insulating layer arranged over the entire range of the panel portion and the blank portion; a lower electrode arranged on the organic insulating layer in the display area; an inorganic insulating layer arranged on the organic insulating layer and covering the peripheral portion of the lower electrode; an organic layer arranged on the lower electrode and including a light-emitting layer; an upper electrode arranged on the organic layer; and a plurality of peripheral partition walls arranged in the peripheral area, each of the plurality of peripheral partition walls comprising: a first lower portion located on the inorganic insulating layer; and a first upper portion located on the first lower portion and protruding from the side of the first lower portion, the inorganic insulating layer having a first annular groove surrounding the display area in the peripheral area, and the plurality of peripheral partition walls comprising a pair of first partition walls opposite to each other across the first groove.

[0011] According to one embodiment, a mother substrate comprises: a panel portion having a display area for displaying an image and a peripheral area on the outside of the display area; a blank portion on the outside of the panel portion; an organic insulating layer arranged over the entire range of the panel portion and the blank portion; a lower electrode arranged on the organic insulating layer in the display area; an inorganic insulating layer arranged on the organic insulating layer and covering the peripheral portion of the lower electrode; an organic layer arranged on the lower electrode and including a light-emitting layer; an upper electrode arranged on the organic layer; and a plurality of peripheral partition walls arranged in the peripheral area, each of the plurality of peripheral partition walls comprising: a first lower portion located on the inorganic insulating layer; and a first upper portion located on the first lower portion and protruding from the side of the first lower portion, the organic insulating layer having a missing portion along the outer shape of the panel portion, the plurality of peripheral partition walls including a second partition wall arranged in the missing portion, the second partition wall being arranged along a corner portion of the outer edge of the organic insulating layer and forming an L-shape in a plan view.

[0012] According to one embodiment, a mother substrate comprises: a panel portion having a display area for displaying an image and a peripheral area on the outside of the display area; a blank portion on the outside of the panel portion; an organic insulating layer arranged over the entire range of the panel portion and the blank portion; a lower electrode arranged on the organic insulating layer in the display area; an inorganic insulating layer arranged on the organic insulating layer and covering the peripheral portion of the lower electrode; an organic layer arranged on the lower electrode and including a light-emitting layer; an upper electrode arranged on the organic layer; and a plurality of peripheral partition walls arranged in the peripheral area, each of the plurality of peripheral partition walls comprising: a first lower portion located on the inorganic insulating layer; and a first upper portion located on the first lower portion and protruding from the side of the first lower portion, the organic insulating layer having a missing portion along the outer shape of the panel portion, the outer edge of the organic insulating layer including a rounded corner portion, the radius of curvature of the rounded corner portion being greater than or equal to 1 / 2 of the width of the missing portion.

[0013] According to the embodiment, a display device and a mother substrate capable of suppressing a decrease in reliability can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a diagram showing a configuration example of a DSP of a display device.

[0015] Figure 2 It is a diagram showing an example of the layout of sub-pixels SP1 , SP2 , and SP3 .

[0016] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display device DSP taken along line AB in FIG.

[0017] Figure 4 It is a diagram for explaining a method of manufacturing the display device DSP.

[0018] Figure 5 It is a diagram for explaining a method of manufacturing the display device DSP.

[0019] Figure 6 It is a diagram for explaining a method of manufacturing the display device DSP.

[0020] Figure 7 It is a diagram for explaining a method of manufacturing the display device DSP.

[0021] Figure 8 It is a diagram for explaining a method of manufacturing the display device DSP.

[0022] Fig. 9 It is a diagram for explaining a method of manufacturing the display device DSP.

[0023] Fig.101 is a plan view showing an example of the mother substrate 100 .

[0024] Fig.11 Yes means Fig.10 FIG. 1 is a top view of a structural example of a region 100A of a mother substrate 100 shown in FIG.

[0025] Fig.12 Yes means Fig.11 A top view of an example structure of region 100B is shown.

[0026] Fig.13 It means in Fig.12 FIG. 1 is a top view of the display panel PNL after being cut at the cutting line CL.

[0027] Fig.14 1 is a cross-sectional view showing a structural example of the mother substrate 100 .

[0028] Fig.15 2 is a cross-sectional view showing another structural example of the mother substrate 100 .

[0029] Fig.16 2 is a cross-sectional view showing another structural example of the mother substrate 100 .

[0030] Fig.17 It is a cross-sectional view which enlarges the region including the groove 5G.

[0031] Fig.18 It is used to illustrate Fig.14 The illustrated cross-sectional view is a state where the laminated film FL1 is formed in the region including the missing portion G.

[0032] Fig.19 It is used to illustrate Fig.17 The illustrated cross-sectional view is a state where the laminated film FL1 is formed in the region including the groove 5G.

[0033] Fig. 20 Yes means Fig.11 FIG. 1 is a top view of another configuration example of region 100B shown.

[0034] Fig.21 It means in Fig. 20 FIG. 1 is a top view of the display panel PNL after being cut at the cutting line CL.

[0035] Fig. 22 1 is a cross-sectional view showing a structural example of the mother substrate 100 .

[0036] Fig.23 2 is a cross-sectional view showing another structural example of the mother substrate 100 .

[0037] Fig.24 2 is a cross-sectional view showing another structural example of the mother substrate 100 .

[0038] Fig.25 This is a diagram for explaining a problem that may occur when the peripheral partition wall 9A is not provided.

[0039] Fig.26 Yes means Fig.10 FIG. 1 is a plan view of another structural example of the region 100A of the mother substrate 100 shown.

[0040] Fig. 27 Yes means Fig.26 A top view of an example structure of region 100B is shown.

[0041] Fig.28 It means in Fig. 27 FIG. 1 is a top view of the display panel PNL after being cut at the cutting line CL. DETAILED DESCRIPTION

[0042] Please refer to the attached Figure 1 The implementation method is described below.

[0043] The disclosed content is only an example, and appropriate changes that can be easily thought of by those skilled in the art while maintaining the main idea of ​​the invention are of course included in the scope of the present invention. In addition, in order to make the description clearer, there are cases where the width, thickness, shape, etc. of each part are schematically shown in the drawings compared with the actual state, but this is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, the same figure mark is sometimes used to mark the structural elements that perform the same or similar functions as the structural elements described in the figures that have appeared, and repeated detailed descriptions are appropriately omitted.

[0044] In addition, in the drawings, mutually orthogonal X-axis, Y-axis, and Z-axis are described as needed for easy understanding. The direction along the X-axis is called the first direction X, the direction along the Y-axis is called the second direction Y, and the direction along the Z-axis is called the third direction Z. Viewing various elements parallel to the third direction Z is called a top view.

[0045] The display device of this embodiment is an organic electroluminescent display device including an organic light emitting diode (OLED) as a display element, and can be mounted on a television, a personal computer, an in-vehicle device, a tablet terminal, a smartphone, a mobile phone terminal, and the like.

[0046] Figure 1 It is a diagram showing a configuration example of a DSP of a display device.

[0047] The display device DSP includes a display panel PNL having a display area DA for displaying an image and a peripheral area SA located outside the display area DA on an insulating substrate 10. The substrate 10 may be glass or a flexible resin film.

[0048] In the present embodiment, the shape of the substrate 10 in a plan view is a rectangle, but the shape of the substrate 10 in a plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0049] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. The pixel PX includes a plurality of sub-pixels SP. In one example, the pixel PX includes a sub-pixel SP1 of a first color, a sub-pixel SP2 of a second color, and a sub-pixel SP3 of a third color. The first color, the second color, and the third color are different colors from each other. In addition, the pixel PX may include a sub-pixel SP of another color such as white in addition to or instead of any of the sub-pixels SP1, SP2, and SP3.

[0050] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements formed of, for example, thin film transistors.

[0051] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and the drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the driving transistor 3 and the capacitor 4. In the driving transistor 3, one of the source electrode and the drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element DE.

[0052] In addition, the structure of the pixel circuit 1 is not limited to the example shown in the figure. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0053] The display element DE is an organic light emitting diode (OLED) which is a light emitting element, and is sometimes called an organic EL element.

[0054] The peripheral area SA has a plurality of terminals TE arranged in one direction. In the example shown in the figure, the plurality of terminals TE are arranged along the first direction X. Each of the terminals TE extends along the second direction Y, but is not limited thereto. For example, a portion of the plurality of terminals TE may also extend in an oblique direction. Such a plurality of terminals TE are electrically connected to, for example, a flexible printed circuit substrate or an IC chip.

[0055] Figure 2 It is a diagram showing an example of the layout of sub-pixels SP1 , SP2 , and SP3 .

[0056] In the example shown in the figure, the sub-pixel SP2 and the sub-pixel SP3 are arranged in the second direction Y. The sub-pixel SP1 and the sub-pixel SP2 are arranged in the first direction X, and the sub-pixel SP1 and the sub-pixel SP3 are arranged in the first direction X.

[0057] When the sub-pixels SP1, SP2, and SP3 are arranged in this way, columns in which the sub-pixels SP2 and SP3 are alternately arranged in the second direction Y and columns in which a plurality of sub-pixels SP1 are arranged in the second direction Y are formed in the display area DA. These columns are alternately arranged in the first direction X.

[0058] In addition, the layout of the sub-pixels SP1, SP2, and SP3 is not limited to Figure 2 As another example, the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged in sequence in the first direction X.

[0059] The inorganic insulating layer 5 and the partition wall 6 are arranged in the display area DA. The inorganic insulating layer 5 has openings AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. The inorganic insulating layer 5 having these openings AP1, AP2, and AP3 is sometimes also called a rib.

[0060] The partition wall 6 overlaps with the inorganic insulating layer 5 in a plan view. The partition wall 6 is formed in a lattice shape surrounding the openings AP1, AP2, and AP3. The partition wall 6 can also have openings in the sub-pixels SP1, SP2, and SP3 similarly to the inorganic insulating layer 5. The partition wall 6 is conductive and Figure 1 Among the plurality of terminals TE shown, terminals TE having a common potential are electrically connected.

[0061] The sub-pixels SP1 , SP2 , and SP3 include display elements DE1 , DE2 , and DE3 , respectively, as the display elements DE.

[0062] The display element DE1 of the sub-pixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with the opening AP1 respectively. The peripheral portion of the lower electrode LE1 is covered by the inorganic insulating layer 5. The lower electrode LE1, the organic layer OR1, and the upper electrode UE1 are surrounded by a partition wall 6 in a plan view. The peripheral portions of the organic layer OR1 and the upper electrode UE1 overlap with the inorganic insulating layer 5 in a plan view. The organic layer OR1 includes a light-emitting layer that emits light in a blue wavelength range, for example.

[0063] The display element DE2 of the sub-pixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with the opening AP2, respectively. The peripheral portion of the lower electrode LE2 is covered by the inorganic insulating layer 5. The lower electrode LE2, the organic layer OR2, and the upper electrode UE2 are surrounded by a partition wall 6 in a plan view. The peripheral portions of the organic layer OR2 and the upper electrode UE2 overlap with the inorganic insulating layer 5 in a plan view. The organic layer OR2 includes a light-emitting layer that emits light in, for example, a green wavelength range.

[0064] The display element DE3 of the sub-pixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with the opening AP3 respectively. The peripheral portion of the lower electrode LE3 is covered by the inorganic insulating layer 5. The lower electrode LE3, the organic layer OR3, and the upper electrode UE3 are surrounded by a partition wall 6 in a plan view. The peripheral portions of the organic layer OR3 and the upper electrode UE3 overlap with the inorganic insulating layer 5 in a plan view. The organic layer OR3 includes a light-emitting layer that emits light in, for example, a red wavelength range.

[0065] In the example shown in the figure, the outer shapes of the lower electrodes LE1, LE2, LE3 are shown with dotted lines, and the outer shapes of the organic layers OR1, OR2, OR3 and the upper electrodes UE1, UE2, UE3 are shown with dashed lines.

[0066] The lower electrodes LE1 , LE2 , and LE3 correspond to, for example, anodes of the display element, and the upper electrodes UE1 , UE2 , and UE3 correspond to cathodes or common electrodes of the display element and are in contact with the partition wall 6 .

[0067] The lower electrode LE1 and the pixel circuit 1 of the sub-pixel SP1 (refer to Figure 1 The lower electrode LE2 is electrically connected to the pixel circuit 1 of the sub-pixel SP2. The lower electrode LE3 is electrically connected to the pixel circuit 1 of the sub-pixel SP3.

[0068] In the example shown in the figure, the area of ​​the opening AP1, the area of ​​the opening AP2, and the area of ​​the opening AP3 are different from each other. The area of ​​the opening AP1 is larger than the area of ​​the opening AP2, and the area of ​​the opening AP2 is larger than the area of ​​the opening AP3. In other words, the area of ​​the lower electrode LE1 exposed from the opening AP1 is larger than the area of ​​the lower electrode LE2 exposed from the opening AP2, and the area of ​​the lower electrode LE2 exposed from the opening AP2 is larger than the area of ​​the lower electrode LE3 exposed from the opening AP3.

[0069] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display device DSP taken along line AB in FIG.

[0070] The circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes Figure 1The circuit layer 11 is covered with an insulating layer 12 , which is an organic insulating layer that flattens the unevenness generated by the circuit layer 11 .

[0071] The lower electrodes LE1, LE2, and LE3 are arranged on the insulating layer 12 and are separated from each other. The inorganic insulating layer 5 is arranged on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The opening AP1 of the inorganic insulating layer 5 overlaps with the lower electrode LE1, the opening AP2 overlaps with the lower electrode LE2, and the opening AP3 overlaps with the lower electrode LE3. The peripheral portions of the lower electrodes LE1, LE2, and LE3 are covered by the inorganic insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3 through contact holes provided in the insulating layer 12. In addition, the contact holes of the insulating layer 12 are provided at Figure 3 Omitted in .

[0072] The partition wall 6 includes a conductive lower portion 61 disposed on the inorganic insulating layer 5, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a greater width than the lower portion 61. Both ends of the upper portion 62 protrude from the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called an overhang shape.

[0073] In the example shown in the figure, the lower portion 61 includes a first conductive layer 63 disposed on the inorganic insulating layer 5, and a second conductive layer 64 disposed on the first conductive layer 63. For example, the first conductive layer 63 is formed thinner than the second conductive layer 64. In addition, in the example shown in the figure, both ends of the first conductive layer 63 protrude from the side surfaces of the second conductive layer 64.

[0074] The upper portion 62 includes a first thin film 65 disposed on the second conductive layer 64 and a second thin film 66 disposed on the first thin film 65. Both ends of the first thin film 65 and the second thin film 66 protrude from the side surface of the second conductive layer 64.

[0075] The organic layer OR1 contacts the lower electrode LE1 through the opening AP1 , covers the lower electrode LE1 exposed from the opening AP1 , and has its peripheral portion located on the inorganic insulating layer 5 . The upper electrode UE1 covers the organic layer OR1 and contacts the lower portion 61 .

[0076] The organic layer OR2 contacts the lower electrode LE2 through the opening AP2 , covers the lower electrode LE2 exposed from the opening AP2 , and has its peripheral portion located on the inorganic insulating layer 5 . The upper electrode UE2 covers the organic layer OR2 and contacts the lower portion 61 .

[0077] The organic layer OR3 contacts the lower electrode LE3 through the opening AP3 , covers the lower electrode LE3 exposed from the opening AP3 , and its peripheral portion is located on the inorganic insulating layer 5 . The upper electrode UE3 covers the organic layer OR3 and contacts the lower portion 61 .

[0078] In the example shown in the figure, the sub-pixel SP1 has a cover layer CP1 and a sealing layer SE1, the sub-pixel SP2 has a cover layer CP2 and a sealing layer SE2, and the sub-pixel SP3 has a cover layer CP3 and a sealing layer SE3. The cover layers CP1, CP2, and CP3 respectively function as optical adjustment layers to improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3. In addition, the cover layers CP1, CP2, and CP3 may also be omitted.

[0079] The cover layer CP1 is disposed on the upper electrode UE1.

[0080] The cover layer CP2 is disposed on the upper electrode UE2.

[0081] The cover layer CP3 is disposed on the upper electrode UE3.

[0082] The sealing layer SE1 is disposed on the cover layer CP1 , is in contact with the partition wall 6 , and continuously covers each component of the sub-pixel SP1 .

[0083] The sealing layer SE2 is disposed on the cover layer CP2 , is in contact with the partition wall 6 , and continuously covers each component of the sub-pixel SP2 .

[0084] The sealing layer SE3 is disposed on the cover layer CP3 , is in contact with the partition wall 6 , and continuously covers each component of the sub-pixel SP3 .

[0085] In the example shown in the figure, a portion of each of the organic layer OR1, the upper electrode UE1 and the cover layer CP1 is located on the partition wall 6 around the sub-pixel SP1. These portions are separated from the portions of the organic layer OR1, the upper electrode UE1 and the cover layer CP1 located at the opening AP1 (the portions constituting the display element DE1).

[0086] Similarly, portions of the organic layer OR2, the upper electrode UE2 and the covering layer CP2 are each located on the partition wall 6 around the subpixel SP2, and these portions are separated from portions of the organic layer OR2, the upper electrode UE2 and the covering layer CP2 located in the opening AP2 (the portions constituting the display element DE2).

[0087] Similarly, portions of the organic layer OR3, the upper electrode UE3 and the covering layer CP3 are located on the partition wall 6 around the subpixel SP3, and these portions are separated from portions of the organic layer OR3, the upper electrode UE3 and the covering layer CP3 located in the opening AP3 (portions constituting the display element DE3).

[0088] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1 and the covering layer CP1 is referred to as the stacked film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2 and the covering layer CP2 is referred to as the stacked film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3 and the covering layer CP3 is referred to as the stacked film FL3.

[0089] The ends of the sealing layers SE1, SE2, and SE3 and the ends of the laminated films FL1, FL2, and FL3 are respectively located on the partition wall 6. In the example shown in the figure, the laminated film FL1 and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP2 are separated from the laminated film FL2 and the sealing layer SE2 on the partition wall 6. In addition, the laminated film FL1 and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP3 are separated from the laminated film FL3 and the sealing layer SE3 on the partition wall 6.

[0090] The partition wall 6 and the sealing layers SE1, SE2, and SE3 are covered with a resin layer 13. The resin layer 13 is covered with a sealing layer 14. The sealing layer 14 is covered with a resin layer 15.

[0091] The inorganic insulating layer 5 , the sealing layers SE1 , SE2 , SE3 , and the sealing layer 14 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al 2 O 3 ).

[0092] The lower portion 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The first conductive layer 63 is formed of a titanium-based material such as titanium or a titanium compound. The second conductive layer 64 is formed of a material different from the first conductive layer 63 and the upper portion 62, and is formed of an aluminum-based material such as aluminum or an aluminum compound.

[0093] The upper portion 62 of the partition wall 6 is formed of, for example, a conductive material, but may also be formed of an insulating material. The upper portion 62 is formed of a material different from that of the lower portion 61. The first thin film 65 is formed of a titanium-based material such as titanium or a titanium compound. The second thin film 66 is formed of an oxide conductive material such as indium tin oxide (ITO).

[0094] The lower electrodes LE1, LE2, and LE3 are multilayer bodies including a transparent layer formed of an oxide conductive material such as indium tin oxide (ITO) and a reflective layer formed of a metal material such as silver. In one example, the lower electrodes LE1, LE2, and LE3 are multilayer bodies including a reflective layer between a pair of transparent layers. The lower transparent layer functions as a close contact layer that is in close contact with the insulating layer 12.

[0095] The organic layer OR1 includes a light-emitting layer EM1. The organic layer OR2 includes a light-emitting layer EM2. The organic layer OR3 includes a light-emitting layer EM3. The light-emitting layer EM1, the light-emitting layer EM2, and the light-emitting layer EM3 are formed of different materials. In one example, the light-emitting layer EM1 is formed of a material that emits light in a blue wavelength range, the light-emitting layer EM2 is formed of a material that emits light in a green wavelength range, and the light-emitting layer EM3 is formed of a material that emits light in a red wavelength range.

[0096] In addition, each of the organic layers OR1, OR2, and OR3 includes a plurality of functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0097] The upper electrodes UE1 , UE2 , and UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg).

[0098] The cover layers CP1, CP2, and CP3 are multilayer bodies of a plurality of thin films, all of which are transparent and have different refractive indices.

[0099] The circuit layer 11 , the insulating layer 12 , and the inorganic insulating layer 5 shown in the figure are arranged in the entire range of the display area DA and the peripheral area SA.

[0100] Next, a method for manufacturing the display device DSP will be described. In addition, in each figure for describing the manufacturing method, illustration of a portion below the insulating layer 12 is omitted.

[0101] First, on the substrate 10, a circuit layer 11 and an insulating layer 12 are formed in the entire range of the display area DA and the peripheral area SA, and then, as shown in FIG. Figure 4 As shown, a lower electrode LE1 of the sub-pixel SP1 , a lower electrode LE2 of the sub-pixel SP2 , and a lower electrode LE3 of the sub-pixel SP3 are formed on the insulating layer 12 .

[0102] Thereafter, an inorganic insulating layer 5 is formed to cover the peripheral edge portions of the lower electrodes LE1, LE2, and LE3. The inorganic insulating layer 5 is formed of silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0103] Then, a partition wall 6 having a lower portion 61 located on the inorganic insulating layer 5 and an upper portion 62 located on the lower portion 61 is formed. The first conductive layer 63 of the lower portion 61 and the upper portion 62 protrude from the side surface of the second conductive layer 64 of the lower portion 61. The first conductive layer 63 is formed of a conductive material such as a titanium-based material, and the second conductive layer 64 is formed of a conductive material such as an aluminum-based material.

[0104] It should be noted that the step of forming the openings AP1 , AP2 , and AP3 in the inorganic insulating layer 5 may be performed before forming the partition walls 6 or after forming the partition walls 6 .

[0105] Next, the display element DE1 is formed.

[0106] First, if Figure 5 As shown, a stacked film FL1 including an organic layer OR1, an upper electrode UE1 and a covering layer CP1 is formed. The process of forming the stacked film FL1 includes: a process of forming an organic layer OR1 in contact with the lower electrode LE1 in the opening AP1; a process of forming an upper electrode UE1 covering the organic layer OR1 and in contact with the lower portion 61 of the partition wall 6; and a process of forming a covering layer CP1 located on the upper electrode UE1. In addition, the process of forming the organic layer OR1 includes the process of forming a hole injection layer, a hole transport layer, an electron blocking layer, a light emitting layer, a hole blocking layer, an electron transport layer, an electron injection layer, etc. respectively. The organic layer OR1, the upper electrode UE1 and the covering layer CP1 are respectively formed by vapor deposition using the partition wall 6 as a mask. The stacked film FL1 is divided into a plurality of parts by the protruding partition wall 6. These organic layers OR1, the upper electrode UE1 and the covering layer CP1 are continuously formed while maintaining a vacuum environment.

[0107] Then, an inorganic insulating material is deposited to form a sealing layer SE1 on the laminate film FL1. The sealing layer SE1 is formed by CVD (Chemical Vapor Deposition). The sealing layer SE1 continuously covers the disconnected portions of the laminate film FL1 and the partition wall 6.

[0108] Then, if Figure 6 As shown in FIG. 1 , a resist RS patterned in a predetermined shape is formed on the sealing layer SE1 . The resist RS overlaps the sub-pixel SP1 and a part of the partition wall 6 around it.

[0109] Then, if Figure 7 As shown, etching is performed using the resist RS as a mask, and the sealing layer SE1 and the laminated film FL1 exposed from the resist RS are removed in sequence. In this etching, after the sealing layer SE1 exposed from the resist RS is removed, the cover layer CP1 exposed from the sealing layer SE1 is removed, and after the upper electrode UE1 exposed from the cover layer CP1 is removed, the organic layer OR1 exposed from the upper electrode UE1 is removed. As a result, the lower electrode LE2 of the sub-pixel SP2 and the lower electrode LE3 of the sub-pixel SP3 are exposed.

[0110] Thereafter, the resist RS is removed, thereby forming the display element DE1 in the sub-pixel SP1.

[0111] Then, if Figure 8As shown, the display element DE2 is formed. The order of forming the display element DE2 is the same as the order of forming the display element DE1. That is, an organic layer OR2 including a light-emitting layer EM2, an upper electrode UE2 and a covering layer CP2 are sequentially formed on the lower electrode LE2 to form a laminated film FL2. Thereafter, a sealing layer SE2 is formed on the laminated film FL2. Thereafter, a resist is formed on the sealing layer SE2, and the sealing layer SE2, the covering layer CP2, the upper electrode UE2 and the organic layer OR2 are patterned by etching using the resist as a mask. After the patterning, the resist is removed. Thus, the display element DE2 is formed in the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 is exposed.

[0112] Then, if Fig. 9 As shown, a display element DE3 is formed. The order of forming the display element DE3 is the same as the order of forming the display element DE1. That is, an organic layer OR3 including a light-emitting layer EM3, an upper electrode UE3 and a cover layer CP3 are sequentially formed on the lower electrode LE3 to form a laminated film FL3. Thereafter, a sealing layer SE3 is formed on the laminated film FL3. Thereafter, a resist is formed on the sealing layer SE3, and the sealing layer SE3, the cover layer CP3, the upper electrode UE3 and the organic layer OR3 are patterned by etching using the resist as a mask. After the patterning, the resist is removed. Thus, a display element DE3 is formed in the sub-pixel SP3.

[0113] Afterwards, the Figure 3 The resin layer 13, the sealing layer 14 and the resin layer 15 are shown. Thus, the display device DSP is completed.

[0114] It should be noted that, in the above manufacturing process, it is assumed that the display element DE1 is formed first, the display element DE2 is formed next, and the display element DE3 is formed last, but the order of forming the display elements DE1, DE2, and DE3 is not limited to this example.

[0115] Next, a mother substrate for a display device (hereinafter, simply referred to as a mother substrate) 100 for manufacturing a plurality of display devices DSP at once will be described.

[0116] Fig.10 1 is a plan view showing an example of the mother substrate 100 .

[0117] The mother substrate 100 includes a plurality of panel portions PP and a margin portion MP located outside the panel portions PP on a large substrate 10. The large substrate 10 is formed, for example, in a rectangular shape. The plurality of panel portions PP are arranged in a matrix in the first direction X and the second direction Y. Each panel portion PP is removed by cutting the mother substrate 100 along the cutting line. Each of the removed panel portions PP corresponds to Figure 1 The display panel PNL is shown.

[0118] Fig.11 Yes means Fig.10 FIG. 1 is a top view of a structural example of a region 100A of a mother substrate 100 shown in FIG.

[0119] The region 100A includes a panel portion PP. The cut lines CL shown by the single-dot chain lines in the figure extend, for example, along the first direction X and the second direction Y. These cut lines CL can be Figure 1 The display panel PNL is shown in FIG. 1. Each panel portion PP includes a display area DA and a peripheral area SA.

[0120] The organic insulating layer IL at least comprises Figure 3 The insulating layer 12 shown. The organic insulating layer IL is arranged in each panel part PP and also in the blank part MP. The organic insulating layer IL has a missing part G along the outer shape of the panel part PP. The cutting line CL overlaps with the missing part G. The missing part G is a region that penetrates the organic insulating layer IL to expose the base, and is formed into a grid-shaped groove that surrounds each panel part PP. In the example shown in the figure, the missing part G extends in the first direction X and the second direction Y respectively. In addition, the missing part G has a terminal part GE located in the blank part MP.

[0121] When focusing on one panel portion PP, the missing portion G is formed in a ring shape surrounding the panel portion PP. In the panel portion PP, the display area DA overlaps with the island-shaped organic insulating layer IL. In addition, a part of the peripheral area SA also overlaps with the organic insulating layer IL.

[0122] The inorganic insulating layer 5 has an annular groove (first groove) 5G surrounding the display area DA in the peripheral area SA of the panel portion PP. The groove 5G is formed between the display area DA and the missing portion G. In addition, the inorganic insulating layer 5 has a groove (second groove) 5GA surrounding the terminal portion GE of the missing portion G in the margin portion MP. The groove 5G and the groove 5GA are regions that penetrate the inorganic insulating layer 5 to expose the base (organic insulating layer IL). The missing portion G of the organic insulating layer IL is located between the groove 5G and the groove 5GA.

[0123] The portion of the inorganic insulating layer 5 overlapping the display area DA is separated from the portion between the groove 5G and the missing portion G or the portion between the groove 5G and the groove 5GA. In addition, the portion between the groove 5G and the groove 5GA in the inorganic insulating layer 5 is separated from the portion outside the groove 5GA.

[0124] Fig.12 Yes means Fig.11 A top view of an example structure of region 100B is shown.

[0125] The region 100B includes an intersection of the scribe line CL extending in the first direction X and the scribe line CL extending in the second direction Y. As shown in FIG.

[0126] The metal layer MT is arranged in the missing portion G. In the intersection, the four metal layers MT are separated from each other and form an L shape along the cutting line CL. The cutting line CL extending in the first direction X is located between two metal layers MT adjacent to each other in the second direction Y. In addition, the cutting line CL extending in the second direction Y is located between two metal layers MT adjacent to each other in the first direction X. A cross-shaped space is formed between the four metal layers MT. These four metal layers MT function as alignment marks for aligning the mother substrate 100, for example.

[0127] The peripheral partition walls 7, 8, and 9 are arranged in the peripheral area SA and the margin MP of the panel portion PP and are separated from each other. In a plan view, the peripheral partition walls 7 and 8 overlap with the organic insulating layer IL, and the peripheral partition wall 9 overlaps with the missing portion G. Although not described in detail here, each of these peripheral partition walls 7, 8, and 9 has the same interface shape as the partition wall 6 of the display area DA, and has a lower portion and an upper portion located above the lower portion and protruding from the side of the lower portion.

[0128] The peripheral partition wall 7 is formed in a lattice shape. Figure 2 The grid-like partition walls 6 shown are formed in the same pattern.

[0129] A plurality of peripheral partition walls (first partition walls) 8 are located between the peripheral partition wall 7 and the missing portion G and are arranged along the groove 5G. For example, the plurality of peripheral partition walls 8 include a pair of peripheral partition walls 8 that extend in the first direction X and are arranged in the second direction Y. The pair of peripheral partition walls 8 arranged in the second direction Y are opposite to each other across the groove 5G extending in the first direction X. In addition, the plurality of peripheral partition walls 8 include a pair of peripheral partition walls 8 that extend in the second direction Y and are arranged in the first direction X. The pair of peripheral partition walls 8 arranged in the first direction X are opposite to each other across the groove 5G extending in the second direction Y. In addition, the plurality of peripheral partition walls 8 include an L-shaped peripheral partition wall 8 arranged along the corner of the groove 5G.

[0130] A plurality of peripheral partition walls (second partition walls) 9 are arranged in the missing portion G. In the missing portion G, the peripheral partition walls 9 are arranged along the cutting line CL. For example, the plurality of peripheral partition walls 9 include peripheral partition walls 9 extending in the first direction X. Such peripheral partition walls 9 are arranged along the cutting line CL extending in the first direction X. In addition, the plurality of peripheral partition walls 9 include peripheral partition walls 9 extending in the second direction Y. Such peripheral partition walls 9 are arranged along the cutting line CL extending in the second direction Y. In addition, the plurality of peripheral partition walls 9 include L-shaped peripheral partition walls 9 arranged along the intersection of the cutting line CL. In a top view, several peripheral partition walls 9 located at the intersection overlap with the metal layer MT. However, from the viewpoint of preventing misidentification of the alignment mark, it is desired that the peripheral partition walls 9 overlapping with the metal layer MT will not be arranged across the area where the metal layer MT does not exist. In the missing portion G, from the viewpoint of preventing poor cutting, the metal layer MT and the peripheral partition walls 9 are arranged so as not to overlap with the cutting line CL.

[0131] In the wet etching for forming the peripheral partition walls 7, 8, and 9, from the viewpoint of preventing the peripheral partition walls 9 disposed in the missing portion G from disappearing due to excessive removal, it is desirable that the width W9 of the peripheral partition walls 9 disposed in the missing portion G is greater than the width W7 of the peripheral partition walls 7 disposed above the organic insulating layer IL. In the example shown in the figure, the width W8 of the peripheral partition wall 8 is greater than the width W7, but may be equal to the width W7.

[0132] Fig.13 It means in Fig.12 FIG. 1 is a top view of the display panel PNL after being cut at the cutting line CL.

[0133] Fig.12 The cut line CL shown corresponds to the outer edge 10E of the substrate 10. However, when the mother substrate 100 is cut at the cut line CL and the panel portion is further cut to form a desired shape, the position of at least a part of the outer edge 10E is different from the outer edge 10E. Fig.12 The positions of the cut lines CL are shown differently.

[0134] The organic insulating layer IL is disposed over the entire display area DA and the peripheral area SA. The organic insulating layer IL has a missing portion LP along the outer edge 10E in the peripheral area SA. In the example shown in the figure, the missing portion LP is formed in a ring shape and is formed along the entire circumference of the outer edge 10E. The missing portion LP is equivalent to Fig.12 A portion of the missing portion G is shown.

[0135] The outer edge ILE of the organic insulating layer IL does not overlap with the outer edge 10E of the substrate 10 in a plan view, and is located between the outer edge 10E and the display area DA.

[0136] If one corner of the substrate 10 is enlarged, it becomes Fig.12 A portion of the metal layer MT and the peripheral partition wall 9 of the alignment mark shown are arranged in the missing portion LP. In other words, the metal layer MT and the peripheral partition wall 9 are located between the outer edge ILE and the outer edge 10E in a plan view. The metal layer MT is formed in an L-shape along the corner of the substrate 10. A portion of the peripheral partition wall 9 overlapping the metal layer MT is formed in a straight line along the outer edge 10E. In addition, the other peripheral partition walls 9 overlapping the metal layer MT are formed in an L-shape along the corner of the substrate 10.

[0137] In the peripheral area SA, the peripheral partition walls 7 overlapping the organic insulating layer IL are formed in a lattice shape in a plan view. In addition, a pair of peripheral partition walls 8 arranged at a distance among the peripheral partition walls 8 overlapping the organic insulating layer IL face each other via the groove 5G.

[0138] Next, about following Fig.12 The cross-sectional structure of the mother substrate 100 along the CD line will be described below with reference to several structural examples.

[0139] Fig.14 1 is a cross-sectional view showing a structural example of the mother substrate 100 .

[0140] The insulating layer 111 is an inorganic insulating layer and is disposed on the substrate 10. The insulating layer 112 is an organic insulating layer and is disposed on the insulating layer 111. The insulating layer 111 and the insulating layer 112 are included in Figure 3 The circuit layer 11 shown. In addition, the insulating layer 111 may also be omitted. In addition, other insulating layers and conductive layers may also be arranged between the substrate 10 and the insulating layer 111. Fig.12 The metal layer MT is shown to be disposed between the substrate 10 and the insulating layer 111 .

[0141] The insulating layer 12 is an organic insulating layer, covers the insulating layer 112, and has a missing portion G in a region in contact with the insulating layer 111. Fig.14 In the illustrated structural example, the organic insulating layer IL includes the insulating layer 112 and the insulating layer 12. When the cross-sectional shape of the organic insulating layer IL is focused, the organic insulating layer IL has a step-shaped cross-section in which the thickness decreases toward the missing portion G.

[0142] The thickness T1 of the organic insulating layer IL is the sum of the thickness of the insulating layer 111 and the thickness of the insulating layer 12 , and corresponds to the length along the third direction Z from the upper surface of the insulating layer 111 to the substantially flat upper surface 121A of the insulating layer 12 .

[0143] The thickness T2 of the organic insulating layer IL is the thickness of the insulating layer 12, and corresponds to the length from the upper surface of the insulating layer 111 to the substantially flat upper surface 122A of the insulating layer 12 along the third direction Z. The thickness T2 is smaller than the thickness T1. The upper surface 122A is located between the upper surface 121A and the missing portion G, and is located below the upper surface 121A.

[0144] The inorganic insulating layer 5 covers the insulating layer 12, and covers the insulating layer 111 in the missing portion G. The groove 5G penetrates to the upper surface 121A of the insulating layer 12. The groove 5G can be connected to, for example, Figure 2 The opening AP1 and the like shown in the figure are formed in the same process.

[0145] The peripheral partition walls 7 and 8 are arranged above the organic insulating layer IL, and the peripheral partition wall 9 is arranged in the missing portion G. In the example shown in the figure, the peripheral partition walls 7 and 8 are arranged above the upper surface 121A, but are not arranged above the upper surface 122A. However, the peripheral partition walls 7 and 8 may also be arranged above the upper surface 122A.

[0146] The peripheral partition wall 7 has a lower portion 71 disposed on the inorganic insulating layer 5 and an upper portion 72 disposed on the lower portion 71. The upper portion 72 has a greater width than the lower portion 71. Both ends of the upper portion 72 protrude from the side surfaces of the lower portion 71.

[0147] The peripheral partition wall 8 has a lower portion 81 disposed on the inorganic insulating layer 5 and an upper portion 82 disposed on the lower portion 81. The upper portion 82 has a greater width than the lower portion 81. Both ends of the upper portion 82 protrude from the side surfaces of the lower portion 81.

[0148] The peripheral partition wall 9 has a lower portion 91 disposed on the inorganic insulating layer 5 and an upper portion 92 disposed on the lower portion 91. The upper portion 92 has a greater width than the lower portion 91. Both ends of the upper portion 92 protrude from the side surfaces of the lower portion 91.

[0149] As such, the peripheral partition walls 7, 8, 9 are each Figure 3 The peripheral partition walls 7, 8, 9 can be formed in the same process as the partition wall 6. In this case, the lower part 71, 81, 91 is formed of the same material as the lower part 61, and the upper part 72, 82, 92 is formed of the same material as the upper part 62.

[0150] The organic insulating layer IL having a stepped cross section can be formed, for example, by the following method.

[0151] First, the insulating layer 112 is formed on the insulating layer 111. Then, the insulating layer 12 having the missing portion G, the upper surface 121A, and the upper surface 122A is formed. Such an insulating layer 12 can be formed, for example, by the following method.

[0152] That is, an insulating layer is formed on the entire surface of the mother substrate 100 on which the insulating layer 112 is formed, using, for example, a positive organic material. Then, the insulating layer is exposed. In this exposure process, the exposure amount of the missing portion G is set to be the maximum, and the exposure amount is set to be gradually reduced from the missing portion G toward the outside. Then, the exposed insulating layer is developed. Then, the insulating layer is fired.

[0153] Thus, the organic insulating layer IL having the above-mentioned cross-sectional shape is formed. Fig.11 As shown in FIG. 1 and FIG. 2 , the display area DA or the panel portion PP is formed in a ring shape.

[0154] In such a structural example, when the mother substrate 100 is cut at the cutting line CL, Fig.13 The cross section of the display panel PNL along the C'-D' line is equivalent to Fig.14 The cross section of the region of the mother substrate 100 shown is located on the left side of the cutting line CL.

[0155] Fig.15 2 is a cross-sectional view showing another structural example of the mother substrate 100 .

[0156] Fig.15 The structure example shown is Fig.14 Compared with the structure example shown in FIG. 1 , the insulating layer 112 is different in that the insulating layer 12 extends toward the cutting line CL compared with the insulating layer 12. The insulating layer 112 has a missing portion G. The insulating layer 12 is disposed on the insulating layer 112. If attention is paid to the cross-sectional shape of the organic insulating layer IL having the insulating layer 112 and the insulating layer 12, the organic insulating layer IL has a stepped cross-section in which the thickness decreases toward the missing portion G.

[0157] The thickness T1 of the organic insulating layer IL is the sum of the thickness of the insulating layer 111 and the thickness of the insulating layer 12 , and corresponds to the length along the third direction Z from the upper surface of the insulating layer 111 to the substantially flat upper surface 12A of the insulating layer 12 .

[0158] The thickness T2 of the organic insulating layer IL is the thickness of the insulating layer 112 exposed from the insulating layer 12, and corresponds to the length from the upper surface of the insulating layer 111 to the substantially flat upper surface 112A of the insulating layer 112 along the third direction Z. The thickness T2 is smaller than the thickness T1. The upper surface 112A is located between the upper surface 12A and the missing portion G, and is located below the upper surface 12A.

[0159] The inorganic insulating layer 5 covers the insulating layer 12 , covers the insulating layer 112 exposed from the insulating layer 12 , and covers the insulating layer 111 at the missing portion G. The groove 5G penetrates to the upper surface 12A of the insulating layer 12 .

[0160] The peripheral partition walls 7 and 8 are arranged above the organic insulating layer IL, and the peripheral partition wall 9 is arranged in the missing portion G. In the example shown in the figure, the peripheral partition walls 7 and 8 are arranged above the upper surface 12A, while on the other hand, they are not arranged above the upper surface 112A. However, the peripheral partition walls 7 and 8 may also be arranged above the upper surface 112A. The lower portions 71, 81, 91 of the peripheral partition walls 7, 8, and 9 are all arranged on the inorganic insulating layer 5.

[0161] The organic insulating layer IL having a stepped cross section can be formed, for example, by the following method.

[0162] First, insulating layer 112 having missing portion G and upper surface 112A is formed on insulating layer 111. Then, insulating layer 12 having upper surface 12A is formed on insulating layer 112. At this time, insulating layer 12 is formed so that a part of insulating layer 112 is exposed near missing portion G.

[0163] Thus, the organic insulating layer IL having the above-mentioned cross-sectional shape is formed.

[0164] In such a structural example, when the mother substrate 100 is cut at the cutting line CL, Fig.13 The cross section of the display panel PNL along the C'-D' line is equivalent to Fig.15 The cross section of the region of the mother substrate 100 shown is located on the left side of the cutting line CL.

[0165] Fig.16 2 is a cross-sectional view showing another structural example of the mother substrate 100 .

[0166] Fig.16 The structure example shown is Fig.14 Compared with the structure example shown in the figure, the organic insulating layer IL having a stepped cross section is different in that it is a single layer of the insulating layer 12. There is no insulating layer 112. The insulating layer 12 is arranged on the insulating layer 111 and has a missing portion G. If the cross-sectional shape of the organic insulating layer IL is focused, the organic insulating layer IL has a stepped cross section in which the thickness decreases toward the missing portion G.

[0167] The thickness T1 of the organic insulating layer IL corresponds to the length from the upper surface of the insulating layer 111 to the substantially flat upper surface 121A of the insulating layer 12 along the third direction Z. The thickness T2 of the organic insulating layer IL corresponds to the length from the upper surface of the insulating layer 111 to the substantially flat upper surface 122A of the insulating layer 12 along the third direction Z. The thickness T2 is smaller than the thickness T1. The upper surface 122A is located between the upper surface 121A and the missing portion G, and is located below the upper surface 121A.

[0168] The inorganic insulating layer 5 covers the insulating layer 12 , and covers the insulating layer 111 at the missing portion G. The groove 5G penetrates to the upper surface 121A of the insulating layer 12 .

[0169] The peripheral partition walls 7 and 8 are arranged above the organic insulating layer IL, and the peripheral partition wall 9 is arranged in the missing portion G. In the example shown in the figure, the peripheral partition walls 7 and 8 are arranged above the upper surface 121A, and on the other hand, they are not arranged above the upper surface 122A. However, the peripheral partition walls 7 and 8 may also be arranged above the upper surface 122A. The lower portions 71, 81, and 91 of the peripheral partition walls 7, 8, and 9 are all arranged on the inorganic insulating layer 5.

[0170] The insulating layer 12 having a stepped cross section can be formed, for example, by the following method.

[0171] That is, an insulating layer is formed on the entire surface of the mother substrate 100 on which the insulating layer 111 is formed, for example, by a positive organic material. Then, the insulating layer is exposed. In this exposure process, the exposure amount of the missing portion G is set to be the maximum, and the exposure amount is set to be gradually reduced from the missing portion G toward the outside. Then, the exposed insulating layer is developed. Then, the insulating layer is fired.

[0172] Thus, the insulating layer 12 having the above-mentioned cross-sectional shape is formed.

[0173] In such a structural example, when the mother substrate 100 is cut at the cutting line CL, Fig.13 The cross section of the display panel PNL along the C'-D' line is equivalent to Fig.16 The cross section of the region of the mother substrate 100 shown is located on the left side of the cutting line CL.

[0174] Fig.17 It is a cross-sectional view which enlarges the region including the groove 5G.

[0175] The insulating layer 12 has a recessed portion 12C overlapping the groove 5G. The recessed portion 12C is extended in a direction perpendicular to the extending direction of the groove 5G (in the example shown in the figure, the first direction X) compared with the groove 5G. The inorganic insulating layer 5 has an edge 5E along the groove 5G. The edge 5E overlaps with the recessed portion 12C and is separated from the insulating layer 12. In other words, the inorganic insulating layer 5 is formed in a protruding shape. In addition, the peripheral partition wall 8 does not overlap with the recessed portion 12C and the edge 5E.

[0176] As described above, the peripheral partition wall 8 is formed in a protruding shape in the same manner as the partition wall 6. In the peripheral partition wall 8, the lower portion 81 has a first conductive layer 83 disposed on the inorganic insulating layer 5 and a second conductive layer 84 disposed on the first conductive layer 83. For example, the first conductive layer 83 is formed thinner than the second conductive layer 84. In addition, in the example shown in the figure, both ends of the first conductive layer 83 protrude from the side surfaces of the second conductive layer 84.

[0177] The upper portion 82 includes a first thin film 85 disposed on the second conductive layer 84 and a second thin film 86 disposed on the first thin film 85. Both ends of the first thin film 85 and the second thin film 86 protrude from the side surface of the second conductive layer 84.

[0178] A pair of peripheral partition walls 8 are disposed on both sides of the groove 5G, so that the inorganic insulating layer 5 is pressed against the insulating layer 12 by the peripheral partition walls 8. Therefore, it is possible to suppress the inorganic insulating layer 5 from floating starting from the edge 5E of the inorganic insulating layer 5 and the inorganic insulating layer 5 from separating from the insulating layer 12.

[0179] Fig.18 It is used to illustrate Fig.14 The illustrated cross-sectional view is a state where the laminated film FL1 is formed in the region including the missing portion G.

[0180] For example, in the above-mentioned process of forming the display element DE1, the laminated film FL1 is formed not only in the display area but also in the margin MP and the peripheral area SA. The laminated film FL1 here includes, for example, an organic layer OR1, an upper electrode UE1 and a cover layer CP1 for forming the display element DE1. The laminated film FL1 is formed on the inorganic insulating layer 5 and the peripheral partition walls 7, 8, and 9.

[0181] The laminated film FL1 is disconnected by the protruding peripheral partition walls 7, 8, 9. That is, when the organic layer OR1, the upper electrode UE1, and the cover layer CP1 are formed by evaporation, the material released from the evaporation source is blocked by the upper portions 72, 82, 92 of the peripheral partition walls 7, 8, 9. Therefore, a portion of the organic layer OR1, the upper electrode UE1, and the cover layer CP1 is stacked on the upper portions 72, 82, 92. The organic layer OR1, the upper electrode UE1, and the cover layer CP1 located on the upper portions 72, 82, 92 are separated from the organic layer OR1, the upper electrode UE1, and the cover layer CP1 arranged on the inorganic insulating layer 5. As a result, the laminated film FL1 is partially disconnected.

[0182] Compared with the case where the laminate film FL1 is not disconnected by the peripheral partition walls 7, 8, 9, the area of ​​the continuous laminate film FL1 is reduced, and the stress that may be generated in the laminate film FL1 is dispersed. In addition, the inorganic insulating layer 5 and the laminate film FL1 are pressed by the peripheral partition walls 7, 8, 9. Therefore, it is possible to suppress the floating of the inorganic insulating layer 5 from the insulating layer 12 and the floating of the laminate film FL1 from the inorganic insulating layer 5. In addition, when the sealing layer SE1 is formed on the laminate film FL1, the sealing layer SE1 presses the laminate film FL1 together with the peripheral partition walls 7, 8, 9. Therefore, it is possible to suppress the laminate film FL1 and the sealing layer SE1 from detaching from the inorganic insulating layer 5.

[0183] In addition, the organic insulating layer IL has a stepped cross section whose thickness decreases toward the missing portion G. Therefore, the formation of a steep step can be suppressed. The thinner the thickness of the organic insulating layer IL, the smaller the elongation. Therefore, when a laminated film FL1 is formed on the organic insulating layer IL, the strain of the laminated film FL1 is small, and local stress concentration can be suppressed in the laminated film FL1. As a result, the laminated film FL1 can be suppressed from detaching from the inorganic insulating layer 5.

[0184] Here, the following describes a possible problem that may occur when the laminated film FL1 floats from the inorganic insulating layer 5 and breaks. The inorganic insulating layer 5 separated from the insulating layer 12 and the laminated film FL1 separated from the inorganic insulating layer 5 become foreign matter and float in the manufacturing device, which may become a source of contamination. In addition, if the floating foreign matter adheres to the processing substrate, it may cause various defects.

[0185] In contrast, according to the present embodiment, the inorganic insulating layer 5 and the laminated film FL1 can be prevented from being detached, thereby preventing contamination of the manufacturing equipment and generation of undesired foreign matter, thereby preventing a decrease in reliability.

[0186] In addition, even when the laminated film FL1 is replaced with a laminated film FL2 including the organic layer OR2 , the upper electrode UE2 , and the cover layer CP2 for forming the display element DE2 , the same effect can be obtained.

[0187] In addition, even when the stacked film FL1 is replaced with a stacked film FL3 including the organic layer OR3 , the upper electrode UE3 , and the cover layer CP3 for forming the display element DE3 , the same effect can be obtained.

[0188] Here, about Fig.14 The illustrated structural example explains the effect of suppressing the separation of the inorganic insulating layer 5 and the laminated film FL1 , but the same effect can be obtained with respect to the other structural examples.

[0189] Fig.19 It is used to illustrate Fig.17The illustrated cross-sectional view is a state where the laminated film FL1 is formed in the region including the groove 5G.

[0190] The laminated film FL1 is formed on the inorganic insulating layer 5 and the peripheral partition wall 8, and is also formed in the recessed portion 12C of the insulating layer 12. The laminated film FL1 is disconnected by the protruding inorganic insulating layer 5 and the peripheral partition wall 8. That is, the laminated film FL1 formed on the peripheral partition wall 8 is separated from the laminated film FL1 formed on the inorganic insulating layer 5. In addition, the laminated film FL1 formed on the inorganic insulating layer 5 is separated from the laminated film FL1 formed in the recessed portion 12C. In this way, the laminated film FL1 is disconnected between the inner area surrounded by the annular groove 5G and the outer area.

[0191] As a result, the stress generated in the laminate film FL1 is reduced, and the same Fig.18 The effect described above is the same as the effect.

[0192] In addition, compared with the case where the groove 5G does not exist, since the stacked film FL1 is disconnected, the capacitance of the stacked film FL1 is reduced. Therefore, electrostatic discharge from the stacked film FL1 can be suppressed. Thus, damage to the stacked film FL1 and its peripheral portion caused by electrostatic discharge can be suppressed. Therefore, a decrease in reliability can be suppressed.

[0193] Fig. 20 Yes means Fig.11 FIG. 1 is a top view of another configuration example of region 100B shown.

[0194] Fig. 20 The structure example shown is Fig.12 Compared with the structure example shown in the figure, the plurality of peripheral partition walls 9 arranged in the missing portion G include a peripheral partition wall (second partition wall) 9A arranged along the corner of the outer edge ILE of the organic insulating layer IL. The corner of the outer edge ILE is substantially a right angle in a plan view. The peripheral partition wall 9A is formed in an L shape in a plan view.

[0195] In addition, Fig. 20 The groove 5G of the inorganic insulating layer 5 and the peripheral partition wall 8 are omitted in the illustration.

[0196] In the example shown in the figure, the conductive layer 9B is arranged along the straight line portion of the outer edge ILE. The conductive layer 9B is, for example, a residue generated in the process of forming the conductive peripheral partition walls 7, 8, and 9. Therefore, the conductive layer 9B does not necessarily exist.

[0197] In the example shown in the figure, the conductive layer 9B is connected to the peripheral partition wall 9A. In a plan view, the width W9B of the conductive layer 9B is smaller than the width W9A of the peripheral partition wall 9A. In one example, the width W9A is about 20 μm, and the width W9B is several μm. The width W9B of the conductive layer 9B is smaller than the width W9 of the other peripheral partition walls 9. The width W9 is equal to the width W9A. As described above, from the viewpoint of suppressing the disappearance of the peripheral partition wall 9 or the poor formation of the peripheral partition wall 9, the width W9 and the width W9A are larger than the width W7 of the peripheral partition wall 7.

[0198] Fig.21 It means in Fig. 20 FIG. 1 is a top view of the display panel PNL after being cut at the cutting line CL.

[0199] If one corner of the substrate 10 is enlarged, Fig. 20 A portion of the metal layer MT and the peripheral partition walls 9 and 9A of the alignment mark shown are arranged in the missing portion LP. In other words, the metal layer MT and the peripheral partition walls 9 and 9A are located between the outer edge ILE and the outer edge 10E in a plan view. The metal layer MT is formed in an L-shape along the corner of the substrate 10. A portion of the peripheral partition wall 9 overlapping with the metal layer MT is formed in a straight line along the outer edge 10E. In addition, the peripheral partition wall 9A along the corner of the outer edge ILE is formed in an L-shape.

[0200] Next, about following Fig. 20 The cross-sectional structure of the mother substrate 100 along the line E-F is shown in FIG. Figure 22 to Figure 24 In each of the cross-sectional views shown, illustration of the groove 5G and the peripheral partition wall 8 is omitted.

[0201] Fig. 22 1 is a cross-sectional view showing a structural example of the mother substrate 100 .

[0202] Fig. 22 The structure example shown is similar to the structure example shown in FIG. 1 except that the peripheral partition wall 9A is arranged along the outer edge ILE. Fig.14 The structural examples shown are substantially the same.

[0203] The insulating layer 111 is an inorganic insulating layer and is disposed on the substrate 10. The insulating layer 112 is an organic insulating layer and is disposed on the insulating layer 111. The insulating layer 112 is an organic insulating layer and covers the insulating layer 112, and has a missing portion G in a region in contact with the insulating layer 111. The organic insulating layer IL including the insulating layer 112 and the insulating layer 12 has a stepped cross section in which the thickness decreases toward the missing portion G.

[0204] The peripheral partition wall 9A has a lower portion 91 disposed on the inorganic insulating layer 5 and an upper portion 92 disposed on the lower portion 91. The upper portion 92 has a greater width than the lower portion 91. Both ends of the upper portion 92 protrude from the side surfaces of the lower portion 91. Fig.14 The peripheral partition walls 9 shown have the same cross-sectional shape. Such peripheral partition walls 9A can also be formed in the same process as the partition walls 6 .

[0205] In such a structural example, when the mother substrate 100 is cut at the cutting line CL, Fig.21 The cross section of the display panel PNL along the E'-F' line is equivalent to Fig. 22 The cross section of the region of the mother substrate 100 shown is located on the left side of the cutting line CL.

[0206] Fig.23 2 is a cross-sectional view showing another structural example of the mother substrate 100 .

[0207] Fig.23 The structure example shown is similar to the structure example shown in FIG. 1 except that the peripheral partition wall 9A is arranged along the outer edge ILE. Fig.15 The structural examples shown are substantially the same.

[0208] The insulating layer 112 extends toward the cut line CL compared to the insulating layer 12 and has a missing portion G. The insulating layer 12 is disposed on the insulating layer 112. The organic insulating layer IL including the insulating layer 112 and the insulating layer 12 has a stepped cross section in which the thickness decreases toward the missing portion G. The lower portion 91 of the peripheral partition wall 9A is disposed on the inorganic insulating layer 5.

[0209] In such a structural example, when the mother substrate 100 is cut at the cutting line CL, Fig.21 The cross section of the display panel PNL along the E'-F' line is equivalent to Fig.23 The cross section of the region of the mother substrate 100 shown is located on the left side of the cutting line CL.

[0210] Fig.24 2 is a cross-sectional view showing another structural example of the mother substrate 100 .

[0211] Fig.24 The structure example shown is similar to the structure example shown in FIG. 1 except that the peripheral partition wall 9A is arranged along the outer edge ILE. Fig.16 The structural examples shown are substantially the same.

[0212] The insulating layer 12 is disposed on the insulating layer 111 and has a missing portion G. The organic insulating layer IL is a single layer of the insulating layer 12, and the insulating layer 112 does not exist. When focusing on the cross-sectional shape of the organic insulating layer IL, the organic insulating layer IL has a stepped cross-section in which the thickness decreases toward the missing portion G. The lower portion 91 of the peripheral partition wall 9A is disposed on the inorganic insulating layer 5.

[0213] In such a structural example, when the mother substrate 100 is cut at the cutting line CL, Fig.21 The cross section of the display panel PNL along the E'-F' line is equivalent to Fig.24 The cross section of the region of the mother substrate 100 shown is located on the left side of the cutting line CL.

[0214] Fig.25 This is a diagram for explaining a problem that may occur when the peripheral partition wall 9A is not provided.

[0215] When the conductive layer 9B is formed along the outer edge ILE as a residue generated in the process of forming the peripheral partition wall, the conductive layer 9B has a tendency to taper toward the corner of the outer edge ILE. At this time, charges tend to be concentrated on the sharp tip of the conductive layer 9B. Therefore, electrostatic discharge may be induced between adjacent conductive layers 9B or between the conductive layer 9B and its peripheral portion. In addition, when the laminated film FL1 is formed in a subsequent process, electrostatic discharge may be induced between the laminated film FL1 and the conductive layer 9B.

[0216] In contrast, according to Fig. 20 In the structural example shown, the peripheral partition wall 9A is intentionally arranged at the corner of the outer edge ILE. Even if the conductive layer 9B is formed, the conductive layer 9B is connected to the peripheral partition wall 9A, and it is difficult to form a sharp top. Therefore, electrostatic discharge starting from the conductive layer 9B can be suppressed. As a result, damage to the peripheral part of the conductive layer 9B and the stacked film FL1 caused by electrostatic discharge can be suppressed. Therefore, the reduction in reliability can be suppressed.

[0217] Fig.26 Yes means Fig.10 FIG. 1 is a plan view of another structural example of the region 100A of the mother substrate 100 shown.

[0218] Fig.26 The structure example shown is Fig.11Compared with the structure example shown in FIG. 1 , the outer edge ILE of the organic insulating layer IL is different in that the outer edge ILE of the organic insulating layer IL includes a rounded corner portion. The rounded corner portion here corresponds to the portion formed in an arc shape in the outer edge ILE of the organic insulating layer IL in a plan view. In the example shown in the figure, in the peripheral area SA of the panel part PP, the rounded corner portion is formed near the intersection of the cutting line CL. In addition, in the blank part MP, the rounded corner portion is formed near the intersection of the cutting line CL and at the terminal GE of the missing part G.

[0219] Fig. 27 Yes means Fig.26 FIG. 1 is a top view of a structural example of the region 100B shown in FIG. Fig. 27 The groove 5G of the inorganic insulating layer 5 and the peripheral partition wall 8 are omitted in the illustration.

[0220] The rounded portion of the outer edge ILE of the organic insulating layer IL is formed into an arc shape with a curvature radius RIL. The curvature radius RIL is, for example, greater than or equal to 1 / 2 of the width WG of the missing portion G extending in the second direction Y along the first direction X (WG / 2≤RIL). In one example, the curvature radius RIL is greater than 150 μm.

[0221] In the example shown in the figure, the conductive layer 9B is arranged along the outer edge ILE including the rounded corner. The conductive layer 9B has a substantially constant width. As described above, the conductive layer 9B is a residue generated during the process of forming the conductive peripheral partition walls 7, 8, 9, and does not necessarily exist.

[0222] Fig.28 It means in Fig. 27 FIG. 1 is a top view of the display panel PNL after being cut at the cutting line CL.

[0223] If one corner of the substrate 10 is enlarged, Fig. 27 A portion of the metal layer MT and the peripheral partition wall 9 of the alignment mark shown are arranged in the missing portion LP. The metal layer MT is formed into an L-shape along the corner of the substrate 10. A portion of the peripheral partition wall 9 overlapping the metal layer MT is formed into a straight line along the outer edge 10E. The corner of the outer edge ILE is rounded. The conductive layer 9B is arranged along the outer edge ILE.

[0224] The rounded portion in the outer edge ILE is formed in an arc shape with a curvature radius RIL. The curvature radius RIL is, for example, greater than or equal to a width WLP of the missing portion LP extending in the second direction Y along the first direction X (WLP≤RIL).

[0225] By rounding the corners of the outer edge ILE in this way, even if the conductive layer 9B is formed, the conductive layer 9B has a substantially constant width along the outer edge ILE, and it is difficult to form a sharp tip. Therefore, electrostatic discharge starting from the conductive layer 9B can be suppressed. As a result, damage to the peripheral portion of the conductive layer 9B and the laminated film FL1 caused by electrostatic discharge can be suppressed.

[0226] In addition, the radius of curvature RIL of the rounded corner is greater than or equal to 1 / 2 of the width WG of the missing portion G in the mother substrate 100, or greater than or equal to the width WLP of the missing portion LP in the display panel PNL. Therefore, it is possible to suppress floating or detachment starting from the corner vicinity of the laminated film FL1 or the inorganic insulating layer 5. Therefore, it is possible to suppress a reduction in reliability.

[0227] In the above-mentioned embodiment, for example, in each of the peripheral partition walls 7, 8, and 9, the lower portion 71, 81, and 91 corresponds to the first lower portion, the upper portion 72, 82, and 92 corresponds to the first upper portion, the peripheral partition wall 8 corresponds to the first partition wall, and the peripheral partition walls 9 and 9A correspond to the second partition wall. In addition, in the partition wall 6, the lower portion 61 corresponds to the second lower portion, and the upper portion 62 corresponds to the second upper portion. In the organic insulating layer IL, the insulating layer 112 corresponds to the first layer, and the insulating layer 12 corresponds to the second layer. In the inorganic insulating layer 5, the groove 5G corresponds to the first groove, and the groove 5GA corresponds to the second groove.

[0228] As described above, according to the present embodiment, it is possible to provide a display device and a mother substrate capable of suppressing a decrease in reliability.

[0229] All display devices and mother substrates that can be appropriately designed and implemented by those skilled in the art based on the display devices and mother substrates described above as embodiments of the present invention also belong to the scope of the present invention as long as they include the gist of the present invention.

[0230] Within the scope of the present invention, those skilled in the art can think of various variations, and these variations are also interpreted as belonging to the scope of the present invention. For example, for the above-mentioned embodiments, those skilled in the art can appropriately add, delete or design changes to structural elements, or add, omit or change conditions to obtain solutions, as long as they have the gist of the present invention, they are also included in the scope of the present invention.

[0231] Furthermore, other effects brought about by the schemes described in the above embodiments are of course interpreted as being brought about by the present invention, as long as they are clear from the description of this specification or can be appropriately imagined by those skilled in the art.

Claims

1. A display device, characterized in that: have: substrate; an organic insulating layer disposed above the substrate in the entire range of a display region for displaying an image and a peripheral region outside the display region; a lower electrode, which is arranged on the organic insulating layer in the display area; an inorganic insulating layer, which is disposed on the organic insulating layer and covers the peripheral portion of the lower electrode; An organic layer, which is disposed on the lower electrode and includes a light-emitting layer; An upper electrode, which is disposed on the organic layer; as well as a plurality of peripheral partition walls arranged in the peripheral area, Each of the plurality of peripheral partition walls has: a first lower portion located above the inorganic insulating layer; and a first upper portion located above the first lower portion and protruding from a side surface of the first lower portion, The organic insulating layer has a missing portion along the outer edge of the substrate in the peripheral region, The inorganic insulating layer has a ring-shaped groove surrounding the display area in the peripheral area, The plurality of peripheral partition walls include a pair of first partition walls facing each other across the groove.

2. The display device according to claim 1, characterized in that The organic insulating layer has a concave portion overlapping the groove, The edge portion of the inorganic insulating layer along the groove overlaps with the recessed portion and is separated from the organic insulating layer.

3. The display device according to claim 1, characterized in that The inorganic insulating layer is disposed in the missing portion. The plurality of peripheral partition walls include a second partition wall disposed on the inorganic insulating layer at the missing portion.

4. The display device according to claim 3, characterized in that: The second partition wall is disposed along a corner portion of an outer edge of the organic insulating layer and is formed in an L-shape in a plan view.

5. The display device according to claim 4, characterized in that: further comprising a conductive layer disposed along a straight line portion of an outer edge of the organic insulating layer, The conductive layer is connected to the second partition wall, The width of the conductive layer is smaller than the width of the second partition wall.

6. The display device according to claim 1, characterized in that: The outer edge of the organic insulating layer includes a rounded corner portion, The radius of curvature of the rounded corner is greater than or equal to the width of the missing portion.

7. The display device according to claim 6, characterized in that: The invention further includes a conductive layer disposed along the outer edge of the organic insulating layer.

8. A display device, characterized in that: have: substrate; an organic insulating layer disposed above the substrate in the entire range of a display region for displaying an image and a peripheral region outside the display region; a lower electrode, which is arranged on the organic insulating layer in the display area; an inorganic insulating layer, which is disposed on the organic insulating layer and covers the peripheral portion of the lower electrode; An organic layer, which is disposed on the lower electrode and includes a light-emitting layer; An upper electrode, which is disposed on the organic layer; as well as a plurality of peripheral partition walls arranged in the peripheral area, Each of the plurality of peripheral partition walls comprises: a first lower portion; and a first upper portion located above the first lower portion and protruding from a side surface of the first lower portion, The organic insulating layer has a missing portion along the outer edge of the substrate in the peripheral region, The plurality of peripheral partition walls include a second partition wall disposed in the missing portion, The second partition wall is disposed along a corner portion of an outer edge of the organic insulating layer and is formed in an L-shape in a plan view.

9. The display device according to claim 8, characterized in that: further comprising a conductive layer arranged along a straight line portion of an outer edge of the organic insulating layer, The conductive layer is connected to the second partition wall, The width of the conductive layer is smaller than the width of the second partition wall.

10. A display device, characterized in that: have: substrate; an organic insulating layer disposed above the substrate in the entire range of a display region for displaying an image and a peripheral region outside the display region; a lower electrode, which is arranged on the organic insulating layer in the display area; an inorganic insulating layer, which is disposed on the organic insulating layer and covers the peripheral portion of the lower electrode; An organic layer, which is disposed on the lower electrode and includes a light-emitting layer; An upper electrode, which is disposed on the organic layer; as well as a plurality of peripheral partition walls arranged in the peripheral area, Each of the plurality of peripheral partition walls comprises: a first lower portion; and a first upper portion located above the first lower portion and protruding from a side surface of the first lower portion, The organic insulating layer has a missing portion along the outer edge of the substrate in the peripheral region, The outer edge of the organic insulating layer includes a rounded corner portion, The radius of curvature of the rounded corner is greater than or equal to the width of the missing portion.

11. The display device according to claim 10, characterized in that: The invention further includes a conductive layer disposed along the outer edge of the organic insulating layer.

12. The display device according to any one of claims 1, 8 and 10, characterized in that: A partition wall is also provided in the display region, the partition wall having: a second lower portion disposed on the inorganic insulating layer and formed of a conductive material; and a second upper portion disposed on the second lower portion and protruding from a side surface of the second lower portion, The lower electrode, the organic layer and the upper electrode are surrounded by the partition wall, The upper electrode is in contact with the second lower portion of the partition wall.

13. The display device according to any one of claims 1, 8 and 10, characterized in that: The organic insulating layer includes a first layer and a second layer covering the first layer, and has a stepped cross section in which a thickness decreases toward the missing portion.

14. The display device according to any one of claims 1, 8 and 10, characterized in that: The organic insulating layer includes a first layer and a second layer disposed on the first layer and exposing the first layer near the missing portion, and has a step-shaped cross section in which a thickness decreases toward the missing portion.

15. The display device according to any one of claims 1, 8 and 10, characterized in that: The organic insulating layer is a single layer and has a stepped cross section in which the thickness decreases toward the missing portion.

16. A mother substrate, characterized in that: have: A panel portion having a display area for displaying an image and a peripheral area outside the display area; a margin portion located outside the panel portion; An organic insulating layer, which is arranged in the entire range of the panel portion and the blank portion; a lower electrode, which is arranged on the organic insulating layer in the display area; an inorganic insulating layer, which is disposed on the organic insulating layer and covers the peripheral portion of the lower electrode; An organic layer, which is disposed on the lower electrode and includes a light-emitting layer; An upper electrode, which is disposed on the organic layer; as well as a plurality of peripheral partition walls arranged in the peripheral area, Each of the plurality of peripheral partition walls has: a first lower portion located above the inorganic insulating layer; and a first upper portion located above the first lower portion and protruding from a side surface of the first lower portion, The inorganic insulating layer has a first annular groove surrounding the display area in the peripheral region. The plurality of peripheral partition walls include a pair of first partition walls facing each other across the first groove.

17. The mother substrate according to claim 16, characterized in that: The organic insulating layer has a concave portion overlapping with the first groove, An edge portion of the inorganic insulating layer along the first groove overlaps with the recessed portion and is separated from the organic insulating layer.

18. The mother substrate according to claim 16, characterized in that: The organic insulating layer has a missing portion along the outer shape of the panel portion, The missing portion has a terminal portion located at the margin portion, The inorganic insulating layer has a second groove surrounding the terminal portion in the blank portion.

19. A mother substrate, characterized in that: have: A panel portion having a display area for displaying an image and a peripheral area outside the display area; a margin portion located outside the panel portion; An organic insulating layer, which is arranged in the entire range of the panel portion and the blank portion; a lower electrode, which is arranged on the organic insulating layer in the display area; an inorganic insulating layer, which is disposed on the organic insulating layer and covers the peripheral portion of the lower electrode; An organic layer, which is disposed on the lower electrode and includes a light-emitting layer; An upper electrode, which is disposed on the organic layer; as well as a plurality of peripheral partition walls arranged in the peripheral area, Each of the plurality of peripheral partition walls has: a first lower portion located above the inorganic insulating layer; and a first upper portion located above the first lower portion and protruding from a side surface of the first lower portion, The organic insulating layer has a missing portion along the outer shape of the panel portion, The plurality of peripheral partition walls include a second partition wall disposed in the missing portion, The second partition wall is disposed along a corner portion of an outer edge of the organic insulating layer and is formed in an L-shape in a plan view.

20. A mother substrate, characterized in that: have: A panel portion having a display area for displaying an image and a peripheral area outside the display area; a margin portion located outside the panel portion; An organic insulating layer, which is arranged in the entire range of the panel portion and the blank portion; a lower electrode, which is arranged on the organic insulating layer in the display area; an inorganic insulating layer, which is disposed on the organic insulating layer and covers the peripheral portion of the lower electrode; An organic layer, which is disposed on the lower electrode and includes a light-emitting layer; An upper electrode, which is disposed on the organic layer; as well as a plurality of peripheral partition walls arranged in the peripheral area, Each of the plurality of peripheral partition walls has: a first lower portion located above the inorganic insulating layer; and a first upper portion located above the first lower portion and protruding from a side surface of the first lower portion, The organic insulating layer has a missing portion along the outer shape of the panel portion, The outer edge of the organic insulating layer includes a rounded corner portion, The radius of curvature of the rounded corner portion is greater than or equal to 1 / 2 of the width of the missing portion.

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