Display device and mother substrate

Abstract

The invention relates to a display device and a mother substrate. The display device includes: an organic insulating layer disposed across a display region in which an image is displayed and a peripheral region outside the display region; a lower electrode disposed on the organic insulating layer in the display area; an inorganic insulating layer disposed on the organic insulating layer and covering a peripheral portion of the lower electrode; an organic layer disposed on the lower electrode and including a light emitting layer; an upper electrode disposed on the organic layer; and a plurality of peripheral partition walls disposed in the peripheral region. Each of the plurality of peripheral partition walls has a first lower portion located on the inorganic insulating layer and a first upper portion located on the first lower portion and protruding from a side surface of the first lower portion, the organic insulating layer has a flat upper surface and a recessed portion recessed relative to the upper surface in a peripheral region, and the plurality of peripheral partition walls include first partition walls overlapping the recessed portion. The distance from the first upper portion of the first partition wall to the edge portion of the recess is 50 [mu] m or more.

Description

[0001] Cross-references to related applications

[0002] This application claims priority based on Japanese Patent Application No. 2023-179595 filed on October 18, 2023, and cites all the contents described in the Japanese application. Technical Field

[0003] Embodiments of the present invention relate to a display device and a mother substrate. Background Art

[0004] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have become practical. The display element includes a pixel circuit including a thin film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. In addition to the light-emitting layer, the organic layer also includes functional layers such as a hole transport layer and an electron transport layer.

[0005] In the process of manufacturing such a display element, a technology for suppressing a decrease in reliability is required. Summary of the invention

[0006] An object of the embodiment is to provide a display device and a mother substrate capable of suppressing a decrease in reliability.

[0007] According to one embodiment, a display device comprises: a substrate; an organic insulating layer, which is arranged above the substrate over a display area where an image is displayed and a peripheral area outside the display area; a lower electrode, which is arranged on the organic insulating layer in the display area; an inorganic insulating layer, which is arranged on the organic insulating layer and covers the peripheral portion of the lower electrode; an organic layer arranged on the lower electrode and including a light-emitting layer; an upper electrode arranged on the organic layer; and a plurality of peripheral partitions arranged in the peripheral area, each of the plurality of peripheral partitions having: a first lower portion located above the inorganic insulating layer; and a first upper portion located above the first lower portion and protruding from a side surface of the first lower portion, the organic insulating layer having a flat upper surface in the peripheral area, and a recessed portion recessed relative to the upper surface, the plurality of peripheral partitions including a first partition overlapping the recessed portion, and a distance from the first upper portion of the first partition to an edge portion of the recessed portion being greater than 50 μm.

[0008] According to one embodiment, a display device comprises: a substrate; an organic insulating layer, which is arranged above the substrate over a display area where an image is displayed and a peripheral area outside the display area; a lower electrode, which is arranged on the organic insulating layer in the display area; an inorganic insulating layer, which is arranged on the organic insulating layer and covers the peripheral portion of the lower electrode; an organic layer arranged on the lower electrode and including a light-emitting layer; an upper electrode arranged on the organic layer; and a plurality of peripheral partitions arranged in the peripheral area, each of the plurality of peripheral partitions having: a first lower portion located above the inorganic insulating layer; and a first upper portion located above the first lower portion and protruding from a side surface of the first lower portion, the organic insulating layer having a flat upper surface, a recessed portion recessed relative to the upper surface, and an inclined surface surrounding the recessed portion in the peripheral area, the plurality of peripheral partitions including a first partition overlapping the recessed portion, and a second partition overlapping the upper surface, and the inorganic insulating layer having a missing portion overlapping the inclined surface.

[0009] According to one embodiment, a mother substrate comprises: a panel portion having a display area for displaying an image, and a peripheral area on the outside of the display area; a blank portion on the outside of the panel portion; an organic insulating layer arranged throughout the panel portion and the blank portion; a lower electrode arranged on the organic insulating layer in the display area; an inorganic insulating layer arranged on the organic insulating layer and covering the peripheral portion of the lower electrode; an organic layer arranged on the lower electrode and including a light-emitting layer; an upper electrode arranged on the organic layer; and a plurality of peripheral partitions arranged in the peripheral area and the blank portion, each of the plurality of peripheral partitions respectively comprising: a first lower portion located on the inorganic insulating layer; and a first upper portion located on the first lower portion and protruding from the side of the first lower portion, the organic insulating layer having a flat upper surface in the peripheral area or the blank portion, and a recessed portion recessed relative to the upper surface, the plurality of peripheral partitions including a first partition overlapping the recessed portion, and a distance from the first upper portion of the first partition to the edge of the recessed portion being greater than 50 μm.

[0010] According to one embodiment, the mother substrate comprises: a panel portion having a display area for displaying an image and a peripheral area on the outside of the display area; a blank portion on the outside of the panel portion; an organic insulating layer arranged throughout the panel portion and the blank portion; a lower electrode arranged on the organic insulating layer in the display area; an inorganic insulating layer arranged on the organic insulating layer and covering the peripheral portion of the lower electrode; an organic layer arranged on the lower electrode and including a light-emitting layer; an upper electrode arranged on the organic layer; and an inorganic insulating layer arranged in the peripheral area. and a plurality of peripheral partition walls in the blank portion, each of the plurality of peripheral partition walls respectively comprising: a first lower portion located above the inorganic insulating layer; and a first upper portion located above the first lower portion and protruding from a side surface of the first lower portion, the organic insulating layer having a flat upper surface, a recessed portion recessed relative to the upper surface, and an inclined surface surrounding the recessed portion in the peripheral region or the blank portion, the plurality of peripheral partition walls comprising a first partition wall overlapping the recessed portion, and a second partition wall overlapping the upper surface, and the inorganic insulating layer having a missing portion overlapping the inclined surface.

[0011] According to the embodiment, a display device and a mother substrate capable of suppressing a decrease in reliability can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a diagram showing a configuration example of a DSP of a display device.

[0013] Figure 2 It is a diagram showing an example of the layout of sub-pixels SP1 , SP2 , and SP3 .

[0014] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display device DSP taken along line AB in FIG.

[0015] Figure 4 It is a diagram for explaining a method of manufacturing the display device DSP.

[0016] Figure 5 It is a diagram for explaining a method of manufacturing the display device DSP.

[0017] Figure 6 It is a diagram for explaining a method of manufacturing the display device DSP.

[0018] Figure 7 It is a diagram for explaining a method of manufacturing the display device DSP.

[0019] Figure 8 It is a diagram for explaining a method of manufacturing the display device DSP.

[0020] Fig. 9It is a diagram for explaining a method of manufacturing the display device DSP.

[0021] Fig.10 1 is a plan view showing an example of the mother substrate 100 .

[0022] Fig.11 It is a plan view showing a configuration example of the pad PD or the terminal TE.

[0023] Fig.12 1 is a cross-sectional view showing a configuration example of the mother substrate 100 .

[0024] Fig.13 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0025] Fig.14 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0026] Fig.15 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0027] Fig.16 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0028] Fig.17 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0029] Fig.18 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0030] Fig.19 It is shown Fig.10 FIG. 1 is a plan view of a configuration example of a region 100A of a mother substrate 100 shown.

[0031] Fig. 20 1 is a cross-sectional view showing a configuration example of the mother substrate 100 .

[0032] Fig.21 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0033] Fig. 22 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0034] Fig.23 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0035] Fig.24 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0036] Fig.25 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0037] Fig.26 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0038] Fig. 27 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0039] Fig.28 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0040] Fig.29 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0041] Fig.30 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0042] Fig.31 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0043] Fig.32 This is a diagram for explaining one of the effects of the embodiment.

[0044] Fig.33 1 is a plan view showing an example of the peripheral partition wall 7 arranged in the recessed portion DP of the organic insulating layer IL.

[0045] Fig.34 It is a plan view showing another configuration example of the pad PD or the terminal TE.

[0046] Fig.35 1 is a cross-sectional view showing a configuration example of the mother substrate 100 .

[0047] Fig.36 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0048] Fig.37 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0049] Fig.38 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0050] Fig.39 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0051] Fig.40 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0052] Fig.41 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0053] Fig.42 It is shown Fig.19A top view of another configuration example of the region 100A is shown.

[0054] Fig.43 1 is a cross-sectional view showing a configuration example of the mother substrate 100 .

[0055] Fig.44 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0056] Fig.45 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0057] Fig.46 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0058] Fig.47 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0059] Fig.48 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0060] Fig.49 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0061] Fig.50 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0062] Fig.51 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0063] Fig.52 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0064] Fig.53 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0065] Fig.54 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0066] Fig.55 It is used to illustrate that Fig.35 The illustrated cross-sectional view is a state where the laminated film FL1 is formed in the region of the missing portion LP. DETAILED DESCRIPTION

[0067] The embodiments are described with reference to the drawings.

[0068] The disclosed content is only an example, and appropriate changes that can be easily thought of by those skilled in the art while maintaining the main idea of ​​the invention are certainly included in the scope of the present invention. In addition, in order to make the description clearer, the drawings sometimes roughly show the width, thickness, shape, etc. of each part compared with the actual way, but it is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, the same reference numerals are marked for the constituent elements that perform the same or similar functions as the constituent elements previously described in the figures that have appeared, and repeated detailed descriptions are sometimes appropriately omitted.

[0069] It should be noted that in the drawings, mutually orthogonal X-axis, Y-axis and Z-axis are described as needed for easy understanding. The direction along the X-axis is called the first direction X, the direction along the Y-axis is called the second direction Y, and the direction along the Z-axis is called the third direction Z. Observing various elements parallel to the third direction Z is called a top view.

[0070] The display device according to this embodiment is an organic electroluminescent display device including an organic light emitting diode (OLED) as a display element, and can be mounted on a television, a personal computer, an in-vehicle device, a tablet terminal, a smartphone, a mobile phone terminal, and the like.

[0071] Figure 1 This is a diagram showing a configuration example of a DSP of a display device.

[0072] The display device DSP includes a display panel PNL on an insulating substrate 10. The display panel PNL includes a display area DA for displaying an image and a peripheral area SA outside the display area DA. The substrate 10 may be glass or a flexible resin film.

[0073] In the present embodiment, the shape of the substrate 10 in plan view is a rectangle, but the shape of the substrate 10 in plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0074] The display area DA has a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. The pixel PX includes a plurality of sub-pixels SP. In one example, the pixel PX includes a sub-pixel SP1 of a first color, a sub-pixel SP2 of a second color, and a sub-pixel SP3 of a third color. The first color, the second color, and the third color are different colors. It should be noted that the pixel PX may also include a sub-pixel SP of another color such as white together with the sub-pixels SP1, SP2, and SP3 or instead of any of the sub-pixels SP1, SP2, and SP3.

[0075] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements composed of, for example, thin film transistors.

[0076] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and the drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the driving transistor 3 and the capacitor 4. In the driving transistor 3, one of the source electrode and the drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element DE.

[0077] It should be noted that the configuration of the pixel circuit 1 is not limited to the illustrated example. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0078] The display element DE is an organic light emitting diode (OLED) as a light emitting element, sometimes referred to as an organic EL element.

[0079] The peripheral area SA has a plurality of terminals TE arranged in one direction. In the example shown in the figure, the plurality of terminals TE are arranged along the first direction X. Each of the terminals TE extends in the second direction Y, but is not limited thereto. For example, a part of the plurality of terminals TE may also extend in an oblique direction. Such a plurality of terminals TE is electrically connected to, for example, a flexible printed circuit substrate or an IC chip.

[0080] Figure 2 It is a diagram showing an example of the layout of sub-pixels SP1 , SP2 , and SP3 .

[0081] In the example shown in the figure, the sub-pixel SP2 and the sub-pixel SP3 are arranged in the second direction Y. The sub-pixel SP1 and the sub-pixel SP2 are arranged in the first direction X, and the sub-pixel SP1 and the sub-pixel SP3 are arranged in the first direction X.

[0082] When the sub-pixels SP1, SP2, and SP3 are arranged in this way, columns in which the sub-pixels SP2 and SP3 are alternately arranged in the second direction Y and columns in which a plurality of sub-pixels SP1 are arranged in the second direction Y are formed in the display area DA. These columns are alternately arranged in the first direction X.

[0083] It should be noted that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to Figure 2 As another example, the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged in sequence in the first direction X.

[0084] In the display area DA, an inorganic insulating layer 5 and partitions 6 are disposed. The inorganic insulating layer 5 has openings AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. The inorganic insulating layer 5 having these openings AP1, AP2, and AP3 is sometimes called a rib.

[0085] The partition wall 6 overlaps with the inorganic insulating layer 5 in a plan view. The partition wall 6 is formed in a lattice shape surrounding the openings AP1, AP2, and AP3. The partition wall 6 may also have openings in the sub-pixels SP1, SP2, and SP3 similarly to the inorganic insulating layer 5. The partition wall 6 is conductive and Figure 1 Among the plurality of terminals TE shown, terminals TE of a common potential are electrically connected.

[0086] The sub-pixels SP1 , SP2 , and SP3 include display elements DE1 , DE2 , and DE3 as display elements DE, respectively.

[0087] The display element DE1 of the sub-pixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with the opening AP1 respectively. The peripheral portion of the lower electrode LE1 is covered by the inorganic insulating layer 5. The lower electrode LE1, the organic layer OR1, and the upper electrode UE1 are surrounded by the partition wall 6 when viewed from above. The peripheral portions of the organic layer OR1 and the upper electrode UE1 overlap with the inorganic insulating layer 5 when viewed from above. The organic layer OR1 includes, for example, a light-emitting layer that emits light in the blue wavelength band.

[0088] The display element DE2 of the sub-pixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with the opening AP2 respectively. The peripheral portion of the lower electrode LE2 is covered by the inorganic insulating layer 5. The lower electrode LE2, the organic layer OR2, and the upper electrode UE2 are surrounded by the partition wall 6 when viewed from above. The peripheral portions of the organic layer OR2 and the upper electrode UE2 overlap with the inorganic insulating layer 5 when viewed from above. The organic layer OR2 includes, for example, a light-emitting layer that emits light in the green wavelength band.

[0089] The display element DE3 of the sub-pixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with the opening AP3 respectively. The peripheral portion of the lower electrode LE3 is covered by the inorganic insulating layer 5. The lower electrode LE3, the organic layer OR3, and the upper electrode UE3 are surrounded by the partition wall 6 when viewed from above. The peripheral portions of the organic layer OR3 and the upper electrode UE3 overlap with the inorganic insulating layer 5 when viewed from above. The organic layer OR3 includes, for example, a light-emitting layer that emits light in the red wavelength band.

[0090] In the example shown in the figure, the outer shapes of the lower electrodes LE1, LE2, LE3 are indicated by dotted lines, and the outer shapes of the organic layers OR1, OR2, OR3 and the upper electrodes UE1, UE2, UE3 are indicated by dotted lines. It should be noted that the outer shapes of the lower electrodes, organic layers, and upper electrodes shown in the figure are not limited to those reflecting precise shapes.

[0091] The lower electrodes LE1 , LE2 , and LE3 correspond to, for example, anodes of the display element, and the upper electrodes UE1 , UE2 , and UE3 correspond to cathodes or common electrodes of the display element, and are in contact with the partition wall 6 .

[0092] The lower electrode LE1 and the pixel circuit 1 of the sub-pixel SP1 (see Figure 1 The lower electrode LE2 is electrically connected to the pixel circuit 1 of the sub-pixel SP2. The lower electrode LE3 is electrically connected to the pixel circuit 1 of the sub-pixel SP3.

[0093] In the example shown in the figure, the area of ​​the opening AP1, the area of ​​the opening AP2, and the area of ​​the opening AP3 are different from each other. The area of ​​the opening AP1 is larger than the area of ​​the opening AP2, and the area of ​​the opening AP2 is larger than the area of ​​the opening AP3. In other words, the area of ​​the lower electrode LE1 exposed from the opening AP1 is larger than the area of ​​the lower electrode LE2 exposed from the opening AP2, and the area of ​​the lower electrode LE2 exposed from the opening AP2 is larger than the area of ​​the lower electrode LE3 exposed from the opening AP3.

[0094] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display device DSP taken along line AB in FIG.

[0095] The circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes Figure 1 The circuit layer 11 is covered with an insulating layer 12 , which is an organic insulating layer that flattens the unevenness generated by the circuit layer 11 .

[0096] The lower electrodes LE1, LE2, and LE3 are arranged on the insulating layer 12 and are separated from each other. The inorganic insulating layer 5 is arranged on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The opening AP1 of the inorganic insulating layer 5 overlaps with the lower electrode LE1, the opening AP2 overlaps with the lower electrode LE2, and the opening AP3 overlaps with the lower electrode LE3. The peripheral portions of the lower electrodes LE1, LE2, and LE3 are covered by the inorganic insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3 respectively through contact holes provided in the insulating layer 12. It should be noted that the contact holes of the insulating layer 12 are provided in Figure 3 Omitted in .

[0097] The partition wall 6 includes a conductive lower portion 61 disposed on the inorganic insulating layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a greater width than the lower portion 61. Both ends of the upper portion 62 protrude from the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called an overhang.

[0098] In the example shown in the figure, the lower portion 61 includes a first conductive layer 63 disposed on the inorganic insulating layer 5, and a second conductive layer 64 disposed on the first conductive layer 63. For example, the first conductive layer 63 is formed thinner than the second conductive layer 64. In addition, in the example shown in the figure, both ends of the first conductive layer 63 protrude from the side surfaces of the second conductive layer 64.

[0099] The upper portion 62 includes a first thin film 65 disposed on the second conductive layer 64 and a second thin film 66 disposed on the first thin film 65. Both ends of the first thin film 65 and the second thin film 66 protrude from the side surface of the second conductive layer 64.

[0100] The organic layer OR1 contacts the lower electrode LE1 through the opening AP1 , covers the lower electrode LE1 exposed from the opening AP1 , and has its peripheral portion located on the inorganic insulating layer 5 . The upper electrode UE1 covers the organic layer OR1 and contacts the lower portion 61 .

[0101] The organic layer OR2 contacts the lower electrode LE2 through the opening AP2 , covers the lower electrode LE2 exposed from the opening AP2 , and has its peripheral portion located on the inorganic insulating layer 5 . The upper electrode UE2 covers the organic layer OR2 and contacts the lower portion 61 .

[0102] The organic layer OR3 contacts the lower electrode LE3 through the opening AP3 , covers the lower electrode LE3 exposed from the opening AP3 , and its peripheral portion is located on the inorganic insulating layer 5 . The upper electrode UE3 covers the organic layer OR3 and contacts the lower portion 61 .

[0103] In the example shown in the figure, the sub-pixel SP1 has a cap layer CP1 and a sealing layer SE1, the sub-pixel SP2 has a cap layer CP2 and a sealing layer SE2, and the sub-pixel SP3 has a cap layer CP3 and a sealing layer SE3. The cap layers CP1, CP2, and CP3 respectively function as optical adjustment layers for improving the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3. It should be noted that the cap layers CP1, CP2, and CP3 may also be omitted.

[0104] The cap layer CP1 is disposed on the upper electrode UE1.

[0105] The cap layer CP2 is disposed on the upper electrode UE2.

[0106] The cap layer CP3 is disposed on the upper electrode UE3.

[0107] The sealing layer SE1 is disposed on the cap layer CP1 , is in contact with the partition wall 6 , and continuously covers each component of the sub-pixel SP1 .

[0108] The sealing layer SE2 is disposed on the cap layer CP2 , in contact with the partition wall 6 , and continuously covers the components of the sub-pixel SP2 .

[0109] The sealing layer SE3 is disposed on the cap layer CP3 , is in contact with the partition wall 6 , and continuously covers each component of the sub-pixel SP3 .

[0110] In the example shown in the figure, a portion of each of the organic layer OR1, the upper electrode UE1 and the cover layer CP1 is located on the partition wall 6 around the sub-pixel SP1. These portions are separated from portions of the organic layer OR1, the upper electrode UE1 and the cover layer CP1 located at the opening AP1 (parts constituting the display element DE1).

[0111] Similarly, a portion of the organic layer OR2, the upper electrode UE2 and the cover layer CP2 is located on the partition wall 6 around the subpixel SP2, and these portions are separated from the portions of the organic layer OR2, the upper electrode UE2 and the cover layer CP2 located in the opening AP2 (the portions constituting the display element DE2).

[0112] Similarly, a portion of the organic layer OR3, the upper electrode UE3 and the cover layer CP3 is located on the partition wall 6 around the sub-pixel SP3, and these portions are separated from the portion of the organic layer OR3, the upper electrode UE3 and the cover layer CP3 located in the opening AP3 (the portion constituting the display element DE3).

[0113] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1 and the cover layer CP1 is referred to as the stacked film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2 and the cover layer CP2 is referred to as the stacked film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3 and the cover layer CP3 is referred to as the stacked film FL3.

[0114] The ends of the sealing layers SE1, SE2, and SE3 and the ends of the laminated films FL1, FL2, and FL3 are respectively located on the partition wall 6. In the example shown in the figure, the laminated film FL1 and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP2 are separated from the laminated film FL2 and the sealing layer SE2 on the partition wall 6. In addition, the laminated film FL1 and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP3 are separated from the laminated film FL3 and the sealing layer SE3 on the partition wall 6.

[0115] The partition wall 6 and the sealing layers SE1, SE2, and SE3 are covered with a resin layer 13. The resin layer 13 is covered with a sealing layer 14. The sealing layer 14 is covered with a resin layer 15.

[0116] The inorganic insulating layer 5 , the sealing layers SE1 , SE2 , SE3 , and the sealing layer 14 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al 2 O 3 ).

[0117] The lower portion 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The first conductive layer 63 is formed of a titanium-based material such as titanium or a titanium compound. The second conductive layer 64 is formed of a material different from the first conductive layer 63 and the upper portion 62, for example, an aluminum-based material such as aluminum or an aluminum compound.

[0118] The upper portion 62 of the partition wall 6 is formed of, for example, a conductive material, but may also be formed of an insulating material. The upper portion 62 is formed of a material different from that of the lower portion 61. The first thin film 65 is formed of, for example, a titanium-based material such as titanium or a titanium compound. The second thin film 66 is formed of, for example, an oxide conductive material such as indium tin oxide (ITO).

[0119] The lower electrodes LE1, LE2, and LE3 are, for example, a multilayer body including a transparent layer formed of an oxide conductive material such as indium tin oxide (ITO) and a reflective layer formed of a metal material such as silver. In one example, the lower electrodes LE1, LE2, and LE3 are a multilayer body including a reflective layer between a pair of transparent layers. The lower transparent layer functions as a bonding layer that is bonded to the insulating layer 12.

[0120] The organic layer OR1 includes a light-emitting layer EM1. The organic layer OR2 includes a light-emitting layer EM2. The organic layer OR3 includes a light-emitting layer EM3. The light-emitting layer EM1, the light-emitting layer EM2, and the light-emitting layer EM3 are formed of different materials. In one example, the light-emitting layer EM1 is formed of a material that emits light in a blue wavelength band, the light-emitting layer EM2 is formed of a material that emits light in a green wavelength band, and the light-emitting layer EM3 is formed of a material that emits light in a red wavelength band.

[0121] In addition, each of the organic layers OR1, OR2, and OR3 includes a plurality of functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0122] The upper electrodes UE1 , UE2 , and UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg).

[0123] The cap layers CP1, CP2, and CP3 are multilayer bodies of a plurality of thin films, all of which are transparent and have different refractive indices.

[0124] The circuit layer 11 , the insulating layer 12 , and the inorganic insulating layer 5 shown in the figure are arranged over the display area DA and the peripheral area SA.

[0125] Next, a method for manufacturing the display device DSP will be described. It should be noted that, in the drawings for describing the manufacturing method, illustration of the portion below the insulating layer 12 is omitted.

[0126] First, on the substrate 10, a circuit layer 11 and an insulating layer 12 are formed over the display area DA and the peripheral area SA. Figure 4 As shown, a lower electrode LE1 of the sub-pixel SP1 , a lower electrode LE2 of the sub-pixel SP2 , and a lower electrode LE3 of the sub-pixel SP3 are formed on the insulating layer 12 .

[0127] Thereafter, an inorganic insulating layer 5 is formed to cover the peripheral edge portions of the lower electrodes LE1, LE2, and LE3. The inorganic insulating layer 5 is formed of silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0128] Then, a partition wall 6 is formed which has a lower portion 61 located on the inorganic insulating layer 5 and an upper portion 62 located on the lower portion 61. The first conductive layer 63 of the lower portion 61 and the upper portion 62 protrude from the side surface of the second conductive layer 64 of the lower portion 61. The first conductive layer 63 is formed of a conductive material such as a titanium-based material, and the second conductive layer 64 is formed of a conductive material such as an aluminum-based material.

[0129] It should be noted that the step of forming the openings AP1 , AP2 , and AP3 in the inorganic insulating layer 5 may be performed before forming the partition walls 6 or after forming the partition walls 6 .

[0130] Next, the display element DE1 is formed.

[0131] First, if Figure 5 As shown, a stacked film FL1 including an organic layer OR1, an upper electrode UE1 and a cover layer CP1 is formed. The process of forming the stacked film FL1 includes a process of forming an organic layer OR1 in contact with the lower electrode LE1 in the opening AP1, a process of forming an upper electrode UE1 covering the organic layer OR1 and in contact with the lower portion 61 of the partition wall 6, and a process of forming a cover layer CP1 located on the upper electrode UE1. In addition, the process of forming the organic layer OR1 includes a process of forming a hole injection layer, a hole transport layer, an electron blocking layer, a light emitting layer, a hole blocking layer, an electron transport layer, an electron injection layer, etc., respectively. The organic layer OR1, the upper electrode UE1 and the cover layer CP1 are respectively formed by vapor deposition using the partition wall 6 as a mask. The stacked film FL1 is cut into a plurality of parts by the overhanging partition wall 6. These organic layers OR1, the upper electrode UE1 and the cover layer CP1 are continuously formed while maintaining a vacuum environment.

[0132] Then, an inorganic insulating material is deposited to form a sealing layer SE1 on the laminate film FL1. The sealing layer SE1 is formed by CVD (Chemical Vapor Deposition). The sealing layer SE1 continuously covers the divided portions of the laminate film FL1 and the partition wall 6.

[0133] Then, if Figure 6 As shown in FIG. 1 , a resist RS patterned into a predetermined shape is formed on the sealing layer SE1 . The resist RS overlaps the sub-pixel SP1 and a part of the partition wall 6 around it.

[0134] Then, if Figure 7 As shown, etching is performed using the resist RS as a mask, and the sealing layer SE1 and the laminated film FL1 exposed from the resist RS are removed in sequence. In this etching, after the sealing layer SE1 exposed from the resist RS is removed, the cap layer CP1 exposed from the sealing layer SE1 is removed, and further, after the upper electrode UE1 exposed from the cap layer CP1 is removed, the organic layer OR1 exposed from the upper electrode UE1 is removed. As a result, the lower electrode LE2 of the sub-pixel SP2 and the lower electrode LE3 of the sub-pixel SP3 are exposed.

[0135] Then, the resist RS is removed. Thus, the display element DE1 is formed in the sub-pixel SP1.

[0136] Then, if Figure 8 As shown, a display element DE2 is formed. The steps for forming the display element DE2 are the same as the steps for forming the display element DE1. That is, an organic layer OR2 including a light-emitting layer EM2, an upper electrode UE2 and a cover layer CP2 are sequentially formed on the lower electrode LE2 to form a laminated film FL2. Thereafter, a sealing layer SE2 is formed on the laminated film FL2. Then, a resist is formed on the sealing layer SE2, and the sealing layer SE2, the cover layer CP2, the upper electrode UE2 and the organic layer OR2 are patterned by etching using the resist as a mask. After the patterning, the resist is removed. Thus, the display element DE2 is formed in the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 is exposed.

[0137] Then, if Fig. 9As shown, a display element DE3 is formed. The steps for forming the display element DE3 are the same as the steps for forming the display element DE1. That is, an organic layer OR3 including a light-emitting layer EM3, an upper electrode UE3 and a cover layer CP3 are sequentially formed on the lower electrode LE3 to form a laminated film FL3. After that, a sealing layer SE3 is formed on the laminated film FL3. Then, a resist is formed on the sealing layer SE3, and the sealing layer SE3, the cover layer CP3, the upper electrode UE3 and the organic layer OR3 are patterned by etching using the resist as a mask. After the patterning, the resist is removed. Thus, a display element DE3 is formed in the sub-pixel SP3.

[0138] Then, form Figure 3 The resin layer 13, the sealing layer 14 and the resin layer 15 are shown. Thus, the display device DSP is completed.

[0139] It should be noted that, although in the above manufacturing process, it is assumed that the display element DE1 is formed first, the display element DE2 is formed next, and the display element DE3 is formed last, the order of forming the display elements DE1, DE2, and DE3 is not limited to this example.

[0140] Next, a mother substrate for a display device (hereinafter simply referred to as a mother substrate) 100 for collectively manufacturing a plurality of display device DSPs will be described.

[0141] Fig.10 1 is a plan view showing an example of the mother substrate 100 .

[0142] The mother substrate 100 has a plurality of panel portions PP on a large substrate 10 and blank portions MP on the outside of the panel portions PP. The large substrate 10 is formed in a rectangular shape, for example. The plurality of panel portions PP are arranged in a matrix in the first direction X and the second direction Y. Each of the panel portions PP is removed by cutting the mother substrate 100 along the cutting line. Each of the removed panel portions PP corresponds to Figure 1 The display panel PNL shown includes a display area DA and a peripheral area SA.

[0143] The blank portion MP has a plurality of pads PD electrically connected to a test element group (Test Element Group) and the like, for example.

[0144] Fig.11 It is a plan view showing a configuration example of the pad PD or the terminal TE.

[0145] For example, the pad PD is equivalent to Fig.10 The pad PD of the blank portion MP shown. The terminal TE is equivalent to, for example, Figure 1 The terminals TE of the peripheral area SA are shown.

[0146] The organic insulating layer IL includes, for example, Figure 3 As described later, the organic insulating layer IL may be a single layer of the insulating layer 12 or other insulating layers, or a multilayer of the insulating layer 12 and other insulating layers. The organic insulating layer IL is disposed in each of the panel portion PP and also in the blank portion MP. It should be noted that the inorganic insulating layer 5, which is omitted from the illustration, is also disposed not only in the panel portion PP but also in the blank portion MP.

[0147] The metal layer MT shown by the dotted line corresponds to, for example, the electrode of the pad PD or the terminal TE. The metal layer MT overlaps with the recess DP of the organic insulating layer IL in a plan view. The recess DP corresponds to the through-portion of the organic insulating layer IL, exposing a portion of the metal layer MT. The peripheral portion of the metal layer MT is covered by the organic insulating layer IL or the inorganic insulating layer 5.

[0148] Next, about following Fig.11 The cross-sectional structure of the mother substrate 100 along the CD line is shown to illustrate several configuration examples.

[0149] Fig.12 1 is a cross-sectional view showing a configuration example of the mother substrate 100 .

[0150] The insulating layer 111 is an inorganic insulating layer and is disposed on the substrate 10. The wiring layer 112 is provided on the insulating layer 111. The insulating layer 113 is an inorganic insulating layer and is disposed on the wiring layer 112. The insulating layer 113 exposes a portion of the wiring layer 112. The insulating layer 114 is an organic insulating layer and is disposed on the insulating layer 113. The metal layer MT is in contact with the wiring layer 112. In addition, the peripheral portion of the metal layer MT is disposed on the insulating layer 114. Thus, the metal layer MT is electrically connected to the wiring layer 112. The insulating layer 111, the wiring layer 112, the insulating layer 113, the insulating layer 114, and the metal layer MT are included in Figure 3 In the circuit layer 11 shown. It should be noted that the circuit layer 11 may include an insulating layer and a conductive layer in addition to the layers shown in the figure.

[0151] The insulating layer 12 is an organic insulating layer, and is disposed on the insulating layer 114 and the metal layer MT. The insulating layer 114 is set back from the insulating layer 12 and is covered by the insulating layer 12. The peripheral portion of the metal layer MT is covered by the insulating layer 12.

[0152] The organic insulating layer IL includes an insulating layer 114 and an insulating layer 12. The organic insulating layer IL includes a flat upper surface TS, a recessed portion DP that is recessed relative to the upper surface TS, and a slope SS that surrounds the recessed portion DP. The recessed portion DP is a through portion of the insulating layer 12 formed in a manner that exposes the metal layer MT. The upper surface TS is the upper surface of the insulating layer 12. The slope SS is a slope connected to the upper surface of the insulating layer 12. An edge portion DPE of the recessed portion DP is defined as an edge portion of the insulating layer 12. An edge portion TSE of the upper surface TS is defined as an intersection of the upper surface TS and the slope SS.

[0153] The inorganic insulating layer 5 covers the insulating layer 12 and is in contact with the metal layer MT in the recess DP. The inorganic insulating layer 5 has an opening OP overlapping the recess DP. The opening OP is a through portion of the inorganic insulating layer 5 formed to expose the metal layer MT. The area of ​​the opening OP is smaller than the area of ​​the recess DP.

[0154] The peripheral partition walls 7 are arranged so as to overlap with the upper surface TS and the recessed portion DP of the organic insulating layer IL. Each of the peripheral partition walls 7 has a lower portion 71 arranged on the inorganic insulating layer 5 and an upper portion 72 arranged on the lower portion 71. The upper portion 72 has a greater width than the lower portion 71. Both ends of the upper portion 72 protrude from the side surfaces of the lower portion 71.

[0155] Thus, the surrounding walls 7 are Figure 3 The peripheral partition wall 7 can be formed in the same process as the partition wall 6. In this case, the lower portion 71 is formed of the same material as the lower portion 61, and the upper portion 72 is formed of the same material as the upper portion 62.

[0156] When focusing on the peripheral partition wall (first partition wall) 7 located in the recessed portion DP, the distance D1 from the edge of the upper portion 72 to the edge DPE of the recessed portion DP is 50 μm or more.

[0157] When focusing on peripheral partition wall (second partition wall) 7 located above top surface TS, distance D2 from edge portion of upper portion 72 to edge portion TSE of top surface TS is 20 μm or more.

[0158] Fig.13 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0159] and Fig.12 Compared with the configuration example shown, Fig.13 The illustrated configuration example is different in that the organic insulating layer IL is a single layer body of the insulating layer 114 at least in the periphery of the recessed portion DP.

[0160] The recessed portion DP of the organic insulating layer IL is a through portion of the insulating layer 114 formed in such a manner as to expose the metal layer MT. The upper surface TS is the upper surface of the insulating layer 114. The inclined surface SS is an inclined surface connected to the upper surface of the insulating layer 114. The edge portion DPE of the recessed portion DP is defined as an edge portion of the insulating layer 114. The edge portion TSE of the upper surface TS is defined as an intersection portion of the upper surface TS and the inclined surface SS.

[0161] The inorganic insulating layer 5 is provided on the insulating layer 114 and the metal layer MT. The peripheral portion of the metal layer MT is covered with the inorganic insulating layer 5. The opening OP of the inorganic insulating layer 5 exposes the metal layer MT.

[0162] The plurality of peripheral partition walls 7 are arranged so as to overlap with the upper surface TS of the organic insulating layer IL and the recessed portion DP, and all of them have an overhanging shape.

[0163] The distance D1 with respect to the peripheral partition wall 7 located in the recessed portion DP and the distance D2 with respect to the peripheral partition wall 7 located above the upper surface TS are as described above.

[0164] Fig.14 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0165] and Fig.12 Compared with the configuration example shown, Fig.14 The illustrated configuration example is different in that the organic insulating layer IL is a single layer body of the insulating layer 12 at least in the periphery of the recessed portion DP.

[0166] The recessed portion DP of the organic insulating layer IL is a through portion of the insulating layer 12 formed in such a manner as to expose the metal layer MT. The upper surface TS is the upper surface of the insulating layer 12. The inclined surface SS is an inclined surface connected to the upper surface of the insulating layer 12. The edge portion DPE of the recessed portion DP is defined as an edge portion of the insulating layer 12. The edge portion TSE of the upper surface TS is defined as an intersection portion of the upper surface TS and the inclined surface SS.

[0167] The inorganic insulating layer 5 is disposed on the insulating layer 12 and the metal layer MT. The peripheral portion of the metal layer MT is covered with the inorganic insulating layer 5. The opening OP of the inorganic insulating layer 5 exposes the metal layer MT.

[0168] The plurality of peripheral partition walls 7 are arranged so as to overlap with the upper surface TS of the organic insulating layer IL and the recessed portion DP, and all of them have an overhanging shape.

[0169] The distance D1 with respect to the peripheral partition wall 7 located in the recessed portion DP and the distance D2 with respect to the peripheral partition wall 7 located above the upper surface TS are as described above.

[0170] Fig.15 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0171] and Fig.12 Compared with the configuration example shown, Fig.15 The structure example shown is different in that the organic insulating layer IL has a step-shaped cross section.

[0172] The insulating layer 114 extends toward the recessed portion DP beyond the insulating layer 12. The insulating layer 12 is disposed on the insulating layer 114. The peripheral portion of the metal layer MT is located between the insulating layer 114 and the insulating layer 12.

[0173] The organic insulating layer IL has an upper surface TS1 located at the top, an upper surface TS2 located below the upper surface TS1, and a slope SS between the upper surface TS1 and the upper surface TS2 in the periphery of the recess DP. The upper surface TS2 is located between the upper surface TS1 and the recess DP. The upper surfaces TS1 and TS2 are the upper surfaces of the insulating layer 12. The slope SS is the slope of the insulating layer 12. The insulating layer 12 having such a stepped cross-section is formed by adjusting the exposure amount corresponding to each portion.

[0174] The recess DP of the organic insulating layer IL is a through portion of the insulating layer 114 formed to expose the metal layer MT. The edge DPE of the recess DP is defined as the edge of the insulating layer 114. The edge TSE of the upper surface TS1 is defined as the intersection of the upper surface TS1 and the slant surface SS.

[0175] The inorganic insulating layer 5 is disposed on the insulating layer 12, the metal layer MT, and the insulating layer 114. The opening OP of the inorganic insulating layer 5 exposes the metal layer MT.

[0176] The plurality of peripheral partition walls 7 are arranged so as to overlap with the upper surface TS1 of the organic insulating layer IL and the recessed portion DP, and all of them have an overhanging shape.

[0177] The distance D1 with respect to the peripheral partition wall 7 located in the recessed portion DP and the distance D2 with respect to the peripheral partition wall 7 located above the upper surface TS1 are as described above.

[0178] Fig.16 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0179] and Fig.12 Compared with the configuration example shown, Fig.16 The structure example shown is different in that the organic insulating layer IL has a step-shaped cross section.

[0180] The insulating layer 114 is set back from the insulating layer 12 and is covered by the insulating layer 12. The peripheral portion of the metal layer MT is located between the insulating layer 114 and the insulating layer 12.

[0181] The organic insulating layer IL has an upper surface TS1, an upper surface TS2, and a slant surface SS in the periphery of the recess DP. The upper surface TS2 is located between the upper surface TS1 and the recess DP. The upper surfaces TS1 and TS2 are the upper surfaces of the insulating layer 12. The slant surface SS is the slant surface of the insulating layer 12. The insulating layer 12 having such a stepped cross-section is formed by adjusting the exposure amount corresponding to each portion.

[0182] The recess DP of the organic insulating layer IL is a through portion of the insulating layer 12 formed to expose the metal layer MT. The edge DPE of the recess DP is defined as the edge of the insulating layer 12. The edge TSE of the upper surface TS1 is defined as the intersection of the upper surface TS1 and the slant surface SS.

[0183] The inorganic insulating layer 5 is disposed on the insulating layer 12 and the metal layer MT. The opening OP of the inorganic insulating layer 5 exposes the metal layer MT.

[0184] The plurality of peripheral partition walls 7 are arranged so as to overlap with the upper surface TS1 of the organic insulating layer IL and the recessed portion DP, and all of them have an overhanging shape.

[0185] The distance D1 with respect to the peripheral partition wall 7 located in the recessed portion DP and the distance D2 with respect to the peripheral partition wall 7 located above the upper surface TS1 are as described above.

[0186] Fig.17 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0187] and Fig.12 Compared with the configuration example shown, Fig.17 The structure example shown is different in that the organic insulating layer IL has a step-shaped cross section.

[0188] The insulating layer 114 extends toward the recessed portion DP beyond the insulating layer 12. The insulating layer 12 is disposed on the insulating layer 114. The peripheral portion of the metal layer MT is located between the insulating layer 114 and the insulating layer 12.

[0189] The organic insulating layer IL has an upper surface TS and a slant surface SS. The upper surface TS is the upper surface of the insulating layer 12. The slant surface SS is the slant surface of the insulating layer 12.

[0190] The recess DP of the organic insulating layer IL is a through portion of the insulating layer 114 formed to expose the metal layer MT. The edge DPE of the recess DP is defined as the edge of the insulating layer 114. The edge TSE of the upper surface TS is defined as the intersection of the upper surface TS and the slant surface SS.

[0191] The inorganic insulating layer 5 is disposed on the insulating layer 12, the metal layer MT, and the insulating layer 114. The opening OP of the inorganic insulating layer 5 exposes the metal layer MT.

[0192] The plurality of peripheral partition walls 7 are arranged so as to overlap with the upper surface TS of the organic insulating layer IL and the recessed portion DP, and all of them have an overhanging shape.

[0193] The distance D1 with respect to the peripheral partition wall 7 located in the recessed portion DP and the distance D2 with respect to the peripheral partition wall 7 located above the upper surface TS are as described above.

[0194] Fig.18 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0195] and Fig.12 Compared with the configuration example shown, Fig.18 The illustrated configuration example is different in that the organic insulating layer IL is a single layer and has a step-shaped cross section at least in the periphery of the recessed portion DP.

[0196] The insulating layer 12 is disposed on the insulating layer 113 . The peripheral portion of the metal layer MT is located between the insulating layer 113 and the insulating layer 12 .

[0197] The organic insulating layer IL has an upper surface TS1, an upper surface TS2, and a slant surface SS in the periphery of the recess DP. The upper surface TS2 is located between the upper surface TS1 and the recess DP. The upper surfaces TS1 and TS2 are the upper surfaces of the insulating layer 12. The slant surface SS is the slant surface of the insulating layer 12. The insulating layer 12 having such a stepped cross-section is formed by adjusting the exposure amount corresponding to each portion.

[0198] The recess DP of the organic insulating layer IL is a through portion of the insulating layer 12 formed to expose the metal layer MT. The edge DPE of the recess DP is defined as the edge of the insulating layer 12. The edge TSE of the upper surface TS1 is defined as the intersection of the upper surface TS1 and the slant surface SS.

[0199] The inorganic insulating layer 5 is disposed on the insulating layer 12 and the metal layer MT. The opening OP of the inorganic insulating layer 5 exposes the metal layer MT.

[0200] The plurality of peripheral partition walls 7 are arranged so as to overlap with the upper surface TS1 of the organic insulating layer IL and the recessed portion DP, and all of them have an overhanging shape.

[0201] The distance D1 with respect to the peripheral partition wall 7 located in the recessed portion DP and the distance D2 with respect to the peripheral partition wall 7 located above the upper surface TS1 are as described above.

[0202] Fig.19 It is shown Fig.10 FIG. 1 is a plan view of a configuration example of a region 100A of a mother substrate 100 shown.

[0203] The region 100A includes one panel portion PP. In the figure, the cut lines CL indicated by the dotted lines extend, for example, along the first direction X and the second direction Y. These cut lines CL can be Figure 1 The outer shape of the display panel PNL is shown in FIG. Each of the panel portions PP includes a display area DA and a peripheral area SA.

[0204] The organic insulating layer IL is disposed in each of the panel portion PP and also in the blank portion MP. The organic insulating layer IL has a recessed portion DP along the outer shape of the panel portion PP. The cut line CL overlaps with the recessed portion DP. The recessed portion DP may be a through portion of the organic insulating layer IL or a thin-walled portion of the organic insulating layer IL. The recessed portion DP is formed in a lattice shape surrounding each of the panel portion PP. In the example shown in the figure, the recessed portion DP extends in the first direction X and the second direction Y, respectively.

[0205] If one panel portion PP is focused on, the recessed portion DP is formed in a ring shape surrounding the panel portion PP. In the panel portion PP, the display area DA overlaps with the organic insulating layer IL. In addition, a portion of the peripheral area SA also overlaps with the organic insulating layer IL.

[0206] Next, about following Fig.19 The cross-sectional structure of the mother substrate 100 along the EF line is shown to illustrate several configuration examples.

[0207] Fig. 20 1 is a cross-sectional view showing a configuration example of the mother substrate 100 .

[0208] The insulating layer 111 is an inorganic insulating layer, and is disposed on the substrate 10. The insulating layer 113 is an inorganic insulating layer, and is disposed on the insulating layer 111. The insulating layer 114 is an organic insulating layer, and is disposed on the insulating layer 113. The insulating layer 111, the insulating layer 113, and the insulating layer 114 are included in Figure 3 In the circuit layer 11 shown in the figure, it should be noted that the circuit layer 11 may include an insulating layer and a conductive layer in addition to the layers shown in the figure.

[0209] The insulating layer 12 is an organic insulating layer, and is disposed on the insulating layer 113 and the insulating layer 114. The insulating layer 114 is set back from the insulating layer 12 and is covered by the insulating layer 12.

[0210] The organic insulating layer IL includes an insulating layer 114 and an insulating layer 12. The organic insulating layer IL includes a flat upper surface TS, a recessed portion DP that is recessed relative to the upper surface TS, and a slope SS that surrounds the recessed portion DP. The recessed portion DP is a through portion of the insulating layer 12 formed in such a manner as to expose the insulating layer 113. The upper surface TS is the upper surface of the insulating layer 12. The slope SS is a slope connected to the upper surface of the insulating layer 12. An edge portion DPE of the recessed portion DP is defined as an edge portion of the insulating layer 12. An edge portion TSE of the upper surface TS is defined as an intersection of the upper surface TS and the slope SS.

[0211] The inorganic insulating layer 5 covers the insulating layer 12 , and covers the insulating layer 113 in the recessed portion DP.

[0212] The peripheral partition walls 7 are arranged so as to overlap with the upper surface TS and the recessed portion DP of the organic insulating layer IL. Each of the peripheral partition walls 7 has a lower portion 71 arranged on the inorganic insulating layer 5 and an upper portion 72 arranged on the lower portion 71. Figure 3 The partition walls 6 shown are also in an overhanging shape. The peripheral partition walls 7 can be formed in the same process as the partition walls 6 .

[0213] When focusing on the peripheral partition wall (first partition wall) 7 located in the recessed portion DP, the distance D1 from the edge of the upper portion 72 to the edge DPE of the recessed portion DP is 50 μm or more.

[0214] When focusing on peripheral partition wall (second partition wall) 7 located above top surface TS, distance D2 from edge portion of upper portion 72 to edge portion TSE of top surface TS is 20 μm or more.

[0215] Fig.21 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0216] and Fig. 20 Compared with the configuration example shown, Fig.21 The illustrated configuration example is different in that the organic insulating layer IL is a single layer body of the insulating layer 114 at least in the periphery of the recessed portion DP.

[0217] The recessed portion DP of the organic insulating layer IL is a through portion of the insulating layer 114 formed in a manner to expose the insulating layer 113. The upper surface TS is the upper surface of the insulating layer 114. The inclined surface SS is an inclined surface connected to the upper surface of the insulating layer 114. The edge portion DPE of the recessed portion DP is defined as an edge portion of the insulating layer 114. The edge portion TSE of the upper surface TS is defined as an intersection of the upper surface TS and the inclined surface SS.

[0218] The inorganic insulating layer 5 covers the insulating layer 114 , and covers the insulating layer 113 in the recessed portion DP.

[0219] The plurality of peripheral partition walls 7 are arranged so as to overlap with the upper surface TS of the organic insulating layer IL and the recessed portion DP, and all of them have an overhanging shape.

[0220] The distance D1 with respect to the peripheral partition wall 7 located in the recessed portion DP and the distance D2 with respect to the peripheral partition wall 7 located above the upper surface TS are as described above.

[0221] Fig. 22 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0222] and Fig. 20 Compared with the configuration example shown, Fig. 22 The illustrated configuration example is different in that the organic insulating layer IL is a single layer body of the insulating layer 12 at least in the periphery of the recessed portion DP.

[0223] The recessed portion DP of the organic insulating layer IL is a through portion of the insulating layer 12 formed in a manner to expose the insulating layer 113. The upper surface TS is the upper surface of the insulating layer 12. The inclined surface SS is an inclined surface connected to the upper surface of the insulating layer 12. The edge portion DPE of the recessed portion DP is defined as an edge portion of the insulating layer 12. The edge portion TSE of the upper surface TS is defined as an intersection of the upper surface TS and the inclined surface SS.

[0224] The inorganic insulating layer 5 covers the insulating layer 12 , and covers the insulating layer 113 in the recessed portion DP.

[0225] The plurality of peripheral partition walls 7 are arranged so as to overlap with the upper surface TS of the organic insulating layer IL and the recessed portion DP, and all of them have an overhanging shape.

[0226] The distance D1 with respect to the peripheral partition wall 7 located in the recessed portion DP and the distance D2 with respect to the peripheral partition wall 7 located above the upper surface TS are as described above.

[0227] Fig.23 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0228] and Fig. 20 Compared with the configuration example shown, Fig.23 The structure example shown is different in that the organic insulating layer IL has a step-shaped cross section.

[0229] The insulating layer 114 extends toward the recessed portion DP beyond the insulating layer 12. The insulating layer 12 is disposed on the insulating layer 114 so that the insulating layer 114 near the recessed portion DP is exposed.

[0230] The organic insulating layer IL has an upper surface TS1 located at the top, an upper surface TS2 located below the upper surface TS1, and a slope SS between the upper surface TS1 and the upper surface TS2 in the periphery of the recess DP. The upper surface TS2 is located between the upper surface TS1 and the recess DP. The upper surfaces TS1 and TS2 are the upper surfaces of the insulating layer 12. The slope SS is the slope of the insulating layer 12. The insulating layer 12 having such a stepped cross-section is formed by adjusting the exposure amount corresponding to each portion.

[0231] The recess DP of the organic insulating layer IL is a through portion of the insulating layer 114 formed to expose the insulating layer 113. The edge DPE of the recess DP is defined as the edge of the insulating layer 114. The edge TSE of the upper surface TS1 is defined as the intersection of the upper surface TS1 and the slant surface SS.

[0232] The inorganic insulating layer 5 covers the insulating layer 12 and the insulating layer 114 , and covers the insulating layer 113 in the recessed portion DP.

[0233] The plurality of peripheral partition walls 7 are arranged so as to overlap with the upper surface TS1 of the organic insulating layer IL and the recessed portion DP, and all of them have an overhanging shape.

[0234] The distance D1 with respect to the peripheral partition wall 7 located in the recessed portion DP and the distance D2 with respect to the peripheral partition wall 7 located above the upper surface TS1 are as described above.

[0235] Fig.24 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0236] and Fig. 20 Compared with the configuration example shown, Fig.24 The structure example shown is different in that the organic insulating layer IL has a step-shaped cross section.

[0237] The insulating layer 114 is set back from the insulating layer 12 and is covered by the insulating layer 12 .

[0238] The organic insulating layer IL has an upper surface TS1, an upper surface TS2, and a slant surface SS in the periphery of the recess DP. The upper surface TS2 is located between the upper surface TS1 and the recess DP. The upper surfaces TS1 and TS2 are the upper surfaces of the insulating layer 12. The slant surface SS is the slant surface of the insulating layer 12. The insulating layer 12 having such a stepped cross-section is formed by adjusting the exposure amount corresponding to each portion.

[0239] The recess DP of the organic insulating layer IL is a through portion of the insulating layer 12 formed to expose the insulating layer 113. The edge DPE of the recess DP is defined as the edge of the insulating layer 12. The edge TSE of the upper surface TS1 is defined as the intersection of the upper surface TS1 and the slant surface SS.

[0240] The inorganic insulating layer 5 covers the insulating layer 12 , and covers the insulating layer 113 in the recessed portion DP.

[0241] The plurality of peripheral partition walls 7 are arranged so as to overlap with the upper surface TS1 of the organic insulating layer IL and the recessed portion DP, and all of them have an overhanging shape.

[0242] The distance D1 with respect to the peripheral partition wall 7 located in the recessed portion DP and the distance D2 with respect to the peripheral partition wall 7 located above the upper surface TS1 are as described above.

[0243] Fig.25 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0244] and Fig. 20 Compared with the configuration example shown, Fig.25 The structure example shown is different in that the organic insulating layer IL has a step-shaped cross section.

[0245] The insulating layer 114 extends toward the recessed portion DP beyond the insulating layer 12 . The insulating layer 12 is disposed on the insulating layer 114 .

[0246] The organic insulating layer IL has an upper surface TS and a slant surface SS. The upper surface TS is the upper surface of the insulating layer 12. The slant surface SS is the slant surface of the insulating layer 12.

[0247] The recess DP of the organic insulating layer IL is a through portion of the insulating layer 114 formed to expose the insulating layer 113. The edge DPE of the recess DP is defined as the edge of the insulating layer 114. The edge TSE of the upper surface TS is defined as the intersection of the upper surface TS and the slant surface SS.

[0248] The inorganic insulating layer 5 covers the insulating layer 12 and the insulating layer 114 , and covers the insulating layer 113 in the recessed portion DP.

[0249] The plurality of peripheral partition walls 7 are arranged so as to overlap with the upper surface TS of the organic insulating layer IL and the recessed portion DP, and all of them have an overhanging shape.

[0250] The distance D1 with respect to the peripheral partition wall 7 located in the recessed portion DP and the distance D2 with respect to the peripheral partition wall 7 located above the upper surface TS are as described above.

[0251] Fig.26 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0252] and Fig. 20 Compared with the configuration example shown, Fig.26 The illustrated configuration example is different in that the organic insulating layer IL is a single layer and has a step-shaped cross section at least in the periphery of the recessed portion DP.

[0253] The insulating layer 12 is disposed on the insulating layer 113 .

[0254] The organic insulating layer IL has an upper surface TS1, an upper surface TS2, and a slant surface SS in the periphery of the recess DP. The upper surface TS2 is located between the upper surface TS1 and the recess DP. The upper surfaces TS1 and TS2 are the upper surfaces of the insulating layer 12. The slant surface SS is the slant surface of the insulating layer 12. The insulating layer 12 having such a stepped cross-section is formed by adjusting the exposure amount corresponding to each portion.

[0255] The recess DP of the organic insulating layer IL is a through portion of the insulating layer 12 formed to expose the insulating layer 113. The edge DPE of the recess DP is defined as the edge of the insulating layer 12. The edge TSE of the upper surface TS1 is defined as the intersection of the upper surface TS1 and the slant surface SS.

[0256] The inorganic insulating layer 5 covers the insulating layer 12 , and covers the insulating layer 113 in the recessed portion DP.

[0257] The plurality of peripheral partition walls 7 are arranged so as to overlap with the upper surface TS1 of the organic insulating layer IL and the recessed portion DP, and all of them have an overhanging shape.

[0258] The distance D1 with respect to the peripheral partition wall 7 located in the recessed portion DP and the distance D2 with respect to the peripheral partition wall 7 located above the upper surface TS1 are as described above.

[0259] Fig. 27 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0260] and Fig. 20 Compared with the configuration example shown, Fig. 27 The configuration example shown is different in that the recessed portion DP of the organic insulating layer IL is a thin-walled portion.

[0261] The insulating layer 114 is disposed on the insulating layer 113 . The insulating layer 12 covers the insulating layer 113 and the insulating layer 114 .

[0262] The organic insulating layer IL includes an insulating layer 114 and an insulating layer 12. The organic insulating layer IL includes a flat upper surface TS1, a recessed portion DP that is recessed relative to the upper surface TS1, a flat upper surface TS2 that is located below the upper surface TS1, and a slope SS that is located between the upper surface TS1 and the upper surface TS2 and surrounds the recessed portion DP. The upper surface TS2 is equivalent to the bottom surface of the recessed portion DP. The recessed portion DP is equivalent to a thin-walled portion in the organic insulating layer IL that is formed only by the insulating layer 12. In addition, in the recessed portion DP, the insulating layer 113 is not exposed from the organic insulating layer IL.

[0263] The thickness T0 of the organic insulating layer IL is the sum of the thicknesses of the insulating layer 114 and the insulating layer 12, which is equivalent to the length from the upper surface of the insulating layer 113 to the upper surface TS1 along the third direction Z. The thickness T2 of the organic insulating layer IL is equivalent to the thickness of the thin-walled portion of the organic insulating layer IL forming the recess DP, and is the thickness of only the insulating layer 12 excluding the insulating layer 114. That is, the thickness T2 is equivalent to the length from the upper surface of the insulating layer 113 to the upper surface TS2 along the third direction Z. The thickness T2 is smaller than the thickness T0 (T0>T2). In addition, the thickness T1 of the insulating layer 12 overlapping with the insulating layer 114 is substantially equal to the thickness T2 (T1≈T2).

[0264] The upper surfaces TS1 and TS2 are the upper surfaces of the insulating layer 12. The slant surface SS is the slant surface of the insulating layer 12. The edge portion DPE of the recess DP is defined as the intersection of the upper surface TS2 and the slant surface SS. The edge portion TSE of the upper surface TS1 is defined as the intersection of the upper surface TS1 and the slant surface SS.

[0265] The inorganic insulating layer 5 covers the insulating layer 12 .

[0266] The plurality of peripheral partition walls 7 are arranged so as to overlap with the upper surface TS1 of the organic insulating layer IL and the recessed portion DP, and all of them have an overhanging shape.

[0267] The distance D1 related to the peripheral partition wall 7 located above the upper surface TS2 or in the recessed portion DP and the distance D2 related to the peripheral partition wall 7 located above the upper surface TS1 are as described above.

[0268] Fig.28 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0269] and Fig. 27 Compared with the configuration example shown, Fig.28 The illustrated configuration example is different in that the organic insulating layer IL has a step-shaped cross section and the recessed portion DP of the organic insulating layer IL is a thin-walled portion.

[0270] The insulating layer 114 is disposed on the insulating layer 113 . The insulating layer 12 is disposed on the insulating layer 114 .

[0271] The organic insulating layer IL has an upper surface TS1 located at the top, an upper surface TS2 located below the upper surface TS1, and a slope SS between the upper surface TS1 and the upper surface TS2 in the periphery of the recess DP. The upper surface TS2 is located between the upper surface TS1 and the recess DP. The upper surfaces TS1 and TS2 are the upper surfaces of the insulating layer 12. The slope SS is the slope of the insulating layer 12. The insulating layer 12 having such a stepped cross-section is formed by adjusting the exposure amount corresponding to each portion.

[0272] The recessed portion DP of the organic insulating layer IL is a through portion of the insulating layer 12 formed in such a manner as to expose the insulating layer 114, and corresponds to a thin-walled portion of the organic insulating layer IL formed only by the insulating layer 114. In addition, in the recessed portion DP, the insulating layer 113 is not exposed from the organic insulating layer IL. The edge portion DPE of the recessed portion DP is defined as the edge portion of the insulating layer 12. The edge portion TSE of the upper surface TS1 is defined as the intersection of the upper surface TS1 and the inclined surface SS.

[0273] The inorganic insulating layer 5 covers the insulating layer 12 and the insulating layer 114 .

[0274] The plurality of peripheral partition walls 7 are arranged so as to overlap with the upper surface TS1 of the organic insulating layer IL and the recessed portion DP, and all of them have an overhanging shape.

[0275] The distance D1 related to the peripheral partition wall 7 located above the insulating layer 114 or in the recessed portion DP and the distance D2 related to the peripheral partition wall 7 located above the upper surface TS1 are as described above.

[0276] Fig.29 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0277] and Fig. 20 Compared with the configuration example shown, Fig.29 The configuration example shown is different in that the recessed portion DP of the organic insulating layer IL is a thin-walled portion.

[0278] The insulating layer 114 and the insulating layer 113 are covered with the insulating layer 12 .

[0279] The organic insulating layer IL has an upper surface TS1, an upper surface TS2, and a slant surface SS. The upper surface TS2 corresponds to the bottom surface of the recess DP. The recess DP corresponds to a thin-walled portion of the organic insulating layer IL formed only by the insulating layer 12. In addition, in the recess DP, the insulating layer 113 is not exposed from the organic insulating layer IL.

[0280] The thickness T2 is smaller than the thickness T0 (T0>T2). In addition, the thickness T2 is smaller than the thickness T1 (T1>T2). The upper surfaces TS1 and TS2 are the upper surfaces of the insulating layer 12. The slope SS is the slope of the insulating layer 12. The insulating layer 12 having such a stepped cross-section is formed by adjusting the exposure amount corresponding to each portion.

[0281] The edge portion DPE of the recessed portion DP is defined as an intersection of the upper surface TS2 and the slant surface SS. The edge portion TSE of the upper surface TS1 is defined as an intersection of the upper surface TS1 and the slant surface SS.

[0282] The inorganic insulating layer 5 covers the insulating layer 12 .

[0283] The plurality of peripheral partition walls 7 are arranged so as to overlap with the upper surface TS1 of the organic insulating layer IL and the recessed portion DP, and all of them have an overhanging shape.

[0284] The distance D1 related to the peripheral partition wall 7 located above the upper surface TS2 or in the recessed portion DP and the distance D2 related to the peripheral partition wall 7 located above the upper surface TS1 are as described above.

[0285] Fig.30 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0286] and Fig. 20 Compared with the configuration example shown, Fig.30 The configuration example shown is different in that the recessed portion DP of the organic insulating layer IL is a thin-walled portion.

[0287] The insulating layer 114 is disposed on the insulating layer 113 . The insulating layer 12 is disposed on the insulating layer 114 .

[0288] The organic insulating layer IL has an upper surface TS and a slant surface SS. The upper surface TS is the upper surface of the insulating layer 12. The slant surface SS is the slant surface of the insulating layer 12.

[0289] The recessed portion DP of the organic insulating layer IL is a through portion of the insulating layer 12 formed in such a manner as to expose the insulating layer 114, and corresponds to a thin-walled portion of the organic insulating layer IL formed only of the insulating layer 114. In addition, in the recessed portion DP, the insulating layer 113 is not exposed from the organic insulating layer IL. The edge portion DPE of the recessed portion DP is defined as the edge portion of the insulating layer 12. The edge portion TSE of the upper surface TS is defined as the intersection of the upper surface TS and the inclined surface SS.

[0290] The inorganic insulating layer 5 covers the insulating layer 12 and the insulating layer 114 .

[0291] The plurality of peripheral partition walls 7 are arranged so as to overlap with the upper surface TS of the organic insulating layer IL and the recessed portion DP, and all of them have an overhanging shape.

[0292] The distance D1 related to the peripheral partition wall 7 located above the insulating layer 114 or in the recessed portion DP and the distance D2 related to the peripheral partition wall 7 located above the top surface TS are as described above.

[0293] Fig.31 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0294] and Fig. 20 Compared with the configuration example shown, Fig.31 The illustrated configuration example is different in that the recessed portion DP of the organic insulating layer IL is a thin-walled portion, and the organic insulating layer IL is a single layer body and has a stepped cross section at least in the periphery of the recessed portion DP.

[0295] The insulating layer 12 is disposed on the insulating layer 113 .

[0296] The organic insulating layer IL has an upper surface TS1, an upper surface TS2, and a slant surface SS. The upper surface TS2 corresponds to the bottom surface of the recess DP. The recess DP corresponds to a thin-walled portion of the organic insulating layer IL formed only by the insulating layer 12. In addition, in the recess DP, the insulating layer 113 is not exposed from the organic insulating layer IL.

[0297] The thickness T0 of the organic insulating layer IL is equivalent to the thickness of the insulating layer 12 from the upper surface of the insulating layer 113 to the upper surface TS1 along the third direction Z. The thickness T2 of the organic insulating layer IL is the thickness of the thin-walled portion of the organic insulating layer IL forming the recess DP, and is equivalent to the thickness of the insulating layer 12 from the upper surface of the insulating layer 113 to the upper surface TS2 along the third direction Z. The thickness T2 is smaller than the thickness T0 (T0>T2).

[0298] The upper surfaces TS1 and TS2 are the upper surfaces of the insulating layer 12. The inclined surface SS is the inclined surface of the insulating layer 12. The insulating layer 12 having such a stepped cross-section is formed by adjusting the exposure amount corresponding to each portion. The edge portion DPE of the recessed portion DP is defined as the intersection of the upper surface TS2 and the inclined surface SS. The edge portion TSE of the upper surface TS1 is defined as the intersection of the upper surface TS1 and the inclined surface SS.

[0299] The inorganic insulating layer 5 covers the insulating layer 12 .

[0300] The plurality of peripheral partition walls 7 are arranged so as to overlap with the upper surface TS1 of the organic insulating layer IL and the recessed portion DP, and all of them have an overhanging shape.

[0301] The distance D1 related to the peripheral partition wall 7 located above the upper surface TS2 or in the recessed portion DP and the distance D2 related to the peripheral partition wall 7 located above the upper surface TS1 are as described above.

[0302] about Figures 20 to 31 In the various configuration examples shown, the inorganic insulating layer 5 may also be Fig.12 The illustrated configuration example also has an opening OP overlapping with the recessed portion DP.

[0303] Fig.32 This is a diagram for explaining one of the effects of this embodiment.

[0304] In the mother substrate 100, the recessed portion DP of the organic insulating layer IL includes a portion where the insulating layer 114 and the insulating layer 12 are missing, a portion where the insulating layer 12 is missing and the insulating layer 114 remains, and a portion where the insulating layer 114 is missing and the insulating layer 12 remains. It should be noted that in the drawings, elements other than the organic insulating layer IL, the peripheral partition wall 7, and the resist RS are omitted from illustration.

[0305] For example, in the formation Figure 6 The process of applying the resist RS shown in the figure includes a step of applying the liquid resist RS. The arrow AD in the figure indicates the direction in which the resist RS is applied.

[0306] In the recess DP of the organic insulating layer IL, the peripheral partition wall 7 is arranged at a distance D1 from the edge DPE of the recess DP. As described above, the distance D1 is greater than 50 μm. Therefore, when the resist RS is applied to the recess DP, the resist RS flows into the area between the peripheral partition wall 7 and the inclined surface of the organic insulating layer IL (the area near the edge DPE), and spreads while contacting the peripheral partition wall 7. As a result, the formation of undesirable voids in the resist RS is suppressed. In other words, Figure 7 As shown, the area to be protected during subsequent etching can be reliably covered with the resist RS.

[0307] It should be noted that when the distance D1 is less than 50 μm, the present inventors have confirmed that when the resist RS flows into the recess DP, the resist RS is less likely to fill below the upper portion 72 of the peripheral partition wall 7 , and a void is likely to be formed around the peripheral partition wall 7 .

[0308] In the upper surface TS of the organic insulating layer IL, the peripheral partition wall 7 is arranged at a distance D2 from the edge portion TSE of the upper surface TS. As described above, the distance D2 is 20 μm or more. Thus, when the resist RS is applied, the resist RS flows into the recess DP and spreads while contacting the peripheral partition wall 7 on the upper surface TS. Thus, the formation of undesirable voids in the resist RS is suppressed.

[0309] It should be noted that when the distance D2 is less than 20 μm, the inventors' research has confirmed that a large step difference is formed between the recess DP of the organic insulating layer IL and the peripheral partition wall 7 arranged on the upper surface TS, and a gap is easily formed near the edge DPE of the recess DP or around the peripheral partition wall 7.

[0310] When voids are formed in the resist RS, the voids may expand and break in a decompressed environment for drying the resist RS. In this case, a portion of the resist RS is lost, and the area to be protected is exposed from the resist RS. Therefore, etching is excessively performed, and desired patterning cannot be performed.

[0311] According to this embodiment, when forming the display element DE1, the defect of the resist RS can be suppressed, and the sealing layer SE1 and the laminated film FL1 can be patterned into a desired shape. In addition, when forming the display element DE2, the sealing layer SE2 and the laminated film FL2 can be patterned into a desired shape. In addition, when forming the display element DE3, the sealing layer SE3 and the laminated film FL3 can be patterned into a desired shape. Therefore, the reduction in reliability can be suppressed.

[0312] Fig.33 1 is a plan view showing an example of the peripheral partition wall 7 arranged in the recessed portion DP of the organic insulating layer IL.

[0313] A plurality of peripheral partition walls 7 are arranged in the recessed portion DP. In a plan view, each of the peripheral partition walls 7 is formed in a lattice shape. Figure 2 The lattice-shaped partition walls 6 shown in the figure are formed in the same pattern. In addition, the plurality of peripheral partition walls 7 are arranged in the first direction X and the second direction Y and are separated from each other. It should be noted that, although not described in detail here, as described above, the plurality of peripheral partition walls 7 are arranged at a position away from the edge portion DPE of the recessed portion DP by a distance D1.

[0314] The arrow ADX in the figure indicates the coating direction of the resist RS along the first direction X, and the arrow ADY indicates the coating direction of the resist RS along the second direction Y.

[0315] When the resist RS is applied along the first direction X, the resist RS flows into the recessed portion DP. At this time, the resist RS is not blocked by the peripheral partition walls 7, but passes between the peripheral partition walls 7 arranged in the second direction Y and spreads while contacting the peripheral partition walls 7. In addition, the resist RS fills the area surrounded by the peripheral partition walls 7. Thus, the formation of undesirable voids in the resist RS is suppressed.

[0316] When the resist RS is applied along the second direction Y, the resist RS is not blocked by the peripheral partition walls 7, but passes between the peripheral partition walls 7 arranged in the first direction X and spreads while contacting the peripheral partition walls 7. In addition, the resist RS fills the area surrounded by the peripheral partition walls 7. Thus, the formation of undesirable voids in the resist RS is suppressed.

[0317] Therefore, it is possible to suppress the chipping of the resist RS and suppress the reduction in reliability.

[0318] In this way, the technique of arranging the plurality of peripheral partition walls 7 in the recessed portion DP so as to be separated from each other can be applied to all the configuration examples disclosed in this specification.

[0319] Fig.34 It is a plan view showing another configuration example of the pad PD or the terminal TE.

[0320] and Fig.11 Compared with the configuration example shown, Fig.34 The configuration example shown is different in that the inorganic insulating layer 5 has a missing portion LP outside the opening OP. The missing portion LP is a through portion of the inorganic insulating layer 5 and is formed in a ring shape when viewed from above. Such a missing portion LP can be connected to, for example, Figure 2 The opening AP1 and the like shown in the figure are formed in the same process.

[0321] A portion of the organic insulating layer IL close to the recessed portion DP overlaps with the missing portion LP. In the illustrated example, the organic insulating layer IL overlapping with the missing portion LP is exposed from the inorganic insulating layer 5. It should be noted that, in the missing portion LP, sometimes the overlapping organic insulating layer IL is not exposed, and the metal layer MT is exposed from the inorganic insulating layer 5.

[0322] The recessed portion DP corresponds to a through portion of the organic insulating layer IL, and exposes a portion of the metal layer MT. The peripheral portion of the metal layer MT is covered with the organic insulating layer IL or the inorganic insulating layer 5 .

[0323] Next, about following Fig.34 The cross-sectional structure of the mother substrate 100 along the CD line is shown in FIG. 1 to describe several configuration examples. It should be noted that, in each of the following configuration examples, the main differences are described.

[0324] Fig.35 1 is a cross-sectional view showing a configuration example of the mother substrate 100 .

[0325] and Fig.12 Compared with the configuration example shown, Fig.35 The illustrated configuration example is different in that the inorganic insulating layer 5 has a missing portion LP that overlaps with the slope SS of the organic insulating layer IL.

[0326] The organic insulating layer IL has a flat upper surface TS, a recessed portion DP recessed from the upper surface TS, and a slope SS surrounding the recessed portion DP. The recessed portion DP is a through portion of the organic insulating layer IL. The slope SS is a slope of the insulating layer 12.

[0327] The inorganic insulating layer 5 is arranged on the upper surface TS, and is arranged on the metal layer MT in the recessed portion DP. The inorganic insulating layer 5 has an opening OP overlapping with the recessed portion DP. The opening OP is a through portion of the inorganic insulating layer 5 formed in a manner to expose the metal layer MT. The missing portion LP exposes the inclined surface SS. In the example shown in the figure, the missing portion LP also exposes a portion of the upper surface TS, the edge portion TSE, and the edge portion DPE, and in the recessed portion DP, the metal layer MT is exposed between the edge portion DPE and the inorganic insulating layer 5. The missing portion LP only needs to overlap with at least a portion of the inclined surface SS.

[0328] Fig.36 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0329] and Fig.13 Compared with the configuration example shown, Fig.36 The illustrated configuration example is different in that the inorganic insulating layer 5 has a missing portion LP overlapping with the slope SS of the organic insulating layer IL. The slope SS is a slope of the insulating layer 114. The missing portion LP exposes the metal layer MT overlapping with the slope SS.

[0330] Fig.37 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0331] and Fig.14 Compared with the configuration example shown, Fig.37 The illustrated configuration example is different in that the inorganic insulating layer 5 has a missing portion LP overlapping with the slope SS of the organic insulating layer IL. The slope SS is a slope of the insulating layer 12. The missing portion LP exposes the metal layer MT overlapping with the slope SS.

[0332] Fig.38 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0333] and Fig.15 Compared with the configuration example shown, Fig.38 The illustrated configuration example is different in that the inorganic insulating layer 5 has a missing portion LP overlapping with the inclined surface SS1, the inclined surface SS2, and the inclined surface SS3 of the organic insulating layer IL. The inclined surface SS1 and the inclined surface SS2 are inclined surfaces of the insulating layer 12. The inclined surface SS3 is an inclined surface of the insulating layer 114. The missing portion LP exposes the inclined surface SS1, the inclined surface SS2, and the upper surface TS2, and exposes the metal layer MT overlapping with the inclined surface SS3.

[0334] Fig.39 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0335] and Fig.16 Compared with the configuration example shown, Fig.39 The illustrated configuration example is different in that the inorganic insulating layer 5 has a missing portion LP overlapping with the inclined surfaces SS1 and SS2 of the organic insulating layer IL. The inclined surfaces SS1 and SS2 are inclined surfaces of the insulating layer 12. The missing portion LP exposes the inclined surfaces SS1, SS2, and the upper surface TS2.

[0336] Fig.40 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0337] and Fig.17 Compared with the configuration example shown, Fig.40The illustrated configuration example is different in that the inorganic insulating layer 5 has a missing portion LP overlapping the inclined surface SS1 and the inclined surface SS3 of the organic insulating layer IL. The inclined surface SS1 is the inclined surface of the insulating layer 12. The inclined surface SS3 is the inclined surface of the insulating layer 114. The missing portion LP exposes the inclined surface SS1 and exposes the metal layer MT overlapping the inclined surface SS3.

[0338] Fig.41 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0339] and Fig.18 Compared with the configuration example shown, Fig.41 The illustrated configuration example is different in that the inorganic insulating layer 5 has a missing portion LP overlapping with the inclined surfaces SS1 and SS2 of the organic insulating layer IL. The inclined surfaces SS1 and SS2 are inclined surfaces of the insulating layer 12. The missing portion LP exposes the inclined surfaces SS1, SS2, and the upper surface TS2.

[0340] exist Figures 35 to 41 In each of the illustrated configuration examples, the peripheral partition walls 7 are arranged to overlap with the upper surface TS or upper surface TS1 of the organic insulating layer IL and overlap with the recessed portion DP, and are all overhanging. In each configuration example, the distance D1 is 50 μm or more, and the distance D2 is 20 μm or more.

[0341] Fig.42 It is shown Fig.19 1 is a plan view of another configuration example of the region 100A shown in FIG. Here, a region including the concave portion DP formed in the peripheral region SA or the blank portion MP in the region 100A is shown in an enlarged manner.

[0342] The recessed portion DP may be a penetrating portion of the organic insulating layer IL or a thin-walled portion of the organic insulating layer IL.

[0343] The missing portion LP is a through portion of the inorganic insulating layer 5 . A portion of the organic insulating layer IL close to the recessed portion DP overlaps with the missing portion LP. The organic insulating layer IL overlapping with the missing portion LP is exposed from the inorganic insulating layer 5 .

[0344] Next, about following Fig.42 The cross-sectional structure of the mother substrate 100 along the EF line is shown in FIG.

[0345] Fig.43 1 is a cross-sectional view showing a configuration example of the mother substrate 100 .

[0346] and Fig. 20 Compared with the configuration example shown, Fig.43The illustrated configuration example is different in that the inorganic insulating layer 5 has a missing portion LP that overlaps with the slope SS of the organic insulating layer IL.

[0347] The organic insulating layer IL has a flat upper surface TS, a recessed portion DP recessed from the upper surface TS, and a slope SS surrounding the recessed portion DP. The recessed portion DP is a through portion of the organic insulating layer IL. The slope SS is a slope of the insulating layer 12.

[0348] The inorganic insulating layer 5 is arranged on the upper surface TS, and is arranged on the insulating layer 113 in the recessed portion DP. The missing portion LP exposes the inclined surface SS. In the example shown in the figure, the missing portion LP also exposes a portion of the upper surface TS, the edge portion TSE, and the edge portion DPE, and the insulating layer 113 is exposed between the edge portion DPE and the inorganic insulating layer 5 in the recessed portion DP. The missing portion LP only needs to overlap with at least a portion of the inclined surface SS.

[0349] Fig.44 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0350] and Fig.21 Compared with the configuration example shown, Fig.44 The illustrated configuration example is different in that the inorganic insulating layer 5 has a missing portion LP overlapping the slope SS of the organic insulating layer IL. The slope SS is a slope of the insulating layer 114. The missing portion LP exposes the slope SS.

[0351] Fig.45 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0352] and Fig. 22 Compared with the configuration example shown, Fig.45 The illustrated configuration example is different in that the inorganic insulating layer 5 has a missing portion LP overlapping the slope SS of the organic insulating layer IL. The slope SS is a slope of the insulating layer 12. The missing portion LP exposes the slope SS.

[0353] Fig.46 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0354] and Fig.23 Compared with the configuration example shown, Fig.46 The illustrated configuration example is different in that the inorganic insulating layer 5 has a missing portion LP overlapping with the inclined surface SS1, the inclined surface SS2, and the inclined surface SS3 of the organic insulating layer IL. The inclined surface SS1 and the inclined surface SS2 are inclined surfaces of the insulating layer 12. The inclined surface SS3 is an inclined surface of the insulating layer 114. The missing portion LP exposes the inclined surface SS1, the inclined surface SS2, the upper surface TS2, and the inclined surface SS3.

[0355] Fig.472 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0356] and Fig.24 Compared with the configuration example shown, Fig.47 The illustrated configuration example is different in that the inorganic insulating layer 5 has a missing portion LP overlapping with the inclined surfaces SS1 and SS2 of the organic insulating layer IL. The inclined surfaces SS1 and SS2 are inclined surfaces of the insulating layer 12. The missing portion LP exposes the inclined surfaces SS1, SS2, and the upper surface TS2.

[0357] Fig.48 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0358] and Fig.25 Compared with the configuration example shown, Fig.48 The illustrated configuration example is different in that the inorganic insulating layer 5 has a missing portion LP overlapping with the inclined surface SS1 and the inclined surface SS3 of the organic insulating layer IL. The inclined surface SS1 is the inclined surface of the insulating layer 12. The inclined surface SS3 is the inclined surface of the insulating layer 114. The missing portion LP exposes the inclined surfaces SS1 and SS3.

[0359] Fig.49 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0360] and Fig.26 Compared with the configuration example shown, Fig.49 The illustrated configuration example is different in that the inorganic insulating layer 5 has a missing portion LP overlapping with the inclined surfaces SS1 and SS2 of the organic insulating layer IL. The inclined surfaces SS1 and SS2 are inclined surfaces of the insulating layer 12. The missing portion LP exposes the inclined surfaces SS1, SS2, and the upper surface TS2.

[0361] Fig.50 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0362] and Fig. 27 Compared with the configuration example shown, Fig.50 The illustrated configuration example is different in that the inorganic insulating layer 5 has a missing portion LP that overlaps with the slope SS of the organic insulating layer IL. The slope SS is a slope of the insulating layer 12 .

[0363] The inorganic insulating layer 5 is arranged on the upper surface TS1, and is arranged on the upper surface TS2 in the recessed portion DP. The missing portion LP exposes the inclined surface SS. In the example shown in the figure, the missing portion LP also exposes a portion of the upper surface TS1, the edge portion TSE, and the edge portion DPE, and exposes the upper surface TS2 between the edge portion DPE and the inorganic insulating layer 5 in the recessed portion DP. The missing portion LP only needs to overlap with at least a portion of the inclined surface SS.

[0364] Fig.51 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0365] and Fig.28 Compared with the configuration example shown, Fig.51 The illustrated configuration example is different in that the inorganic insulating layer 5 has a missing portion LP that overlaps with the inclined surface SS1 and the inclined surface SS2 of the organic insulating layer IL. The inclined surface SS1 and the inclined surface SS2 are inclined surfaces of the insulating layer 12.

[0366] The inorganic insulating layer 5 is disposed on the upper surface TS1, and is disposed on the insulating layer 114 in the recessed portion DP. The missing portion LP exposes the slope SS1, the upper surface TS2, and the slope SS2.

[0367] Fig.52 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0368] and Fig.29 Compared with the configuration example shown, Fig.52 The illustrated configuration example is different in that the inorganic insulating layer 5 has a missing portion LP overlapping the slope SS of the organic insulating layer IL. The slope SS is a slope of the insulating layer 12. The missing portion LP exposes the slope SS.

[0369] Fig.53 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0370] and Fig.30 Compared with the configuration example shown, Fig.53 The illustrated configuration example is different in that the inorganic insulating layer 5 has a missing portion LP overlapping the slope SS of the organic insulating layer IL. The slope SS is a slope of the insulating layer 12. The missing portion LP exposes the slope SS.

[0371] Fig.54 2 is a cross-sectional view showing another configuration example of the mother substrate 100 .

[0372] and Fig.31 Compared with the configuration example shown, Fig.54 The illustrated configuration example is different in that the inorganic insulating layer 5 has a missing portion LP overlapping the slope SS of the organic insulating layer IL. The slope SS is a slope of the insulating layer 12. The missing portion LP exposes the slope SS.

[0373] about Figures 43 to 54 In the various configuration examples shown, the inorganic insulating layer 5 may also be Fig.35 The illustrated configuration example also has an opening OP overlapping with the recessed portion DP.

[0374] exist Figures 43 to 54In each of the configuration examples shown, the peripheral partition walls 7 are arranged to overlap with the upper surface TS or the upper surface TS1 of the organic insulating layer IL and overlap with the recessed portion DP, and are all overhanging. In addition, the distance D1 in each configuration example is preferably 50 μm or more, and the distance D2 is preferably 20 μm or more.

[0375] As described above, by providing the inorganic insulating layer 5 with the missing portion LP overlapping the slope SS, local stress concentration near the edge DPE of the recess DP can be suppressed, thereby suppressing the inorganic insulating layer 5 from floating from the organic insulating layer IL.

[0376] In addition, when a laminated film is formed near the missing portion LP, it is possible to suppress the laminated film from floating. This point will be described below.

[0377] Fig.55 Is used to illustrate the inclusion of Fig.35 The illustrated cross-sectional view is a view in which the laminated film FL1 is formed in the region of the missing portion LP.

[0378] For example, in the process of forming the display element DE1, the laminated film FL1 is formed not only in the display area but also in the blank portion MP and the peripheral area SA. The laminated film FL1 here includes, for example, an organic layer OR1, an upper electrode UE1 and a cap layer CP1 for forming the display element DE1. The laminated film FL1 is formed on the inorganic insulating layer 5 and the peripheral partition wall 7, and is also formed on the inclined surface SS of the organic insulating layer IL.

[0379] The laminated film FL1 is interrupted by the overhanging peripheral partition wall 7. That is, when the organic layer OR1, the upper electrode UE1, and the cap layer CP1 are formed by evaporation, the material released from the evaporation source is blocked by the upper portion 72 of the peripheral partition wall 7. Therefore, a portion of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 is stacked on the upper portion 72. Each of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 located on the upper portion 72 is separated from the organic layer OR1, the upper electrode UE1, and the cap layer CP1 located around the peripheral partition wall 7. As a result, the laminated film FL1 is partially interrupted.

[0380] Compared with the case where the laminate film FL1 is not interrupted by the peripheral partition wall 7, the area of ​​the continuous laminate film FL1 is reduced, and the stress that can be generated in the laminate film FL1 is dispersed. In addition, the inorganic insulating layer 5 and the laminate film FL1 are pressed by the peripheral partition wall 7. Therefore, the floating of the inorganic insulating layer 5 from the organic insulating layer IL and the floating of the laminate film FL1 from the inorganic insulating layer 5 can be suppressed. In addition, since the stress concentration near the edge portion DPE of the recessed portion DP is suppressed, the floating of the laminate film FL1 from the inclined surface SS can be suppressed. Furthermore, when the sealing layer SE1 is formed on the laminate film FL1, the sealing layer SE1 presses the laminate film FL1 together with the peripheral partition wall 7. Therefore, the laminate film FL1 and the sealing layer SE1 can be suppressed from detaching from the inorganic insulating layer 5.

[0381] In addition, when the organic insulating layer IL has a stepped cross-section whose thickness decreases toward the recessed portion DP, the formation of a steep step can be suppressed. The thinner the thickness of the organic insulating layer IL, the smaller the elongation. Therefore, when the stacked film FL1 is formed on the organic insulating layer IL, the strain of the stacked film FL1 is small, and local stress concentration can be suppressed in the stacked film FL1. As a result, the stacked film FL1 can be suppressed from detaching from the inorganic insulating layer 5 or the slope SS.

[0382] Here, the following describes the possible problems that may occur when the laminated film FL1 floats or breaks from the inorganic insulating layer 5. The inorganic insulating layer 5 separated from the organic insulating layer IL and the laminated film FL1 separated from the inorganic insulating layer 5 become foreign matter and float in the manufacturing device, which may become a source of contamination. In addition, if the floating foreign matter adheres to the processing substrate, it may cause various defects.

[0383] In contrast, according to the present embodiment, the inorganic insulating layer 5 and the laminated film FL1 can be prevented from being detached, thereby preventing contamination of the manufacturing apparatus and generation of undesired foreign matter, thereby preventing a decrease in reliability.

[0384] It should be noted that the same effect can be obtained even when the stacked film FL1 is replaced with a stacked film FL2 including an organic layer OR2 for forming the display element DE2 , an upper electrode UE2 , and a cover layer CP2 .

[0385] In addition, even when the stacked film FL1 is replaced with a stacked film FL3 including the organic layer OR3 , the upper electrode UE3 , and the cap layer CP3 for forming the display element DE3 , the same effect can be obtained.

[0386] Here, about Fig.35 In the illustrated configuration example, the effect of suppressing the separation of the inorganic insulating layer 5 and the laminated film FL1 is described, but the same effect can be obtained in each of the other configuration examples.

[0387] In the above embodiment, for example, in the peripheral partition wall 7, the lower portion 71 corresponds to the first lower portion, and the upper portion 72 corresponds to the first upper portion. In addition, in the partition wall 6, the lower portion 61 corresponds to the second lower portion, and the upper portion 62 corresponds to the second upper portion. In the organic insulating layer IL, the insulating layer 114 corresponds to the first layer, and the insulating layer 12 corresponds to the second layer.

[0388] As described above, according to the present embodiment, it is possible to provide a display device and a mother substrate capable of suppressing a decrease in reliability.

[0389] Based on the display device and mother substrate described above as embodiments of the present invention, all display devices and mother substrates that can be implemented by those skilled in the art through appropriate design changes also belong to the scope of the present invention as long as they include the gist of the present invention.

[0390] Within the scope of the present invention, those skilled in the art can think of various variations, which also belong to the scope of the present invention. For example, for the above-mentioned embodiments, those skilled in the art appropriately perform an embodiment in which constituent elements are added, deleted or the design is changed, or perform an embodiment in which a process is added, omitted or the condition is changed, and as long as they have the gist of the present invention, they are included in the scope of the present invention.

[0391] In addition, regarding other effects brought about by the methods described in the above embodiments, effects that are clear from the description of this specification, or effects that can be appropriately conceived by those skilled in the art are of course understood as effects brought about by the present invention.

Claims

1. A display device comprising: substrate; an organic insulating layer disposed above the substrate and extending over a display region for displaying an image and a peripheral region outside the display region; a lower electrode, which is arranged on the organic insulating layer in the display area; an inorganic insulating layer, which is disposed on the organic insulating layer and covers the peripheral portion of the lower electrode; an organic layer disposed on the lower electrode and including a light-emitting layer; an upper electrode disposed on the organic layer; and a plurality of peripheral partitions arranged in the peripheral area, Each of the plurality of peripheral partitions has: a first lower portion located above the inorganic insulating layer; and a first upper portion located above the first lower portion and protruding from a side surface of the first lower portion, The organic insulating layer has a flat upper surface and a concave portion that is recessed relative to the upper surface in the peripheral region. The plurality of peripheral partition walls include a first partition wall overlapping the recessed portion, A distance from the first upper portion of the first partition wall to an edge of the recess is 50 μm or more.

2. The display device according to claim 1, wherein: The plurality of peripheral partition walls include a second partition wall overlapping the upper surface, A distance from the first upper portion of the second partition wall to an edge portion of the upper surface is 20 μm or more.

3. A display device comprising: substrate; an organic insulating layer disposed above the substrate and extending over a display region for displaying an image and a peripheral region outside the display region; a lower electrode, which is arranged on the organic insulating layer in the display area; an inorganic insulating layer, which is disposed on the organic insulating layer and covers the peripheral portion of the lower electrode; an organic layer disposed on the lower electrode and including a light-emitting layer; an upper electrode disposed on the organic layer; and a plurality of peripheral partitions arranged in the peripheral area, Each of the plurality of peripheral partitions has: a first lower portion located above the inorganic insulating layer; and a first upper portion located above the first lower portion and protruding from a side surface of the first lower portion, The organic insulating layer has a flat upper surface, a concave portion recessed relative to the upper surface, and an inclined surface surrounding the concave portion in the peripheral region. The plurality of peripheral partition walls include a first partition wall overlapping the recessed portion and a second partition wall overlapping the upper surface. The inorganic insulating layer has a missing portion overlapping the inclined surface.

4. The display device according to claim 3, wherein: The distance from the first upper portion of the first partition wall to the edge of the recess is 50 μm or more. A distance from the first upper portion of the second partition wall to an edge portion of the upper surface is 20 μm or more.

5. The display device according to claim 1 or 3, wherein: The concave portion is a portion penetrating the organic insulating layer.

6. The display device according to claim 5, further comprising a metal layer located in the concave portion, The inorganic insulating layer has an opening that exposes the metal layer.

7. The display device according to claim 1 or 3, wherein: The concave portion is a thin-walled portion of the organic insulating layer.

8. The display device according to claim 1 or 3, wherein: The first partition wall is formed in a lattice shape when viewed from above. The plurality of first partition walls are separated from each other.

9. The display device according to claim 1 or 3, further comprising the following partition wall in the display area, the partition wall having: a second lower portion arranged on the inorganic insulating layer and formed of a conductive material; and a second upper portion arranged on the second lower portion and protruding from a side surface of the second lower portion, The lower electrode, the organic layer and the upper electrode are surrounded by the partition wall. The upper electrode is in contact with the second lower portion of the partition wall.

10. The display device according to claim 1 or 3, wherein: The organic insulating layer has a stepped cross-section in which a thickness decreases toward the recessed portion.

11. The display device according to claim 1 or 3, wherein: The organic insulating layer includes a first layer and a second layer covering the first layer.

12. The display device according to claim 1 or 3, wherein: The organic insulating layer includes a first layer and a second layer disposed on the first layer and exposing the first layer near the recessed portion.

13. The display device according to claim 1 or 3, wherein: The organic insulating layer is a single layer body.

14. A mother substrate, comprising: A panel portion having a display area for displaying an image and a peripheral area outside the display area; a blank portion located outside the panel portion; an organic insulating layer disposed over the panel portion and the blank portion; a lower electrode, which is arranged on the organic insulating layer in the display area; an inorganic insulating layer, which is disposed on the organic insulating layer and covers the peripheral portion of the lower electrode; an organic layer disposed on the lower electrode and including a light-emitting layer; an upper electrode disposed on the organic layer; and A plurality of peripheral partitions are arranged in the peripheral area and the blank portion, Each of the plurality of peripheral partitions has: a first lower portion located above the inorganic insulating layer; and a first upper portion located above the first lower portion and protruding from a side surface of the first lower portion, The organic insulating layer has a flat upper surface and a concave portion that is recessed relative to the upper surface in the peripheral region or the blank portion. The plurality of peripheral partition walls include a first partition wall overlapping the recessed portion, A distance from the first upper portion of the first partition wall to an edge of the recess is 50 μm or more.

15. The mother substrate according to claim 14, wherein: The plurality of peripheral partition walls include a second partition wall overlapping the upper surface, A distance from the first upper portion of the second partition wall to an edge portion of the upper surface is 20 μm or more.

16. A mother substrate, comprising: A panel portion having a display area for displaying an image and a peripheral area outside the display area; a blank portion located outside the panel portion; an organic insulating layer disposed over the panel portion and the blank portion; a lower electrode, which is arranged on the organic insulating layer in the display area; an inorganic insulating layer, which is disposed on the organic insulating layer and covers the peripheral portion of the lower electrode; an organic layer disposed on the lower electrode and including a light-emitting layer; an upper electrode disposed on the organic layer; and A plurality of peripheral partitions are arranged in the peripheral area and the blank portion, Each of the plurality of peripheral partitions has: a first lower portion located above the inorganic insulating layer; and a first upper portion located above the first lower portion and protruding from a side surface of the first lower portion, The organic insulating layer has a flat upper surface, a concave portion recessed relative to the upper surface, and an inclined surface surrounding the concave portion in the peripheral region or the blank portion. The plurality of peripheral partition walls include a first partition wall overlapping the recessed portion and a second partition wall overlapping the upper surface. The inorganic insulating layer has a missing portion overlapping the inclined surface.

17. The mother substrate according to claim 16, wherein: The distance from the first upper portion of the first partition wall to the edge of the recess is 50 μm or more. A distance from the first upper portion of the second partition wall to an edge portion of the upper surface is 20 μm or more.

18. The mother substrate according to claim 14 or 16, wherein: The concave portion is a portion penetrating the organic insulating layer.

19. The mother substrate according to claim 18, further comprising a metal layer located in the concave portion, The inorganic insulating layer has an opening that exposes the metal layer.

20. The mother substrate according to claim 14 or 16, wherein: The concave portion is a thin-walled portion of the organic insulating layer.

21. The mother substrate according to claim 14 or 16, wherein: The first partition wall is formed in a lattice shape when viewed from above. The plurality of first partition walls are separated from each other.

22. The mother substrate according to claim 14 or 16, further comprising the following partition wall in the display area, the partition wall having: a second lower portion arranged on the inorganic insulating layer and formed of a conductive material; and a second upper portion arranged on the second lower portion and protruding from a side surface of the second lower portion, The lower electrode, the organic layer and the upper electrode are surrounded by the partition wall. The upper electrode is in contact with the second lower portion of the partition wall.

23. The mother substrate according to claim 14 or 16, wherein: The organic insulating layer has a stepped cross-section in which a thickness decreases toward the recessed portion.

24. The mother substrate according to claim 14 or 16, wherein: The organic insulating layer includes a first layer and a second layer covering the first layer.

25. The mother substrate according to claim 14 or 16, wherein: The organic insulating layer includes a first layer and a second layer disposed on the first layer and exposing the first layer near the recessed portion.

26. The mother substrate according to claim 14 or 16, wherein: The organic insulating layer is a single layer body.

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