Apparatus and method for separate write enable for single pass access of data, metadata, and parity information

Abstract

Devices, systems, and methods for separate write enable signals for data, metadata, and parity information. The memory array is divided into a column plane and an additional column plane. In some modes of the memory device, data and parity information are stored in the column plane and metadata is stored in the additional column plane. The additional column plane includes separate write enable signals (or separate states of a single signal) that activate different portions of bit lines (e.g., even and odd bit lines). In an example access operation, a column select signal is provided to the additional column plane along with one or another write enable signal such that fewer bit lines than all the bit lines activated by the column select signal provide data.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of filing U.S. Provisional Application No. 63 / 383,738, filed on November 15, 2022. The entirety of that application is incorporated herein by reference for all purposes. Background Art

[0003] The present disclosure relates generally to semiconductor devices, and more particularly to semiconductor memory devices. In particular, the present disclosure relates to volatile memory, such as dynamic random access memory (DRAM). Information can be stored as physical signals (e.g., charge on a capacitive element) on individual memory cells of the memory. During an access operation, an access command may be received along with address information specifying which memory cells should be accessed.

[0004] There is a growing interest in enabling memory to store information associated with data segments in an array. For example, error correction information and / or metadata may be stored in an array along with its associated data. It may be desirable to ensure that such information can be accessed along with the specified data without unduly affecting the performance of the device. Summary of the invention

[0005] In at least one aspect, the present disclosure is directed to an apparatus comprising a first column plane comprising a first plurality of bit lines, a second column plane comprising a second plurality of bit lines, and an input / output circuit that receives data and metadata as part of a write operation, wherein data is written to the first plurality of bit lines and metadata is written to even or odd bit lines of the second plurality of bit lines.

[0006] The apparatus may also include a column decoder configured to provide a column select signal based on a column address, wherein the first plurality of bit lines and the second plurality of bit lines are activated by the same value of the column select signal. The apparatus may also include a column decoder providing a first write enable signal and a second write enable signal, wherein data is written to the first plurality of bit lines in response to the first write enable signal, an even or odd bit line of the second plurality of bit lines is selected based on a value of the second write enable signal, and metadata is written to a selected one of the even or odd bit lines of the second plurality of bit lines.

[0007] The device may also include a global column repair (GCR) column plane and a fuse array, the global column repair column plane including a plurality of redundant bit lines. The fuse array may remap the first plurality of bit lines or the second plurality of bit lines to the plurality of redundant bit lines, so that if the first plurality of bit lines are remapped to the plurality of redundant bit lines, data is written to the plurality of redundant bit lines, and if the second plurality of bit lines are remapped to the plurality of redundant bit lines, metadata is written to even or odd redundant bit lines in the plurality of redundant bit lines. The device may also include a logic circuit that provides a first write enable signal if the first plurality of bit lines are remapped to the plurality of redundant bit lines, and provides a second write enable signal if the second plurality of bit lines are remapped to the plurality of redundant bit lines.

[0008] The device may also include a third column plane including a third plurality of bit lines and an error correction code (ECC) circuit that receives data and metadata as part of a write operation and generates parity bits based on the metadata. The parity bits may be written to the third plurality of bit lines. The device may include an ECC mask circuit that receives a set of bits including metadata from the second plurality of bit lines as part of a read operation and provides even or odd bits in the set of bits to the ECC circuit.

[0009] In at least one aspect, the present disclosure may be directed to a method that includes activating a first write enable signal and a second write enable signal in response to a write operation, wherein the second write enable signal has a first state or a second state based on a column address. The method also includes writing data to a selected bit line in a first column plane in response to the first write enable signal, and writing metadata to a first portion or a second portion of the selected bit line in a second column plane in response to the state of the second write enable signal.

[0010] The first portion may be even bit lines of the selected bit lines, and the second portion may be odd bit lines of the selected bit lines. The method may also include generating a column select signal having a value based on the column address, and selecting the selected bit lines in the first column plane and the selected bit lines in the second column plane based on the value of the column select signal. The method may also include generating parity bits based on the data and the metadata, and writing the parity bits to the selected bit lines in the third column plane.

[0011] The method may include selecting a first portion or a second portion of a plurality of column planes based on a column plane select bit of a column address. The first column plane may be in the first portion or the second portion, and the second column plane may not be in the first portion or the second portion. The method may include: reading a first set of bits from a first portion of selected bit lines in a second column plane and reading a second set of bits from a second portion of selected bit lines in the second column plane as part of a read operation; selecting the first set of bits or the second set of bits; and providing the selected one of the first set of bits or the second set of bits to an error correction code (ECC) circuit.

[0012] The method may include: repairing a selected bit line in a first column plane or a selected bit line in a second column plane to a selected bit line in a global column repair (GCR) column plane; if the selected bit line in the first column plane is repaired, writing data to the selected bit line in the GCR column plane in response to a first write enable signal; and if the selected bit line in the second column plane is repaired, writing metadata to a first portion or a second portion of the selected bit line in the GCR column plane in response to a state of a second write enable signal.

[0013] In at least one aspect, the present disclosure may be directed to a device comprising a first column plane, a second column plane, and a column decoder. The first column plane comprises a first local input / output (LIO) line coupled to a first read / write transfer gate, and a second LIO line coupled to a second read / write transfer gate. The second column plane comprises a third LIO line coupled to a third read / write transfer gate, and a fourth LIO line coupled to a fourth read / write transfer gate. The column decoder provides a first write enable signal to the first column plane and a second write enable signal to the second column plane. The first and second read / write transfer gates are activated by the first write enable signal, and the third or fourth read / write transfer gate is activated by the second write enable signal.

[0014] The first column plane may also include a first plurality of bit lines and a second plurality of bit lines, a selected one of the first plurality of bit lines being coupled to the first LIO line and a selected one of the second plurality of bit lines being coupled to the second LIO line. The second column plane may also include a third plurality of bit lines and a fourth plurality of bit lines, a selected one of the third plurality of bit lines being coupled to the third LIO line and a selected one of the fourth plurality of bit lines being coupled to the fourth LIO line. The selected one of the first, second, third and fourth pluralities of bit lines may be selected by the same value of a column select signal.

[0015] The apparatus may also include an error correction code (ECC) circuit and an ECC mask circuit that receives a first bit from a third read / write transfer gate and a second bit from a fourth read / write transfer gate and provides the first bit or the second bit to the ECC circuit. The apparatus may also include a third column plane and a logic circuit that includes a fifth LIO line coupled to a fifth read / write transfer gate and provides a first write enable signal or a second write enable signal to the fifth read / write transfer gate. The logic circuit may provide a first write enable signal if the first or second LIO line is repaired to the fifth LIO line, and may provide a second write enable signal if the third or fourth LIO line is repaired to the fifth LIO line. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 2 is a block diagram of a memory device according to some embodiments of the present disclosure.

[0018] Figure 3 is a block diagram showing an example of a read operation of a memory according to some example embodiments of the present disclosure.

[0019] Figure 4 is a schematic diagram of a portion of a memory bank according to some embodiments of the present disclosure.

[0020] Figure 5 is a block diagram of an additional column plane according to some embodiments of the present disclosure.

[0021] Figure 6 is a block diagram of additional columns according to some embodiments of the present disclosure.

[0022] Figure 7 is a block diagram of a sense amplifier region according to some embodiments of the present disclosure.

[0023] Figure 8 is a flow chart of a method according to some embodiments of the present disclosure.

[0024] Fig. 9 is a timing diagram of a mode register write operation according to some embodiments of the present disclosure.

[0025] Fig.10 is a flow chart of a method according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0026] The following description of certain embodiments is merely exemplary in nature and is in no way intended to limit the scope of the present disclosure or its application or use. In the following detailed description of the embodiments of the systems and methods of the present invention, reference is made to the accompanying drawings, which form a part of this document and show, by way of illustration, specific embodiments of the systems and methods described in which they can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the currently disclosed systems and methods, and it should be understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the present disclosure. In addition, for the sake of clarity, when certain features are apparent to those skilled in the art, the detailed description of these features will no longer be discussed, so as not to obscure the description of the embodiments of the present disclosure. Therefore, the following detailed description should not be understood in a restrictive sense, and the scope of the present disclosure is limited only by the appended claims.

[0027] The memory array may typically include a number of memory cells arranged at the intersection of word lines (rows) and bit lines / digit lines (columns). Columns may be grouped together into column planes, and a column select (CS) signal may be used to select a set of columns within each of the active column planes to provide data. When an access command is received, the memory may pre-fetch a codeword (e.g., a number of data bits) along with one or more associated bits from the memory and replace the pre-fetched data with new data (e.g., as part of a write operation) or provide the pre-fetched data from the memory device (e.g., as part of a read operation). Some memory modes may involve providing less than all of the pre-fetched data from the memory device. For example, in a conventional memory device, in certain modes, half of the pre-fetched data may be provided from the device, and the remainder may be ignored.

[0028] The memory device may store additional information associated with each codeword. For example, the additional information may include parity bits used as part of an error correction scheme, metadata including information about the data codeword (or part of information about a larger data set including the codeword), or a combination thereof. However, the maximum number of bits that can be retrieved as part of a single access pass may be limited by the architecture of the memory, and this number may generally be based on the maximum number of data bits in a codeword plus some number of additional bits (e.g., 128 data bits + 8 additional bits).

[0029] As used herein, the term data may represent any information bit that the controller wishes to store and / or retrieve from the memory. The term metadata may represent any information bit about the data written to the memory and / or received from the memory by the controller. For example, metadata may be information generated by the controller about the data, about how or where the data memory is stored in the memory, about how many errors have been detected in the data, etc. Data and metadata together represent information written to the memory by the controller and then also read from the memory by the controller, wherein the difference between data and metadata in terms of content and how they are generated is that metadata is based on information about the data. The term parity may represent any bit generated by the error correction circuit of the memory based on data, metadata, or a combination thereof. Parity may generally be kept in the memory. In some embodiments, the amount of data and / or metadata retrieved as part of a single access operation may represent a bit set as a fragment of a larger piece of information. For example, a metadata bit (e.g., 4 bits) retrieved as part of a single access operation may not have any meaning by itself, but may have meaning when combined with a set of metadata bits retrieved as part of other access operations (e.g., to other memory arrays and / or to the same array at different times).

[0030] Some memories may include a set of data column planes, as well as additional column planes for storing additional information. However, it may be desirable to include additional information (e.g., including parity bits and metadata, including more parity bits, etc.) than can be retrieved from additional column planes for various applications. Some memory devices may use a "two-pass" architecture, in which at least some of the additional bits are first retrieved and stored, and then the codeword data bits are retrieved in a second access pass. However, this may result in a loss of latency for any given access operation. It may be desirable to store the extended additional information in one or a single pass so that the codeword and additional bits are retrieved as part of a single access pass to the memory array.

[0031] The present disclosure relates to devices, systems and methods for single-pass access of ECC information, metadata information, or a combination thereof, together with associated codewords. Some memory devices may operate in a mode where fewer than all data bits that can be pre-fetched are provided from the device. For example, a memory device may pre-fetch 128 data bits as part of a codeword in x8 or x16 mode, whereas in x4 memory mode, a 64-bit codeword is provided at the data terminals of the device. The data bits of the codeword in the x4 memory mode are stored in some but not all data column planes (e.g., half of the column planes). The selection of which half of the data column planes may be based on the column address. Additional bits associated with the data (e.g., parity bits and / or metadata bits) may be stored either in additional column planes or in data column planes that are not selected by the column address as part of the current access.

[0032] According to some embodiments of the present disclosure, an instance memory device may include a set of data column planes and an additional column plane. The memory may be set in a mode in which metadata is stored together with its associated data. When an access operation is performed, a column select signal having a first value is provided to columns in a first portion of the data column plane and the additional column plane, and a column select signal having a second value is provided to one or more columns that are not in the first portion of the data column plane. The memory may store data in the first portion of the data column plane, metadata in the additional column plane, and error correction parity bits in accessed columns that are not in the first portion of the data column plane. In this way, the data, metadata, and ECC information of a codeword may be prefetched together as part of a single access pass without prefetching additional data bits.

[0033] In some embodiments, stimulating a column select signal may retrieve a greater number of bits than required. For example, 8 bit lines may be activated, but only 4 bits of metadata are required for each pre-fetched codeword. To prevent the extra bits from being accidentally modified, it may be useful to mask those bits to prevent them from being accessed. The column plane may include two sets of sense amplifiers, each sense amplifier set including sense amplifiers coupled to every other bit line (e.g., even sense amplifiers and odd sense amplifiers). During a write operation in one of the data column planes, the write enable signal activates both sense amplifier sets. However, in the additional column planes, one or metadata write enable signals may be used. The metadata write enable signal includes a first write enable signal (e.g., an even write enable signal) that activates a first sense amplifier set and a second write enable signal (e.g., an odd write enable signal) that activates a second sense amplifier set. In some embodiments, the even and odd write enable signals may represent two states of a binary metadata write enable signal (e.g., high = write enable even valid, low = write enable odd valid). The column control circuit may selectively activate one or the other write enable signal so that half of the bit lines activated by a given column select signal are activated. In this way, only the required metadata bits are accessed in the extra column plane.

[0034] To account for this change, the global column redundancy (GCR) plane for the repair column can receive a write enable signal (if the repair is performed on the data column plane) or a metadata write enable signal (if the repair is performed on the additional column plane). For example, the sense amplifier in the GCR can be coupled to a multiplexer that passes the write enable signal or the metadata write enable signal depending on where the repair is performed. The memory may also include a mode register that can be enabled using the metadata write enable signal.

[0035] Figure 11 is a block diagram of a semiconductor device according to an embodiment of the present disclosure. Semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip. Memory device 100 may be operated by controller 150. Controller 150 may be a device separate from memory 100 that stores and retrieves information from memory 100. For example, controller 150 may be a processor such as a CPU or a GPU. In some embodiments, multiple memory devices may be packaged together into a single memory module, and the controller may send and receive information from multiple memories at the same time. For the sake of clarity, the present invention will be discussed with respect to a single memory device 100. Figure 1 .

[0036] The semiconductor device 100 includes a memory array 118. The memory array 118 is shown as including a plurality of memory banks. Figure 1 In the embodiment of the present invention, the memory array 118 is shown as including eight memory banks BANK0-BANK7. Other embodiments may include more or fewer banks in the memory array 118. As explained in more detail herein, each bank may be further divided into two or more sub-banks. Although embodiments in which each bank includes two sub-banks are generally described herein, other embodiments may include more sub-banks per bank.

[0037] Each memory subgroup includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. The selection of the word line WL is performed by the row decoder 108, and the selection of the bit line BL is performed by the column decoder 110. Figure 1 In some embodiments, row decoder 108 includes a respective row decoder for each memory bank, and column decoder 110 includes a respective column decoder for each memory bank. In some embodiments, components such as row and column decoders and refresh control circuit 116 that are repeated on a per-bank basis may also include components that are repeated on a per-bank basis. For example, there may be a refresh control circuit 116 for each bank.

[0038] The bit line BL is coupled to a corresponding sense amplifier (SAMP). The read data from the bit line BL is amplified by the sense amplifier SAMP and is transferred to the ECC circuit 120 via the local data line (LIO), the transfer gate (TG), and the global data line (GIO). Conversely, the write data output from the ECC circuit 120 is transferred to the sense amplifier SAMP via the complementary main data line GIO, the transfer gate TG, and the complementary local data line LIO, and is written in the memory cell MC coupled to the bit line BL. In response to the column select (CS) signal, the bit line is selected and its sense amplifier is coupled to the corresponding LIO line. In response to the read or write enable signal, the LIO line can be coupled to the corresponding GIO line through the transfer gate TG.

[0039] The semiconductor device 100 may employ multiple external terminals, such as pads, coupled to the controller 150, wherein the multiple external terminals include: a command and address (C / A) terminal coupled to a command and address bus to receive commands and addresses; a clock terminal for receiving clocks CK and / CK; a data terminal DQ coupled to a data bus to provide data; and a power supply terminal for receiving power supply potentials VDD, VSS, VDDQ and VSSQ.

[0040] The external clocks CK and / CK provided to the input circuit 112 are supplied to the clock terminal by the controller 150. The external clocks may be complementary. The input circuit 112 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to the command decoder 106 and provided to the internal clock generator 114. The internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used for timing operations of various internal circuits. The internal data clock LCLK is provided to the input / output circuit 122 to time the operation of the circuit included in the input / output circuit 122, such as being provided to the data receiver to time the reception of the write data. The input / output circuit 122 may include several interface connections, each of which may be coupled to one of the DQ pads (e.g., a pad that may serve as an external connection to the device 100).

[0041] The controller 150 may supply a memory address for the C / A terminal. The memory address supplied to the C / A terminal is passed to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and supplies the decoded row address XADD to the row decoder 108 and supplies the decoded column address YADD to the column decoder 110. The decoded row address XADD may be used to determine which row should be turned on, which may cause data along the bit line to be read out along the bit line. The column decoder 110 may provide a column select signal CS, which may be used to determine which sense amplifiers provide data to LIO. The address decoder 104 may also supply a decoded group address BADD, which may indicate a group of the memory array 118 containing the decoded row address XADD and the column address YADD.

[0042] The controller 150 may supply commands to the C / A terminal. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory (e.g., read commands for performing read operations and write commands for performing write operations), and other commands and operations. The access command may be associated with one or more row addresses XADD, column addresses YADD, and group addresses BADD to indicate memory cells to be accessed.

[0043] The command may be provided as an internal command signal to the command decoder 106 via the command / address input circuit 102. The command decoder 106 includes circuitry to decode the internal command signal to generate various internal signals and commands for performing operations. For example, the command decoder 106 may provide a signal indicating whether data is to be read, written, etc. For example, the command decoder 106 may provide a write enable signal that couples data on the GIO to the LIO, thereby allowing the data on the GIO to be written to the bit line coupled to the LIO via the CS signal.

[0044] The device 100 may receive an access command as a read command. When the read command is received and the read command is supplied in time for the group address, the row address, and the column address, the read data is read from the memory cell corresponding to the row address and the column address in the memory array 118. The read command is received by the command decoder 106, which provides an internal command (e.g., a read enable signal) so that the read data from the memory array 118 is provided to the ECC circuit 120. The ECC circuit 120 receives the data bits, the metadata bits, and the parity bits from the array, and detects and / or corrects errors in the data and metadata bits. The correct read data is provided along the data bus and output to the outside from the data terminal DQ via the input / output circuit 122.

[0045] The device 100 may receive an access command as a write command. When the write command is received and the write command is supplied in time for the group address, the row address, and the column address, the write data supplied to the data terminal DQ is provided along the data bus and written to the memory cell corresponding to the row address and the column address in the memory array 118. The write command is received by the command decoder 106, which provides an internal command (e.g., a write enable signal) so that the write data is received by the data receiver in the input / output circuit 122 together with the metadata. The write data and the metadata are supplied to the ECC circuit 120 via the input / output circuit 122. The ECC circuit generates a parity bit based on the received data and metadata, and the ECC circuit 120 provides the data, metadata, and parity to the memory array 118 to be written into the memory cell MC.

[0046] The device 100 includes refresh control circuits 116, each of which is associated with a group of the memory array 118. Each refresh control circuit 116 can determine when to perform a refresh operation on the associated group. The refresh control circuit 116 provides a refresh address RXADD (along with one or more refresh signals, Figure 11. The row decoder 108 performs a refresh operation on one or more word lines associated with RXADD. The refresh control circuit 116 can perform multiple types of refresh operations, which can determine how to generate the address RXADD, as well as other details, such as how many word lines are associated with the address RXADD.

[0047] The ECC circuit 120 can detect and / or correct errors in the accessed data. As part of a write operation, the ECC circuit 120 can receive bits from the IO circuit 122 and generate parity bits based on those received bits. The received bits and parity bits are written to the memory array 118. During an example read operation, the ECC circuit 120 receives a set of bits and their associated parity bits from the array 118 and uses them to locate and / or correct errors. For example, in a single error correction (SEC) scheme, up to one error bit can be located and detected. In a single error correction double error detection (SECDED) scheme, up to one error bit can be corrected, but two errors can be detected (but the bits causing those errors are not individually located and therefore cannot be corrected). The ECC circuit 120 can correct the information and then provide the corrected information (and / or a signal indicating a detected error) to the IO circuit 122. The parity bit may not typically be provided to the IO circuit 122.

[0048] Mode register 130 may include various settings and may be used to enable a metadata mode of memory 100. When metadata is enabled, device 100 may store metadata associated with the data. For example, as part of a write operation, the controller may provide data and its associated metadata, and as part of a read operation, may receive data and its associated metadata. In some embodiments, ECC circuit 120 may include metadata bits as part of an error correction process, and in some embodiments, metadata bits may be excluded. In some embodiments, whether metadata is included in the ECC process may be a setting of the memory (e.g., in mode register 130). The metadata may include information about the associated data.

[0049] The memory 100 may operate in various modes based on the number of DQ pads used. The mode may determine the number of DQ pads along which the controller expects to send / receive data and the format and / or number of bits that the controller expects as part of a single access command. For example, a memory may have 16 physical DQ pads. In x16 mode, all 16 DQ pads are used. In x8 mode, eight of the DQ pads are used, and in x4 mode, four of the DQ pads are used. The mode may also determine the burst length at each DQ terminal as part of the DQ operation. The burst length represents the number of serial bits at each DQ terminal during an access operation.

[0050] For example, in x8 mode, the memory may send or receive 128 data bits along 8 DQ terminals, each with a burst length of 16. In an example x4 mode, a burst length of 16 may also be used, and thus 64 bits may be sent or received as part of an access operation. The present disclosure will generally be described with respect to an example embodiment, wherein as part of the x4 mode, a codeword of 64 data bits is accessed along with 4 bits of metadata, and the ECC circuit 120 uses 8 bits of ECC parity. Other example embodiments may use different numbers of data, metadata, and parity.

[0051] The device 100 includes a mode register 130 that can be used to control various optional modes of the memory. For example, the mode register 130 may include settings that determine whether metadata is used. If metadata is enabled, the mode register 130 may set a first x4 operating mode (e.g., a two-pass x4 operating mode) or a second x4 operating mode (e.g., a one-pass x4 operating mode). The controller may perform a mode register write (MRW) operation to set the value in the mode register 130, or may perform a mode register read (MRR) operation to check what the value in the mode register 130 is. The mode register 130 includes several registers, each of which may store one or more bits corresponding to a setting or fragment of information about the memory. When the memory is in a one-pass x4 operating mode, further settings of the mode register 130 may be used to set the memory to a separate write enable mode or a common write enable mode in an additional column plane, as described in more detail herein.

[0052] The controller 150 may provide commands and row and column addresses as part of an access operation. In a two-pass x4 mode of operation, in response to an access operation from the controller, the column decoder may perform a first access pass on the memory array to retrieve a first portion of information that may then be stored, and then perform a second access pass on the memory array to retrieve the remainder of the information combined with the stored information. For example, during a read operation, the controller may provide an address and a single read command, but in response thereto, the memory 100 may retrieve 4 metadata bits as part of a first pass, and then retrieve the remaining 64 data bits and 8 parity bits as part of a second pass. In a single-pass x4 mode of operation, in response to an address and a read command, the memory may retrieve data, metadata, and parity as part of a single access pass on the memory array.

[0053] The memory device 100 may also be repaired. The memory includes a fuse array 152 that includes a number of non-volatile storage elements (e.g., fuses or antifuses). The states of the fuses in the fuse array 152 may be used to permanently encode information in the memory 100. For example, a repaired address may be programmed into the fuse array 152. When an address is received as part of an access operation, if the address matches the repaired address in the fuse array 152, the memory may instead access a redundant row or column of the memory.

[0054] The power supply terminals are supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VARY based on the power supply potentials VDD and VSS supplied to the power supply terminals.

[0055] The power supply terminals are also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 122. In an embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be the same potentials as the power supply potentials VDD and VSS supplied to the power supply terminals. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminals. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals are used for the input / output circuit 122 so that the power supply noise generated by the input / output circuit 122 does not propagate to other circuit blocks.

[0056] Figure 2 is a block diagram of a memory device according to some embodiments of the present disclosure. In some embodiments, the memory device 200 may represent Figure 1 A portion of the memory device 100. Figure 2 A view showing a memory group (e.g. Figure 1 118) of a portion of memory arrays 210-214 and 220-224, and selected circuits used in the data path, such as ECC circuit 232 (e.g., Figure 1 120) and IO circuit 234 (e.g., Figure 1 122). For the sake of clarity, Figure 2 Certain circuits and signals are omitted from the illustration.

[0057] The memory device 200 is organized into several column planes 210-214. Each of the column planes represents a portion of a memory group. Each column plane 210-214 includes several memory cells at the intersection of a word line WL and a bit line. The bit lines can be grouped together into a set activated by the value of the CS signal. For clarity, only a single vertical line is used to represent the bit lines of each column selection set, however, there may be multiple columns accessed by the value of CS. For example, each line may represent 8 bit lines, all of which are accessed together by the value of CS. For example, there may be 8 LIOs in each column plane, and the CS signal may be used to determine which bit lines (via their corresponding sense amplifiers) are coupled to those LIOs. As used herein, the "value" of CS may refer to a decoded signal provided to a set of bit lines. Therefore, a first value may represent a first value of a multi-bit CS signal, or a signal line associated with the value after decoding is valid. A word line may extend across multiple of the column planes 210-214.

[0058] The memory 200 includes a set of data column planes 210 and an additional column plane 212. The additional column plane 212 may be used to store additional information, such as error correction parity bits or metadata bits.

[0059] In some embodiments, memory 200 may also include a global column redundancy (GCR) column plane 214. In some embodiments, GCR plane 214 may have fewer memory cells (e.g., fewer column select groups) than data column plane 210. GCR CP 214 includes a number of redundant columns that may be used as part of a repair operation. If the value of the CS signal is identified as repaired (e.g., it is consistent with the value stored in Figure 1 If the address in the fuse array 152 of the memory matches the address in the fuse array 152 of the memory), the memory can be remapped so that the data of the value of CS originally stored in the column plane is stored in the GCR CP 214 instead.

[0060] In addition to the column select signals from the column decoder, during a write operation, the column timing logic in the group region provides a write enable signal WrEN to the transfer gate associated with the data column plane 210 and a metadata write enable signal WrEN_MD to the transfer gate associated with the additional column plane 212. The two write enable signals are provided to the transfer gate associated with the GCR column plane 214 via a logic circuit 240. For clarity, a single box is shown as a logic circuit 240, however, there may be a logic circuit 240 for each transfer gate (e.g., each LIO / GIO). The column select signal CS determines which sense amplifiers (and therefore which bit lines) are coupled to the corresponding LIO. The write enable signals WrEn and WrEn_MD, when valid, couple the LIO to the GIO, thereby allowing data along the GIO to be written along the LIO via the valid sense amplifier and to the memory cell at the intersection with the valid word line. When the write enable signal is invalid, the LIO can remain decoupled from the GIO, similar to a read operation. Accordingly, when the write enable signal is invalid, data cannot be written to the bit line selected by CS.

[0061] As described in more detail herein, sense amplifiers 220, 222, and 224 may be divided into two regions: an even region and an odd region. Different regions include sense amplifiers coupled to alternating bit lines. For example, an even sense amplifier region includes sense amplifiers coupled to even-numbered bit lines, and an odd sense amplifier region includes sense amplifiers coupled to odd-numbered bit lines. Similarly, there may be corresponding even and odd LIOs and GIOs associated with those regions. The write enable signal WrEn activates the transfer gates associated with both the even and odd sense amplifier regions in sense amplifier 220 when it is valid. The metadata write enable signal WrEn_MD activates the transfer gates associated with the even or odd sense amplifier regions of the additional sense amplifier 222, but not both at the same time. The transfer gate associated with the GCR sense amplifier 224 may be activated by either WrEn or WrEn_MD, depending on which of those signals is provided by logic 240. For example, if WrEn_MD is provided to a given pass gate, only the even or odd sense amplifiers in that set will be coupled to the GIO as part of the write operation.

[0062] In an example embodiment, the memory 210 may include 16 data column planes 210(0)-210(15). Each of these data column planes 210 includes 64 bit line sets that can be selected by corresponding values ​​of column select signals (e.g., CS0 to CS63), and each bit line set includes 8 bit lines that are coupled to corresponding LIOs when the CS signal has that value. Accordingly, when the word lines are turned on in response to a row address and the column select signals are provided to all 16 column planes (e.g., as part of x8, x16, or two-pass x4 mode), then 8 bits are accessed from each of the 16 data column planes 210, for a total of 128 bits. Column select signals are also provided to additional column planes 212, which may or may not have the same value as the CS signal provided to the data column plane 210, for up to an additional 8 bits. If repair has been performed, the GCR CP 214 may also be accessed and the value on the GCR LIO may be used while ignoring the LIO of the column plane it is replacing. Accordingly, the maximum number of bits that may be retrieved as part of an access pass is 128 bits from the data column plane 210 (8 bits replaced from the GCR CP 214 if repair has been performed) and 8 additional bits from the additional CP 212.

[0063] The memory can be operated in x4 mode, where data from an external device (such as Figure 1 The controller 150 of the controller 150 sends / provides to the external device a number of bits less than the maximum number of bits that can be accessed. For example, in x4 mode, the controller can send / receive 64 data bits instead of 128 data bits. The column address can indicate which of the column planes 210 are used to store data accessed in x4 mode. For example, the CP selection bit of the column address (e.g., the 10th bit of the column address, C10) can select data from the even column plane or the odd column plane or from the first half of the column plane or the second half of the column plane. In other example embodiments, other schemes can be used.

[0064] Mode registers (for example, Figure 1 of 130, Figure 22 (not shown) may be used to enable metadata on the device. If metadata is enabled, the mode register may have settings that set the memory device in a first x4 operating mode (two-pass mode) or a second x4 operating mode (one-pass mode). In both operating modes, the overall information received / sent from / to the external device is the same. For example, a controller of the memory may expect 64 data bits and 4 metadata bits for each access of the memory 200 in either mode, however, the operating mode may determine how the memory array is accessed, how many access passes are used to extract data (e.g., how quickly the data is accessed), the power consumption of the access operation, the size of the pre-fetched information, the behavior of the ECC circuit 232, and what information is stored in what column plane. In the first x4 operating mode, two access passes are used to retrieve data (e.g., metadata from the first pass and data and ECC bits from the second pass), while in the second x4 operating mode, a single pass is used to retrieve the information.

[0065] In an example read command in the first (two-pass) x4 mode of operation, column, row, and bank addresses are received from the controller. The row decoder (e.g., Figure 1 108) opens the selected word line based on the row address. The column decoder generates a column select signal based on the column address. As part of the first access pass, the column select signal is provided to one of the column planes 210 selected by the CP select bit (e.g., C10) of the column address. Some of the metadata sets associated with the current access operation (e.g., 128 metadata bits) and the parity bits (associated with the metadata sets) from the additional column plane 212 are retrieved from the column plane 210. The ECC circuit 232 can check and correct errors based on the 128 metadata bits + 8 associated parity bits. The metadata bits (e.g., 4 metadata bits) within the set associated with the current access operation (e.g., as indicated by the column address) are stored in a buffer (not shown) that is part of the IO circuit 234. As part of the second access pass, the column select signal is provided to all data column planes 210, and the additional column select signal is provided to the additional column plane. The column select signal and the additional column select signal have the same value as each other and do not necessarily have the same value as the column select signal provided as part of the first access pass. As part of the second access pass, data bits are retrieved from data column plane 210, and parity bits are retrieved from extra column plane 212. ECC circuit 232 uses the retrieved data and parity bits to locate and / or correct errors in the data. Half of the retrieved (corrected) data bits are then concatenated with the previously retrieved metadata in IO circuit 234, and the IO circuit provides the data and metadata leaving the device at the DQ pad.

[0066] The example write command in the first x4 operation mode can be substantially similar. The controller provides data bits and metadata bits as well as commands and addresses, such as a write enable signal WrEn. In the first (two-pass) x4 operation mode, the signal WrEn can be provided to the additional sense amplifier 222, and both the even and odd sense amplifiers can be activated together. The metadata is stored in a buffer of the IO circuit 234. Data is pre-fetched from the array, and half of the data is replaced with new write data. The ECC circuit 232 then generates a new parity from the updated data set, and the data is written to the data column plane 210. In a similar manner, in the second access pass, the metadata set is retrieved so that the metadata can be added thereto, and the ECC circuit 232 can generate a new parity associated with the updated metadata set. The updated metadata set and parity are then written to the array. In the second access pass, the parity is written to the additional column plane 212.

[0067] There may be a latency time tCCD_L_WR that is part of the design specification of the memory. The time tCCD_L_WR represents the minimum amount of time that must pass before a group in the same group group can be accessed again. The time tCCD_L_WR represents a long column-to-column (or command) delay cycle for writes, which may be a specification of the memory. During a write operation, a two-pass operation mode may cause a latency of 2x tCCD_L_WR because each access pass requires a delay of tCCD_L_WR before the group can be accessed again. One tCCD_L_WR is caused by adding an extra pass to overwrite the metadata, and the extra tCCD_L_WR is caused by generating parity bits, which are based on all pre-fetched data in this mode, and half of the pre-fetched data bits that are not written must still be pre-fetched (e.g., read) so that they can be added to the write bits received from the controller.

[0068] The second x4 operating mode can be a "one-pass" mode in which fewer data bits are pre-fetched and the location of metadata and parity is changed compared to the first x4 operating mode. Instead of pre-fetching additional data bits that are not part of the access operation as in the first x4 operating mode, in the second x4 operating mode, only the accessed data bits are pre-fetched.

[0069] In an example read command in the second x4 mode of operation (when the individual write enable mode is disabled), column, row, and bank addresses are received from the controller. The row decoder (e.g., Figure 1108) opens the selected word line based on the row address. The column decoder generates a column select signal based on the column address. As part of a single access pass, a column select value having a first value is provided to a first portion of the column plane, and a column select signal having a second value is provided to at least one column plane that is not in the first portion. At the same time, a column select signal (which may or may not have the same value as the first or second column select signal) is provided to an additional column plane 212. Which columns are in the first portion may be based on the CP selection bit (e.g., C10) of the column address. The data column plane of the first portion provides data bits, the data column plane not in the first portion provides ECC parity bits, and the additional column plane 212 provides metadata bits. During the second x4 operating mode, since only a portion of the column plane 210 is accessed, only a number of data bits (as well as metadata and ECC bits) provided to / from the device are accessed. The ECC circuit 232 receives the data and metadata and the parity bits, and locates and / or corrects any errors in the data and metadata. The (corrected) data and (corrected) metadata are provided to IO circuitry 234 which provides the data and metadata to the DQ terminals.

[0070] In an example write command in the second x4 operating mode (when the separate write enable mode is disabled), column, row and group addresses and data and metadata are received from the controller. The data and metadata are provided to the ECC circuit via the IO circuit, which generates parity bits based on the data and metadata, and then writes the data, metadata and parity to the column plane accessed in a manner similar to that described for the read operation. The column select and WrEn signals are also provided to the additional sense amplifier 222. Accordingly, when the separate write enable mode is disabled, the number of bits retrieved when the columns in the additional column plane are accessed (e.g., 8) can be greater than the specified number of metadata bits (e.g., 4). In order to protect the additional bits from being overwritten, as part of a read-modify-write (RMW) cycle, metadata can be pre-fetched (e.g., read), and then the new metadata overwrites some bits. This may result in a tCCD_L_WR loss (). However, since only a single additional tCCD_L_WR loss is caused (compared to two in the two-pass 4x operating mode), the single-pass mode can have a reduced latency.

[0071] The separate write enable mode can further reduce the latency of the write operation by masking the extra metadata bits so that only four metadata bits associated with the accessed data bits can be written. In the separate write enable mode, the signal WrEn_MD is provided to the sense amplifier 222 of the extra column plane 212. The metadata write enable signal WrEn_MD activates the even or odd sense amplifier, but does not activate both at the same time. The state of WrEn_MD can be based on the column plane selection bit (e.g., C10) of the column address. For example, the column select signal can indicate a group of 8 bit lines and their associated 8 sense amplifiers LIO and GIO. When the column selection is valid, all 8 sense amplifiers are coupled to their corresponding LIO. However, the state of the WrEn_MD signal determines whether the even or odd of these LIOs are coupled to their corresponding GIO. In this way, only the selected even or odd LIO (and therefore the bit line) can be written. This can eliminate the need for the RMW cycle for protecting the extra bit. Furthermore, when the separate write enable signal is enabled, this can remove the extra RMW latency loss from the x4 one-pass operation mode.

[0072] When performing column repair, information can be programmed into the fuse array (e.g., Figure 1 152) to remap the columns to the GCR column plane 214. After repair, when a column address is received, it can be compared to the repaired column address in the fuse array, and if there is a match, an enable signal along with a corresponding column select signal is provided to the GCR column plane 214. The data on the LIO of the column plane containing the defective row can then be swapped with the GCR LIO so that the memory cells in the GCR column plane 214 are accessed instead of the memory cells in the column plane with the damaged bit line.

[0073] When the separate write enable mode is enabled, the behavior of write enable is different for the data column plane 210 and the additional column plane 212. If the repaired CS value is in the data column plane 210, the logic circuit 240 associated with the CS value in the GCR-CP 214 can pass the write enable signal WrEn. If the repaired CS value is in the additional column plane with metadata 212, the logic 240 associated with the CS value passes WrEn_MD. In this way, the repair can act in a manner that matches the set of columns being repaired.

[0074] In the first (two-pass) x4 operating mode, each of the data column planes 210 stores a mix of data and metadata, with ECC parity bits stored in the extra column plane 212. In the second (one-pass) x4 operating mode, each of the data column planes 210 stores a mix of data and ECC parity bits, and metadata is stored in the extra column plane 212. In the single-pass mode, the ECC circuit 232 locates and corrects errors in both the data and metadata (e.g., because the parity is based on both the data and the metadata). In the two-pass mode, the ECC circuit 232 locates and corrects errors in the data only in one cycle, and corrects errors in the metadata in another cycle. In other words, in the one-pass mode, the parity bits are based on both the data and the metadata, while in the two-pass mode, there are separate parity bits for the data and the metadata.

[0075] In the separate write enable mode, only four bits of metadata provided to / received from the controller are provided to the ECC circuit 232. When the separate write enable mode is disabled, the ECC circuit operates on both the selected four bits of metadata and the unselected four bits accessed with it. To accommodate this difference, when the separate write enable mode is enabled, during a read operation, 8 bits are accessed and the extra bits may be discarded so that only 4 selected metadata bits are provided to the ECC circuit 232. For example, the ECC circuit 232 may include an ECC read mask circuit that passes a selected half of the GIO lines from an extra column plane based on the column plane select bits (e.g., C10) or one of the CS addresses (e.g., CA9). This address will select data from either the even or odd sense amplifier stripes.

[0076] In addition, accesses in a one-pass x4 operating mode may draw less power than accesses in a two-pass x4 operating mode. In the two-pass operating mode, all column planes are activated and data read from their sense amplifiers 220 along the LIOs are driven to the ECC circuit 232 along with the sense amplifiers 222 and LIOs associated with the additional column planes 212 (and the sense amplifiers 224 and LIOs of the GCR 214 if a repair has already been present). However, in a one-pass x4 operating mode, only a selected portion (e.g., half) of the data column planes 210 are activated, and thus less than all of the data LIOs are driven by the corresponding sense amplifiers 220. Similarly, various switches, signal lines, etc. may also not be used in every access in a one-pass x4 operating mode. Accordingly, less power is drawn in the x4 operating mode than in the two-pass x4 operating mode. Even less power may be drawn when the separate write enable mode is enabled because fewer LIOs are driven during write operations and fewer GIOs are driven during reads.

[0077] Figure 3is a block diagram showing an example of a read operation of a memory according to some example embodiments of the present disclosure. Figure 3 A view of a memory array 300 is shown showing a representation of which portions of the memory array are set aside for different types of information. Figure 3 The blocks shown in represent portions of a memory array, but do not necessarily represent the spatial layout of where information is stored in the memory array. In some embodiments, the memory array 300 may be Figure 1 The memory array 118 and / or Figure 2 Implementation of column planes 210 - 214 in a second x4 operating mode as described herein.

[0078] Description of Example Embodiments Figure 3 , where there are 16 data column planes, each providing 8 bits when activated by a column select signal, and additional column planes also providing 8 bits when activated by their corresponding column select values. The example memory operates in x4 mode, where the controller accesses 64 data bits and 4 metadata bits. The CP select bit C10 of the column address is used to determine which column planes provide data.

[0079] During an example read operation in which C10 is in a low logic state (e.g., C10=0), 8 column planes are accessed in the first portion 301 of the memory array 300, with each column plane providing 8 bits for a total of 64 data bits. A second column select is also provided to the column planes in the second portion 302. The second column select signal is provided to a single column plane, and a total of 8 ECC parity bits are retrieved. The column select signal is also provided to an additional column plane 308, which provides 8 metadata bits. If the device is in a separate write enabled mode, half of these bits are selected (based on the state of C10) and provided to the ECC circuit 310, while the unselected bits are discarded. If the device is not in a separate write enabled mode, the selected 4 of the 8 bits are provided to the ECC circuit. The ECC circuit 310 (e.g., Figure 2 232) receives 64 data bits and 4 metadata bits and 8 parity bits, and provides 64 data bits and 4 metadata bits. When four metadata bits are provided, which of the eight bits retrieved from the additional column plane can be based on C10 or a different column address bit (e.g., C9).

[0080] In another example read operation where C10 has an opposite value (eg, C10=1), then 64 data bits may be accessed from the second portion 302 , 8 parity bits may be accessed from the first portion 301 , and metadata bits may be accessed from the extra column plane 308 .

[0081] In an example write operation when the individual write enable mode is disabled, since 8 metadata bits are accessed, but only four metadata bits are actually specified by the access operation, an additional 4 metadata bits can be protected. For example, the memory 300 can adopt a read-modify-write (or RMW) strategy in which all 8 metadata bits are pre-fetched, then four of these bits are changed (as needed) based on the newly written metadata, and then all 8 bits are written back. The ECC circuit 310 generates parity based on the updated 8-bit set. This can protect the additional four bits (so they are not inadvertently changed by a direct write operation because no data is written to these cells) at the cost of additional latency (e.g., tCCD_L_WR required for RMW).

[0082] In an example write operation when the individual write enable mode is enabled, only the four metadata bits selected by the column plane select bits of the column address are accessed. The ECC circuit 310 receives 64 data bits and 4 metadata bits and generates 8 parity bits based on the 64+4 bits. The 64 data bits and 8 parity bits are then written to the data column plane 301 or 302, and the 4 metadata bits are written to the extra column plane 308. Since only the required bits can be written (since only the selected transfer gate is activated by WrEn_MD), no additional tCCD_L_WR delay penalty is incurred.

[0083] The blocks in the first portion 301 and the second portion 302 represent portions of those column planes that may be set aside for different storage, and do not necessarily represent the physical arrangement of where information is stored in the portions of the column planes, or the spatial relationship of the column planes in each portion to each other. For example, the first portion may represent even column planes, while the second portion represents odd column planes, and the columns set aside for storing ECC bits may be distributed throughout the data column planes. Figure 3 In the example of , since 8 bits of ECC are required for every 64 bits of data, each portion 301 and 302 can have 87.5% of its total memory space used for data and 12.5% ​​for ECC and metadata bits. In other words, from the controller's perspective, only 87.5% of the memory array can be addressed because the remainder is set aside for metadata that is expected to appear with the data. In a two-pass x4 operating mode, more of the memory array can be available because metadata is stored in the data array and there are 4 bits of metadata for every 64 bits of data. Accordingly, in a two-pass x4 operating mode, 93.75% of the array can be set aside for data and 6.25% of the array can be set aside for metadata. When metadata is disabled, 100% of the array space can be used for data.

[0084] Table 1 is a summary of different operations in two different x4 modes with metadata according to some embodiments of the present disclosure.

[0085]

[0086] Table 1. Comparison of two-pass and one-pass x4 operation modes

[0087] In Table 1, the symbols d, p, and md are used to represent data bits, parity bits, and metadata bits, respectively. For example, the first row uses the notation 8p+128md / 128d+8p to represent that in two-pass mode, 8 metadata bits are extracted in the first pass (but only 4 metadata bits are used), and then 128 data bits and 8 parity bits are extracted in the second pass, while the notation 64d+8(4)md+8p is used to represent that 64 data bits, 8 metadata bits, and 8 parity bits are pre-fetched as part of a single access pass (but only 4 metadata bits are used). In one-pass mode, when separate write enable is valid, only four required metadata bits are accessed. The mode register may also have a setting to disable metadata. When metadata is not used, the device can function in a manner similar to the "two-pass" mode, except that only a single pass is required to pre-fetch 128 data bits and 8 parity bits.

[0088] In the two-pass x4 operating mode (and in the metadata disabled mode), the ECC circuit 232 uses 128 metadata bits (four of which are associated with data access) and 8 parity bits associated with the 128 metadata bits in the first pass, and the ECC circuit 232 uses 128 data bits and 8 parity bits in the second pass. In the one-pass x4 operating mode, the ECC circuit 232 uses 64 bits of data, 8 bits of metadata, and 8 bits of parity. When the separate write enable is enabled, the ECC circuit 232 uses 4 bits of metadata. In the two-pass x4 mode, the ECC circuit 232 can implement the SEC scheme for both 128 metadata bits and 128 data bits, respectively, and in the one-pass x4 mode, the SECDED scheme can be used together for both data and metadata. In other words, in the two-pass mode, each parity set can correspond to data or metadata, and in the one-pass mode, the parity corresponds to data and metadata together. Since a higher number of parity checks for other bits are used in the one-pass mode, more protection can be provided. Additionally, in one-pass mode, metadata may also be checked by the ECC circuit, while in two-pass mode, metadata may be protected by the ECC circuit in the second pass.

[0089] In two-pass x4 operation mode, there may be an additional latency of 2x tCCD_L_WR, since two access passes (of metadata and prefetched data) may need to go through RMW cycles. In one-pass x4 operation mode, only a single additional tCCD_L_WR is incurred. When separate write enable is enabled, no additional tCCD_L_WR penalty is incurred. Metadata disabled mode may also only incur an additional tCCD_L_WR, since the amount of prefetched data is greater than the amount to be written, so RMW is used to prefetch the entire data set and then overwrite selected bits.

[0090] The one-pass x4 operation mode can draw less power than the two-pass x4 operation mode (or metadata disabled mode). In the one-pass mode, the CS signal can be provided only to a selected half of the column planes (based on C10). Accordingly, only half of the column planes need to activate their switches, drive voltages along the LIO lines, etc. This can reduce the power draw of a single access operation. For example, in the two-pass mode, 17 different CS signals (16 data column planes and 1 additional column plane) and their associated LIO / GIO, etc. are stimulated, while in the one-pass mode, 9 different CS signals and their associated LIO / GIO, etc. are stimulated. When individual write enable is enabled, the additional column plane only needs to stimulate half the number of LIO / GIO. This is noted in Table 1 as 8.5 CSs need to be stimulated, which is a power reduction compared to the one-pass mode when the individual write enable signal is disabled.

[0091] Figure 4 is a schematic diagram of a portion of a memory bank according to some embodiments of the present disclosure. In some embodiments, the memory bank 400 may be included in Figure 1 Memory 100 of FIG. 20 , memory 200 of FIG. 20 , and / or Figure 3 Memory bank 400 shows a simplified schematic diagram of the layout of the memory bank and example signals that may be used to activate individual columns in the column plane as part of a second x4 operating mode (eg, a one-pass x4 operating mode) when a separate write enable signal is asserted.

[0092] Similar to Figure 3 , regarding the description of the example embodiments Figure 4 , where there are 16 data column planes, each of which contains 64 bit line sets (e.g., 64 values ​​of CS signals), each of which provides 8 bits of data when activated by a corresponding CS signal. It should be understood that this is an example implementation of the present disclosure, and other arrangements (e.g., more or fewer CS sets per CP, more or fewer CPs per memory bank, etc.) may be used in other example embodiments.

[0093] Memory bank 400 is shown organized into sixteen column planes 412-448 (eg, Figure 2 210 and / or Figure 3 301-302) of the memory, each of the column planes is associated with a DQ pad 410-440. Thus, the first DQ pad 410 is associated with the column planes 412-418, the second DQ pad 420 is associated with the column planes 422-428, the third DQ pad 430 is associated with the column planes 432-438, and the fourth DQ pad is associated with the column planes 442-448. Figure 4 In the example x4 mode of FIG. 4 , each of the four DQ pads 410 , 420 , 430 , and 440 processes 16 data bits as part of an access operation, for a total of 64 data bits. In addition to the four DQ pads 410 , 420 , 430 , and 440 , the memory group 400 may also be associated with a metadata terminal 450 that may be used to send / receive metadata as part of an access operation. The metadata terminal is associated with an additional column plane 452 (e.g., Figure 1 212 and / or Figure 3 308). Figure 4 In the simplified view of FIG. 4 , a single word line WL is shown, along with a global row decoder 402 driving the word line. Similarly, for the bit lines, only selected lines are shown, each line representing a set of bit lines activated by a common CS signal in the CP.

[0094] The memory bank 400 is organized into sectors or tiles 403, where the cells of the memory array are between two sense amplifier regions 404. There may be several sectors, each with several word lines and bit lines in each column plane, however, for clarity, Figure 4 Only a single segment 403 is shown in FIG. Sense amplifier region 404 may be elongated in the same direction as word line WL. Different segments may extend in a direction perpendicular to the direction in which the word line is elongated. Each segment may be separated by a sense amplifier region (e.g., 404-409). The sense amplifiers in each of the regions may be coupled to bit lines in the segment and bit lines in adjacent segments. During access operations, bit lines in the segment containing valid word lines may be accessed, while bit lines extending into unaccessed segments may serve as references. During write operations, sense amplifier segments 404 and 405 may be activated (e.g., coupled to GIO) in response to a write enable signal WrEn.

[0095] Additional column plane 452 is also surrounded by first sense amplifier section 408 and second sense amplifier section 409, which may be substantially similar to sense amplifier regions 404 and 405, respectively. First sense amplifier region 408 is activated by a first state of a column signal (CA10), and second sense amplifier region 409 is activated by a second state of the column signal (CA10).

[0096] Column planes 412-448 in segment 403 are separated by sub-wordline (SWL) drivers 406. Each column plane is adjacent to another column plane and the SWL driver 406. For example, column plane 412 is adjacent to SWL driver 406 on one side and adjacent to column plane 414 on the other side. Column plane 414 is adjacent to column plane 412 on a first side and adjacent to a second SWL driver 406 on the opposite side. On the opposite side of the SWL driver 406 is another column plane 416, and so on.

[0097] Accordingly, each data terminal is associated with four column planes, two pairs of column planes are adjacent to each other and separated from another pair of column planes by a SWL driver. Each pair is associated with a different value of the column plane selection bit C10. For example, the first DQ pad 410 is associated with column planes 412 and 414, which are activated by C10 at a high logic level; and with column planes 416 and 418, which are activated by C10 at a low logic level. Accordingly, column planes 412, 414, 422, 424, 432, 434, 442 and 444 all contain data accessed when C10=1, and column planes 416, 418, 426, 428, 436, 438, 446 and 448 all contain data accessed when C10=0. Regardless of which set of column planes is selected by C10, one or more column planes of another set can be used to store ECC parity bits.

[0098] Figure 4 An example access operation in a second x4 operation mode (e.g., one-pass x4 mode) is shown when a separate write enable mode is active. Segment 403 is bounded on either side by a first sense amplifier region 404 and a second sense amplifier region. Each sense amplifier region receives a column select signal and a write enable signal WrEn. The sense amplifiers of each region 404 and 405 are alternately coupled to every other bit line in segment 403. For example, sense amplifier region 404 may be an even sense amplifier region and sense amplifier region 405 may be an odd sense amplifier region.

[0099] In an example write operation, the memory device receives a column address that includes C10=0 and has a value decoded to the first column select signal CS0. Accordingly, CS0 is provided by the column decoder to column planes 416, 418, 426, 428, 436, 438, 446, and 448 along with a write enable signal WrEn, and the bit lines associated with CS0 in each of those column planes each provide 8 bits of data, with four bits of data per column plane from each of the sense amplifier regions 404 and 406. The column decoder also provides CS0 and one state of WrEn_MD (selected by C10) to an additional column plane 452. Accordingly, 4 bits of data are accessed from the additional column plane 452 (e.g., from the sense amplifier 408). In addition, the column decoder also generates an additional CS signal and provides it to one of the column planes that is not selected by the value of C10. In this example embodiment, the value CS56 is provided to column plane 444. Accordingly, column plane 444 provides 8 bits of ECC parity. In this way, with a single access pass, 64 bits of data (8 bits each from column planes 416, 418, 426, 428, 436, 438, 446, and 448), 4 bits of metadata (half retrieved from extra column plane 452), and 8 bits of parity (from column plane 444) are accessed. Arrows are used to show which CS signals and which column planes are accessed as part of a single access pass.

[0100] Although Figure 4 , but similar access may occur as part of a second access operation, where a column address is received that includes C10=1 but the same decoded value of CS. In the example, the column decoder provides CS0 to column planes 412, 414, 422, 424, 432, 434, 442, and 444, as well as to additional column plane 452, while providing a CS56 value to column plane 448. In this operation, another value of WrEn_MD is provided, and the other four bits are accessed (e.g., from sense amplifier 409 instead of 408).

[0101] Figure 5 is a block diagram of an additional column plane according to some embodiments of the present disclosure. In some embodiments, the additional column plane 500 may represent Figure 2 Additional column plane 212, Figure 3 Additional columns of plane 308 and / or Figure 4 The additional column plane 500 is provided together with a command decoder 510 that provides various signals (e.g., Figure 1 106) are displayed together. Figure 5 The view of FIG. 5 shows how write enable is provided to different sense amplifier regions 502 and 503 in the additional column plane 500 .

[0102] The additional sense amplifier region 500 includes a number of sections 506 (eg, Figure 4 Each of the segments 506 includes a number of memory cells at the intersection of a word line and a bit line. Each segment 506 includes a pair of sense amplifier regions 502 and 503 (e.g., Figure 4 Furthermore, each sense amplifier region 502 and 503 is delimited by two segments 506 (except at the edges of the array).

[0103] The even write enable signal WrEn_Even activates the sense amplifier in region 502 as part of a write operation, while the odd write enable signal WrEn_Odd activates the sense amplifier 503 as part of a write operation. In some embodiments, the command decoder 510 can provide a single binary signal WrEn_MD, which can be in a first state to activate WrEn_Even, and in a second state to activate WrEn_Odd. For example, if WrEn_MD high activates WrEn_Even, then WrEn_MD low can activate WrEn_Odd (and vice versa).

[0104] Figure 6 is a block diagram of an additional column according to some embodiments of the present disclosure. In some embodiments, the additional column plane 600 may represent Figure 2 Additional column plane 212, Figure 3 Additional column plane 308, Figure 4 Additional columns of plane 452 and / or Figure 5 Specifically, the additional column plane 500 may represent an additional column plane 500, but in Figure 6 The circuits and signals associated with the read operation are shown in Figure 5 )

[0105] exist Figure 6 , a read operation has been performed on one of the sectors of the additional column plane 600, and data is being read out along the GIO. For example, sector 606 may be accessed based on a row address, and a column select signal may be provided to the sense amplifiers in the delimited sense amplifier regions 602 and 603. Those sense amplifiers may read out the data and couple the read data to the corresponding GIO. Since 8 bit lines are accessed, there may be a set of 8 GIOs. Figure 6 In the example of , GIO<3:0> is coupled to the even sense amplifier 602 , and GIO<7:4> is coupled to the odd sense amplifier 603 .

[0106] During a read operation, eight metadata bits are accessed, including four selected bits and four unselected bits (in contrast to a write operation, where only four accessed metadata bits are accessed due to a separate WrEn signal). However, parity bits are generated by the ECC circuit 612 during a write operation, and therefore, the parity bits are based only on the selected four metadata bits. With this in mind, the memory may include an ECC mask circuit 610 that receives the GIO lines from the additional column plane 600 and provides one set or the other to the ECC circuit 612 during a read operation. Which set of GIO lines is provided to the ECC circuit 612 may be based on the state of the column plane select bit in the column address (e.g., C10).

[0107] For example, if C10 indicates an even sense amplifier, the ECC mask circuit 610 may provide GIO<3:0> as metadata bits MD<3:0> to the ECC circuit 612. If C10 indicates an odd sense amplifier, the ECC mask circuit 610 may provide GIO<7:4> as metadata bits MD<3:0> to the ECC circuit 612. In this way, only selected bits are passed to the ECC circuit 612 during a read operation.

[0108] Figure 7 is a block diagram of a sense amplifier region according to some embodiments of the present disclosure. In some embodiments, the sense amplifier region 700 may represent Figure 4 The sense amplifier regions 404 and 408 (or 405 and 409) or include Figure 5 A sense amplifier set of the sense amplifier region 502 or 503 . Figure 7 Shows a simplified view where several components, signal lines, etc. have been omitted. Similarly, Figure 7 A single data portion 710 is shown along with an additional portion 720 and a GCR portion 730, all of which are aligned adjacent to each other, but there may be multiple data portions (e.g., 16) and any spatial arrangement of these portions (e.g., 8 data portions, an additional portion, another 8 data portions, etc.).

[0109] Sense amplifier region 700 includes a stripe of sense amplifiers 706 and portions of delimited sections 702 and 704. The stripe of sense amplifiers 706 includes several individual sense amplifiers (for clarity, Figure 7 Sense amplifiers are coupled to bit lines in both segments 702 and 704 (not shown), with each sense amplifier coupled to a bit line in both segments 702 and 704 (whichever is accessed, the other will serve as a reference). Sense amplifiers are coupled to every other bit line in segments 702 and 704, with the other bit lines being coupled to sense amplifiers in other strips (not shown).

[0110] The sense amplifier region 700 includes three portions 710, 720, and 730. The first portion 710 is aligned with the data column plane (eg, Figure 2 The second portion 720 is associated with an additional column plane (e.g., Figure 2 The third portion 730 is associated with the GCR column plane (eg, Figure 2 214). In each segment, corresponding read / write pass gates 712, 722, and 732 are shown. Each segment may have several read / write pass gates (e.g., one for each LIO / GIO in the segment), however, for clarity, only one read / write pass gate per segment is shown.

[0111] During an example read operation, data may be read out along the bit lines and amplified by the sense amplifiers, and the column select signals determine which bit lines are coupled to their corresponding LIOs. The read / write pass gates 712, 722, and 732 may receive a read enable signal (not shown) that couples the data on the LIO to the GIO so that it may be read out along the GIO to the ECC (e.g., Figure 1 120) and data terminal DQ.

[0112] During an example write operation, data and metadata are received, and the ECC generates parity based on the data and metadata. Data, parity, and metadata are provided along the GIO line, and the read / write transfer gates 712, 722, and 732 can receive corresponding write enable signals (WrEn or WrEn_MD). If the write enable signal is valid, the data along the GIO is coupled to the LIO, which causes the sense amplifier to change the voltage of the bit line selected by the CS, which in turn changes the signal stored in the memory cell at the intersection of the bit line and the valid word line.

[0113] The read / write pass gate 712 in the data portion 710 receives a signal WrEn. The signal WrEn may be a binary signal that is valid in a first state (e.g., logic high) and invalid in a second state (e.g., logic low). The read / write pass gate 722 in the additional portion 720 receives a signal WrEn_MD. When WrEn_MD is in the first state, the read / write pass gate 722 may be valid if it is an even read / write pass gate, and when WrEn_MD is in the second state, the read / write pass gate 722 may be valid if it is an odd pass gate.

[0114] Logic circuit 708 (eg, Figure 2The logic circuit 708 may be one of the logic circuits 240 of the GCR portion 730) to provide WrEn or WrEn_MD to the read / write pass gate 732 in the GCR portion 730. For example, the logic circuit 708 may be a multiplexer that provides WrEn or WrEn_MD to the read / write pass gate 732. The multiplexer selects which write enable signals to provide based on the repair signal GCR_REPAIR_MD. The repair signal may be specific to each logic circuit 708 and each read / write pass gate 732 in the GCR portion 730, and may indicate whether the pass gate 732 is part of a repair operation for a column from the data portion 710 or the additional portion 720. If the repair signal indicates that the repair is from the additional portion 720, WrEn_MD is passed, and the read / write pass gate may mimic the behavior of the read / write pass gate 722. If the repair signal indicates that the repair is from the data portion 710, the signal WrEn is passed, and the read / write pass gate 732 may mimic the behavior of the read / write pass gate 712. The repair signal may be based on a signal stored in the fuse array (e.g., Figure 1 152) to generate a repair signal.

[0115] Figure 8 is a flow chart of a method according to some embodiments of the present disclosure. In some embodiments, method 800 may be implemented by one or more of the devices or systems disclosed herein. For example, method 800 may be implemented by Figure 1-7 One or more implementations in a system or component of.

[0116] The method 800 includes block 810, which describes activating a first write enable signal and a second write enable signal in response to a write operation, wherein the second write enable signal has a first state or a second state based on a column address. For example, the first write signal may be WrEn and the second write signal may be WrEn_MD. The method 800 may include determining a state of the second write enable signal based on a column plane select bit of a column address (e.g., C10).

[0117] Block 810 may be followed by block 820, which depicts writing data to the selected bit line in the first column plane in response to the first write enable signal. For example, method 800 may include receiving data and providing the data along a GIO line, and in response to the first write enable signal, using a transfer gate (e.g., Figure 7 712) couples the GIO line to the LIO line associated with the first column plane.

[0118] Block 830 represents a step that may occur more or less simultaneously with the step of block 820. Block 830 describes writing metadata to a first portion or a second portion of a selected bit line in a second column plane in response to the state of a second write enable signal. For example, metadata may be provided along a GIO line and the GIO line is connected to a first or second portion of a selected bit line in a second column plane via a transfer gate (e.g., Figure 7 722) is selectively coupled to the LIO line. The LIO line is coupled to a second column plane (e.g., an additional column plane, such as Figure 2 212). The first or second portion of the transfer gate may be activated by a second write enable signal (e.g., WrEn_MD) based on its value. For example, if the second write enable signal is in a first state, an even-numbered transfer gate in the transfer gate may be activated, and thus metadata is written to an even-numbered bit line in the selected bit line. If the second write enable signal is in a second state, an odd-numbered transfer gate in the transfer gate may be activated, and thus metadata is written to an odd-numbered bit line in the selected bit line.

[0119] The method 800 may include generating a column select signal based on the column address, and selecting bit lines in the first and second column planes based on the value of the column select signal. The method 800 may include selecting a first portion (e.g., C10) of the plurality of column planes based on the column plane select bit (e.g., C10). Figure 1 The method 800 may include generating parity bits based on the received data and metadata bits, and writing the parity bits to selected bit lines in a third column plane. The third column plane may be a column plane that is not selected by the column plane select bits.

[0120] The method 800 may include: as part of a read operation, reading a first set of bits from a first portion of selected bit lines in a second column plane and reading a second set of bits from a second portion of selected bit lines in the second column plane; and selecting the first set of bits or the second set of bits (e.g., using an ECC read mask circuit such as Figure 6 610). The selection may be based on a column plane selection bit (e.g., C10). The method 800 may include providing a selected one of the first set of bits or the second set of bits to an ECC circuit (e.g., Figure 6 of 612).

[0121] The method 800 may include repairing selected bit lines in the first column plane or selected bit lines in the second column plane to selected bit lines in the global column repair (GCR) column plane. For example, the method 800 may include repairing selected bit lines in the first column plane or selected bit lines in the second column plane to selected bit lines in the global column repair (GCR) column plane. Figure 1The method 800 may include: if the selected bit line in the first column plane is repaired, writing data to the selected bit line in the GCR column plane in response to the first write enable signal, or if the selected bit line in the second column plane is repaired, writing metadata to the first portion or the second portion of the selected bit line in the GCR column plane in response to the state of the second write enable signal. For example, the logic (e.g., Figure 2 240) can pass the first write enable signal or the second write enable signal to the transfer gates associated with the bit lines in the GCR column plane based on which bit lines are repaired.

[0122] Fig. 9 900 is a timing diagram of a mode register write operation according to some embodiments of the present disclosure. The timing diagram 900 may represent a controller (eg, Figure 1 150) can write a value to the mode register (for example, Figure 1 130) to set the memory mode instance.

[0123] Timing diagram 900 shows the clock signal CK_t / CK_c (eg, Figure 1 The chip select signal is used to indicate that the controller is addressing this specific memory device (e.g., chip). Figure 6 In FIG. 1 , a higher level is used to indicate that the chip select signal is valid, but in some embodiments, the chip select signal may be a low level valid. Signals along the command / address bus CA and the command CMD are also shown.

[0124] Timing diagram 900 shows three MRW operations occurring sequentially at time points Ta0R, Tb1R, and Tc1R. Each MRW operation includes providing an address within a mode register and data to be written to the register along the CA (shown in a box labeled "valid" to indicate that the value MR address and data are being provided). Two sequential MRW commands labeled MRW-1 and MRW-2 are used to indicate that the information along the CA bus is part of a MRW operation.

[0125] Fig.10 is a flow chart of a method according to some embodiments of the present disclosure. In some embodiments, method 1000 may be implemented by one or more of the devices or systems described herein. For example, method 1000 may be implemented by Figure 1 The controller 150 is implemented.

[0126] Method 1000 includes block 1010, which describes writing a value to a mode register of the device to enable a first mode or a second mode. For example, the controller may perform an MRW operation, such as Fig. 9The first mode may be a one-pass x4 operation mode in which the individual write enable signal is disabled, and the second mode may be a one-pass x4 operation mode in which the individual write enable signal is enabled.

[0127] Block 1010 may be followed by block 1020, which describes performing a first write operation on a memory bank of a memory device. The first write operation includes writing data and metadata to the device. For example, the controller may provide a write command and row, column, and group addresses to the C / A terminal. The controller may provide data bits and metadata bits to the DQ terminal. For example, the controller may provide 64 data bits and 4 metadata bits. The controller may also generate and provide a column address as part of an access operation. The column address may be generated to address an addressable portion of a memory array. For example, a column address may be generated based on a CS value desired to be addressed, and in both the first and second modes, the column address may be associated with a CS value range (e.g., CS0 to CS55) that is less than the range of all possible CS values ​​(e.g., CS0 to CS63).

[0128] Block 1020 may be followed by block 1030 or block 1040, depending on whether the memory device is in the first mode or the second mode. Block 1030 describes waiting for at least a first amount of time after a write operation when the device is in the first mode. Block 1040 describes waiting for at least a second amount of time after a write operation when the device is in the second mode. The first amount of time may be at least tCCD_L_WR. The second amount of time may be less than tCCD_L_WR. In some embodiments, method 1000 may include waiting for the first or second amount of time before accessing a different group in the same group group.

[0129] Blocks 1030 and 1040 may be followed by block 1050, which describes performing a second write operation to the memory bank. The second write operation may be substantially similar to the first write operation described with respect to block 1020. In the first mode, the controller may wait at least a first amount of time between the first and second write operations, and in the second mode, the controller may wait at least a second amount of time between the first and second write operations.

[0130] The method 1000 may include reading data and metadata from the memory array as part of a read operation. Since both modes may allow the memory to operate in a SECDED ECC scheme, the method 1000 may include receiving a signal from the memory indicating that a double bit error was detected (but not corrected) in the data and metadata. The first or second write operation may include: when the device is in the first mode, reading metadata from an additional column plane by activating a column select signal, modifying some of the read metadata with the newly written metadata, and writing back the modified metadata. The first or second write operation may include: when the device is in the second mode, activating write enable signals associated with some (but not all) of the column lines associated with the same column select signal, and writing metadata only to the column lines selected by the write enable signal.

[0131] In some embodiments, the controller may write a value to the mode register to set the memory to a third mode (eg, two-pass mode).

[0132] Of course, it should be understood that any of the examples, embodiments, or processes described herein may be combined or separated from one or more other examples, embodiments, and / or processes and / or performed between separate devices or device portions according to the systems, devices, and methods of the present invention.

[0133] Finally, the above discussion is intended only to illustrate the inventive system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, although the inventive system has been described in detail with reference to exemplary embodiments, it should also be understood that many modifications and alternative embodiments may be devised by those of ordinary skill in the art without departing from the broader intended spirit and scope of the inventive system as set forth in the appended claims. Therefore, the specification and drawings should be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. A device comprising: a first column plane comprising a first plurality of bit lines; a second column plane comprising a second plurality of bit lines; An input / output circuit is configured to receive data and metadata as part of a write operation, wherein the data is written to the first plurality of bit lines, and wherein the metadata is written to an even or odd bit line of the second plurality of bit lines.

2. The apparatus of claim 1, further comprising a column decoder configured to provide a column select signal based on a column address, wherein the first plurality of bit lines and the second plurality of bit lines are activated by a same value of the column select signal.

3. The apparatus of claim 1 , further comprising a column decoder configured to provide a first write enable signal and a second write enable signal, wherein the data is written to the first plurality of bit lines in response to the first write enable signal, and wherein the even or odd bit lines of the second plurality of bit lines are selected based on a value of the second write enable signal, and wherein the metadata is written to a selected one of the even or odd bit lines of the second plurality of bit lines.

4. The apparatus according to claim 1, further comprising: a global column repair (GCR) column plane including a plurality of redundant bit lines; A fuse array configured to remap the first plurality of bit lines or the second plurality of bit lines to the plurality of redundant bit lines, wherein if the first plurality of bit lines are remapped to the plurality of redundant bit lines, the data are written to the plurality of redundant bit lines, and wherein if the second plurality of bit lines are remapped to the plurality of redundant bit lines, the metadata are written to an even or odd redundant bit line among the plurality of redundant bit lines.

5. The apparatus of claim 4 , further comprising a logic circuit configured to provide a first write enable signal if the first plurality of bit lines are remapped to the plurality of redundant bit lines, and to provide a second write enable signal if the second plurality of bit lines are remapped to the plurality of redundant bit lines.

6. The apparatus of claim 1, further comprising: a third column plane comprising a third plurality of bit lines; An error correction code (ECC) circuit is configured to receive the data and the metadata as part of the write operation and generate parity bits based on the metadata, wherein the parity bits are written to the third plurality of bit lines.

7. The apparatus of claim 6, further comprising an ECC mask circuit configured to receive a set of bits including the metadata from the second plurality of bit lines as part of a read operation and configured to provide even or odd bits in the set of bits to the ECC circuit.

8. A method comprising: activating a first write enable signal and a second write enable signal in response to a write operation, wherein the second write enable signal has a first state or a second state based on a column address; writing data to selected bit lines in a first column plane in response to the first write enable signal; as well as Metadata is written to a first portion or a second portion of a selected bit line in a second column plane in response to the state of the second write enable signal. 9 . The method of claim 8 , wherein the first portion is even-numbered bit lines among the selected bit lines, and the second portion is odd-numbered bit lines among the selected bit lines.

10. The method according to claim 8, further comprising: generating a column select signal having a value based on the column address; as well as The selected bit lines in the first column plane and the selected bit lines in the second column plane are selected based on the value of the column select signal.

11. The method according to claim 8, further comprising: generating a parity bit based on the data and the metadata; as well as The parity bits are written to selected bit lines in the third column plane.

12. The method of claim 8, further comprising selecting a first portion or a second portion of a plurality of column planes based on a column plane select bit of the column address, wherein the first column plane is in the first portion or the second portion, and wherein the second column plane is not in the first portion or the second portion.

13. The method according to claim 8, further comprising: as part of a read operation, reading a first set of bits from the first portion of the selected bit lines in the second column plane, and reading a second set of bits from the second portion of the selected bit lines in the second column plane; selecting the first bit set or the second bit set; as well as A selected one of the first set of bits or the second set of bits is provided to an error correction code (ECC) circuit.

14. The method according to claim 8, further comprising: repairing the selected bit line in the first column plane or the selected bit line in the second column plane to a selected bit line in a global column repair (GCR) column plane; writing the data to the selected bit line in the GCR column plane in response to the first write enable signal if the selected bit line in the first column plane is repaired; If the selected bit line in the second column plane is repaired, the metadata is written to a first portion or a second portion of the selected bit line in the GCR column plane in response to the state of the second write enable signal.

15. An apparatus comprising: The first plane includes: a first local input / output (LIO) line coupled to the first read / write transfer gate; a second LIO line coupled to a second read / write transfer gate; The second plane includes: a third LIO line coupled to a third read / write transfer gate; a fourth LIO line coupled to a fourth read / write transfer gate; and a column decoder configured to provide a first write enable signal to the first column plane and a second write enable signal to the second column plane, wherein the first and the second read / write transfer gates are activated by the first write enable signal and the third or the fourth read / write transfer gate is activated by the second write enable signal.

16. The apparatus of claim 15, wherein the first column plane further comprises: a first plurality of bit lines, a selected one of which is coupled to the first LIO line; as well as a second plurality of bit lines, a selected one of which is coupled to the second LIO line, and wherein the second column plane further comprises: a third plurality of bit lines, a selected one of which is coupled to the third LIO line; as well as A selected one of a fourth plurality of bit lines is coupled to the fourth LIO line.

17. The apparatus of claim 16, wherein a selected one of the first, the second, the third, and the fourth pluralities of bit lines is selected by a same value of a column select signal.

18. The apparatus of claim 15, further comprising: Error correction code (ECC) circuit; as well as An ECC mask circuit is configured to receive a first bit from the third read / write transfer gate and a second bit from the fourth read / write transfer gate and provide the first bit or the second bit to the ECC circuit.

19. The apparatus of claim 15, further comprising: The third plane includes: a fifth LIO line coupled to a fifth read / write transfer gate; and A logic circuit is configured to provide the first write enable signal or the second write enable signal to the fifth read / write transfer gate.

20. The apparatus of claim 19, wherein the logic circuit is configured to provide the first write enable signal if the first or the second LIO line is repaired to the fifth LIO line, and wherein the logic circuit is configured to provide the second write enable signal if the third or the fourth LIO line is repaired to the fifth LIO line.

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